Mn h c Thi#t b' ngo)i vi v k+ thu.

t ghp n/i (Peripherals & Interfacing Technique)

Gio vin: Bi Qu/ c Anh, B0 mn K + thu.t My tnh Introduction: The purpose of this course is to provide student with technical knowledge of each major subsystem of Interface, including processors, memories, IO bus,... especially Nonstandard zed Input Output via ports and applies to industry architectures across a wide range of hardware vendors This document could contain technical inaccuracies or typographical errors. Author believes the statements contained herein are accurate as of the date of editing of this doc. However, the Author makes no warranty of any kind with respect to the accuracy of the contents hereof.

1. Hardware

Central Sys.

Adaptor

Wide world
Computerized Dev: KB, Printer, Scanner, Mouse

Ports CPU, Mem, Bus, Controlle rs, ...

Controllers HDC, CRTC

Specific Devices: HDD, CRT, ...

Ti li u tham kh$o: Publications: - Microprocessor Interfacing techniques, R. Zaks & A. Lease, Sybex - Micro Processor and Interfacing, D. Hall, McGraw Hill; - IBM PC AT Technical Reference (Buses, Ports), IBM; - Introduction to the PC Architecture Course, IBM PC Institute, 1997 - Interfacing to IBM PC L. C. Eggebrecht, IBM Corp. - Parallel Port Complete, J.Axelson, LakeViewResearch. - Mastering Serial Communication, P.W. Gofton, Sybex. - PC Intern (System Programming), M. Tischer, Abacus. - Programming & Interfacing the 8051 MC, S. Yeralan, Addison-Wesley - ... Software: - TechHelp Ver. 4.0 / 6.0 - MSDN, Online Help. - Design tools: OrCAD, Protel, Cadence... - Programming Languages (C, Pascal, MASM, C++, VB, Delphi, VC++...) - .... Websites, .pdf files: - IBM, Microsoft, Intel, Motorola ... - ATMEL: atmel.com/product/microcontrollers 89Cxx (51/52/2051/8252, AVR - RISC, MSC51)... - National Semiconductor: ns.com/products: ADC 0809, DAC0800/1210, S&H LM198)... - INTERSIL: intersil.com/products/ICL7109, 7135... - Analog Devices Inc.: adi.com/products/adc, S&H...: AD574, AD1674 - USB: usb.org (pdf files for version 1.x & 2.x) - Cypress EZ USB, Developing Kit... - ...

ADC, DAC

Industry Objects: Scale, Furnace, GenSet, Tanks,...

2. Software: Device Drivers: SLLs, DLLs, DRVs, VxDs, DCUs,...

Interfacing?
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Ch12ng.1 Ki#n trc h3 VXL MT

Ki#n trc thi# t b' h3 kinh 4i5n, Ki#n trc h3 my tnh Hi Performance Ho)t 40ng c7a h3 th/ng.

1.1. Ki# n trc H3 VXL, My tnh kinh 4i5n Embedded systems 1.1.1. S2 4: : 3 ph;n: - CS, - Ngo )i vi & - Interface

1.1.1. a. Central Sub System CS: + CPU: Central Processing Unit: Khi ni m: L b' )i*u khi+n trung tm, th-c hi n cng vi c )./c giao )1t trong b' nh3 ch.0ng trnh b5ng cch th-c hi n cc php x6 l ln cc bi7n nh9 phn v )i*u khi+n thi7t b9 ngo;i vi. Cng vi c bao g<m: Tm l nh, gi$i m l nh, [tm ton h; ng, x6 l v c= t k7 t qu$], In/Out v3i cc port ki+u Interrupt v DMA )+ ) i*u khi+n thi7t b9 ngo; i vi. <=c tr1ng Specifications: Kch th.3c ton h; ng (bit): 4, 8, 12, 16, 32, 64... T>c )' x6 l: Mips, clock multiplier, Ki7n trc: RISC vs CISC, DSP, Micro Controller... Pinning/Signalling (Data/Address - Mux, Control bus, IRQ, HRQ, RD/WR...), Register set, Instruction set Addressing Modes, Power: Slow/ sleep/ power down modes ... Memories (Semiconductor): K/n & ROM: Khi ni3m: L. u thng tin (ch/tr v s> li u) d;ng nh9 phn, Dung l./ng l3n (upto 100s Mega bit), t>c )' truy nh?p nhanh (downto ns access time). Physically: tnh ch$t v't l nh( th) no? ROMs: g<m Mask ROM, PROM, EPROM, EAROM, OTROM, NonVolatile mem, ... L b' nh3 ch@ )Bc, vC n l.u thng tin khi m=t )i n, Package : byte Access time:100..120ns Ghi/n;p n'i dung: T/b9 chuyn dng (ROM Burner/Programmator) Memories (Semiconductor): SRAM RAMs: L.u thng tin t;m thEi, khng l.u )./c khi m=t )i n, )Bc v ghi )./c, [Read/Write Mem].
Page 3 of 56

Static RAM: nhanh (80..3 ns), byte/nibble package, m?t )' byte/chip nhG (upto 64/256 KB/ chip), )Ht, tiu thI cng su =t nhi*u, CMOS RAM: ch?m v tiu thI c- c t, less W. VdI: MC 146818 RealTimeClockCMOS RAM Dng trong cc h nhG, cache memory. Memories (Semiconductor): DRAM Dynamic RAM: DRAM: T>c )'/Access time (50-70ns), [10..20ns] Pre-fetched M?t )' bit/chip >> (1 Gbit/chip 1996, Korea), bit package => DRAM bank, Tiu thI cng su =t nhG. Thng tin ch@ l.u )./c 10ms => refreshing DRAM v3i chu kK @ 7,5ms => phMc t; p. Dng trong cc h c dung l./ng nh3 l3n: my tnh, my chN... Memories (Semiconductor): FLASH & Others Flash memory: EAROM typed, ).Bc )/c, xo tOng bank, ghi l;i )./c tOng byte. Thng tin l.u )./c 20 nPm, dng nhi*u hi n nay v t.0ng lai: BIOS, diskchip... Serial EAROM/FLASH: dng )+ l.u configuration, dng bus I2C (Philips). V dI Mng dI ng : thQ vi m;ch, TV, ... Dual [Quad] Ported RAM: Switching Sys., PGA RAM-DAC: VGA, VoiceChip PCMCIA .... Memories (Semiconductor): Logically: B0 nh? chAa thng tin g? Program memory: chMa ch/tr )ang )./c th-c hi n Data memory: cc bi7n ngCu nhin, bi7n c c=u trc, s> li u c ki+u truy nh?p )1c bi t FIFO, LIFO (Stack memory). + Controllers: [Optional], vi m)ch, nng hi3u nBng (performance) h3 th/ng, bao g:m: B* ,i-u khi.n (u tin ng0t PIC Priority Interrupt Controller, Intel 8259A B* ,i-u khi.n truy nh'p tr2c ti)p b* nh3 DMAC Direct memory Access Controller, Intel 8237A. Timer: m6ch t6o cc kho7ng th9i gian, PIT- Programmable Interval Timer, Intel 8254. M6ch qu7n tr; nh3: MMU- Memory Management Unit, sau ny, th.Eng )/c built on chip v3i CPU. Bus controller/Arbitor ... Bus System: K/n & Addr bus PCB (Printed Circuit Board)/ Cable (Twisted pairs, flat..), slot, connector... N>i h0n 1 slave device, time sharing Thng tin: Address, data, control, status, Power Supply Chi*u (dir), 3 state (Hi Z), Loading ADDRESS BUS: TO cc BusMaster (CPU, DMAC, PCI host Controller) )7n SlaveDevices (Mem, Ports) )+ chBn/ chG tOng IO/ Mem location trong tOng chu k K bus n Addr bit 2n Mem Locations & 2m IO Locations, m<n Bus System: Data bus Data bus: S> bit (th.Eng) ph h/p v3i kch th.3c ALU (8/16/32/64 bit)
Page 4 of 56

Chuy+n Op-code (m l nh) trong chu k K my M1, - CPU <= Program Memory, trong cc bus cycle M1 V?n chuy+n data: - CPU <=> Data memory, - CPU <=> IO Ports v - Data Memory <=> IO Ports, DMA. Bus System: Control/Status bus: g=m cc tn hi u: Control/ Response: CPU to Others (MEMR, MEMW, IOR, IOW, INTA, HLDA, BHE...), from CPU Status/Request to CPU: IRQ, HRQ, Ready, ... to CPU Bus System: Power Supply: +5V 5%, 10 ,)n 20 Amp, c$p cho cc Vi m6ch s>, RedWire. (3.3V and less) Ground, Gnd, 0V, signal reference ground, chassis, BlackWire. +12V 10%, 1Amp, c$p cho cc m6ch analog, motors, RS232, YellowWire. -12V 10%, 1Amp, (nh trn), BlueWire. - 5 V5%, 0.5 Amp, analog circuitries, WhiteWire. Power good: OrangeWire. Ngu n thng minh: AXT 1.1.1.b. Thi#t b' Ngo)i vi: Data Input Devices: - Key board/ Key pad, Touch SCR: s> phm, cng ngh phm, ki+u d phm, output code, ghp n>i CS - Mouse, track ball - Scanner, Camera, Camcoder: Colors, resolution, f, cng ngh CCD - Charge Couple Device, graphics file bmp - Digitizer, nh?p graphics file vector - b$n )< - Light Pen, Joy stick (Games) - Demodulator (MODEM): Ki+u )i*u ch7, t>c )' bps, ki+u nn - Microphone, - Barcode reader: my )Bc m v; ch Laser/ LED, - Sensor, Transducers, Transmitters: V ?t li u, thi7t b9, )' nh?y, )' tuy7n tnh, d$ i ) o... 1.1.1.b. T/b' Ngo)i vi: Data Output Devices: - Displays: Ki+u hi+n th9: Point/ 7Seg/ Text/ Graphics; Mono Chrome/Color (color numbers); Size, Resolution, Rate of Refreshing... - Cng ngh : - LED (Light Emitting Diodes): point, 7(16) Segment, Matrix character box (Bill Board), Outdoor LED Screen... - LCD (Liquid Crystal Display): single color, color, active, TFT (thin film transistor)... - Organic LED (Preliminary), - CRT (Cathode Ray Tube). - Printers: - Spec: Text-Graphics, Mono-Color, Resolution, ppm page per minute, Size, Line-PostScript, media... : - Pin Printer, - Jet Printer, - Laser Printer, - Thermal Transfer Printer, barcode Printer. - High Speed Text Printer, - ... 1.1.1.b. T/b' Ngo)i vi: Data Output Devices: Others - Plotter, jet - Modulator (MODEM) - Speaker - Actuator: Motor (dc/ac, Step), Relay, Valve,
Page 5 of 56

1.1.1.b. T/b' Ngo)i vi: Data Massive Storages: - Magnetic devices: FDD, HDD, RAID, Tape backup drive... - Optical devices: CD [Writer] Drives, Magnetic Optic disk drive... - Semiconductor devices: FlashChip, PCMCIA Card... 1.1.1.c. Interface: L do: khc nhau: - Tn hi u (dng, p), - T>c )' lm vi c/t>c )' trao )Ri s> li u, - Khng )<ng b'... Nn cSn c m;ch ) i n t6 )+ thch Mng ho (Adapting) v ch/tr ) i*u khi+n, g<m: - Thi7t b9 (Hardware Circuitries), so called Adaptors: - Input/Output Ports: (Parallel/Serial): ghep n>i v3i Computerized devices (KB, Printer, Mouse, Scanner, Modem...) - Controllers: )+ ghp n>i v3i nhTng thi7t b9 chuyn dng FDC, HDC (IDE, EIDE), CRTC (EGA, VGA, SVGA...) - Converter: )+ chuy+n )Ri tn hi u s> thnh t.0ng t- v ng./c l;i: ADC, DAC 1.1.1.c. Interface: Ch/tr 4iCu khi5n Device Driver: - K/n: Hardware or Software? - )+ lin k7t System Programs and/or Application Programs v3i IO hardware (SPIs v APIs). Cc hm cN a thi7 t b9, BIOS, OS ho1c theo Mng dIng: SLLs, DLLs, DRVs, ... 1.1.2. Ki#n trc my tnh hi3u nBng cao - hi performance architecture

1.1.2. Hi-Per. Architecture: 1.1.2.a. Local Buses: V dI VESA VL-Bus 2.0 [late 1993], Memory [1985]. Also called system/host/processor bus. Ch@ lin k7t CPU, MMU (Cache & DRAM) v PCI Host [Bridge], t, gSn, unbuffered (direct connected to Processor); 33, 66, 100, 133, 200, 400, 800 MHz... clock. 32 bit A/D (16 bit support also), burst mode, max 132 MBps,

Page 6 of 56

reset ProgCounter = ResetAddr/vector

Addr

D0

D1
(data 4 byte)

D2

D3

D4
n

DMA?

Machine On Halt

DMA? y

H.1.3. V d? burst mode 1.1.2.b. Hi Speed Bus: - Peripheral Component Interconnect PCI - 5/1993, Intel Ver. 2.0, Open Standard, - Local bus, mMc trung gian giTa Local v cc bus chuVn khc (ISA, MC, EISA) thng qua PIC Bridge/Controller. - C ki+m tra parity cho Addr v Data - Auto configuration of all PCI devices, share the same IRQ. Disabling IRQ => c=m ton b' PCI devices. - No DMA, device on PCI bus l bus master (T>t cho vi c dng MultiTasking OS). - Burst mode: 32 bit @33MHz --> 96..132MBps, tuK thu'c s> byte (tO 32 byte )7n 4KB). Option 64bit @33MHz --> 264MBps - Most Platforms use:Intel, DEC Alpha, PowerPC, Spark - Modern OS: Block Typed Devices: tSn su =t v?n chuy+n cao, nhanh, data block 1.1.2.c. Expansion Bus: So called: standard buses, expansion bus, slots, IO bus, IO system, channel bus): ISA, EISA, MC... - MC bus: 32 bit, 10MHz, 20..40MBps, 15 BusMaster, Auto config, 1987, IBM - EISA bus: 32 bit, 8MHz, 33MBps, 4 BMs, AutoConfig (EISA card only), 1989, Compaq - ISA (Industry Standard Architecture), AT bus: - Spec. 8/16 bit (data), 8MHz, 5MBps max, 1 BM, no PnP, 1984, IBM. - R=t phR bi7n, cn t<n t;i lu, Espec. @ iPC, - H;n ch7 s> IRQs, 4 DRQs, - Dng DIP switch/jumper )+ config. - No data integrity features (no party checking) - Modern OS: Character Typed Devices 1.2. Ho)t 40ng c 7a h3 th/ng: Reset, Opcode fetch and Execute, Interrupt, DMA & Ready (wait state - ws) 1.2.1. L1u 4: tDng qut:

IRQ? n OpCode Fetch

y y

MaskOn

PC = Intr. Vector

OpCodeDecode

Execute

Hnh 1.3. L (u ,= tFng qut cCa VXL (Motorola), Training courses

1.2.2. Reset : Cold Start: Nt reset/Power-On =>Xo tr ;ng thi hi n hnh, c=m ngHt, DMA. CPU )./c khWi t;o (PCProgram Counter (IP), Flags v SP...). Th.Eng cc thi7t b9 trong h cng )./c reset. (Sau khi reset, CPU s A tm v t/h l nh v3i cc thC t?c sau) Warm Start: do l nh gBi, (Int 19h, Ctrl_Alt_Del) POST (Power On Self Test ch/tr monitor/ BIOS) )+ ki+m tra mBi thi7t b9 theo nguyn tHc ghi v )Bc l;i (Registers, RAM) ho1c )Bc v ki+m tra Check Sum (ROM). Initializing: )1t cc tham s> => configuring. [My tnh - N;p h )i*u hnh ]. 1.2.3. DMA: (Xem Ch. 3.2.) 1.2.4. Interrupt: (Xem Ch. 3.3.) 1.2.5. Tm v thEc hi3n l3nh : DiXn ra chN y7u trong thEi gian ho;t )'ng. Ch/tr ngn ngT my: t?p h/p cc l nh c c=u trc, c nghYa, th-c hi n 1 thu ?t ton. Chu kK l nh (Instruction Cycle): Kho$ng thEi gian CPU th-c hi n xong 1 l nh, g<m: tm l nh, gi$i m l nh, [tm ton h6ng v th2c hi n l nh (th2c hi n cc php xD l hoEc vo-ra)]. )' di l nh: 1 hay nhi*u byte, CISC ThEi gian t/h: 1 hay nhi*u chu k K my (chu kK bus). Chu kK my (Bus/Machine Cycle): thEi gian BusMaster th-c hi n thao tc trn bus. Clock cycle: Chu kK my: 4..12 chu kK clock, tu K CPU. 1.2.5.1. Ho)t 40ng c7a h3 th/ng: C 8 CPUs BusCycles: M1, opcode fetching, Addr =>Program mem, -MEMR Data mem Reading, Addr=>Data mem, -MEMR Data mem Writing, Addr=>Data mem, -MEMW Input Port Reading, Addr=> IO space, -IOR Out Port Writing, Addr => IO space, -IOW Interrupt Acknowledge, -INTA, Halt, waiting for Ext. Intr. ho1c reset Bus Idle 2 DMACs bus (machine) cycles: IOR-MemW v MemR-IOW. 1.2.6. Wait State (Ready):
Page 7 of 56 Page 8 of 56

 Th.Eng dng )+ ghp n>i: b' nh3, ngo;i vi t>c )' ch?m. Ho;t )'ng Khi BusMaster pht )9a ch@ & tn hi u )Bc/ghi (thm cc tn hi u khc) )+ th-c hi n 1 chu kK bus, MMU/IO port [Controller] chN )'ng pht ra tn hi u Ready=0 (not Ready) )+ yu cSu BusMaster giT nguyn tr;ng thi bus thm 1 [vi] nh9p clock. Case Study: IOW bus cycles w/o and w 1 wait state:

Ch12ng. 2 Giao thAc ghp n/i (Interfacing Protocols)

- Giao thAc ghp n/i - <=c 4i5m l.p trnh I/O 2.1. Interface Protocols: K/n: L cc qui )9nh: Signals - Data format - Rate - Error detection & correction - Command & Response set - Scenario (k9ch b$n) ISO 7 layer Model (Ref. Computer networks) C th+ phn chia thnh 2 nhm chnh (Siemens) : Transport-Oriented Protocols (1..4) (!!!) PhysicAL (wire, cable, connector), DataLink (CRC, CS, Token), NetWork (Comm. 2 networks ), Transport (Err-protected raw infor) , Application-Oriented Protocols (5..7) : Session (Opening, End), Presentation (Common Language) v Application (Read/Write, Start/Stop, FileTransfer) 2.1.1. Signals: Khi thi7t k 7, xy d-ng ghp n>i my tnh, cSn ch )1 c bi t t3i tn hi u theo cc yu cSu: bus hay khng? => c dng bit (tr.Eng) )9a ch@, Standard bus? ?: IDE v LPT cable c ph7i l bus? t6i sao? Data: Serial vs Parallel Interface, format? Daisy chain cho t/h ho1c ngu<n c=p... Cc tn hi u )i*u khi+n v tr; ng thi: Control signals Status signals Handshaking signals - bHt tay V dI 1: PC-LPT handshaking:

PC
LPT port

SLCT

SLTC_in
Line Printer

Hnh 2.1.a.LPT handshake Signal Ph.0ng php bi7 n )Ri tn hi u: bin, tSn, pha, dng, quang (cp quang, Ir) V dI 2: PC Comm-Modem handshaking:

RTS

CTS

PC 1

Modem
or PC 2
DTR DSR

Comm
Port

Comm Port

Hnh 2.1.b. CommPort Handshake Signals T/c v.t l c 7a tn hi3u: MM c )i n p: Voltage ? (TTL, 12V/ 24V/48V...) In/Out, Single End vs Differential (vi sai)
Page 9 of 56 Page 10 of 56

MM c dng )i n: (Fan Out, Loading): - Number of Standard TTL/ LS TTL loads, - Sink: dng ch$ y vo LowLevel, mA, - Source: dng ch$ y ra HighLevel, mA/ A. (H. 2.1.c) N>i chung cc tn hi u ra: 3 state, open collector, (Open Drain), Mux - d<n knh, Switch - kha. Hot swap hot plugible: Y/c Vcc v t/h Cch ly (isolation): Relay, Opto Coupler, IrLED... Bus Slot, Connector, chuVn, s> chn (pin)

Hnh 2.3.b. Optical Connector & S4 ,=: S0 )< cch ly quang hBc )/v tn hi u In/Out:

Cable & Connectors: Connectors: D shell: DB9, DB25,... DIN, Cable: Flat, Coaxial, Shield, Twisted Pair Normal Optical Fiber...

Hnh 2.3.c. SGi cp quang: 2.1.2. Format s/ li3u: Z>i v3i file/text: s> li u nhi*u => khi trao )Ri (v3i DAS, PLC, Digi-Oscilloscope, GPS, TelSat...) )ng gi s> li u (packaging). M[i gi tin (packet) g<m 3 phSn: - Header: [c th+ c: tn b$n tin, tn gi, s> thM t-, k t- bHt tay, k t- )<ng b', s> k t-/ byte trong gi tin...], khng mang tin. - Content: n'i dung tin mang thng tin. - Tailer: M bHt tay k7t thc, [m ki+m tra l[i] khng mang tin. V dI: HDC, FDC: Full Sector: gap - 5 byte ID field - 2 byte ID CRC - gap - data field: 512 byte - 2 byte CRC. FTP, Kermit, X-Modem.. Protocols: 128[256] B/pack.

Hnh 2.3.a. Connectors Hnh 2.3.d. USB data packet format Byte s> li u/character/frame: (truy*n khng )<ng b', RS-232, RS-485, RS-422...): k t- hay byte )./c )9nh d; ng thnh 1 frame:
Page 11 of 56 Page 12 of 56

1 start bit = 0, 5/6/7/8 data bit, D0 first, [parity: Even/ Odd], 1 / [1.5 / 2] stop bit = 1(s).

2.1.3. T/c 40 trao 4Di thng tin: Xu=t pht tO: Nhu cSu trao )Ri thng tin cN a T/b ngo; i vi (nhanh nh. LED Board, ADC..), => chBn mi tr.Eng truy*n thch h/p, c lin quan t3i t/h: Xem Bottle-neck? Kho$ng cch - tch s> k/c v t>c )' => Song song (Word/ Byte/ nibble)/ n>i ti7p (bit) Mi tr.Eng, ).Eng truy* n (cp )<ng, quang, wireless (radio, infrared) Synchronous/Asynchronous? Modulation/Demodulation ... => t>c )' bao nhiu kbps/kBps, t>c )' chuVn? V dI: LPT: SPP mode: 50..100kBps - software, ECP: 2..4 MBps - DMA LAN Ethernet IEEE 802.3: 10/100 Mbps dual speed RS232: 2400/ 4800/ 9600/ 19200... bps 2.1.4. Ki5m tra, s Fa lGi, nng cao 40 tin c.y: Khi trao )Ri thng tin th.Eng hay gy ra l[i, )1c bi t truy*n xa/ chuy+n )Ri t/h. Nhi*u ph.0ng php (Hardware, Software) h[ tr / )+ ki+m tra: [Block] check sum - BCC, phSn m*m, CRC, ECC,... vi m;ch/ software - subroutine Parity, 1 ho1c 2 chi*u Redundancy (RAID), thOa dl, trao )Ri n'i dung s> li u h0n 1 lSn v so snh. Case study: Barcode Ph0ng php m ha, gi$ i m v ki.m tra lHi Bar Code: EAN 13, CODE 39 (Intermec), CODE 128 (Zebra), UPC ... EAN 13 (European article numbering) Encoding: AAA BBBBB CCCC D; 4 )' dy v; ch, 6 v; ch/digit (b&w) A(National): VN 893, CN 690-692, JP 45-49, GE 400-440, RU 460-469 B: com/ org C: Product D - Check sum, right most: (right to left): 10 - [(D2*3 + D3*1 + D4*3 + D5*1...+ D13*1)mod10] V dI: 893 12345 1234 7 CODE 128, Zebra, check sum modulo 103 2.1.5. Command & Response (Result/Reaction) set: Intelligent Devices (Computerized devices - mouse, KB, Printer, modem, FDC, HDC, RTU...) c nhi*u tham s>, ch7 )' ho;t )'ng => xy d-ng b' l nh (command set) v thng tin tr $ v* (response set). Dng phSn m*m )+ x6 l => b3t tn hi u. o T?p h/p cc yu cSu tO CS - command set, o T?p h/p cc tr$ lEi, tr;ng thi - result/response/ reaction set. Cc cu l nh v tr $ lEi c syntax ring (c=u trc v ngT php). Case Studies: l nh AT v Response Hayes MODEMs: L nh: ATDT 1260 ' V3i nhi-u Options Tr7 l9i (reaction) OK [Error] . . . Connect @19200 (result) L nh FX Printer: Esc * m, n1, n2; Sel Graph Mode Tham kh$o cc b' l nh cNa cc thi7t b9 chuyn dng: GPS, Gyrocompass, Digital Oscilloscope, SAGEM, TelSat, Programmer (Hi-Lo System All-11P2)... M't command/response th.Eng c c=u trc: o m bHt )Su k t- ring nh @ / # / $/ AT... o m l nh, 1..3 bytes/ char, o tham s> l nh, 1... n bytes, o m ki+m tra l[i check sum, CRC (dX x6 l) o m k7t thc, k t- ring.
Page 13 of 56

C thm cc m (k t-) )>i tho; i/ reaction, [dng] k t- )i*u khi+n cN a ASCII nh. : ENQ, ACK, NACK, Bell, OK, ERR, BUSY ... 2.1.6. K'ch bIn 4/i tho)i Scenario: Li t k cc tr.Eng h/p c th+ r<i p cc php x6 l t.0ng M ng )+ )$m b$o vi c ghp n>i: khng m=t tin, thOa tin, quVn, treo... Th.Eng xy d-ng: Step List ho1c Chart: Time Out ! Master ENQ Slave ACK NAK nothing

Hnh 2.4. Scenario Chart

Hnh 2.5. USB Interlayer Interconnection Model 2.2.1. IO Mapping:

Hnh 2.6. Phn mi-n cc cFng I/O Memory Mapped IOs: o IOs chung v3i Mem trong MemSpace => chi7m vng nh3, t>n vng nh3 o CPU x6 l cc cRng IO b5ng cc l nh nh )/v mem. - IO Mapped IOs: (Z80, x86...):
Page 14 of 56

o Khng chi7m khng gian nh3, o CPU ch@ th-c hi n 2 l nh: IN v OUT x86 CPUs IO map: IO mapped IOs, 16 Addr bit IO => 64Kilo IO locations. - PCs IO map: o IO Mapped IOs, o Ch@ dng 10 lowest addr bit, A0..A9 => 1 kilo IO locations Soi g.0ng 1st kilo Mirrored v3i 63 kilo cn l;i, M[i IO port chi7m nhi*u )9a ch@ (nh PIC, PIT, PPI..) => thi)u IO space. SA dng thm ki.u Mem Mapped IOs. 2.2.2. L3 nh In/Out: (x86) : L nh IN v OUT: ch@ dng cc thanh ghi Accumulator: 8 bit: AL, 16 bit: AX v 32 bit: EAX. Ch7 )' )9a ch@: o Direct: for IO space: 0..0FFh V dI: in al,60h ; Read KB port out 23Eh, ax ; l nh sai, IOaddr>255 out 61h,al ; beep, set/reset key flag o Indirect: for IO space 0..0FFFFh, via dx register V dI: mov dx,378h ; PLT port Addr mov al, A ;41h/ 65d out dx,al ; 'A' ==> Printer mov dx,3F8h ;Comm 1 port in al,dx;

Ch12ng 3. Cc ph12ng php trao 4Di thng tin Polling - ThBm d Interrupt - ngJt & DMA - truy nh.p tr Ec ti#p mem - IO
3.1. Ph12ng php thBm d (polling) K/n Polling: Dng phSn m*m )+ ki+m tra cc cE tr; ng thi @ IO Ports => quy7t )9nh trao )Ri s> li u hay
khng. Nhanh, )0n gi$n, hay dng trong cc h nh ho1c )0n nhi m t thi7t b# IO, Khng ph h/p v3i )a nhi m

L#u $ t%ng qut:

Polling

Device #1 Request ?

Device #1 Service Routine

Device #2 Request ?

Device #2 Service Routine

Device #n Request ?

Device #n Service Routine

Quit

Hnh 3.1. L(u ,= PP IO interface polling 3.2. Ph12ng php ngJt (Interrupt): 3.2.1. Khi ni3m

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Trong m't s> CPU, )+ bCy/ )+ x6 l cc s - ki n trong khi th-c hi n, nh. Intel x86: - Divide by zero: t.0ng Mng th-c hi n l nh, Int 0, - Trap Single Step: th-c hi n tOng l nh, debug- ger, Int 1, dng cng v3i Trap Flag (Trace). - Break Point: t;o )i+m dOng, debugger, Int 3, - Overflow: (trn s> hBc), Int 4. - ... d. Exceptions: L v=n )* hay )i*u ki n )+ CPU dOng cng vi c )ang t/h, tm )9a ch@ v th-c hi n 1 ctc, )./c thi7 t k7 )+ x6 l s- ki n ny. Exception gi>ng Interrupt, th-c hi n l nh ring. Trong PC, Exp khc Intr qua 2 )i+m: - Lin quan t3i vi c th-c hi n ch.0ng trnh, - C .u tin cao )+ dOng ch/tr - V dI: Math Processor Exception (Apple Macintosh Computers): cc Error, thay ,Fi , i-u ki n, k. c7 ng0t, ,(Gc CPU pht hi n trong khi ch(4ng trnh ,ang ho6t ,*ng. 3.2.3. Case study: t D chAc ngJt c7a cc h3 VXL/My tnh a. Intel 8x51 Micro Controllers: HB Intel 8x51 c 6 vectors ngHt: 02 Ext. Interrupts: Int0 v Int1, 03 Timer Interrupts: Timer 0, 1, 2 v 01 Serial port Interrupt (pht/thu char). Mng v3i cc ngH t ny, c cc )9a ch@ )Su cho ISR t.0ng Mng t;i trang zero @ Prog. Memory: 0003, 000Bh, 0013h, 001Bh, 0023h v 002Bh. T;i cc )9a ch@ ny th.Eng )1t l nh LJMP nnnn v )./c )1t l nh RETI n7u khng c ISR.

Hnh 3.2. K/n ng0t Khi CPU ) ang th-c hi n CTC, )7n dng l nh thM n, ngCu nhin, ngo&i vi thM i xin ph(c v( b5ng cch pht ra tn hi u IRQ(i) (Interrupt Request) )7n CPU. Ni chung, CPU s* ngOng x6 l CTC v c= t ngT c$nh vo Stack Mem, r<i tm )#a ch- c/a ctc ph(c v( ngHt t.0ng M ng (Interrupt Service Routine - ISR) )+ th-c hi n. Sau khi th-c hi n xong ISR, g1p l nh iret (reti...), CPU khi ph(c l&i ngT c$ nh c/a CTC v ti7 p t(c th-c hi n. <=c 4i5 m: L ph.0ng php Vo/ra k7t h/p tn hi u v phSn m*m, )+ th-c hi n )a nhi m. Khi ni m ngHt: CTC b9 dOng x6 l )+ gBi ctc L ch7 )' ho;t )'ng ring cho cc Vi x6 l/ my tnh ki+ u ON-LINE, Ngu<n ngHt: chN y7u tO ngo;i vi, CPU (exceptions, internal), X$ y ra ngCu nhin, Nhi*u IOs, ngCu nhin => Tranh ch=p => Gi$i quy7t .u tin ngHt. Ku tin ngJt Interrupt Priority: T/b9 .u tin cao c th+ dOng ISR cNa t/b9 . u tin th=p H l3n, nhi*u IOs th.Eng dng PIC (Intel PIC8259A) Ch@ s> .u tin do nh sx qui )9nh cho cc t/b9 ngo; i vi, c> )9nh, mMc 0 l cao nh=t. Theo hnh trn: Level (j) > Level(i), i>j. \u tin phn )9nh do cc tn hi u ngHt trong CPU (Intel 8085: INTR, 5.5, 6.5, 7.5 v TRAP), Z80 CPU & others: .u tin theo ki+u Daisy Chain 3.2.2. Phn lo)i: G:m: Hardware, software, internal, exception, NMI... a. Software Interrupt: L vi c gBi 1 ctc (Subroutine) )./c xy d-ng ring m ctc ny cn c th+ )./c gBi bWi thi7t b9 ngo; i vi. Cc l nh gBi nh. INT n; (Intel x86) hay SWI n; (Moto). Tuy nhin, vi c th-c hi n l nh ngHt m*m gi>ng nh. gBi thN tIc, v )i khi )/c hi+u l TRAP. NgHt m*m khng ph$ i l ngHt b. Hardware: - Do Ports pht tn hi u NMI/ IRQ )7n CPU. - Chia thnh 2: Maskable (c th. c$m ,(Gc) v Non Maskable (khng c$m ,(Gc) : Maskable Interrupt: l cc ngHt thng th.Eng, c th+ c=m (disable) hay cho php (enable) bWi cc l nh CLI v STI (Intel vs Moto!), so called mask che. Cc ngHt s] b9 c=m - IF disable: sau khi CPU reset, tr .3c ) ) c IRQ khc, sau khi th/h l nh CLI. Non Maskable Interrupt, NMI l ngHt c mMc .u tin cao nh=t, th.Eng cho cc vi c: m=t )i n, sai s> li u (DRAM parity)... PC hi n nay, th.Eng khng dng NMI. c. Internal:
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b. Z80 system: Z80-CPU, 3 modes ngHt: C c l nh ReStart (nh. Intel 8085), NMI v Daisy Chain. Ki+u Daisy Chain: Ghp n>i v3i cc Z80-Ports: Z80-PIO, Z80-SIO, Z80-CTC... IRQs tO cc ports l Open Drain, Khi CPU: M1 & IO Request => INTA )7n port1, N7u Port1 Resq, s* pht m Addr ln data bus, n7u khng Chuy+ n INTA )7n Port 2... \u tin c> )#nh/ jumper. c. x86 & PC interrupt B$ng vector ngH t IVT Interrupt Vector Table Real mode: CPU x86: 1st kilo byte (RAM) b$ ng vector ngHt 1st KB = 256 elements of 4 bytes ChMa )9a ch@ )Su cN a ISR t0ng Mng. Khi khWi t;o, BIOS n; p vo IVT )c) cN a cc ISR M ng v3i IO.
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ZRi vector ngHt: )Ri n'i dung cc vector ny Cc ng0t cJng, NMI v Internal ,-u t(4ng Jng v3i 1 l nh ng0t m -m c cng vector type, tJc c vector trong b7ng IVT.

Load ISR v xc )9nh )9a ch@ v?t l, Enabling IRQi @ PICs, Mask Reg (OCW1): b(i) = 0, Thay vector ngHt, cLn l(u vector cM? Enabling cE IF trong CPU, l nh STI, Set Interrupt Enable Flag, cho php ngHt

Software Interrupt: L nh Int n, n=0..FFh. M t$ l nh: Tr.3c khi th-c hi n l nh, ph$ i c chtr khWi t;o ngHt (Intr house-keeping): )9nh v9 ISR v )Ri vector ngHt, Khi g1p l nh Int n, CPU s] c=t Flag Reg, CS v IP vo Stack mem, (n x 4) => IVT, )Bc 4 byte t.0ng Mng n; p vo IP v CS, ISR bHt )S u )./c th-c hi n. Khi g1p l nh IRET, CPU khi phIc l;i tO Stack Mem IP, CS v Flag Reg (LIFO). Hardware Interrupt, irq: IRQ trong PC: dng 2 PICs - Priority Interrupt Controller Master PIC (20h, 21h), IRQ0..IRQ7 => Int 8..Int 0Fh Slave PIC (a0h,a1h) = IRQ8..IRQ15 => Int 70h..Int 77h

Ho't $*ng: 1. Khi trao )Ri s> li u: Ngo; i vi <=> v3i IO port 2. IO port pht tn hi u IRQ(i) t3i PIC 8259A, 3. PIC pht tn hi u INT => CPU. CPU th-c hi n n>t l nh hi n t;i 4. C=t ngT c$nh main prog. vo stack mem 5. #1 INTA bus cycle => Prioritizing 6. #2 INTA bus cycle => )Bc Vector type cN a IO port, VectorType = i+8. 7. (VectorType x 4) => IVT, )Bc ) c) ISR t.0ng Mng, n; p vo IP&CS, IRS bHt )Su )./c th-c hi n. 8. ISR: (n7u dng ASM) - Realtime Prog. Languages: MASM, C, ... , - Enabling Interrupt for Higher priority Levels, - C=t nhTng thanh ghi-ISR dngvo STACK Mem, - T/h n'i dung ISR, - Khi phIc Reg tO STACK Mem, LIFO, - Depriorotizing: OCW2: V dI: mov al,20h out 20h, al ; Non Specific EOI iret ; Return fron Intr. d. Xy dEng PC ISR: - NN cao Pascal/C: Pointers (for Old Vector) v procedure c ch@ dCn Interrupt. Ch cSn c thm cc l nh STI v CLI ho1c inline m my FAh v FBh (En/Dis). - MASM v OS: thay vector ngH t tr-c ti7p, l nh mov cc con trG vo IVT; int 21h subfunctions: 25h v 35h cNa DOS. - Case Study: Xy d-ng Mng dIng dng ngHt cMng )+ ghp n>i ngo; i vi: IRQ1 (Any key), IRQ4: CommPort, IRQ5 (Option) v IRQ7 (LPT1, Falling Edge of -ACK)... - Th.Eng tr ngHt thEi gian Int 1Ch thu'c Int 8 ISR, Timer 80x86 Interrupt in Protected Mode: Int. Descriptor Table (IDT) c th+ )9nh v9 b= t kK vng nh3 no V9 tr v kch th.3c trong b$ng IDTR: 32bit addr v 16 bit limit Gate, not vector. 256 gate descriptor: trap/ interrupt/ task - ISR's Addr & Attribute Int/ trap cho php chuy+n )7n ISR trong current task.

x86 & pc, Hardware Int Priority Interrupt Conteroller Intel 8259A: 8 Channel (8 I/O ports) \u tin c> )9nh, vng, vng )9nh tr.3c N>i tSng v3i Slave PIC(s), mW r'ng thm IOs Nhi*u ch7 )' ho;t )'ng ICWs & OCWs Dng v3i nhi*u h VXL, IBM-PC ... Tham kh$o VXL cNa MTV x86 & pc, Hardware Int: Hardware Interrupt, IRQ: Ho; t )'ng Hardware Intr trong PC, xem PIC 8259A Interrupt Housekeeping - chuKn b;: files.sys[com], (Vd gmouse.com - cRng comm 1)
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 DMAC#1: 8 bit Channels, 64KB max:, 0h 01fh addr Ch0 - DRAM Refresh, Spare Ch1 - SDLC, LPTs ECP mode - Alt., Spare Ch2 - FDC, single byte mode Ch3 - LPTs ECP mode, Ir port, Spare DMAC #2: 16 bit Channels, 64KW max, 0C0h Ch4 - Cascade for DMAC 1 Ch5 - HDC, spare Ch6 - Spare, Ch7 - Spare Page Registers: 080h..08Fh: Gi a ch cao SysBus in DMA mode, AEN = 1 (AddrEnable)

CLI STI LIDT EA ; Load IDT tN Effct Addr SIDT EA INT n IRET INT O ; ( INT 4) HLT ; Wait for Ext IRQ or Reset WAIT ; Wait for -Busy => inactive 3.3. Direct memory access DMA 3.3.1. Khi ni3m: Controlled by DMAC, bus master In/Out dng hardware [burst mode] => nhanh, 33/66MBps Chuy+n block/ Single byte IO Mem, Mem Mem (t) Specified Block/ IO Requirement Stealing cycle (DRAM controller Intel 8208) DMA House keeping: Addr lines (DMAC & Page Reg) input/ Hi-Z Init: 8bit(Master:0..1F)/ 16bit (Slave:0C0..0DFh) Channel (i): DRQi v -DACKi Port (IO Addr), AEN = 1 (Address decode) IOR-MEMW hay MEMR-IOW Hi Addr of data memory => th/ghi trang t/ Mng. Addr tO Ch0 (hex): 87, 83, 81, 82, 88, 89, 8A, IO space Low Addr => BaseAddrRegi, (TechHelp 6.0) Kch th.3c m$ng: BaseCounteri Single byte/ block Specificed block/ IO Port Requirement IOR-MEMW bus cycle BH t )Su t/h DMA, ngo;i vi chuy+n data => IO Port IO Port pht tn hi u DRQi t3i DMAC. N 7u ch=p nh?n DMAC pht HRQ t3i CPU (CPU logic circuitry) CPU dOng ho; t )'ng @ state T3, Hi Z bus CPU Tr$ lEi t/h HLDA => DMAC & goes to sleep Th-c hi n DMA bus cycle: - (-DACKi = 0 & -IOR = 0) => IO Port 'nh$' sl ln bus - Addr (DMAC & PR) => data mem, -MEMW => chuy+n 1 byte/word TPng CurrentAddrReg, gi$ m CurrentCounter. N 7u CC=0 th pht T/C, n7u <>0 => , next DMA bus cycle

3.3.2. Dmac intel 8237a: MTV 4 Channel of 8/16 bit IOR-MEMW & MEMR-IOW DMA bus cycles Mem to Mem Single byte/ block transfer (64KB/Kw max) \u tin c> )9nh/ vng Specified block (TC) / IO Requirement (EOP) N>i tSng )+ mW r'ng s> knh DMA ... 3.3.3. PCs DMA:
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Ch12ng 4. I/O Interface bus overview

Gi?i thi3u bus chuLn cho ghp n/i, mM r0ng: ISA/ PC-104 AT bus USB (Universal Serial Bus) Philips I2C PCI (Peripheral Component Interconnect) SCSI (Small Computer Systems Interface) GBIB (General Purpose Interface Bus) Siemens Profibus IEEE 1394 ... 4.0. Khi ni3m vC bus: PCB (Printed Cirrciut Board), Cable (Copper/ Optic), Slot, Connector... N>i nhi*u thi7t b9 slave [master], dng chung Nhi*u line (bit) ho1c ) i dy (I2C, USB, SSA, Profi) Thnh phSn (physical lines/ time sharing): Address Data Control/ Status/Handshake ~ [Power supply] 4.1. Industry small architecture (isa) bus: ISA/ AT bus, 1984, IBM, PC-104 bus, Available in Pentium, PowerPC Platforms Z+ ghp thm cc thi7t b9 I/O chuVn vo Mother Board, 3..8 Slots, Hi n t;i cc my c th+ khng dng slot 8/ 16 bit for data transfers 8,33 MHz => 5 MBps max Only 1 BusMaster, CPU ho1c DMAC No data integrity, khng ki+m tra parity, IO Check Dng )+ ghp v3i cc thi7t b9 ch?m, ki+u k t-: character typed devices : keyboard, mouse... Refer AT Technical Reference or TechHelp for detail

Topology Rev.1.1: 23/09/1998 Chia thnh nhi*u Tiers Cc Tiers n>i cc thi7t b9: Hub ho1c chMc nP ng M[i Tier c Hub(s)

4.3. USB: specifications

Hnh 4.1. AT/ ISA/ PC 104 bus 4.2. Universal serial bus - usb:

Ch@ c 1 USB host (USB Controller) trong h Devices, c 2 lo;i: Hub, mW r'ng thm thi7t b9 n>i vo USB Cc thi7t b9 chMc nPng nh ISDN, JoyStick, KB, Printer... Thi7t b9 chu Vn interface USB theo: USB Protocol Chu Vn H) cN a USB: config v reset Communication Standard USB Controller/ Host polls bus & initiates all data transfer Ku 4i5m: Tn hi u vi sai pht/ thu, bBc kim, ch>ng nhiXu CRC Protection )/v data & control fields
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 T- pht hi n attach/ detach, xc )9nh c=u hnh cc thi7t b9 t- )'ng W mMc h th>ng TimeOut )/v tr.Eng h/p m=t gi tin/ gi tin l[i 4.3. USB: Physical interface

1.5 Mbps Low speed mode v 12Mbps (Revision 1.1) Ngu <n c=p +5V, vi metre Power managment Revision 2.0: 480Mb/s

4.4. Philips I2C bus version 2.1. Jan. 2000

Philips, 1992 Ver. 1.0;... 1998 Ver 2.0, 2000: Ver 2.1, dng cho cc h th>ng nhng (embeded systems) Khng cSn dng bus interface chip(s), built-in Integrated addressing & data-transfer, cho php dng phSn m*m )+ )9nh c=u hnh Thm/ b3t IC khng $nh h.Wng bus system Z0n gi$n tm l[i, khoanh vng l[i nhanh Gi$m thi+u kch th3c: 2-wire serial, khng cS n cc m;ch Addr Decoder v glue logic, dng phSn m*m Truy*n )<ng b', 100 kb/s Standard-mode, 400 kb/s Fast-mode, 3.4Mb/s HiSpeed-mode

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Multi byte R/W :Addr auto Inc/ Dec; Master/ Slave :Send A[ck] (=0) hoc /A (NACK) (=1) ty thuc bit tip theo l data hay Stop M0t s/ vi m)ch dng I2 C bus: Dallas RTC 1307, 1308: 64 byte RAM & Real Time Clock, Philips PCF 8593, Low Power Clock/ Calendar Atmel 93C46/24C96... EEROM C th5 n/i nhiCu Masters, trong 1 t/4 chN 01 BMs Active

Start(Rep Start, S) Stop (P):

SCL=1, SDA= SCL=1, SDA=

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4.5. PCI - Peripheral Component Interconnect 5/1993, Intel Ver. 2.0, Open standard, Local bus, trung gian giTa Local v cc bus chuVn khc (ISA, MC, EISA) thng qua PIC Bridge/Controller. C ki+m tra parity cho Addr v Data Auto configuration of all PCI devices, share the same IRQ. Disabling IRQ => c=m ton b' PCI devices. No DMA, device on PCI bus l bus master (T>t cho vi c dng MultiTasking OS). Burst mode: 32 bit @33MHz --> 96..132MBps, tuK thu'c s> byte (tO 32 byte )7n 4KB). Option 64bit @33MHz --> 264MBps, 64bit 66MHz. Most Platforms use:Intel, DEC Alpha, PowerPC, Spark
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 Modern OS: Block Typed Devices: tSn su=t v?n chuy+n cao, nhanh, data block 4.6. Small computer systems interface - SCSI SCSI (SCSI-1): 1990; SCSI-2: 1993 to now; UltraSCSI:... Dng cho Disk controller c b' l nh cNa n, Th.Eng c 1 Adaptor, khng n5m trn motherboard Support any SCSI device: Disk, CD-ROM, tape, scanner 5 to 40 MB/s 7 devices max, upto 15 with SCSI-2 FastWide and UltraSCSI

Hnh 4.15. M6ng Profibus Tn hi u: C lo;i cable )0n v vi sai (ch>ng nhiXu t>t h0n), cc controller support 2 lo;i tn hi u. Khng n>i 2 ki+u trn cng bus. Most: SingleEnd, RS6000 differential. SCSI Common Command Set: )./c g6i tO device driver, ).x/c d9ch bWi th/b9 => Adaptor khng ph$i thay )Ri khi gHn thm thi7t b9 SCSI subsystem g<m: Host adaptor ()+ interface giTa host system v subsystem), SCSI controller, bus, thi7t b9. SCSI Controller & devices: 8.. 16 devices, 1 as Controller. ThM t- u tin cN a cc thi7t b9, cao nh=t l 7 (Controller) 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 8 data bit => 1 parity bit. K/tra Data: ECC, )9a ch@ CRC @ m[i sector 4.7. Siemens process & field bus profi bus 4.8. General purpose interface bus - GPIB As known IEEE 488; HPIB (Hewlette-Parkard Interface Bus), IEC 625 bus Z./c thi7t k 7 )+ k7t n>i m;ng my tnh v3i cc thi7t b9 ngo;i vi, ) o l.Eng - ki+m nghi m, lab... ki+u Program-mable Instrumentation 14 devices c th+ n>i vo GPIB, ...1MB/s, couple meters 24 pin connector: 16 lines: 8 data, 3 handsshake, 5 management ( )+ )i*u khi+n vi c dng bus), remainders: Twisted/ Logic Gnd, Shield Computer as Controller; cc thi7t b9 khc l Talkers/ Listeners. Trg 1 t/): 1 device - Talker, Others Listeners Z+ n>i m;ng:GPIB Card,cable,connector(Hnh 4-16/17/18)

Gi?i thi3u: Mi tr1Png cng nghi3p, ChuVn EN 50170-1-2 K7t n>i nhTng thi7t b9 vo ra phn tn, thng minh (PLCs, Motor drivers, ), 1 trong nhTng layers cNa m;ng CN: SINEC-L2 Bao g :m cc giao thAc: PROFIBUS DP (Distributed I/O):trao )Ri sl v3i cc slaves qui m nhG, )9nh k K, t>c )' cao Profibus PA: Process Automation: IEC 61158-2: mi tr.Eng khHc nghi t. S> li u v power chung line (PLC), 31.25 kbps PROFIBUS FMS (Fieldbus Message Specification): K7t n>i PC v3i cc thi7t b9 t- )'ng cN a Siemems: S7/M7/C7 Families ki+u cell S> li u c c=u trc, khng phI thu'c vo ).Eng truy*n.PROFIBUS F PROFIBUS FDL (Fieldbus Data Link): t12ng thch v?i cc m)ng con Spec.: Token bus: cho nhi*u masters (active nodes) Master - Slaves >1km (RS-485) v 9.6km (Optical Fiber) M ha Manchester II )' tin c?y v ch>ng nhiXu t>t

Hnh 4.16. M*t s> PC's GPIB interface cards

Hnh 4.17. GPIB connector & signals

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Ch12ng 5. Digital interface

PARALLEL IN/OUT PORTS: principle, PPI, Centronics PCMCIA, Dual ported Ram INTERCACING to devices: LED, LCD, encoder, STEP motor, ... HI-POWER INTERFACE: relay, scr, triac, power mosfet, igbt... SERIAL IN/OUT: Sync, async, RS-232, RS-485, RS-422 modem...

Hnh 4.18. IEEE-488 Instrumentation & connector 4.9. IEEE 1394 - Firewire IEEE 1394 serial bus, 1997, by Apple & TI, thay th7 SCSI Upto 63 nodes (devices) connect to a PC, hot plugible High speed: 60 to 400 Mb/s (7.5 to 50 MB/s) Cable: 6 wire (2- power carier lines 8..40Vdc/ 1.5A), 15'. Daisy chain extending to over 200' P1394 - PCI bus <=> Audio, Video devices, CD, disk, printer... Tree topology: 63...64k nodes (bridge across buses) Addressing single node, broadcasting all nodes, config time < 400 us More than one PC can be connected to P1394 bus

5.1. Parallel interface: 5.1.1. Nguyn l Output Port: latched Output (ch>t ra), D_Flip-Flops Unlatched Input, hnh 5.1. single

CRng ra )0n gi$ n: dng ch>t 74 HC 374, (hnh 5.2) Ngo; i vi )Bc s> li u => pht tn hi u strobe=0 Hnh 4.19. S4 ,= ghp n>i cc ngo6i vi qua IEEE 1394 bus

Out Port: 74 HC 374: CPU pht )9a ch@ ra IO space => c t/h CS Pht data v -IOW => c t/h LE = (Rising Edge) => data )./c ch>t vo HC374 Port song song c tn hi u bHt tay/ tr;ng thi (outport): G6i 1 packet ra ngo;i vi, )<ng b' giTa 2 pha IO device ch@ )Bc c Rng khi ) c s> li u (IBF) CsS ch@ g6i s> li u ra khi byte/char tr.3c ) )./c )Bc bWi IO device (OBE) Ch Time-Out-Error

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 Data Out port, X78h, TTL, (some bi-dir, In when 1s out!) Open Coll. Buffer - 8 bit latched out, back readable LPT: send control & printed chars to Printer Control Out Port: X7Ah, TTL 4 bit latched out, back readable LPT: -Strobe (b0), AutoFeed (b1), -Init (b2), SLCT(b3) IRQ_EN (b4), not outlet Status In, X79h, Unlatched, TTL 5 bit: b3..b7: Err, SLCT_IN, PE, -Ack, busy

5.1.2. Programmable ports Ports: Intel PPI 8255 (Programmable Peripheral Interface) Motorola PIA 6821 (Progr. Interface Adaptor) Z80 PIO (Parallel In/Out) ... Flexible Specifics: 2..4 In/ Out Ports, single line direction (PIA/ PIO) Mode: IN/OUT w [w/o] handshake, bus transceiver Control/ status/ HSK: Edge (, )/ Level (hi, lo) Case study PPI 8255: 4 ports: PA, PB, PCH & PCL, 24 IO lines 3 modes: M0, M1 & M2 Z0n gi$n v hi u qu $

Enable Int Req:

mov dx, 37Ah; LPT 1 control in al, dx or al, 00010000b out dx, al ;

Disable:
Port[BA+2]:=Port[BA+2] and $EF; Mode 1: enhanced parallel port - EPP Xircom, 1992, Hi speed - 2 MB/s (1 ISA bus cycle), bi-directional port, Ext HDD, Network... 8 Registers: Offset 0: SPP data , R/W data lines, w/o HSK Offset 1: SPP status, Read (b3..b7), b0 timeout Offset 2: SPP control, R/W 4bit C0..C3, C4: IRQ En, C5: byte dir Offset 3: EPP addr, R/W addr cycle w HSK Offset 4: EPP data, R/W data cycle w HSK Others: may be use for 16/32, port config, user define Mode 2: extended capabilities port - ECP MS-HP, 1993, 2..5 MB/s (1 ISA bus cycle), bi directional port, Ext HDD, Network... extension sys bus 16 FIFO byte buffer )+ g6i/ nh?n, DMA: Mem <=> buffer C th+ ghp n>i v3i cc ngo; i vi ch?m khi dng Rdy M phGng h) cNa SPP, EPP mode R/W: data & commands: OUT -C1 (HostAck); IN -S7 (Per. Ack). -C1/ -S7 = 1 (sending data); 0 (command) Command: b7=1, b0..6: channel addr, b7=0, b0..6 run-length count for data compression mode ()7m cc byte gi>ng nhau - graphics, hardware) OUT -C1 (HostAck); IN -S7 (Per. Ack).
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Hnh 5.3a. Ghp n>i PPI 8255 v3i PC qua ISA bus 5.1.3. Centronics port Centronics Computer Inc. so called LPT, 2 LPT ports (available) in PC Modes: SPP, EPP, ECP & IEEE 1284 (EPP+ECP) IRQ (7/ 5) & DRQ (1/ 3) support for many applications of Interface: Printer Local Area Network Ext. HDD Test Digi In/Out, ADC, DAC interface Programmers (All 11P2) Mode 0: Simple Parallel Port - SPP (Normal mode) 50..100kB/s, cable: 10' max - 25/ 36 lines

 -C1/ -S7 = 1 (sending data); 0 (command) Command: b7=1, b0..6: channel addr, b7=0, b0..6 run-length count for data compression mode ()7m cc byte gi>ng nhau - graphics) Many chip (SMC's super IO...) h[ tr/ decompress, phS n m*m g6i ra ph$ i 'compress' 6 registers: 3 SPP reg v 3 ECP reg Base addr + 400h: data FIFO & config A-Read only Base addr + 401h: Config B (interrupt, DMA...) Base addr + 402h: Extended Control Register Mode 2: ieee 1284 ( epp + ECP ), 1994, 5 MB/s IEEE 1284 standard - document: defines/ describes protocols for Parallel-port Communication. Include: 1284 port/ 1284 cable/ 1284 Peri. 5 communication modes: (Register use - Table 11-1 p206, Parallel Port Complete) Compatibility Mode: Host sends a byte to Peri. (with Busy v -Ack) Nibble Mode: Peri. to Host 4 bit, remainder - HSK Byte Mode: 8 bit, bi-dir EPP Mode: 8 bit, bi-dir, hi-speed ECP Mode: 8 bit, bi-dir: data, addr, compression 5.1.4. Dual ported ram Z+ chuy+n m$ ng s> li u giTa 2 h VXL (Master-Slave) v3i t>c )' cao, gSn, ... (Switching Systems, PLCs, Graphics Accelerator...) SRAM, dung l./ng tO 1KB )7n 256KB Multiple Reads & Writes )<ng thEi Dng cc tn hi u: 2 x n bit Addr for 2 sides: Left - Right => 2n mem loc. 2 x 8 [16] bit of Data Cc tn hi u )i*u khi+n (RD, WR, CS) v tr ;ng thi Cc tn hi u bHt tay/ trBng ti Hng: Integrated Device Technology Inc. & Others; chip IDT 7707, 32Kbyte DPR

Ki7n trc phn nhi* u tSng )+ )$m b$o tnh v?n hnh )'c l?p v3i phSn cMng: Socket service: Device driver - system manufacturer Card service: Device driver - Operating System Vendor Client Drivers/ Client Enablers, Driver t;o cc y/c t3i h th>ng: do hng ch7 t;o Card c=p Enablers/ Point Enablers: Driver chuyn )+ thng tin tr -c ti7p Host Adaptor PC Card Standard - CardBus: 32 bit transfer Based PCI specification 33MHz/ 132 MB/s BusMasster support Compatible w 16 bit card

LED - Light Emitting Diode Bao g:m: Point, 7(16) segment, matrix: text/ graphics Drive: Static/ Dynamic Scan Dng Latch/ PIO H5.6 Static Display H5.7: scan 8 x Com-mon Cathode 7 seg LEDs

5.1.5. PCMCIA Personal computer memory card international Association, Ver 2.1; pc card standard (5.0) 1996 L chuVn cNa nhi*u tR chMc/ cng ty: >500 members PC card device - credit card size adaptor: nhG, dX mang, hot plugability, tin c ?y khi mi tr.Eng thay )Ri, 68 pin connector Devices: Flash, SRAM, modem, LAN (wire & wireless), disk, audio w DSP, GPS... 16 bit data path (PCMCIA 2.1/ PC Card Standard 5.0) 3.3 and/or 5 V Dng v3i nhi*u lo;i bus

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5.1.6. Led interface drive 8 x 7 Segment Common Cathode: disbuf: 8 byte chMa m 7 seg cSn hi n th9, N: counter Main Program: Burn LEDs, g<m (1) Init: turnoff LEDs; N=0; (2) (disbuf+N) => 1st Latch; turn On LED[N]; delay(1); (3) Turnoff LED[N]; Inc N ; If N = 8 then N=0; (4) Goto(2) drive 8 x 8 matrix char box: disbuf: 8 byte chAa font Main Program: Burn LEDs 1. Init: turnoff rows; n=0; 2. (disbuf+n) => LS164; shift afap; turn on row[n]; delay(1-1.5); 3. turnoff row[n]; Inc n ; If n = 8 then n=0; (4) Goto(2) Smooth shift left/ right? Color: 4/ 256 color LED duty cycle!

Hnh 5.10a. Text LCD Pannel

Hnh 5.10b. C$u trc cCa Graphics LCD Panel

Hnh 5.10c. Tn hi u v gi7n ,= th9i gian ghi LCD panel 5.1.6. LCD panel interface Cng ngh LCD, hi n text/ graphics Z' phn d$ i: 1 line x 16 character box 2 line x 16 character box 4 line x 20 character box (64 x 128) ho1c (128 x 256) dot... font down loadable ASCII... upto 128 characters/ set APA: All Points Addressable Back lit, cng su=t tiu thI nhG Dng cho cc h nhG, mang xch, my )o...
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5.1.7. Encoder

Dng )+ ghp n>i ) o l.Eng d9ch chuy+n c0 hBc: chi*u di, v?n t>c, gia t>c, t>c )' quay, )9nh v9, robot Cng ngh v?t li u tO - nam chm vYnh c6u ho1c quang - h<ng ngo;i/ laser, hi resolution ADC... Z' phn ly cao: 256 ... to 500 kc/t (counts/turn), ch9u shock (100G) T>c )' cao 10krpm, m men c$n nhG (vi 10-3 Nm) Output: cc xung l ch 90O ho1c RS 485 (byte, BCD, GrayCode formatted), truy*n xa 1 km
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 Manufacturers: Tamagawa Seiki, Hewlett-Packard...

Thyristor (SCR - Silicon Controlled Rectifier)

Hnh 5.12a. Step Motor

Hnh 5.12b. Symbolic Diagram of Step Motor

Hnh 5.12d. Cc s4 ,= n>i dy cho step motor 5.1.8. Hi power interface L cc m;ch ghp n>i my tnh/ VXL v3i cc thi7t b9 c )i n th7 cao/ dng )i n l3n nh. l nung [s=y] )i n tr W, l cao tSn, motor (ac v dc) cng su=t l3n... Zi*u khi+n thi7t b9 )i n xoay chi*u (ac): Relay, [r 0 le trung gian] hnh 5.13a: Dng Relay )+ cch ly [v relay trung gian], Zi*u khi+n cng su=t ON-OFF (l ) i n, motor) Triac, Solid State Relay hnh 5.13b: Zi*u ch@nh cng su=t v c =p ZX gy nhiX u cho l.3i )i n, ph$i c Line Filter Zi*u khi+n thi7t b9 m't chi* u (dc): Hnh 5.14.
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5.2. Serial in/out: 5.2.1. Khi ni3m Thng tin trong H VXL/ My tnh: byte Khi truy*n 'xa': byte => dy bit, serialize; dy bit => byte, deserialize: gi$m thi7t b9 thu pht v ).Eng truy*n, gi$m chi ph, t>c )' ch?m, M hnh: Hnh 5.11. Central System: CPU, mem, controllers, sys bus... Serial port: Symbols: UART/USART (Universal [Synchronous] Asynchronous Receiver Transmitter) SIO:Serial In/Out Port ACIA: Async. Communication Interface Adapter , MC 6850

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Hnh 5.21d. QAM:Quaternary Amplitude Modulation

Serial ports: Nhi m vI : Bi7n )Ri byte <=> dy bt + cc bit khng mang tin (start/ stop/ parity...) v dy bt <=> byte, lo;i cc bit khng mang tin, bo l[i khi thu. Ghp n>i v3i h trung tm: cc bus/ tn hi u addr, data, control b5 ng ph.0ng php Polling, Interrupt ho1c DMA. Ghp n>i v3i ).Eng truy*n [via modem]: TxD, RxD Ghp n>i modem: -RTS, -CTS, -DSR, -DTR, -CD, -RI V dI: UART 8250, 16450, 16550A (Intel, NS...), USART 8251 Intel, ACIA 6850 Moto. MODEM: l thi7t b9 bi7n )Ri tnh hi u logic TTL (0/1) thnh cc tn hi u v?t l, ph h/p v3i mi tr .Eng truy*n xa v ng./c l;i, g<m: Converter/ driver: Max 232/ ICL 232 (232 modem): TTL <=> RS-232, Single End: -3V .. -15 V <=> '1' +3V .. +15 V <=> '0' Z0n gi$n, 100' @ 9600 bps, dX b9 nhiXu Th.Eng dng )+ ghp n>i cc thi7t b9 thng minh trong CN (gSn), th nghi m, )o l.Eng, )i*u khi+n Maxim 485/ SN 75 116... (485/422 modem): Differential V(a) - V(b) > 100 mV <=> '1' v V(a) - V(b) < -100 mV <=> '0' 5000' @ 1Mbps, th-c t7 c th+ truy*n xa vi km. Th.Eng dng trong cc x nghi p cng nghi p Current Sourcer: 0 v 20 mA [ho1c 20 v 60 mA] Ch9u nhiXu t>t Truy*n xa, ty thu'c )i n trW R ).Eng dy, Th.Eng c cch ly quang hBc. Hnh 5.21a. ASK: Amplitude Shift Keying

Khi ni m truy*n tin )<ng b' v khng )<ng b': Thng tin th.Eng )./c )ng gi thnh cc gi tin. Z<ng b': Trong 1 packet: byte byte, bit bit, khng c d=u hi u phn cch. T>c )' truy*n do sender: clock (cng v3i data) ho1c ch@ xu=t hi n vo thEi )i+m )Su trong gi tin (sync. character). T>c )' cao, kh, t^ l cc bit khng mang tin nhG. Truy*n tin khng )<ng b': Asynchronous Comm. M[i k t-/byte )*u c 1 xung/s.En )<ng b' (s.En xu>ng cN a start). Clock cNa 2 pha thu v pht c th+ l ch nhau 3-5%: V dI: @ format 8,n,1; T: time of frame; t: time of bit, T )' l ch cho php Tpht v Tthu. T < 1/2 t = 5%T. C kho$ng 'tr >ng' giT a 2 characters, tr ;ng thi 1 - mark. T^ l cc bit khng mang tin l3n (start, stop, parity), ln )7n 33% (v dI 8,PE,2) Z0n gi$n, dX l?p trnh, dX ghp n>i. Z1c bi t )./c ch=p nh?n r 'ng ri: thi7t b9 ngo;i vi thng minh, )o l.Eng )i*u khi+n, modem...

Hnh 5.21b. FSK: Frequency Shift Keying

Hnh 5.22.Ba m hnh ,9ng truy-n: Simplex (a), Half duplex (b) v [full] duplex (c) DTMF: Dual Tone Multi Frequency, ) a tS n, Mitel8880 Hnh 5.21c. PSK: Phase Shift Keying 5.2.2. ChuLn RS-232c/v24 EIA 1969, Electronics Industry Association, cho truy*n tin khng )<ng b' v truy*n qua m;ng ) i n tho;i. Nhi*u nh./c ) i+m so v3i cc chuVn khc: t>c )' ch?m, kho$ng cch gSn, single end signal - dX nhiXu, l./ng bt khng mang tin l3n... nh. ng...

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 R=t thng dIng, c trong nhi*u cc thi7t b9 my tnh, my )i* u khi+n, my ) o ... v cc vi )i*u khi+n, GPS, Gyro Compass, PLC, Switching System... L c6a ng trao )Ri thng tin giTa cc h VXL khng cng chuVn (s> bit, b' l nh, t>c )'...) 5.2.2.1. FORMAT of FRAME: 1 start bit = 0, 5/ 6/ 7/ 8 data bit, D0 - first, [Parity bit - PE/ PO], 1/ 1,5/ 2 stop bit = 1s

Hnh 5.23. C$u trc RS-232 Frame trn ,(9ng truy-n 5.2.2.2. M hnh v cc tn hi3u:

Cc tn hi u truy*n tin: TxD - Transmit Data: Serial data out + bit khng mang tin RxD - Receive Data: Serial data in + bit khng mang tin Signal Ground: 0 Volt. Reference for Single End Signals (Null modem protocols, X-On & X-Off) Modem handshaking signals (Low active): -RTS - Request To Send, Out - DTE -CTS - Clear To Send, In -DTR - Data Terminal Ready, Out -DSR - Data Set Ready, In Line status: -RI - Ring Indication, In -[D]CD - [data] Carrier Detect, In 5.2.2.3. MAc tn hi3u: Cc tn hi3u RS232 c mAc p: -3V .. -15V => mMc logic 1, mark, so v3i Gnd +3V .. +15V => mMc logic 0, space Cc vi m)ch dng 45 bi#n 4Di: Motorola MC-1488 (TTL to 232) v MC-1489 (232 to TTL), 3 ngu <n c=p :+5V, +12V, -12V MAX 232 - ICL 232: l RS232 'modem' ; Single Power Supply +5V. Bn trong c cc b' )Ri ngu<n: Doubler v Inverter => +10V v -10V, Hnh 5.25

Hnh 5.25. MAXIM 232 IC, DC/DC converter 5.2.2.4. T/c 40 truyCn tin: Z0n v9 tnh l bps (bit per second) Cc t>c )' RS-232 : 50, 75, 110, 150, 300, 600, 1.200, 2.400, 4.800 v 9.600 Thm: 19.200, 38.400, 57.600 v 115.200, Dng quartz 1.8432 MHz 16 chu kK clock => truy* n )/c 1 bit Th.Eng trong cc cRng truy*n tin, t>c )' )./c tnh theo: 1.8432 x 106 (Hz) Baud rate (bps) = ----------------------------16 (m x 256 + n) v3i n : low divisor, trong ) m: hi divisor, V dI: 9600bps => m=0, n=12 5.2.2.5. KhoIng cch : Ty thu'c nhi*u mi tr.Eng, cp truy*n, nh.ng: @ 9600 bps, L < 100' @ 19.200 bps, L<50' 5.2.2.6. Connector: D shell 9 ho1c 25 pin [DB9 ho1c DB25] connector 5.2.3. PC RS-232 ports So called: RS 232C/ EIA Communication port Asynchronous [Async] port Serial port UART / Intel 8250, UART National Semiconductor 16450, 16550, 16550A Properties: Port Comm1 Comm2 Comm3 Comm4 BaseAddr 3F8h 2F8h 3E8h 2E8h IRQ 4 3 Option Option UART Intel 8250 , KT VXL - MTV CS interface: 8bit data, IRQ (for Trans, Rec, Modem & Errors), -CS, -RD, -WR v Reg Select lines. Modem Interface: -RTS, -CTS, -DTR, -DSR, -CD v -RI Control Registers (Line & Modem): )+ )9nh format v ch7 )' ho; t )'ng. Divisor Latches: )9nh t>c )' truy*n (thu v pht) Status Registers (Line & Modem) )Bc tr;ng thi, Errors )+ ho; t )'ng polling v Int. UART NS 16550A: FIFO buffers for Rec v Trans 16 byte, Ho; t )'ng: polling, interrupt [c thm] DMA
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 Tham kh$o UART 16550A @ site: www.ns.com Ho )t 40ng c7a comm port Setting: ChBn cRng/ format/ t>c )'/ mode Selecting Port: BaseAddr:= Comm2; {$2F8} Format of character: (Line Control Register - BA+3) VdI 9600, 8, N, 1: Port[BaseAddr+3]:= 3; {$2FB} Baud rate: Access: DLAB bit @ LCR, Low Div v Hi Div. Khi setting baudrate, DLAB=1, otherwise=0 Port[BaseAddr+3] := Port[BaseAddr+3] or $80; Port[BaseAddr+0] := 12; {Low divisor} Port[BaseAddr+1] := 0; { Hi divisor } Port[BaseAddr+3] := Port[BaseAddr+3] and $7F; Mode: Interrupt/ DMA? Ho )t 40ng Transmitting: Line Status Register LSR, BA+5 Sending 1 char: Port[BA+0]:= char_send; Sending 1 packet n byte. bit 5 (of LSR) = 1 => THRE (Trans Hold Reg Empty): For i:= 1 to n do Begin Repeat Until Port[BA+5] and $20 = $20; Port[BA+0]:= char[i] End; {khng cLn ki.m tra TimeOut hoEc lHi} G6i 1 packet dng Int?. Ho )t 40ng Receiving Line Status Register LSR, BA+5, cc bit/ c E TT: b0 = 1 => data received, =0 khi CPU )Bc Receice Buffer b1 = 1 => OE, OverrunErr b2 = 1 => ParityErr b3 = 1 => FramingErr b4 = 1 => BreakInt V ch TimeOut ThN tIc thu 1 packet )./c m t$ Hnh 5.26:

b3 : MODEM IRQ Interrupt Identification Register: BA+2, ZBc Reg ny )+ bi7t ngu<n ngHt, c 4 mH c .u tin c> )9nh, dng b1 v b2: xxxxx11x Highest Prio., 1 of 4 l[i thu xxxxx10x Thu xong 1 char/ byte xxxxx01x Pht xong 1 char/ byte xxxxx00x ho1c cNa 1 of 4 modem HSK. 5.2.4. Hayes modems Do Cng ty Hayes Microcomputer Product Inc. gi3i thi u vo )Su 80s, t>c )' 300...2400bps, over telephone line C b' l nh (command set) v tr$ lEi (response set), )./c dng nh. cc l nh chu Vn AT (standard modem). Tn hi u: TxD, RxD, Gnd, CD, RI. [Thm] DTR-DSR, [RTS-CTS] Ch7 )' ho;t )'ng: Command v data (online) Modes Command Mode: modem nh?n l nh tO my tnh ho1c CS qua RS-232 port v th-c hi n - khng truy*n tin. Khi thi7t l?p xong k7t n>i v3i remote modem => Online mode (data mode) v ch@ truy*n tin.

Hnh 5.26. L(u ,= Thu 1 packet qua Comm Port - Polling INTERRUPT SETTING IRQ 4 - Comm1, IRQ3 - Comm2. Enable Interrupt Register - IER, BA+1, 4 lowest bit. b0 : Thu xong 1 byte/ char b1 : Pht xong 1 byte/ char b2 : 1 of 4 Errors of Receive Action

b(i) = 1 => Enable; b(i) = 0 => Disable.

Hnh 5.27. Block diagram of Hayes Compatible Data-Fax Modem Chuy+n tO O sang C mode: Khi m=t sng mang (remote modem has hungup) trW v* command mode khng disconnecting )+ )/i Guard time (default 1s) Escape command +++ L nh g6i tO my tnh: software ho1c g tr-c ti7p tO bn phm qua RS-232 port Cc k t- trong cu l nh g6i ra theo 1 trong 2 formats: 7,PE,1 ho1c 8,N,1 Khi truy*n 110 bps => 2 stop bit Khi nh? n command, modem g6i v* result code. Option: Digit code - for controlling modem by software Word code - for controlling modem by keyboard result codes: DIGIT Word Meaning 0 OK Cmmnd executed 1 CONNECT Connect @ 0..300bps 2 RING ring signal detected 3 NO CARRIER 4 ERROR error in cmmnd line 5 CONNECT 1200 6 NO DIALTONE
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7 8 10

BUSY NO ANSWER CONNECT 2400

Ch12ng 6. Analog interfacing

In this Chapter: Analog Signal Interface Overview Analog Electronics Digital to Analog Converters Analog to Digital Converters DAS - SCADA - DCS 6.1. Analog signal interface overview: L hm cNa 1 (ho1c nhi*u) bi7n )'c l?p, );i l./ng v?t l theo thEi gian: nh. ti7ng ni, nhi t )'... theo thEi gian: A=f(t,h) Xu =t hi n lin tIc trong kho$ng thEi gian t0 - t1 Gi tr9 bi7 n thin lin tIc trong kho$ ng bin )' tO A0 )7n A1 , c th+ )a tr9.

AT COMMAND SET Cc l nh bHt )Su b5ng AT or at (not At or aT) )+ modem nh?n d;ng t>c )' v format (ngo;i trO 2 l nh '+++' v A/) v k7t thc: Enter Command line: c th+ c h0n 1 l nh, ch@ cSn 1st c AT, cch nhau d=u ' ' khng qu 40 char/cmmnd line. Cc l nh v Option ATDT 8692463 dial using touch tone ATDP 8696125 pulse ATT/ ATP default tone/ pulse O end of C line, return O mode ; end of C line, stay C mode after executing @ wait for 5s ho1c silent V dI: ATDT 9,3456789 K7t n>i tO my trong tRng ) i ATXn Hayes Smartmodem compatible Other Commands: ATE0/ 1 Disable/ Enable echo +++ Esc Char switch to command mode ATHn 0:On-Hook (hangup),1: Off-Hook ATLn 0/1/2/3 volume of speaker ATMn 0: speaker off, 1: on until DCD, 2: on ATNn 0: connect @ DTE rate, 1: auto rate negot. ATO return to O mode ATQn 0: result code En, 1: result code Dis ATVn 0: digit, 1: word ATZ hangup, reset to default settings A/ Repeat last command (re dial) Cc modem )*u c b' l nh ring, Ref. User's Guide Man.

Trong th-c t7: Trong My tnh s>, thng tin: REi r;c v* thEi gian REi r;c v* gi tr9 => )+ my tnh thu th?p, c Sn ph$i 'rEi r;c ha' cc tn hi u v* thEi gian v gi tr 9, dng thi7t b9 chuy+n )Ri ADC, )+: X6 l, c=t vo kho s> li u Truy*n g6i ) i xa Ti t;o l;i hay tRng h/p tn hi u: dng thi7t b9 DAC

Hnh 6.02a. M hnh ghp n>i tn hi u analog

Hnh 6.02-b. M hnh H Oo l(9ng - Oi-u khi.n s> 6.2. Analog electronics: Operational Amplifiers - OpAmps
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 Analog Switches & Analog Multiplexers Reference Voltage Sources Sample & Hold Conversion Errors ... 6.2.1. Opamp L vi m;ch khu7ch );i, n>i galvanic, x6 l t/h tO 0Hz. Tn hi u g<m: 2 chn tn hi u Inv. Inp v Non Inv. Input Chn Output Ngu<n c=p: +Vcc, -Vcc( Gnd) Ch@nh Offset. C th+ c thm chn n>i tI b tSn s>

Hnh 6.05a. Analog Comparator

Hnh 6.05b

Hnh 6.05c

Hnh 6.05d

H603. Operational Amplifier (OpAmp) <=c 4i5 m opamp X6 l tn hi u dc (0 Hz up) H s> khu7ch );i l3n, tO kilo... Mega... and even more... (GBW - Gain - band width Product, unit @ MHz) TrW vo l3n vi k )7n 1012 , tr W ra nhG, 10s )7n 100s, t>t cho cc m;ch ghp n>i analog, ph>i h/p tr W khng.

Hnh 6.05e

Hnh 6.05f

Hnh 6.04. Thi)t b; 2 'cDa' Ngu<n c=p d$i r'ng, 1 ho1c 2 d=u: 3Vdc to 18Vdc Khu7ch Vi sai (Differential Amplifier), lo;i trO nhiXu t>t => CMRR (Common Mode Rejection Ratio h s> kh6 nhiXu )<ng pha l3n) up to 120dB Band width/ Slew rate: BP ng thng/ T>c )' tPng )i n p t>i ) a pha Output khi c6a vo c b.3c nh$y )0n v9 UOffset: Khi c6a vo =0 m c6a ra khc 0. Zi n p tri theo thEi gian v nhi t )' => ch@nh Uoffset/ bias current ICs: Linear Monolithic: A741 (Fair Child), LM124s...(NS) Linear FET: TL 081/ 082/ 084 (TI), LF356/357/347..(NS) Linear Hybrid:LH0024/ 0032 (NS-Hi Slewrate) Instrumentation OpAmp: LM725/ LH0036/ 0038/ 0084 (NS)

Hnh 6.05g. Instrumentation Ampl.

Hnh 6.05h

Hnh 6.05i

Hnh 6.05j

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Hnh 6.05k

Hnh 6.05l. M6ch lEp l6i tn hi u

Hnh 6.05n. I/ U Converter - ghp n>i DAC out 6.2.2. Analog switches & multiplexers: a. Switches Dng c1p transistor FET b knh p v knh n => dCn dng AC R(on) tO 100 .. 1.5 k Off channel Leakage Current: 100 pA .. 1 nA => Khng dng )+ kha tn hi u p qu th=p Bin )' tn hi u: Vss<Us<Vdd TSn s> ON/OFF : ..GHz ICs: CD 4052/ 53, LF11331

TSn s> tn hi u : ... MHzGHz Dng )i n nhG, c_ A => th.Eng dng m;ch follower )+ lo;i trO Ron ICs: CD 4051, 74HC4051 (TI), DG508A, 509A (Maxim) 6.2.3. Voltage reference - Uref L cc vi m; ch (super zener) t;o ra cc )i n p c )' Rn )9nh cao theo thEi gian v theo nhi t )' mi trEng Gi tr9 )i n p theo th?p phn (5/ 10,00Vdc) hay nh9 phn (5,12/ 10,24Vdc) H s> tri: 3..5 ppm/OC Cng thMc chuy+n )Ri A/D v D/A n bit: bn-12n-1 + bn-22 n-2 + ... + b12 1+b020 Uanalog = ----------------------------------------------------------- Uref (") 2n Cc vi m; ch: LH0070, LM199s (NS) 6.2.4. Sample & Hold (trch mRu & giS) Dng )+ trch mCu cNa tn hi u vo thEi )i+m c xung Sample v giT nguyn gi tr9 ) trong kho$ng thEi gian lu h0n. Dng trong cc h thu th?p s> li u khi t>c )' bi7n thin tn hi u cao (t0ng )>i) v3i thEi gian ADC chuy+n )Ri Thu h`p c6a sR b=t )9nh cNa ADC - do thEi gian chuy+n )Ri di (tens s - ms) thnh c6a sR b=t )9nh cNa S&H (tens ns.. s) => nng cao )' chnh xc chuy+ n )Ri A/D v nng cao tSn s> tn hi u. ThEi gian trch mCu: vi chIc ns )7n vi s TI giT (Chold): dng tI c dng r r=t nhG T>c )' sI t p: mV/s, tuK thu'c tI Guard Ring: ka thu?t ch7 t; o m; ch gi$m thi+u dng r

Hnh 6.06. Symbol of Analog SPDT switch Hnh 6.08. Synbolic Sample & Hold ICs: LF189s (NS); AD585 (Analog Device Inc.)

Hnh 6.07. Functional Block Diagram Analog MUX 6.2.2. Analog switch & multiplexer: b.MUX 2n switches n>i chung 1 c-c n bit chBn knh => 2 n knh, 1 trong s> 2 n knh )./c chBn trong 1 thEi ) i+m. ChMc nPng MUX v DeMUX C tn hi u Inhibit - c =m t=t c$ cc knh Bin )' tn hi u: Vss <U(s) < Vdd , Ch hi n t./ng 'xuyn knh' (Cross-talk)
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Hnh 6.09. Bi.u ,= chuy.n ,Fi tn hi u w/o [w] S&H C tn hi u u(t). Z9nh: )i+m t1 => mCu A1; t2 => mCu A2... khi khi phIc l;i s] )./c ).Eng cong gSn )ng v3i ).Eng ban )Su, ty thu'c vo )' dSy cNa mCu. Th-c t7: t1 => start ADC, t1+ c tn hi u EOC => mCu thu )./c A*1 t2 => start ... mCu A*2 ... khi khi phIc )/c ).Eng cong khc. T>c )' tn hi u bi7n thin cng l3n => sai s> Dng S&H:
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t1=> sample - start ADC, t2 => sample - start ADC...

Hnh 6.10. Tnh tLn s> hnh sin v3i DAC 574 Case study: u(t)= 5+5*sin(t+ ) (V). ADC 12bit, 35 s converssion time, U(ref) = 10,24V. Sai s> l./ng t6 = 1/2 ULSB . HGi tSn s> tn hi u max - khng sai trong 2 tr.Eng h/p w - w/o S&H. Sample time=100ns 6.2.5. Cc sai s/ chuy5n 4Di Sai s> l./ng t6: Sai s> c 'ng tnh - zero => chi7t p/ software, first Sai s> nhn tnh - gain => chi7t p/ software Ngu <n chuVn Uref Cc m; ch khu7ch )a9, span, Full scale... Tn hi u bi7 n thin nhanh TSn s> l=y mCu ch?m. Ref KQ thu't Oo l(9ng - Prof. Dr. Ph; m Th./ng Hn

Hnh 6.20. Dual Slope Integration ADC

Hnh 6.21. Interfacing to the ICL - 7135 ADC Hnh 6.15. DAC Symbolic Diagram

Hnh 6.16. R-2R ladder DAC with I/U converter

Hnh 6.17. Interfacing to DAC Hnh 6.22. Nguyn l c$u trc v ho6t ,*ng cCa SA ADC

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Ch12ng 7. Micro controllers

7.1. Khi ni3m:8/ 16/ 32 bit 7.2. Multi Purpose ~ : Intel 8051, 80196 & Clones: Flash/EPROM, Data RAM, DI, DO, AI, AO, Serial (RS232), Timer/ Counter, RTC, WDT, EEROM, CMOS RAM, ISP/Jtag ... Motorola 68HC11 Families BASIC 386 EX 7.3. Special ~ : RISC: Atmel AVR-90 S 8535 Family, Mega AVR, Micro Chip PIC Family. DSP: Texas Instrument TMS 32 F 240

Ch 8. Device drivers (DD)

8.1. Khi ni3m: MSDN, A Little Device Driver Writer, cc m hnh I/O cNa Microsoft 8.2. PC Layers: Next Page 8.3. DOS Device Drivers: BIOS, DOS Functions Writing DOS DD 8.4. Windows DD: MSDN: DLLs for Beginners DRV, DLL, DCU, VxD System's Win32 APIs & SPIs 8.2. PC Layers

Hnh 6.23. Interfacing to the ADC 0809 ns.com/product/interface/ad-da national semiconductor

Hnh 8.01. PC Layers (Courtesy IBM PC Institute) Hnh 6.24. Multi IO card: DI/ DO/ AI/ AO

Hnh 8.02. Key Code Queue

K#t thc mn h c
<: n mn h c/ Bi t.p l?n: BJt bu0c. C nhn, nhm 4#n 3 ng1Pi Hnh thAc Bo co: khng qu 15 trang A4, tr T d'ch ti li3u, font ARIAL, khng c;n 4ng ba nilon (giIm nhiUm mt) N#u c sIn phLm => 4Bng k l'ch demo N0p tr1?c khi thi, b/ v3 tr1?c and/or sau thi Bi thi: ChN dng giVy A4, vi#t 01 m=t, ghim l)i v ghi s / tP. Khng vi#t nhiCu lPi, khng chp 4;u bi Trnh b;y: visual, flow chart; s)ch, k/h + 1 4i5m K#t quI: Auto Answering, after 19h, tone dialling, 8696125/ 8683590

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