Compal LA-7201P M/B Schematic and Notes

A
PWWHA
2
Delhi 10RG
LA-7201P REV 1.0 Schematic

3
Intel Processor(Sandy Bridge) / PCH(Cougar Point)

2011-01-31 Rev 1.0
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/09/03
Issued Date
Deciphered Date
2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://mycomp.su - . , ,
A
B

.
Title
Cover Page
Size
B
Date:
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Friday, February 25, 2011
Sheet
E
of
53
Fan Control Circuit
Intel CPU
Sandy Bridge
PCI-Express 8X 2.5GHz
page 5
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
rPGA-989
37.5mm*37.5mm
Dual Channel
page 5,6,7,8,9,10
FDI X8
1.5V DDRIII 1066/1333/1600 MT/s
5GT/s
USB Port
VGA Board(GDDR3)
2IN1 RTS5137
USB port 0,1

page 31
USB
CRT
Int. Camera
USB port 10
page 34
USB port 11
page 19
5V 480MHz
page 20
page 13,14,15,16,17,18
USB
5V 480MHz
LVDS Conn.
PCIe 1x
page 19
1.5V 5GT/s
Intel PCH
Cougar Point - M
RJ45
page 11,12
BANK 0, 1, 2, 3
DMI X4
2.7GT/s
NVIDIA N12M-GE-S-B1 BGA 533P
RTL8105E 10/100M
page 33
page 32
PCIeMini Card
WLAN PCIe port 2
page 32
SATA port 0
PCIe 1x
PCIe port 1
page 33
PCIeMini Card
WiMax USB port 9
5V 6GHz(600MB/s)
1.5V 5GT/s
FCBGA-989
25mm*25mm
SATA port 2
5V 3GHz(300MB/s)
SATA HDD
SATA port 0
page 31
SATA ODD
SATA port 2
page 31
page 21,22,23,24,25,26,27,28,29
HD Audio
LPC BUS
3.3V 24MHz
3.3V 33 MHz
RTC CKT.
page 21
DC/DC Interface CKT.
HDA Codec
SPI ROM
(4MB)
page 21
Debug Port
ALC259-VB5-GR
QFN 48P page 36
ENE KB930
page 39
page 38
page 41
Touch Pad
4
page 40
Power Circuit DC/DC
Int.KBD
page 39
EC ROM
(128KB)
page 39
Ext.
MIC Conn
SPK Conn
page 37
HP Conn
page 37
page 37
page 42,43,44,45,46,
47,48,49,50
2010/09/03
Issued Date
page 40
Compal Secret Data
Power/B
Deciphered Date
2012/12/31
A
B

.
Title
Block Diagram
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
of
53
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A
DESIGN CURRENT 0.1A
+3VL
DESIGN CURRENT 10A
+5VALW
DESIGN CURRENT 1.8A
+1.8VS
SUSP#
SY8033BDBC
SUSP
DESIGN CURRENT 5.5A
N-CHANNEL
+5VS
SI4800
DESIGN CURRENT 6A
+3VALW
DESIGN CURRENT 330mA
+3V_LAN
WOL_EN#
P-CHANNEL
AO-3413
SUSP
TPS51125ARGER
DESIGN CURRENT 4.5A
N-CHANNEL
+3VS
VGA_ENVDD
SI4800
SUSP or 0.75VR_EN#
P-CHANNEL
AO-3413
DESIGN CURRENT 2A
+LCD_VDD
DESIGN CURRENT 0.5A
+0.75VS
G2992F1U
2
VR_ON
Ipeak=53A, Imax=36A, Iocp min=70A
DESIGN CURRENT 53A
+CPU_CORE
Ipeak=20A, Imax=14A, Iocp min=26A
DESIGN CURRENT 21A
+VGA_CORE
DESIGN CURRENT 17A
+1.05VS_VCCP
DESIGN CURRENT 6A
+VCCSA
ISL95831CRZ-T
SUSP#
TPS51218DSCR
SUSP#
Ipeak=12.5A, Imax=8.75A, Iocp min=21.4A
TPS5117
VCCPPWRGD
3
TPS51117
SYSON
Ipeak=16.5A, Imax=11.55A, Iocp min=21.03A
TPS51117RGYR
DESIGN CURRENT 20A
+1.5V
DESIGN CURRENT 2A
+1.5V_CPU
DESIGN CURRENT 0.7A
+1.5VS
DESIGN CURRENT 3A
+1.5V_MEM_GFX
SUSP
N-CHANNEL
FDS6676AS
SUSP
N-CHANNEL
FDS6676AS
VGA_PWROK#
N-CHANNEL
4
FDS6676AS
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
Power Tree
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
of
53
Voltage Rails
( O MEANS ON
X MEANS OFF )
+5VS
+RTCVCC
B+
+3VL
+5VALW
+1.5V
+3VS
+3VALW
+1.8VS
+VSB
power
plane
+1.5VS
+1.05VS
+0.75VS
+CPU_CORE
+GFX_CORE
State
BTO Option Table

DIS only
Function
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only

S5 S4/AC & Battery
don't exist
MINI PCI-E SLOT
description
SLOT1
explain
WIMAX
DIS@
BTO
HDMI/Non-HDMI
explain
HDMI@/NHDMI@
Giga
Camera & Mic
8111E@
CAM@
Zero ODD
EC Chip
930
Q65R3@
Camera & Mic
8105ESWR@
8105ELDO@
description
BTO
Camera & Mic
LAN
10/100M
WIMAX@
PCH
Function
LAN
or 9012
930
Complete
Simple
930@
9012@
S9012@
ZODD@
PCH SM Bus Address

3
Power
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
WLAN/WIMAX
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
STATE
Full ON
EC SM Bus1 Address
EC SM Bus2 Address
Power
Device
HEX
Address
Power
Device
HEX
Address
+3VL
Smart Battery
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
HIGH
HIGH
HIGH
S1(Power On Suspend)
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
Notes List
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
of
53
JCPUB
@
Stuff R41 and R42 if do not support eDP
PM_DRAM_PW RGD_R
1 C488
H_PW RGOOD
H_SNB_IVB#
25 H_SNB_IVB#
T1
PAD
TP_SKTOCC#
C26
SNB_IVB#
AN34
SKTOCC#
T2
38
PAD
H_PECI
H_CATERR#
AL33
CATERR#
H_PECI
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
THERMAL
R450
2 H_PROCHOT#_R
56_0402_5%
38,43 H_PROCHOT#
H_THERMTRIP#
26 H_THERMTRIP#
BCLK
BCLK#
A28
A27
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A16
A15
PM_SYNC
H_PROCHOT#
H_PW RGOOD
26 H_PW RGOOD
AP33
UNCOREPWRGOOD
R51
1 10K_0402_5%
H_PW RGOOD
PM_SYS_PW RGD_BUF 1
R454
2 PM_DRAM_PW RGD_R
130_0402_5%
BUF_CPU_RST#
PM_SYS_PW RGD_BUF
R384
SUSP
SUSP
2
G
3
9,32,41,47
1 2
2 0_0402_5%
W PS3@
AK1
A5
A4
SM_RCOMP_0 R1437 2
SM_RCOMP_1 R1438 2
SM_RCOMP_2 R1439 2
PRDY#
PREQ#
AP29
AP27
XDP_PRDY#_R
XDP_PREQ#_R
R1 1
R2 1
@
@
2 0_0402_5%
2 0_0402_5%
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
R4 1
R6 1
R7 1
@
@
@
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
XDP_TCK
XDP_TMS
XDP_TRST#
TDI
TDO
AR28
AP26
XDP_TDI_R
XDP_TDO_R
R8 1
R10 1
@
@
2 0_0402_5%
2 0_0402_5%
XDP_TDI
XDP_TDO
DBR#
AL35
XDP_DBRESET#_R
R11 1
2 0_0402_5%
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
R12 1
R13 1
R15 1
R18 1
@
@
@
@
2
2
2
2
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
Sandy Bridge_rPGA_Rev0p61
+1.05VS_VCCP
XDP_TMS_R
R28
1 51_0402_5%
XDP_TDI_R
R29
1 51_0402_5%
R36
1
2
1K_0402_5%
XDP_TDO
R30
1 51_0402_5%
XDP_TCK_R
R31
1 51_0402_5%
XDP_TRST#_R
R32
EN_DFAN1
1 51_0402_5%
1
2
3
4
10mil 1
23,38 PBTN_OUT#
10
CFG0
23,38,49 VGATE
22 CLK_CPU_ITP
22 CLK_CPU_ITP#
+1.05VS_VCCP
OUT
GND
BUFO_CPU_RST#
R155
43_0402_1%
1
2
H_PW RGOOD
PBTN_OUT#
CFG0
VGATE
R35
R152
R37
R451
PLT_RST#
BUF_CPU_RST#
1
1
1
1
1
R40
@
@
@
@
2
2
2
2
74AHC1G125GW _SOT353-5
R209
0_0402_5%
@
C8
0.1U_0402_10V6K
@
1K_0402_5%XDP_CPU_HOOK0
0_0402_5% XDP_CPU_HOOK1
1K_0402_5%XDP_CPU_HOOK2
0_0402_5% XDP_CPU_HOOK3
CLK_CPU_ITP
CLK_CPU_ITP#
XDP_CPU_HOOK6
2
1K_0402_5% XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
JXDP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
EN
VIN
VOUT
VSET
C15
1000P_0402_50V7K
@
8
7
6
5
GND
GND
GND
GND
FAN Control Circuit
10K_0402_5%
1
+3VS
C14
0.01U_0402_25V7K
@
+3VS
R1444
10K_0402_5%
@
+5VS
38
38
FAN_SPEED1
R1445
1A
1
2
0_0603_5%
2
C902 @
10U_0805_10V6K
1 @
JFAN @
+FAN1
Deciphered Date
1
2
3
4
FANPW M
FANPW M
+FAN1
C899
0.01U_0402_25V7K
@
1
2
3
4
ACES_85204-0400N
+5VS
40 mil
D85
1SS355_SOD323-2
@
D86
BAS16_SOT23-3
@
1
1000P_0402_50V7K
C901
@
C900
1
2
10U_0805_10V6K
@
Close to Connector

2012/12/31
A
B

.
GND
GND
Compal Secret Data

2010/09/03
4
5
FAN_SPEED1
APL5607KI-TRG_SO8
C17
10U_0805_10V6K
MOLEX 52435-2671
Issued Date
1
2
3
ACES_85204-0300N
R24
27
28
1
2
3
XDP_BPM#2
XDP_BPM#3
IN
JFAN2
+FAN2
5
2
VCC
FAN Control Circuit (RPM and PWM)
XDP_PREQ#
XDP_PRDY#
13,25,32,33,35,38,39
1 0.1U_0402_16V4Z
C84
+1.05VS_VCCP
OE#
+3VS
XDP_DBRESET# 23
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
C13
10U_0805_10V6K
38
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
XDP_BPM#0
XDP_BPM#1
R69
75_0402_5%
XDP_DBRESET#
U1
XDP Connector
Routed as a single daisy chain
1A
PU/PD for JTAG signals
+3VS
U3
DDR3 Compensation Signals

Layout Note:Place these
resistors near Processor
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
PLT_RST#
2 1K_0402_5%
H_DRAMRST# 7
Buffered Reset to CPU
2 1K_0402_5%
R41 1
H_DRAMRST#
+FAN2
Q5
2N7002_SOT23-3
@
R42 1
CLK_CPU_DPLL
+5VS
1
R340
39_0402_5%
@
CLK_CPU_DPLL#
R8
SM_DRAMRST#
R339
200_0402_5%
O
A
RESET#
U10
74AHC1G09GW _TSSOP5
PS3@
23 DRAMPW ROK
AR33
SM_DRAMPWROK
+1.5V_CPU
23,38 PM_PW ROK
PS3@ R312
1
21
0_0402_5%
2
+3VALW
PS3@ C93
0.1U_0402_16V4Z
2
1
V8
CLK_CPU_DPLL
CLK_CPU_DPLL#
JTAG & BPM
1 62_0402_5%
AM34
PWR MANAGEMENT
R47
H_PM_SYNC
23 H_PM_SYNC
+1.05VS_VCCP
CLK_CPU_DMI 22
CLK_CPU_DMI# 22
120 MHz
Remove R14(o ohm) for HW Review demand
+1.05VS_VCCP
CLK_CPU_DMI
CLK_CPU_DMI#
1000P_0402_50V7K 2
PROC_SELECT#
CLOCKS
100 MHz
DDR3
MISC
1 C487
MISC
1000P_0402_50V7K 2
Title
Sandy Bridge_JTAG/XDP/FAN
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Friday, March 04, 2011
Sheet
E
of
53
+1.05VS_VCCP
R34
24.9_0402_1%
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
23
23
23
23
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
23 FDI_FSYNC0
23 FDI_FSYNC1
FDI_FSYNC0
FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
23 FDI_INT
FDI_INT
H20
FDI_INT
23 FDI_LSYNC0
23 FDI_LSYNC1
FDI_LSYNC0
FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD
Reserve R33 for HW Review demand
C15
D15
eDP_AUX
eDP_AUX#
eDP_COMP signals should be

shorted near balls and
routed with typical
impedance <25m ohm
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
23
23
23
23
23
23
23
23
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
23
23
23
23
23
23
23
23
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
+1.05VS_VCCP
R9
2 24.9_0402_1%
+1.05VS_VCCP
R33
1 10K_0402_5%
EDP_COMP
PCI EXPRESS* - GRAPHICS
23
23
23
23
B28
B26
A24
B23
DMI
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
Intel(R) FDI
23
23
23
23
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
B27
B25
A25
B24
eDP
23
23
23
23
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
JCPUA
1
PEG_COMP
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 m ohm (12 mils)
PCIE_GTX_C_CRX_N[8..15]
13
PCIE_GTX_C_CRX_P[8..15]
13
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15
C29
C30
C31
C32
C33
C34
C35
C36
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
PCIE_CTX_C_GRX_N[8..15]
13
PCIE_CTX_C_GRX_P[8..15]
13
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15
C45
C46
C47
C48
C49
C50
C51
C52
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
Sandy Bridge_DMI/PEG/FDI
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
of
53
JCPUC
11 DDR_A_D[0..63]
JCPUD
11
11
11
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_W E#
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AE10
AF10
V6
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
SA_CAS#
SA_RAS#
SA_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_W E#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
AB6
AA6
V9
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
AA5
AB5
V10
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1
SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]
AB4
AA4
W9
SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
AK3
AL3
AG1
AH1
DDRA_SCS0#
DDRA_SCS1#
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
AH3
AG3
AG2
AH2
DDRA_ODT0
DDRA_ODT1
DDRA_CLK0 11
DDRA_CLK0# 11
DDRA_CKE0 11
DDRA_CLK1 11
DDRA_CLK1# 11
DDRA_CKE1 11
DDRA_SCS0# 11
DDRA_SCS1# 11
DDRA_ODT0 11
DDRA_ODT1 11
DDR_A_DQS#[0..7]
C4 DDR_A_DQS#0
G6 DDR_A_DQS#1
DDR_A_DQS#2
J3
M6 DDR_A_DQS#3
AL6 DDR_A_DQS#4
AM8 DDR_A_DQS#5
AR12 DDR_A_DQS#6
AM15 DDR_A_DQS#7
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR_A_DQS[0..7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA[0..15]
11
11
11
12
12
12
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_W E#
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AA9
AA7
R6
SB_BS[0]
SB_BS[1]
SB_BS[2]
AA10
AB8
AB9
SB_CAS#
SB_RAS#
SB_WE#
DDR_B_CAS#
DDR_B_RAS#
DDR_B_W E#
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR SYSTEM MEMORY B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR SYSTEM MEMORY A
12 DDR_B_D[0..63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
AE2
AD2
R9
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1
SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]
AB2
AA2
T9
SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
AD3
AE3
AD6
AE6
DDRB_SCS0#
DDRB_SCS1#
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
AE4
AD4
AD5
AE5
DDRB_ODT0
DDRB_ODT1
DDRB_CLK0 12
DDRB_CLK0# 12
DDRB_CKE0 12
DDRB_CLK1 12
DDRB_CLK1# 12
DDRB_CKE1 12
DDRB_SCS0# 12
DDRB_SCS1# 12
DDRB_ODT0 12
DDRB_ODT1 12
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
12
12
12
+1.5V
R466
W PS3@ 0_0402_5%
1
2
Q14
DDR3_DRAMRST#_R
1
R467
1K_0402_5%
2
SM_DRAMRST# 11,12
BSS138_NL_SOT23-3
PS3@
C140
22 DRAMRST_CNTRL_PCH
1
R463
2 DRAMRST_CNTRL
0_0402_5%
PS3@
0.047U_0402_25V6K
PS3@
2010/09/03
Issued Date
Compal Secret Data
R464
4.99K_0402_1%
H_DRAMRST#
5 H_DRAMRST#
R465
1K_0402_5%
PS3@
Deciphered Date
2012/12/31
A
B

.
Title
Sandy Bridge_DDR3
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
of
53
+CPU_CORE
JCPUF
POWER
53A (SV 35W)
+1.05VS_VCCP
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
22U_0805_6.3V6M
1
C146
C144
22U_0805_6.3V6M
1
C143
C141
22U_0805_6.3V6M
C147
22U_0805_6.3V6M
1
C137
C136
22U_0805_6.3V6M
1
C135
C134
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C133
C142
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C145
C163
@
22U_0805_6.3V6M
1
C153
C160
@
@
22U_0805_6.3V6M
1
C152
C139
@
@
22U_0805_6.3V6M
1
C138
C132
@
@
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE Decoupling:
4X 470U (4m ohm), 16X 22U, 10X 10U
2
22U_0805_6.3V6M
22U_0805_6.3V6M
Bottom Socket Cavity

+CPU_CORE
22U_0805_6.3V6M
10U_0805_10V6K
C101
C102
ESR 9mohm
Bottom Socket Cavity x 5
C10 +
C11 +
@ C12 +
10U_0805_10V6K
C104
10U_0805_10V6K
C105
C106
C107
10U_0805_10V6K
1
C108
10U_0805_10V6K
C109
C110
C111
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
Top Socket Edge

+CPU_CORE
22U_0805_6.3V6M
1
C151
22U_0805_6.3V6M
1
C129
C124
22U_0805_6.3V6M
22U_0805_6.3V6M
1
22U_0805_6.3V6M
C122
22U_0805_6.3V6M
C121
C125
@
22U_0805_6.3V6M
22U_0805_6.3V6M
Top Socket Cavity

+CPU_CORE
2
1
R67 1
R63 1
R66
C123
9/02 Remove C126, C131 by Power Demand
close to CPU
R68
75_0402_5%
R70
130_0402_5%
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
C130
+1.05VS_VCCP
2
2 43_0402_1%
2 0_0402_5%
0_0402_5%
22U_0805_6.3V6M
VR_SVID_ALRT# 49
VR_SVID_CLK 49
VR_SVID_DAT 49
C158
C150
C128
22U_0805_6.3V6M
1
C127
C120
22U_0805_6.3V6M
1
C118
22U_0805_6.3V6M
C119
C117
Pull high resistor on VR side

2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Bottom Socket Edge

+CPU_CORE
+CPU_CORE
330U_D2_2V_Y
R64
100_0402_1%
1
C2
1
R65 1
R52 1
B10 VCCIO_SENSE
A10
2 0_0402_5%
2 0_0402_5%
330U_D2_2V_Y
VCCSENSE 49
VSSSENSE 49
+
2
C9
C3
+
2
330U_D2_2V_Y
9/02 Add C898 3Pin Bulk Cap by Power Demand
9/02 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 for Power demand
+1.05VS_VCCP
Issued Date
Compal Secret Data
R62
100_0402_1%
47
2
R105
100_0402_1%
@
C7
R102
0_0402_5%
C5
330U_D2_2V_Y
VCCIO_SENSE
VCCIO_SENSE
VSSIO_SENSE
VSS_SENSE_VCCIO
330U_D2_2V_Y
Close to CPU
VCC_SENSE
VSS_SENSE
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
Close to CPU
330U_D2_2V_Y
C159
AJ29
AJ30
AJ28
330U_D2_2V_Y
+1.05VS_VCCP
VIDALERT#
VIDSCLK
VIDSOUT
10U_0805_10V6K
C103
330U_D2_2V_Y
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
+1.05VS_VCCP Decoupling:
2X 330U (6m ohm), 12X 22U
SVID
TOP Socket Cavity x 7
22U_0805_6.3V6M
SENSE LINES
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CORE SUPPLY
PEG AND DDR
8.5A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
2010/09/03
Deciphered Date
2012/12/31

.
A
B
C
D
Title
Sandy Bridge_POWER-1
Size Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
of
53
POWER
1
C185
@+
C186
2
330U_B2_2.5VM_R15M
C206
1U_0402_6.3V6K
B6
A6
A2
C230
1U_0402_6.3V6K
VCCPLL1
VCCPLL2
VCCPLL3
C148
5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
SA RAIL
2
@
+1.5VS
JUMP_43X118
Q2
@
AP2302GN-HF_SOT23-3
2
RUN_ON_CPU1.5VS3
+1.5V_CPU
1K_0402_5%
R252
1K_0402_5%
8/20 Add PJ32 for Cost down +1.5V to +1.5V_CPU
+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U
+1.5V_CPU
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
1
C114
C115
C116
10U_0805_10V6K
C149
C154
10U_0805_10V6K
C155
+ C875
330U_2.5V_M_R17
ESR 17mohm
10U_0805_10V6K
+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U
+VCCSA
Bottom Socket Cavity
R122
+V_SM_VREF
R486
SENSE
LINES
VREF
SM_VREF
AL1 +V_SM_VREF_CNT
DDR3 -1.5V RAILS
PJ32
R111
0_0402_5%
2
1
VCCSA_VID0
6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
M27
M26
L26
J26
J25
J24
H26
H25
10U_0805_10V6K
10U_0805_10V6K
2VCCSA_SENSE
0_0402_5%
1
R253
VCCSA_VID1
+VCCSA
0.90 V
0.80 V
0.75 V
0.65 V
For Sandy Bridge
1
C100
C447
C476
C477
@
10U_0805_10V6K
+ C877
330U_2.5V_M_R17
@
10U_0805_10V6K
Bottom Socket Edge

VCCSA_SENSE
H23 VCCSA_SENSE
VCCSA_SENSE 46
1 R95
0_0402_5% @
VCCSA_VID0
FC_C22
VCCSA_VID1
C22 VCCSA_VID0
C24
VCCSAP_VID1
46
1.2A
+1.8VS_VCCPLL
10U_0805_10V6K
+V_SM_VREF should
have 20 mil trace width
R114
+1.5V_CPU
R119
Only for PWWHA DIS PS3@
+1.5V
+1.5V_CPU
10K_0402_5%
10K_0402_5%
C213 1
R76
2
1
0_0805_5%
PS3@ short
WPS3@ open
VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U
AK35
AK34
0.1U_0402_16V4Z
+1.8VS
VAXG_SENSE
VSSAXG_SENSE
100K_0402_5%
33A
MISC
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
GRAPHICS
R14
0_0402_5%
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.8V RAIL
JCPUG
+1.5V
2 0.1U_0402_16V4Z
PJ30
2
C212 1
2 0.1U_0402_16V4Z
C211 1
2 0.1U_0402_16V4Z
C210 1
2 0.1U_0402_16V4Z
JUMP_43X118
Q33 PS3@
1
2
3
4
R449
470_0805_5%
PS3@
S
S
S
G
D
D
D
D
8
7
6
5
FDS6676AS_SO8
RUN_ON_CPU1.5VS3
3 1
C179
10U_0805_10V4K
PS3@
+VSB
R420
820K_0402_5%
PS3@
Q46A
2 SUSP
SUSP
4
5,32,41,47
2N7002KDW H_SOT363-6
PS3@
C472
0.1U_0402_25V6
PS3@
PS3@
2
Q46B
SUSP
4
R455 PS3@
1
2
220K_0402_5%
08/18 Reserve R119 to follow CRB 1.0
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
Sandy Bridge_POWER-2
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
of
53
JCPUE
JCPUH
CFG Straps for Processor
JCPUI
(CFG[17:0] internal pull high to VCCIO)

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
T22
T24
T25
T23
PAD
PAD
PAD
PAD
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
CFG2
CFG0
T5
T6
T7
T11
T12
T15
T18
T16
T19
T21
T20
T44
T45
T46
T47
T26
T27
R254
1K_0402_1%
L7
AG7
AE7
AK2
W8
PEG Static Lane Reversal

- CFG2 is for the 16x
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
AR35
AT34
AT33
AP35
AR34
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
B34
A33
A34
B35
C35
1: Normal Operation;
CFG2 Lane # definition matches
socket pin map definition
0:Lane Reversed
RSVD5
SA_DIMM_VREFDQ
CPU_RSVD6
CPU_RSVD7
B4
D1
RSVD6
RSVD7
SB_DIMM_VREFDQ
R115
1K_0402_1%
F25
R116
F24
1K_0402_1% F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
A19
1
R255
1K_0402_1%
@
Embedded Display Port

Presence Strap
RSVD24
RSVD25
RSVD26
VCCIO_SEL
RSVD51
RSVD52
AJ32
AK32
RSVD53
AH27
RSVD54
RSVD55
AN35
AM35
RSVD56
RSVD57
RSVD58
AT2
AT1
AR1
CFG4
T28 PAD
CFG6
CFG5
RSVD27
KEY
R257
1K_0402_1%
B1
R256
1K_0402_1%
@
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1

functions 1 and 2 disabled
CFG7
0 : Enabled; An
external Display
Port device is
connected to the
Embedded Display
Port
CLK_RES_ITP 22
CLK_RES_ITP# 22
R258
1K_0402_1%
@
1 : Disabled; No
Physical Display
Port attached to
mbedded Display
Port
J15
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
CFG4
AJ26
RSVD1
RSVD2
RSVD3
RSVD4
AJ31
AH31
AJ33
AH33
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
RESERVED
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
01: Reserved (Device 1 function 1

disabled ; function
2 enabled)
CFG[6:5]
PEG DEFER TRAINING
CFG7
10: x8, x8 - Device 1

function 1 enabled ;
function 2
disabled
1: (Default) PEG Train immediately following xxRESETB

de assertion
00: x8,x4,x4 - Device 1

functions 1 and 2
enabled
0: PEG Wait for BIOS for training
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
Sandy Bridge_GND/RSVD/CFG
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
10
of
53
+1.5V
JDDRL
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
7
7
DDRA_CKE0
DDRA_CKE0
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
7
7
7
DDR_A_BS0
7
7
DDR_A_W E#
DDR_A_CAS#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK0
DDRA_CLK0#
DDR_A_MA10
DDR_A_BS0
DDR_A_W E#
DDR_A_CAS#
DDR_A_MA13
DDRA_SCS1#
DDRA_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
1
C182
+0.75VS
R91
10K_0402_5%
C181
4
2.2U_0603_6.3V6K
+3VS
0.1U_0402_16V4Z
DDR_A_D58
DDR_A_D59
R90 1
2
10K_0402_5%
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_D6
DDR_A_D7
7
7
7
7
DDR_A_D12
DDR_A_D13
1
SM_DRAMRST#
SM_DRAMRST# 7,12
+1.5V
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
R79
1K_0402_1%
+VREF_DQA
DDR_A_D22
DDR_A_D23
R81
1K_0402_1%
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDRA_CKE1
DDRA_CKE1
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDRA_CLK1 7
DDRA_CLK1# 7
+1.5V
DDR_A_BS1 7
DDR_A_RAS# 7
DDRA_SCS0# 7
DDRA_ODT0 7
R80
1K_0402_1%
DDRA_ODT1 7
+VREF_CAA
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
R82
1K_0402_1%
C161
C162
0.1U_0402_16V4Z
DDR_A_D40
DDR_A_D41
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
2.2U_0603_6.3V6K
DDR_A_D34
DDR_A_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR3 SO-DIMM A
Reverse Type
Close to JDDRL.1
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D4
DDR_A_D5
DDR_A_D8
DDR_A_D9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A_D2
DDR_A_D3
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
close to JDDRL.126
DDR_A_D52
DDR_A_D53
+1.5V
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMA
+1.5V
+0.75VS
2 390U_2.5V_M_R10
C165 1
2 10U_0603_6.3V6M
C169 2
1 1U_0402_6.3V6K
C172 2
1 1U_0402_6.3V6K
2 10U_0603_6.3V6M
C175 2
1 1U_0402_6.3V6K
C176 1
2 10U_0603_6.3V6M
C177 2
1 1U_0402_6.3V6K
C178 1
2 10U_0603_6.3V6M
C166 1
2 10U_0603_6.3V6M
C168 1
2 10U_0603_6.3V6M
C171 1
2 10U_0603_6.3V6M
C174 1
C164 1
2 0.1U_0402_16V4Z
C167 1
2 0.1U_0402_16V4Z
C170 1
DDR_A_D60
DDR_A_D61
C173 1
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Layout Note:
Place near JDDRL1.203 and 204
Change C218 to OSCON at DVT
C218 1
DDR_A_D54
DDR_A_D55
PM_SMBDATA
PM_SMBCLK
Layout Note:
Place near JDDRL
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
C157
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C156
DDR_A_D0
DDR_A_D1
+VREF_DQA
+1.5V
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PM_SMBDATA 12,22,32
PM_SMBCLK 12,22,32
+0.75VS
4
FOX_AS0A626-U2SN-7F_204P
@
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31

.
A
B
C
D
Title
DDRIII-SODIMM0
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
11
of
53
+1.5V
+1.5V
JDDRH
Close to JDDRH.1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDRB_CKE0
DDR_B_BS2
DDRB_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
7
7
DDRB_CLK0
DDRB_CLK0#
DDR_B_BS0
7
7
DDR_B_W E#
DDR_B_CAS#
DDRB_SCS1#
DDRB_CLK0
DDRB_CLK0#
DDR_B_MA10
DDR_B_BS0
DDR_B_W E#
DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#
DDR_B_D37
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
R98 1
2
10K_0402_5%
+3VS
2.2U_0603_6.3V6K
1
1
@
C207
4
1 R99
2
10K_0402_5%
C208
2 @
0.1U_0402_16V4Z
+0.75VS
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_B_DQS[0..7]
DDR_B_D[0..63]
7
7
7
1
SM_DRAMRST#
DDR_B_MA[0..15]
SM_DRAMRST# 7,11
DDR_B_D14
DDR_B_D15
+1.5V
DDR_B_D20
DDR_B_D21
R83
1K_0402_1%
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
+VREF_DQB
DDR_B_DQS#3
DDR_B_DQS3
R84
1K_0402_1%
DDR_B_D30
DDR_B_D31
DDRB_CKE1
DDRB_CKE1
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1 7
DDRB_CLK1# 7
+1.5V
DDR_B_BS1 7
DDR_B_RAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
R86
1K_0402_1%
DDRB_ODT1 7
+VREF_CAB
DDR_B_D32
DDR_B_D33
R94
1K_0402_1%
C187
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
C188
0.1U_0402_16V4Z
DDR_B_D40
DDR_B_D41
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_B_DQS#[0..7]
DDR_B_D12
DDR_B_D13
2.2U_0603_6.3V6K
DDR_B_D34
DDR_B_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D6
DDR_B_D7
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D8
DDR_B_D9
Reverse Type
DDR3 SO-DIMM B
DDR_B_D4
DDR_B_D5
DDR_B_D2
DDR_B_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
C184
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C183
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_B_D0
DDR_B_D1
1
2
+VREF_DQB
2
3
Layout Note:
Place near JDDRH
Layout Note:
Place near JDDRH.203 and 204
Close to JDDRH.126
+1.5V
+1.5V
DDR_B_D52
DDR_B_D53
DDR_B_D50
DDR_B_D51
+0.75VS
C191 1
2 10U_0603_6.3V6M
C195 2
1 1U_0402_6.3V6K
C198 2
1 1U_0402_6.3V6K
2 10U_0603_6.3V6M
C201 2
1 1U_0402_6.3V6K
C202 1
2 10U_0603_6.3V6M
C203 2
1 1U_0402_6.3V6K
C204 1
2 10U_0603_6.3V6M
C192 1
2 10U_0603_6.3V6M
C194 1
2 10U_0603_6.3V6M
C197 1
2 10U_0603_6.3V6M
C200 1
C190 1
2 0.1U_0402_16V4Z
C193 1
2 0.1U_0402_16V4Z
C196 1
DDR_B_D60
DDR_B_D61
C199 1
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_SMBDATA
PM_SMBCLK
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMB
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PM_SMBDATA 11,22,32
PM_SMBCLK 11,22,32
+0.75VS
4
FOX_AS0A626-UASN-7F_204P
@
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31

.
A
B
C
D
Title
DDRIII-SODIMM1
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
12
of
53
+3VS
UV1A
PCIE_GTX_C_CRX_P[8..15]
10K_0402_5%
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
1
2.49K_0402_1%
2
0_0402_5%
CLK_REQ#
2
10K_0402_5%
1 @ RV100
I2CH_SDA
10K_0402_5%
1 @ RV101
I2CB_SCL
2.2K_0402_5% 1
2 RV27
I2CB_SDA
2.2K_0402_5% 1
2 RV28
GPU_GPIO8
10K_0402_5%
1 RV102
GPU_GPIO9
10K_0402_5%
2 RV26
GPU_GPIO12
10K_0402_5%
2 RV29
LCD_EDID_CLK
2.2K_0402_5% 1
2 RV14
LCD_EDID_DATA 2.2K_0402_5% 1
2 RV17
VGA_PW M
10K_0402_5%1
2 RV10
VGA_ENBKL
10K_0402_5%1
DACA_VREF
DACA_RSET
AF1
AE1
U6
U4
DACB_RED
DACB_BLUE
DACB_GREEN
T5
R4
T4
DACB_VREF
DACB_RSET
R6
V6
AF3
AG4
AE4
AF4
AG3
AB10
AC10
PEX_REFCLK
PEX_REFCLK_N
AF10
AE10
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
AG10
PEX_TERMP
20
20
VGA_CRT_R 20
VGA_CRT_B 20
VGA_CRT_G 20
2 RV11
DACA_VREF
DACA_RSET
HDMI_HPD
NHDMI@ 1
R25
CV13 1
2 0.1U_0402_16V4Z
2
124_0402_1%
2
100K_0402_5%
Close to GPU
VGA_CRT_R
RV3
2 150_0402_1%
VGA_CRT_G
RV4
2 150_0402_1%
VGA_CRT_B
RV5
2 150_0402_1%
+3VS
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_JTAG_TRST#
@ TV1
@ TV2
@ TV3
@ TV4
@ RV7
10K_0402_5%
2
1K_0402_1%
GPU_TESTMODE
GPU_TESTMODE
R1
T3
I2CB_SCL
I2CB_SDA
R2
R3
I2CC_SCL
I2CC_SDA
A2
B1
GPIO20
GPIO21
A3
A4
I2CS_SCL
I2CS_SDA
T1
T2
PEX_RST_N
AE9
PEX_CLKREQ_N
I2CB_SCL
I2CB_SDA
LCD_EDID_CLK
LCD_EDID_DATA
I2CH_SCL
I2CH_SDA
FERMI Changed
XTALSSIN
E9
XTALOUTBUFF
XTAL_OUT
E10
RV16
NV_CLK_27M_OUT
XTAL_IN
D10
CLK_27M_IN
CV34
18P_0402_50V8J
+3VS
+3VS
YV1
CLK_27M_IN
RV22
2.2K_0402_5%
27MHZ_16PF_X5H027000FG1H
RV25
2.2K_0402_5%
NV_CLK_27M_OUT
GPU_SMBCLK
4
QV1A
1
GPU_SMBDAT
QV1B
EC_SMB_CK2 22,38
EC_SMB_DA2 22,38
R405
10_0402_5%
@
2
10K_0402_5%
2
10K_0402_5%
RV12
CLK_27M 22
19
19
GPU_SMBCLK
GPU_SMBDAT
D11
XTAL_SSIN
RV8
10K_0402_5%
VGA_CRT_CLK 20
VGA_CRT_DATA 20
I2CA_SCL
I2CA_SDA
XTAL_OUTBUFF
AD9
0_0402_5%
@
CLK_27M
2
VGA_CRT_HSYNC
VGA_CRT_VSYNC
RV9
AD25
N12M-GE-S-B1 BGA 533P

N12MR1@
R39
CLK_27M_IN 1
26,30
TESTMODE
HDMI_HPD
RV6
DACB_HSYNC
DACB_VSYNC
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
GPU_GPIO12
@ TV8
AE2
AD3
AE3
GPU_GPIO8
GPU_GPIO9
GPIO
DACA_RED
DACA_BLUE
DACA_GREEN
FERMI Changed
+3VS
2
RV15
1
RV18
1
RV21
1 RV24
I2CH_SCL
PLT_RST#
2
200_0402_1%
AD2
AD1
VGA_PW M 19
VGA_ENVDD 19
VGA_ENBKL 38
GPU_VID0 50
GPU_VID1 50
5,25,32,33,35,38,39
1
@ RV13
DACA_HSYNC
DACA_VSYNC
VGA_PW M
VGA_ENVDD
VGA_ENBKL
GPU_VID0
GPU_VID1
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
22 CLK_PCIE_VGA
22 CLK_PCIE_VGA#
Differential signal
1 RV23
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4.7K_0402_5% 2
VGA_CRT_DATA 4.7K_0402_5% 2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2
18P_0402_50V8J
CV18
CV19
CV20
CV21
CV22
CV23
CV24
CV25
CV26
CV27
CV28
CV29
CV30
CV31
CV32
CV33
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
CV35
DACA
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
DACB
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_GTX_C_CRX_N[8..15]
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
VGA_CRT_CLK
Part 1 of 5
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27
TEST
6 PCIE_GTX_C_CRX_N[8..15]
PCIE_CTX_C_GRX_N[8..15]
I2C
6 PCIE_GTX_C_CRX_P[8..15]
PCIE_CTX_C_GRX_P[8..15]
CLK
6 PCIE_CTX_C_GRX_N[8..15]
PCI EXPRESS
6 PCIE_CTX_C_GRX_P[8..15]
C88
10P_0402_50V8J
@
Near GPU
4
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
N12M PCIe,DAC,GPIO
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
13
of
53
UV1C
Part 3 of 5
RV99
20K_0402_1%
1
2
RV41
4.99K_0402_1%
1
2
RV57
4.99K_0402_1%
1
2
RV55
4.99K_0402_1%
1
2
RV56
34.8K_0402_1%
1
2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
G4
G5
P4
N4
M5
M4
L4
K4
H4
J4
D3
D4
F5
F4
E4
D5
C3
C4
B3
B4
30 VGA_HDMI_CLK
30 VGA_HDMI_DATA
30 VGA_HDMI_TX2+
30 VGA_HDMI_TX230 VGA_HDMI_TX1+
30 VGA_HDMI_TX130 VGA_HDMI_TX0+
30 VGA_HDMI_TX030 VGA_HDMI_CLK+
30 VGA_HDMI_CLK-
VGA_HDMI_CLK
VGA_HDMI_DATA
VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-
HDMI@
VGA_HDMI_CLK
2
4.7K_0402_5%
HDMI@
VGA_HDMI_DATA
1
2
RV120
4.7K_0402_5%
1
RV119
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
T6
W6
Y6
AA6
N3
2
40.2_0402_1%
RV2
GB1B-64 : MULTI_STRAP_REF2_GND
STRAP0
C7
STRAP0
STRAP1
B9
STRAP1
STRAP2
A9
STRAP2
BUFRST_N
N5
THERMDN
D8
THERMDP
D9
STRAP4
N2
STRAP4
STRAP3
F9
STRAP3
Fermi changed
ROM_CS_N
B10
ROM_SCLK
C9
ROM_SCLK_GPU
ROM_SI
A10
ROM_SI_GPU
ROM_SO
C10
ROM_SO_GPU
IFPAB_RSET
AB6
IFPC_RSET
R5
IFPD_RSET
M6
IFPE_RSET
F8
Physical
Strapping pin
ROM_SO
U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
F6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FB_CAL_PU_GND
A15
FB_CAL_TERM_GND
B16
W16
GND_SENSE
MULTI_STRAP_REF0_GND
F11
E14
GND_SENSE
F10
1
RV42
1
RV43
1
RV44
1
RV46

N12MR1@
1K_0402_1%
@ RV47
1K_0402_1%
RV48
1K_0402_1%
Resistor Values
Power Rail
Logical
Strapping Bit3
Logical
Strapping Bit2
FB_0_BAR_SIZE
Logical
Strapping Bit1
SMB_ALT_ADDR
Logical
Strapping Bit0
VGA_DEVICE
SUB_VENDOR
SLOT_CLK_CFG
PEX_PLLEN_TERM
RAMCFG[2]
RAMCFG[1]
+3VS
XCLK_417
ROM_SCLK
+3VS
PCI_DEVID[4]
ROM_SI
+3VS
STRAP2
+3VS
PCI_DEVID[3]
PCI_DEVID[2]
PCI_DEVID[1]
PCI_DEVID[0]
STRAP1
+3VS
3GIO_PADCFG[3]
3GIO_PADCFG[2]
3GIO_PADCFG[1]
3GIO_PADCFG[0]
STRAP0
+3VS
USER[3]
USER[2]
USER[1]
USER[0]
RV54
4.99K_0402_1%
1
2
RAMCFG[3]
RAMCFG[0]
Hynix (800MHZ) 64MX16 H5TQ1G63DFR-12C SA0000324C0
Hynix (900MHZ) 128MX16 H5TQ2G63BFR-11C SA00003YO00

ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
2
40.2_0402_1%
2
60.4_0402_1%
2
40.2K_0402_1%
2
40.2K_0402_1%
1K_0402_1%
@ RV45
HDMI@
Part 5 of 5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
@ RV32
Samsung (800MHZ) 64MX16 K4W1G1646G-BC12
RV60
10K_0402_1%
1
2
RV53
4.99K_0402_1%
1
2
RV59
15K_0402_1%
1
2
RV58
15K_0402_1%
1
2
RV52
15K_0402_1%
1
2
+3VS
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
2
10K_0402_1%
@ RV1

N12MR1@
+3VS
F7
G6
D6
C6
A6
A7
B6
B7
E6
E7
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
SERIAL
RV98
10K_0402_1%
1
2
RV97
10K_0402_1%
1
2
RV51
15K_0402_1%
1
2
RV50
34.8K_0402_1%
1
2
RV49
45.3K_0402_1%
1
2
B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E17
E20
E23
E26
H2
H5
J11
J14
J17
K9
K19
L2
L5
L11
L12
L13
L14
L15
L16
L17
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13
GND
NC
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
DBG
AB3
AB2
W1
V1
W3
W2
AA2
AA3
AB1
AA1
C15
D15
J5
GB1B-64 : PGOOD
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
UV1E
NC
NC
PGOOD
STRAP
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
GENERAL
+3VS
AC4
AD4
V5
V4
AA5
AA4
W4
Y4
AB4
AB5
LVDS / TMDS
19 LCD_TXCLK+
19 LCD_TXCLK19 LCD_TXOUT0+
19 LCD_TXOUT019 LCD_TXOUT1+
19 LCD_TXOUT119 LCD_TXOUT2+
19 LCD_TXOUT2-
SA00004HS00
Samsung (900MHZ) 128MX16 K4W2G1646C-HC11 SA000047Q00
Pull-up to +3VS
Pull-down to Gnd
5K
1000
0000
10K
1001
0001
15K
1010
0010
20K
1011
0011
25K
1100
0100
30K
1101
0101
35K
1110
0110
45K
1111
0111
512MB
0010
RV59 PD 15K
(SD034150280)
1GB
0110
RV59 PD 34.8K (SD034348280)
512MB
0011
RV59 PD 20K
1GB
0111
RV59 PD 45.3K (SD034453280)
(SD034200280)
X76
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
N12M LVDS,HDMI,DP,GND
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
14
of
53
0.022U_0402_25V7K
0.022U_0402_25V7K
0.022U_0402_25V7K
0.047U_0402_25V6K
SP_PLLVDD
L6
PLLVDD
K5

W>EZ'Wh
FB_PLLAVDD
FB_PLLAVDD
AC19
FB_DLLAVDD
T19
100mA
DACA_VDD
AG2
+DACA_VDD
DACB_VDD
W5
1
RV63
B15
+1.5V_MEM_VDDQ
IFPC_PLLVDD
FB_CAL_PD_VDDQ
IFPD_PLLVDD
VDD_SENSE
W15
VDD_SENSE
E15
20 mil
+FB_AVDD
R19
P6
100mA
1
1
CV82
1
CV83
LV2
SBK160808T-300Y-N_2P
1
+1.05VS_VCCP
add for GB1b-64
2
10K_0402_1%
2
RV65
1
40.2_0402_1%
add
+1.5V_MEM_GFX
VDD_SENSE 50
+1.05VS_VCCP
LV4
SBK160808T-121Y-N_2P
2
1
for GB1b-64
+PEX_PLLVDD
route as 50ohm
1

N12MR1@
+PLLVDD
RV20
10K_0402_5%
add for GB1b-64
CV91
4.7U_0603_6.3V6K
+1.05VS_VCCP
W>EZ'Wh
1
CV93
4.7U_0603_6.3V6K
CV92
1U_0402_6.3V6K
CV168
AF9 +PEX_PLLVDD
K6
IFPAB_PLLVDD
IFPE_PLLVDD
W>>K^dK>>
AG7
AF7
AE7
AD8
AD7
AC9
N6
D7
CV90
.1U_0402_16V7K
CV167
.1U_0402_16V7K
1U_0402_6.3V6K
CV171
4.7U_0603_6.3V6K
POWER
IFPE_IOVDD
CV79
10U_0603_6.3V6M
IFPCD_IOVDD
H6
CV78
22U_0805_6.3V6M
J6
10U_0603_6.3V6M
IFPB_IOVDD
1U_0402_6.3V6K
IFPA_IOVDD
+1.05VS_VCCP
AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7
VID_PLLVDD
PEX_SVDD_3V3
V2
+IFPAB_PLLVDD
+IFPE_PLLVDD
PEX_PLLVDD
V3
AD5
CV77
4.7U_0603_6.3V6K
+IFPE_IOVDD
+1.05VS_VCCP
LV10
SBK160808T-121Y-N_2P
2
1
AG9
+IFPAB_PLLVDD
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
1
CV54
CV165
.1U_0402_16V7K
+IFPAB_IOVDD
A12
B12
C12
D12
E12
F12
1
CV53
CV73
1U_0402_6.3V6K
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
N10M SPEC FBVDDQ TYP. 1.8V.
+1.5V_MEM_GFX
CV72
1U_0402_6.3V6K
CV69
.1U_0402_16V7K
CV81
CV80
.1U_0402_16V7K
4.7U_0603_6.3V6K

CV174
.1U_0402_16V7K
+3VS
CV166
.1U_0402_16V7K
CV172
1U_0402_6.3V6K
+IFPAB_IOVDD
CV175
4.7U_0603_6.3V6K
CV76
.1U_0402_16V7K
LV11
2
220R 100MHZ
PBY160808T-221Y-N_2P
1
CV68
.1U_0402_16V7K
+1.8VS
CV75
1U_0402_6.3V6K
CV74
4.7U_0603_6.3V6K
1
CV52
CV71
.1U_0402_16V7K
CV70
.1U_0402_16V7K
220R 100MHZ
LV1
PBY160808T-221Y-N_2P
+3.3V_RUN_VDD33
1
2
+3VS
+1.5V_MEM_GFX
CV67
22U_0805_6.3V6M
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
CV66
10U_0603_6.3V6M
CV65
4.7U_0603_6.3V6K
CV60
CV64
1U_0402_6.3V6K
under GPU
CV63
1U_0402_6.3V6K
CV59
CV62
.1U_0402_16V7K
CV61
.1U_0402_16V7K
CV58
CV43
1U_0402_6.3V6K
CV42
1U_0402_6.3V6K
1
CV44
CV51
.1U_0402_16V7K
1U_0402_6.3V6K
1
CV161
0.022U_0402_25V7K
0.022U_0402_25V7K
1
CV162
CV41
.1U_0402_16V7K
CV50
.1U_0402_16V7K
CV40
.1U_0402_16V7K
CV49
.1U_0402_16V7K
CV39
10U_0603_6.3V6M
CV48
4.7U_0603_6.3V6K
'Wh

CV47
1U_0402_6.3V6K
CV163
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22
CV46
0.01U_0402_25V7K
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
CV45
0.01U_0402_25V7K
CV164
@
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CV38
0.01U_0402_25V7K
C876
330U_2.5V_M_R17
22U_0603_6.3V6M
22U_0603_6.3V6M
J9
J10
J12
J13
L9
M9
M11
M17
N9
N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17
R9
R11
R12
R13
R14
R15
R16
R17
T9
T11
T17
U9
U19
W9
W10
W12
W13
W18
W19
W
Part 4 of 5
+VGA_CORE
0.047U_0402_25V6K
+VGA_CORE
NV DG for VDD Cap:

0.01uF 10% X7R x6
0.047uF 10% X7R x3
0.1uF 10% X7R x1
4.7uF 10% X5R x1
For GB1b-64 add:
4.7u X5R x1
UV1D
0.047U_0402_25V6K
+1.05VS_VCCP
+IFPE_IOVDD
0.1U_0402_16V4Z
220mA
LV8
2
1
BLM18PG181SN1D_0603
HDMI@
1U_0402_6.3V6K
0.1U_0402_16V4Z
+IFPE_PLLVDD
CV114
4.7U_0603_6.3V6K
add for GB1b-64
+DACA_VDD
CV113
4.7U_0603_6.3V6K
+3VS
300ohm 100MHz ESR0.25ohm
LV7
MMZ1608D301BT_2P
1
2
CV112
.1U_0402_16V7K
CV108
.1U_0402_16V7K
+3VS
4
CV110
.1U_0402_16V7K
CV109
.1U_0402_16V7K
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV170
HDMI@
CV181
10U_0603_6.3V6M
CV173
10K_0402_5%
NHDMI@
CV173
0.1U_0402_16V4Z
HDMI@
+PLLVDD
CV180
.1U_0402_16V7K

CV179
.1U_0402_16V7K
CV160
HDMI@
1
CV169
HDMI@
LV3
SBK160808T-300Y-N_2P
1
CV88
.1U_0402_16V7K
2
CV84
22U_0603_6.3V6M
285mA
CV87
.1U_0402_16V7K
+1.05VS_VCCP
LV12
2
1 4.7U_0603_6.3V6K
BLM18PG181SN1D_0603
HDMI@
1
add for GB1b-64

1
1
CV178
HDMI@
4.7U_0603_6.3V6K
1
CV159
HDMI@
1
CV176
HDMI@
0.1U_0402_16V4Z
1
CV182
HDMI@
CV215
0.1U_0402_16V4Z
HDMI@
CV215
10K_0402_5%
NHDMI@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
N12M Power
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
15
of
53
FBAD[0..63]
FBAD[0..63]
FBA_CMD[0..30]
DQSA_W P[0..7]
1
17,18
DQSA_RN[0..7]
17,18
DQSA_W P[0..7]
17,18
UV1B
Mode E - Mirror Mode Mapping
RV66
10K_0402_5%
FBA_CMD3
CKE_1
RV68
10K_0402_5%
FBA_CMD19
ODT_2
RV71
10K_0402_5%
FBA_CMD0
ODT_1
RV72
10K_0402_5%
FBA_CMD16
CKE_2
RV75
10K_0402_5%
FBA_CMD20
RST
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21
F21
D20
F20
D17
F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24
T23
R23
P24
P22
AC24
AB23
AB24
W24
AA22
W23
W22
V22
AA25
W27
W26
W25
AB25
AB26
AD26
AD27
V25
R25
V26
V27
R26
T25
N25
N26
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
MEMORY INTERFACE
Part 2 of 5
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
G24
F27
F25
F26
G26
G27
G25
J25
J24
H24
H22
J26
G22
G23
J22
J27
M24
L24
J23
K23
K22
M23
K24
M27
N27
M26
K26
K27
K25
M25
L22
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
C26
B19
D19
D23
T24
AA23
AB27
T26
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
D25
A18
E18
B24
R22
Y24
AA27
R27
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
C25
A19
E19
A24
T22
AA24
AA26
T27
DQSA_W P0
DQSA_W P1
DQSA_W P2
DQSA_W P3
DQSA_W P4
DQSA_W P5
DQSA_W P6
DQSA_W P7
FB_VREF
A16
+FB_VREF
FBA_CLK0
FBA_CLK0_N
F24
F23
FBA_CLK1
FBA_CLK1_N
N24
N23
FBA_DEBUG
M22
1
RV76
PAD~D TV6@
DATA Bus
PAD~D TV5@
Address
0..31
CMD0
ODT_L
CMD1
CS1#_L
CMD2
CS0#_L
CMD3
CKE_L
CMD4
A9
A11
CMD5
A6
A7
CMD6
A3
BA1
CMD7
A0
A12
CMD8
A8
A8
CMD9
A12
A0
CMD10
A1
A2
CMD11
RAS#
RAS#
CMD12
A13
A14
CMD13
BA1
A3
CMD14
A14
A13
CMD15
CAS#
CAS#
CMD16
CKE_H
CMD17
CS1#_H
CMD18
CS0#_H
CMD19
CLKA0
CLKA0#
17
17
CLKA1
CLKA1#
18
18
32..63
ODT_H
CMD20
RST
RST
CMD21
A7
A6
CMD22
A4
A5
CMD23
A11
A9
CMD24
A2
A1
CMD25
A10
WE#
CMD26
A5
A4
CMD27
BA2
A15
CMD28
WE#
A10
CMD29
BA0
BA0
CMD30
A15
BA2
2
+1.5V_MEM_GFX
10K_0402_5%

N12MR1@
RV77
16mil
+FB_VREF
CV128
0.01U_0402_25V7K
RV78
@
1.1K_0402_1%
1.1K_0402_1%
+1.5V_MEM_GFX
DQMA#[0..7] 17,18
DQSA_RN[0..7]
17,18
FBA_CMD[0..30]
DQMA#[0..7]
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
N12M MEM Interface

Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
16
of
53
Memory Partition A - Lower 32 bits

FBA_CMD[0..30]
16mil
16mil
UV4
+1.5V_MEM_GFX
CV129
0.01U_0402_25V7K
RV79
1.1K_0402_1%
+FBA_VREF0
M8
H1
FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14
FBA_CMD30
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
FBA_CMD29
FBA_CMD13
FBA_CMD27
M2
N8
M3
FBA_CMD3
J7
K7
K9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
16
16
CLKA0
CLKA0#
RV81
243_0402_1%
BA0
BA1
BA2
CLKA0#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA_W P0
DQSA_W P2
F3
C7
DQSL
DQSU
DQMA#0
DQMA#2
E7
D3
DQSA_RN0
DQSA_RN2
G3
B7
DML
DMU
DQSL
DQSU
RESET
L8
ZQ/ZQ0
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD17
FBAD21
FBAD19
FBAD20
FBAD18
FBAD22
FBAD16
FBAD23
Group0
Group2
+FBA_VREF0
M8
H1
FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14
FBA_CMD30
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
FBA_CMD29
FBA_CMD13
FBA_CMD27
M2
N8
M3
CLKA0
CLKA0#
FBA_CMD3
J7
K7
K9
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
FBA_CMD0
FBA_CMD2
FBA_CMD11
FBA_CMD15
FBA_CMD28
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA_W P3
DQSA_W P1
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#3
DQMA#1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
E7
D3
DQSA_RN3
DQSA_RN1
G3
B7
FBA_CMD20
CK
CK
CKE/CKE0
DML
DMU
DQSL
DQSU
RESET
L8
ZQ/ZQ0
E3
F7
F2
F8
H3
H8
G2
H7
FBAD30
FBAD24
FBAD31
FBAD28
FBAD29
FBAD26
FBAD25
FBAD27
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD14
FBAD10
FBAD15
FBAD11
FBAD12
FBAD8
FBAD13
FBAD9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
J1
L1
J9
L9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
K4W 1G1646E-HC12_FBGA96
@
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
DQSA_W P[0..7]
DATA Bus
CV143
.1U_0402_16V7K
CV142
.1U_0402_16V7K
CV141
.1U_0402_16V7K
CV140
.1U_0402_16V7K
CV139
.1U_0402_16V7K
CV138
1U_0402_6.3V6K
CV137
1U_0402_6.3V6K
CV4
1U_0402_6.3V6K
CV3
1U_0402_6.3V6K
16,18
96-BALL
SDRAM DDR3
@
CV136
.1U_0402_16V7K
CV135
.1U_0402_16V7K
CV134
.1U_0402_16V7K
CV133
.1U_0402_16V7K
CV132
.1U_0402_16V7K
CV131
1U_0402_6.3V6K
CV130
1U_0402_6.3V6K
CV2
1U_0402_6.3V6K
CV1
1U_0402_6.3V6K
16,18
DQSA_W P[0..7]
Group1
+1.5V_MEM_GFX
DQSA_RN[0..7]
Group3
+1.5V_MEM_GFX
16,18
16,18
DQMA#[0..7] 16,18
DQSA_RN[0..7]
+1.5V_MEM_GFX
BA0
BA1
BA2
T2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
T2
FBAD1
FBAD6
FBAD0
FBAD7
FBAD3
FBAD5
FBAD2
FBAD4
RV83
243_0402_1%
RV82
243_0402_1%
FBA_CMD20
CK
CK
CKE/CKE0
FBA_CMD0
FBA_CMD2
FBA_CMD11
FBA_CMD15
FBA_CMD28
E3
F7
F2
F8
H3
H8
G2
H7
+1.5V_MEM_GFX
CLKA0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
FBAD[0..63]
DQMA#[0..7]
UV3
VREFCA
VREFDQ
RV80
1.1K_0402_1%
+FBA_VREF0
FBA_CMD[0..30]
FBAD[0..63]
Address
0..31
CMD0
ODT_L
32..63
CMD1
CS1#_L
CMD2
CS0#_L
CMD3
CKE_L
CMD4
A9
A11
CMD5
A6
A7
CMD6
A3
BA1
CMD7
A0
A12
CMD8
A8
A8
CMD9
A12
A0
CMD10
A1
A2
CMD11
RAS#
RAS#
CMD12
A13
A14
CMD13
BA1
A3
CMD14
A14
A13
CMD15
CAS#
CAS#
CMD16
CKE_H
CMD17
CS1#_H
CMD18
CS0#_H
CMD19
ODT_H
CMD20
RST
RST
CMD21
A7
A6
CMD22
A4
A5
CMD23
A11
A9
CMD24
A2
A1
CMD25
A10
WE#
CMD26
A5
A4
CMD27
BA2
A15
CMD28
WE#
A10
CMD29
BA0
BA0
CMD30
A15
BA2
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
N12M VRAM
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
17
of
53
Memory Partition A - Upper 32 bits

16mil
16mil
FBAD[0..63]
UV6
FBAD[0..63]
UV5
+FBA_VREF1
+FBA_VREF1
M8
H1
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12
FBA_CMD27
CV144
0.01U_0402_25V7K
+FBA_VREF1
RV85
1.1K_0402_1%
RV84
1.1K_0402_1%
+1.5V_MEM_GFX
FBA_CMD29
FBA_CMD6
FBA_CMD30
16
16
CLKA1
CLKA1#
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBAD35
FBAD32
FBAD38
FBAD33
FBAD37
FBAD34
FBAD39
FBAD36
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD42
FBAD46
FBAD40
FBAD45
FBAD44
FBAD43
FBAD41
FBAD47
Group4
Group5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
BA0
BA1
BA2
FBA_CMD16
J7
K7
K9
CK
CK
CKE/CKE0
FBA_CMD19
FBA_CMD18
FBA_CMD11
FBA_CMD15
FBA_CMD25
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA_W P4
DQSA_W P5
F3
C7
DQMA#4
DQMA#5
E7
D3
DQSA_RN4
DQSA_RN5
G3
B7
DQSL
DQSU
FBA_CMD20
T2
RESET
L8
ZQ/ZQ0
DQSL
DQSU
1
2
RV86
243_0402_1%
FBA_CMD29
FBA_CMD6
FBA_CMD30
M2
N8
M3
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
J7
K7
K9
CK
CK
CKE/CKE0
FBA_CMD19
FBA_CMD18
FBA_CMD11
FBA_CMD15
FBA_CMD25
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA_W P7
DQSA_W P6
F3
C7
DQSL
DQSU
DQMA#7
DQMA#6
E7
D3
DML
DMU
DQSA_RN7
DQSA_RN6
G3
B7
FBA_CMD20
T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD51
FBAD52
FBAD49
FBAD53
FBAD48
FBAD54
FBAD50
FBAD55
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
FBA_CMD[0..30]
J1
L1
J9
L9
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
DQSA_W P[0..7]
DQSA_RN[0..7]
16,17
DQSA_W P[0..7]
16,17
Group6

DATA Bus
CV158
.1U_0402_16V7K
CV157
.1U_0402_16V7K
CV156
.1U_0402_16V7K
CV155
.1U_0402_16V7K
CV154
.1U_0402_16V7K
CV153
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV8
1U_0402_6.3V6K
CV7
1U_0402_6.3V6K
CV151
.1U_0402_16V7K
CV150
.1U_0402_16V7K
CV149
.1U_0402_16V7K
CV148
.1U_0402_16V7K
CV147
.1U_0402_16V7K
16,17
DQMA#[0..7] 16,17
DQSA_RN[0..7]
Group7
16,17
FBA_CMD[0..30]
DQMA#[0..7]
+1.5V_MEM_GFX
CV146
1U_0402_6.3V6K
CV145
1U_0402_6.3V6K
CV6
1U_0402_6.3V6K
CV5
1U_0402_6.3V6K
FBAD61
FBAD57
FBAD58
FBAD60
FBAD56
FBAD62
FBAD59
FBAD63
96-BALL
SDRAM DDR3
@
+1.5V_MEM_GFX
E3
F7
F2
F8
H3
H8
G2
H7
+1.5V_MEM_GFX
BA0
BA1
BA2
CLKA1
CLKA1#
FBA_CMD16
96-BALL
SDRAM DDR3
@
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DML
DMU
J1
L1
J9
L9
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
RV88
243_0402_1%
RV87
243_0402_1%
CLKA1#
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12
FBA_CMD27
VREFCA
VREFDQ
+1.5V_MEM_GFX
CLKA1
M8
H1
Address
0..31
CMD0
ODT_L
32..63
CMD1
CS1#_L
CMD2
CS0#_L
CMD3
CKE_L
CMD4
A9
A11
CMD5
A6
A7
CMD6
A3
BA1
CMD7
A0
A12
CMD8
A8
A8
CMD9
A12
A0
CMD10
A1
A2
CMD11
RAS#
RAS#
CMD12
A13
A14
CMD13
BA1
A3
CMD14
A14
A13
CMD15
CAS#
CAS#
CMD16
CKE_H
CMD17
CS1#_H
CMD18
CS0#_H
CMD19
ODT_H
CMD20
RST
RST
CMD21
A7
A6
CMD22
A4
A5
CMD23
A11
A9
CMD24
A2
A1
CMD25
A10
WE#
CMD26
A5
A4
CMD27
BA2
A15
CMD28
WE#
A10
CMD29
BA0
BA0
CMD30
A15
BA2
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
N12P VRAM
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
18
of
53
+LCD_VDD
+3VS
Reserve for EMI request
USB20_N11
+3VS
USB20_P11_R
W=80mils
2
25
R108
100K_0402_5%
USB20_P11
R107
150_0603_5%
25
1 @
2
R78
0_0402_5%
L55
CAM@
1 1
2 2
C229
0.01U_0402_25V7K
Q1B
VGA_ENVDD
Q17
AO3413_SOT23
+LCD_VDD
W=80mils
2
1
13
1
R109 2LCDPW R_GATE
1
47K_0402_5%
1
2
0_0402_5%
1 @
R96
C228
0.1U_0402_16V7K
Q1A
2
USB20_N11_R
W CM-2012-900T_0805
8/20 Swap USB20_P11 and USB20_N11 for layout request
C233
0.1U_0402_16V4Z
R112
100K_0402_5%
LCD/PANEL BD. Conn.
JLVDS
31
32
33
34
G1
G2
G3
G4
CAM@
W=20mils
0.1U_0402_16V4Z
2
1 +3VS_LVDS_CAM 2 CAM@ 1
C225
0_0603_5%
R388
Pin13 GND for EMI , But Cable is NC
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D84 @
USB20_N11_R
USB20_P11_R
2
1
3
INT_MIC_CLK
INT_MIC_DATA
+LCD_VDD_R
LCD_EDID_CLK
LCD_EDID_DATA
INT_MIC_CLK 36
INT_MIC_DATA 36
+3VS
LCD_EDID_CLK 13
LCD_EDID_DATA 13
For EMI
1
@
C231
680P_0402_50V7K
2
LCD_TXOUT0- 14
LCD_TXOUT0+ 14
LCD_TXOUT1- 14
LCD_TXOUT1+ 14
LCD_TXOUT2- 14
LCD_TXOUT2+ 14
VGA_D_PW M
BKOFF#_R
PACDN042Y3R_SOT23-3
LCD_TXCLK- 14
LCD_TXCLK+ 14
1
R120
D2
1
C232
0.1U_0402_16V4Z
2
47K_0402_5%
2
VGA_PW M 13
RB751V40_SC76-2
1 D1
2
RB751V40_SC76-2
1
2
R113
10K_0402_5%
BKOFF# 38
1.5A
+LCD_VDD_R
2 L15
1
0_0805_5%
+LCD_INV
ACES_88341-3001
1
B+
Rated Current MAX:600mA

1
C234
68P_0402_50V8J
2
L2
2
1
FBMA-L11-201209-221LMA30T_0805
+LCD_VDD
1
C226
0.1U_0402_16V4Z
C227
4.7U_0805_10V4Z
C235
0.1U_0402_25V6
2
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
LVDS/eDP
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
19
of
53
D4
D5
CRT CONNECTOR
D3
+3VS
If=1A
+5VS
+CRT_VCC_R
+CRT_VCC
D6
DAN217_SC59
F1
DAN217_SC59
DAN217_SC59
1
1
RB491D_SOT23-3
VGA_CRT_R
L3
2 NBQ100505T-800Y_0402
CRT_R_L
VGA_CRT_G
L4
2 NBQ100505T-800Y_0402
CRT_G_L
13 VGA_CRT_B
L5
2 NBQ100505T-800Y_0402
13
13
40 mils
2
1
1.1A_6V_MINISMDC110F-2
C237
0.1U_0402_16V4Z
2
@
CRT_B_L
JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
C241
1
C242
1
C243
CRT_R_L
2.2P_0402_50V8C
C240
2.2P_0402_50V8C
C239
2.2P_0402_50V8C
C238
2.2P_0402_50V8C
2.2P_0402_50V8C
2
1
150_0402_1%
2
1
150_0402_1%
2
1
150_0402_1%
2.2P_0402_50V8C
T76 PAD
R138 R139 R140
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+CRT_VCC
VSYNC
T77 PAD
CRT_DDC_CLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
ALLTO_C10532-11505-L_15P-T
2
+CRT_VCC
2
0.1U_0402_16V4Z
2
R141
1
10K_0402_5%
D_CRT_HSYNC
1
L6
2
10_0402_5%
D_CRT_VSYNC
1
L7
2
10_0402_5%
+CRT_VCC
HSYNC
5
1
13 VGA_CRT_VSYNC
U7
SN74AHCT1G125GW _SOT353-5
C245
@
VSYNC
1
C246
@
10P_0402_50V8J
U6
SN74AHCT1G125GW _SOT353-5
10P_0402_50V8J
P
OE#
13 VGA_CRT_HSYNC
P
OE#
5
1
1
C244
+CRT_VCC
+3VS
1
5
13 VGA_CRT_CLK
Q205B
4
13 VGA_CRT_DATA
1
C282
33P_0402_50V8K
2
@
Q205A
R159
4.7K_0402_5%
R153
4.7K_0402_5%
CRT_DDC_CLK
6
CRT_DDC_DAT
C284
470P_0402_50V8J
C285
@
33P_0402_50V8K
2 @
C283
470P_0402_50V8J
2 @
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
CRT
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
20
of
53
U2A
iME Setting.
R293 1
20K_0402_5%
NC
OSC
NC
OSC
32.768KHZ_12.5PF_Q13MC14610002
2
1
C205
15P_0402_50V8J
@
2
C248 2
1U_0402_6.3V6K
1
15P_0402_50V8J
36 AZ_BITCLK_HD
36
+RTCVCC
R286 1
2 33_0402_5%
PCH_SPKR
36 AZ_RST_HD#
R142 1
2 33_0402_5%
R118 1
+3VS
PCH_SPK
High = Enabled (No Reboot)
Low = Disabled (Default)
1
R276
PCH_SPKR
2
1K_0402_5%
RTCX1
C20
RTCX2
PCH_RTCRST#
D20
RTCRST#
PCH_SRTCRST#
G22
SRTCRST#
SM_INTRUDER#
K22
INTRUDER#
PCH_INTVRMEN
C17
INTVRMEN
+3VALW
36 AZ_SDOUT_HD
2
R273
N34
HDA_BCLK
AZ_SYNC
L34
HDA_SYNC
PCH_SPKR
T10
SPKR
AZ_RST#
K34
HDA_RST#
R289 1
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
1
1K_0402_5%
2 33_0402_5%
AZ_SDOUT
HDA_SDIN3
A36
HDA_SDO
+3VALW
1
R560
38 PW RME_CTRL#
CR_CPPE#
2
10K_0402_5%
R580 1
2 0_0402_5%
CR_CPPE#
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS
HDA_SDO
ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)
HDA_SYNC
signal has a weak internal pull

*This
H=>On Die PLL is supplied by 1.5V
JTAG_TCK
T37 PAD
PCH_JTAG_TMS
H7
JTAG_TMS
T38 PAD
PCH_JTAG_TDI
K5
JTAG_TDI
T39 PAD
PCH_JTAG_TDO
H1
JTAG_TDO
PCH_SPICLK
T3
PCH_SPICS#
Y14
SPI_CS0#
SPI_CLK
FWH4 / LFRAME#
D36
LPC_FRAME#
LDRQ0#
LDRQ1# / GPIO23
E36
K36
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
Y11
SATAICOMPI
Y10
SATA3RCOMPO
AB12
SATA3COMPI
AB13
SATA3RBIAS
HDD
SATA_PRX_C_DTX_N2 31
SATA_PRX_C_DTX_P2 31
SATA_PTX_DRX_N2 31
SATA_PTX_DRX_P2 31
ODD
+3VS
2
R136
1
10K_0402_5%
+3VS
SATA_LED#
R336 2
1 10K_0402_5%
CR_W AKE#
R334 2
1 10K_0402_5%
PCH_GPIO19
R335 1
2 10K_0402_5%
SATAICOMP
1
R279
2
37.4_0402_1%
+1.05VS_VCC_SATA
SATA3_COMP
1
R280
2
49.9_0402_1%
+1.05VS_SATA3
1
R281
2
750_0402_1%
AH1
RBIAS_SATA3
P3
SATA_LED#
SPI_MOSI
SATA0GP / GPIO21
V14
CR_W AKE#
PCH_SPIDO
U3
SPI_MISO
SATA1GP / GPIO19
P1
PCH_GPIO19
COUGARPOINT_FCBGA989~D
SATA_PTX_DRX_N0 31
SATA_PTX_DRX_P0 31
SERIRQ
SPI_CS1#
for EMI
SERIRQ 38,39
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
T1
SATALED#
38,39
38,39
38,39
38,39
LPC_FRAME# 38,39
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
AM3
AM1
AP7
AP5
SATAICOMPO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SERIRQ
V5
V4
AZ_SYNC
1
1K_0402_5%
2
R284
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PCH_SPIDI
down
L=>On Die PLL is supplied by 1.8V

Need to pull high for Huron River platform
+3VALW
J3
JTAG
PCH_JTAG_TCK
SPI
C38
A38
B37
C37
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
SERIRQ
AZ_BITCLK
AZ_SDIN0_HD
36 AZ_SDIN0_HD
SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
A20
PCH_RTCX2
Integrated SUS 1.05V VRM Enable

High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
R117 1
PCH_RTCX1
LPC
JME
1
2PCH_SRTCRST#
2
C216
Y3
SATA 6G
C247 2
1U_0402_6.3V6K
SATA
JCOMS @
1
2
PCH_RTCRST#
RTC
IHDA
R292 1
20K_0402_5%
R291
10M_0402_5%
2
1
CMOS Setting, near DDR Door

+RTCVCC
PCH_GPIO19 25
BOOT BIOS Strap Bit 0
HM65R1@
+5VS
3
+3VALW
+3VS
8
7
6
5
PCH_SPICLK
PCH_SPIDI
PCH_SPICLK
0.1U_0402_16V4Z
1
R355
R397
10_0402_5%
@
PCH_JTAG_TCK
2
51_0402_1%
W 25Q32BVSSIG_SO8
C494
R301
100_0402_1%
R295
100_0402_1%
1
VCC
HOLD#
CLK
DI
PCH_JTAG_TDI
CS#
DO
WP#
GND
U13
1
2
3
4
PCH_JTAG_TDO
R306
100_0402_1%
@ JRTC
LOTES_AAA-BAT-054-K01
PCH_SPICS#
PCH_SPIDO
PCH_JTAG_TMS
BAV70W _SOT323-3
R278
200_0402_5%
R330
200_0402_5%
R363
200_0402_5%
+3VL
2
1
R277 1K_0402_5%
2
C486
0.1U_0402_16V4Z
+3VALW
3
1
1
4M Byte
+3VALW
+RTCBATT
D13
+RTCVCC
RTC schematic for non-chargeable
BSS138_NL_SOT23-3
@
1
2
R285
0_0402_5%
2
1M_0402_5%
Q21
1
1
R125
36 AZ_SYNC_HD
AZ_SYNC_R
2
33_0402_5%
1
R156
C86
10P_0402_50V8J
@
Socket: SP07000F500/SP07000H900
Compal Secret Data
Please close to U2 PCH

8/30 Change U13 from SA000021A00 to SA00003IN00 due to EOL of SA000021A00
0812 -> Add R277 for RTC reserve charge
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_HDA/JTAG/SATA/SPI/LPC
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
21
of
53
U2B
PERN2
PERP2
PETN2
PETP2
+3VS
R287 1
2 10K_0402_5% CLKREQ_JET#
R338 1
2 10K_0402_5% CLKREQ_W LAN#
35
35
35
35
USB30
PCIE_PRX_C_USBTX_N6
PCIE_PRX_C_USBTX_P6
PCIE_PTX_C_USBRX_N6
PCIE_PTX_C_USBRX_P6
C519 1
C869 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_C_USBTX_N6
PCIE_PRX_C_USBTX_P6
PCIE_PTX_USBRX_N6
PCIE_PTX_USBRX_P6
+3VALW
R343 1
210K_0402_5%
CLKREQ_LAN#
R344 1
210K_0402_5%
PCH_GPIO26
R345 1
210K_0402_5%
CLKREQ_CR#
R346 1
210K_0402_5% CLKREQ_USB30#
R348 1
210K_0402_5%
PANEL_SEL
R351 1
210K_0402_5%
PASSW ORD_CLEAR#
33
33
LAN
CLK_LAN#
CLK_LAN
CLK_LAN#
CLK_LAN
CLKREQ_LAN#
33 CLKREQ_LAN#
R584 1 @
2 10K_0402_5%
PANEL_SEL
R564 1 @
2 10K_0402_5%
LVDS_SEL
WLAN
32
32
BG36
BJ36
AV34
AU34
PERN3
PERP3
PETN3
PETP3
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
Y40
Y39
J2
CLK_W LAN# AB49

CLK_W LAN AB47
CLK_W LAN#
CLK_W LAN
CLKREQ_W LAN#
32 CLKREQ_W LAN#
M1
AA48
AA47
CLKREQ_JET#
LVDS_SEL
LVDS_SEL
Channel
Single
(Default)
Dual
CLKREQ_CR#
PCH_GPIO26
PANEL_SEL
PANEL_SEL
LVDS
EDP
CLK_USB30#
CLK_USB30
35 CLK_USB30#
35 CLK_USB30
Please place under

DDR SODIMM.
10/25
JPW
@
10 CLK_RES_ITP#
10 CLK_RES_ITP
5 CLK_CPU_ITP#
5 CLK_CPU_ITP
4
R233
R282
2
2
R352
R353
2
2
@
@
C9
PCH_SMBDATA
1 2.2K_0402_5%
EC_LID_OUT# 38
PCH_SMBDATA
G12
SML0DATA
SML1ALERT# / PCHHOT# / GPIO74
C13
PCH_GPIO74
SML1CLK / GPIO58
E14
PCH_SMLCLK1
M16
PCH_SMLDATA1
CL_DATA1
T11
CL_RST1#
P10
M10
CLKOUT_PCIE4N
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
2 R364
1 2.2K_0402_5%
2 R385
1 2.2K_0402_5%
+3VS
Q4B
PCH_SMLDATA1
4
EC_SMB_DA2 13,38
3
Q4A
EC_SMB_CK2 13,38
Control Link only for support Intel IAMT.
EC_LID_OUT#
R123 1
2 10K_0402_5%
DRAMRST_CNTRL_PCH
R228 1
2 1K_0402_5%
PCH_GPIO74
R234 1
2 10K_0402_5%
PCH_SMLCLK0
R238 1
2 10K_0402_5%
PCH_SMLDATA0
R239 1
R23
2 CLK_REQ_VGA# @ R251 1
2 10K_0402_5%
CLK_REQ_VGA#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
AB37
AB38
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM12
AM13
CLK_DPLL#
CLK_DPLL
CLKIN_DMI_N
CLKIN_DMI_P
BF18
BE18
PCH_CLK_DMI#
PCH_CLK_DMI
CLKIN_GND1_N CLKIN_DMI2_N
CLKIN_GND1_P CLKIN_DMI2_P
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
CLKIN_DOT_96N
CLKIN_DOT_96P
G24
E24
CLK_DOT#
CLK_DOT
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
AK7
AK5
CLK_SATA#
CLK_SATA
Y43
Y45
PM_SMBCLK 11,12,32
+3VALW
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PM_SMBDATA 11,12,32
M7
CL_CLK1
Y37
Y36
Q3A
1
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCH_SMLCLK1
CLKOUT_PCIE0N
CLKOUT_PCIE0P
4.7K_0402_5%
4.7K_0402_5%
PCH_SMLDATA0
+3VALW
SML1DATA / GPIO75
R400
R386
A12 DRAMRST_CNTRL_PCH
7
DRAMRST_CNTRL_PCH
PCH_SMLCLK0
C8
SML0CLK
+3VS
Q3B
PCH_SMBCLK
V45
V46
AB42
AB40
E6
V40
V42
2
R347 1
PCH_SMBCLK
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLK_PCIE_VGA# 13
CLK_PCIE_VGA 13
T13
T14
PAD
PAD
2 10K_0402_5%
10K_0402_5%
CLK_CPU_DMI# 5
CLK_CPU_DMI 5
120 MHz for eDP
PCH_CLK_DMI#
PCH_CLK_DMI
R242 1
R243 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_GND1#
CLKIN_GND1
R244 1
R245 1
2 10K_0402_5%
2 10K_0402_5%
CLK_DOT#
CLK_DOT
R246 1
R247 1
2 10K_0402_5%
2 10K_0402_5%
CLK_SATA#
CLK_SATA
R248 1
R249 1
2 10K_0402_5%
2 10K_0402_5%
CLK_14M_PCH
R250 1
2 10K_0402_5%
From Clock Gen.

For EMI
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
REFCLK14IN
K45
CLK_14M_PCH
CLKIN_PCILOOPBACK
H45
CLK_PCILOOP
XTAL25_IN
XTAL25_OUT
V47
V49
PCH_X1
PCH_X2
2 10K_0402_5%
LVDS_SEL
1 0_0402_5%
1 0_0402_5%
PANEL_SEL
1 0_0402_5%
1 0_0402_5%
CLK_BCLK_ITP#
CLK_BCLK_ITP
XCLK_RCOMP
Y47
XCLK_RCOMP 1
R354
CLKOUT_PCIE6N
CLKOUT_PCIE6P
1
2
10_0402_5% C474
1
22P_0402_50V8J
CLK_PCILOOP 25
2
90.9_0402_1%
+1.05VS_VCCDIFFCLKN
T13
CLKOUT_PCIE7N
CLKOUT_PCIE7P
K12
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
PCH_X1
CLKOUTFLEX2 / GPIO66
H47
1 @ R578 2
22_0402_5%
PCH_48MCLK 1
R576 2
22_0402_5%
CLK_FLEX2
T31
PAD
K49
CLK_FLEX3
K43
F47
CLK_FLEX0
48MCLK_USB30 35
48MCLK_CR 34
@
1
2 CLK_27M
R38 0_0402_5%
HM65R1@
C506
27P_0402_50V8J
1 1M_0402_5%
2010/09/03
Issued Date
PCH_X2
25MHZ_20PF_7A25000012 1
C507
27P_0402_50V8J
Near PCH
Deciphered Date

2012/12/31
C
CLK_27M 13
Compal Secret Data
A
B

.
R365 2
Y2
V38
V37
AK14
AK13
CLK_PCILOOP 2
@
R417
PEG_B_CLKRQ# / GPIO56
PASSW ORD_CLEAR#
+3VALW
H14
SML0ALERT# / GPIO60
CLKREQ_USB30#
L14 PCIECLKRQ5# / GPIO44
35 CLKREQ_USB30#
Channel
SMBCLK
1 2.2K_0402_5%
2 R260
USB30
EC_LID_OUT#
SMBDATA
V10
A8
SMBALERT# / GPIO11
E12
2 R232
BE34
BF34
BB32
AY32
Link
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PCIE_PRX_W LANTX_N2
PCIE_PRX_W LANTX_P2
PCIE_PTX_W LANRX_N2
PCIE_PTX_W LANRX_P2
SMBUS
C501 2
C502 2
PERN1
PERP1
PETN1
PETP1
+3VALW
Controller
WLAN
PCIE_PRX_W LANTX_N2
PCIE_PRX_W LANTX_P2
PCIE_PTX_C_W LANRX_N2
PCIE_PTX_C_W LANRX_P2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
BG34
BJ34
AV32
AU32
FLEX CLOCKS
32
32
32
32
C498 2
C497 2
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
CLOCKS
LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
PCI-E*
33
33
33
33
Title
PCH_PCI-E/SMBUS/CLK
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
22
of
53
U2C
PCH_RSMRST#
1
10K_0402_5%
PM_PW ROK
1
10K_0402_5%
SYS_PW ROK
1
10K_0402_5%
0_0402_5%
1 @ R259 2
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
6
6
6
6
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
6
6
6
6
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
6
6
6
6
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BJ24
DMI_ZCOMP
FDI_FSYNC0
BG25
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
BH21
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
DSW VREN
DPWROK
E22
PCH_DPW ROK
VGATE
PM_PW ROK
RBIAS_CPY
2
750_0402_1%
PAD
T34
SUSACK#
C12
XDP_DBRESET#
5 XDP_DBRESET#
U12
IN1
SUSACK#
K3
SYS_RESET#
SYS_PW ROK
P12
SYS_PWROK
IN2
5,38 PM_PW ROK
1
R160
5,38,49
DMI_COMP
2
49.9_0402_1%
0.1U_0402_16V4Z
1
2
C250
1
R130
8/30 Reserve R259 For cost down plan
+3VS
PM_PW ROK
SN74AHC1G08DCKR_SC70-5
1
R216
PM_PW ROK_R
2
0_0402_5%
L22
PWROK
L10
5 DRAMPW ROK
SUSACK#
@
2
R137
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
FDI_INT
+1.05VS_PCH
System Power Management
2
R127
2
R128
2
R129
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI
DRAMPW ROK
1
200_0402_5%
PCH_SUSPW RDN_R
1
10K_0402_5%
RI#
1
10K_0402_5%
PCH_LOW _BAT#
1
10K_0402_5%
2
R316
2
R218
2
R220
2
R221
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
+3VALW
1
6
6
6
6
1 PCH_SUSPW RDN_R
0_0402_5%
38 PCH_RSMRST#
Stuff R137 if EC does not want to

involve in the handshake mechanism
for the DeepSX state entry and exit
1
R320
38 PCH_SUSPW RDN
5,38 PBTN_OUT#
+3VALW
1
R469
2
330K_0402_5%
D12
38,44
ACIN
EC_SW I#
CLKRUN# / GPIO32
N3
PM_GPIO32
G8
SUS_STAT#
SUS_STAT# / GPIO61
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
6
6
6
6
6
6
6
6
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
R224
R225
1 330K_0402_5%
@
1 330K_0402_5%
EC_SW I# 33,35
DSWVREN must be always pulled high to +RTCVCC

T17
PAD
32.768 KHz
SLP_S4#
H4
PM_SLP_S4#
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#
F4
PM_SLP_S3#
SLP_A#
G10
PM_SLP_A#
T35
PAD
T58
PAD
RSMRST#
Stuff R222 if do not support DeepSX state
DSW VREN
SLP_S5# / GPIO63
DRAMPWROK
PCH_RSMRST#
2
0_0402_5%
1
R222
+RTCVCC
PM_SLP_S5#
C21
PCH_DPW ROK
6
FDI_FSYNC1
D10
PCH_RSMRST#
FDI_FSYNC0
SUSCLK / GPIO62
APWROK
B13
CLK_EC 38
DSWVREN - Internal Deep Sleep 1.05V regulator

H Enable
L Disable
PM_SLP_S5# 38
+3VS
PM_SLP_S4# 38
PM_GPIO32
PBTN_OUT#
E20
PWRBTN#
PCH_ACIN
H20
ACPRESENT / GPIO31
SLP_SUS#
G16
PM_SLP_SUS#
PCH_LOW _BAT#
E10
BATLOW# / GPIO72
PMSYNCH
AP14
H_PM_SYNC
RI#
A10
K14
PCH_GPIO29
R313 1
2 8.2K_0402_5%
PM_SLP_S3# 38
8/18 Change Net name from PM_CLKRUN# to

PCH_GPIO32 by HW Review demand
+3VALW
3
2
RB751V40_SC76-2
B9
6
6
6
6
6
6
6
6
N14
DRAMPW ROK
2 PCH_SUSPW RDN_R K16

0_0402_5%
WAKE#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
RI#
SLP_LAN# / GPIO29
H_PM_SYNC
EC_SW I#
R319 1
2 10K_0402_5%
PCH_GPIO29
R563 1 @
2 10K_0402_5%
HM65R1@
H_PM_SYNC
9/1
C898
1
@
2 220P_0402_50V7K
Reserve C894 for ESD requset
D16
PM_PW ROK
PCH_RSMRST#
RB751V40_SC76-2
D14
43,45
POK
2
RB751V40_SC76-2
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_DMI/FDI/PM
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
23
of
53
U2D
J47
M45
+3VS
2
R471
LCTL_CLK
1
2.2K_0402_5%
2
R472
LCTL_DATA
1
2.2K_0402_5%
2
R311
CRT_IREF
1
1K_0402_0.5%
T45
P39
L_CTRL_CLK
L_CTRL_DATA
AF37
AF36
LVD_IBG
LVD_VBG
AE48
AE47
LVD_VREFH
LVD_VREFL
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
M47
M49
CRT_HSYNC
CRT_VSYNC
T43
T42
DAC_IREF
CRT_IRTN
SDVO_TVCLKINN
SDVO_TVCLKINP
AP43
AP45
SDVO_STALLN
SDVO_STALLP
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
SDVO_CTRLCLK
SDVO_CTRLDATA
Digital Display Interface
LVDS_IBG
2
2.37K_0402_1%
T40 PAD
L_DDC_CLK
L_DDC_DATA
LVDS
1
R219
L_BKLTCTL
T40
K47
AT49
AT47
AT40
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
100K_0402_5%
1
R1433
P46
P42
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
P38
M39
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPC_CTRLCLK
DDPC_CTRLDATA
CRT
LCTL_CLK
LCTL_DATA
L_BKLTEN
L_VDD_EN
P45
R473 2
1 100K_0402_5%
2
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
R524 2
1 100K_0402_5%
HM65R1@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_CRT/LVDS
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
24
of
53
U2E
8/23 PIN swap for layout request
8
7
6
5
PCH_GPIO52
PCH_GPIO53
PCH_GPIO54
RF_OFF#
1
2
3
4
8.2K_0804_8P4R_5%
RP3
8
7
6
5
PCH_GPIO50
PCI_PIRQB#
ODD_DA#
W L_OFF#
1
2
3
4
8.2K_0804_8P4R_5%
B21
M20
AY16
BG46
PCH_GPIO5
2
8.2K_0402_5%
PCI_PIRQD#
2
8.2K_0402_5%
1
R321
1
R322
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
Boot BIOS Strap

RF_OFF#
PCH_GPIO19
LPC
0
1
0
1
0
0
1
1
Boot BIOS Loaction
Reserved
PCI
SPI
1K_0402_5% 2
1 R537
RF_OFF#
1K_0402_5% 2
1 R538
PCH_GPIO19
Low= A16 swap override Enable

High= A16 swap override Disable
32
1K_0402_5% 2
1 R536
W L_OFF#
31
ODD_DA#
T32 PAD
5,13,32,33,35,38,39
38 CLK_PCI_EC
22 CLK_PCILOOP
39 CLK_PCI_DDR
PLT_RST#
NV_ALE
AV5
AY1
NV_RCOMP
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
C46
C44
E40
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
RF_OFF#
PCH_GPIO53
W L_OFF#
D47
E42
F46
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
NV_RB#
AY5
BA2
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
EHCI 2
22_0402_5% 1
22_0402_5% 1
22_0402_5% 1
K10
C6
2 R525
2 R526
2 R527
CLK_EC_R
CLK_PCH
CLK_SIO
H49
H43
J48
K42
H40
DMI & FDI Termination Voltage

Set to VCC when HIGH
NV_CLE
NV_CLE
+1.8VS
AV10
NV_RE#_WRB0
NV_RE#_WRB1
EHCI 1
Set to VSS when LOW
AT8
NV_WE#_CK0
NV_WE#_CK1
K40
K38
H38
G38
PLT_RST#
AT10
BC8
DF_TVS NV_CLE
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PME#
NV_DQS0
NV_DQS1
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
W L_OFF#
AY7
AV7
AU3
BG4
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
PCH_GPIO19 21
A16 Swap Override Strap

WL_OFF#
TP21
TP22
TP23
TP24
USB
RP2
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
8.2K_0804_8P4R_5%
NVRAM
PCI_PIRQC#
PCH_GPIO4
PCH_GPIO2
PCI_PIRQA#
1
2
3
4
PCI
8
7
6
5
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
RP1
R324
2.2K_0402_5%
AT12
BF3
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS#
C33
NV_CLE
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N0
USB20_P0
USB20_N1
USB20_P1
31
31
31
31
+3VS
2
R323
1
1K_0402_5%
H_SNB_IVB# 5
8/18 Change R324 From 1K to 2.2K by

Intel check list demand
USB-LEFT1
USB-LEFT2
H_SNB_IVB#
9/1
C895
1
@
2 220P_0402_50V7K
Reserve C895 for ESD requset
USB port6 and port7 are disabled on HM65
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N9 32
USB20_P9 32
USB20_N10 34
USB20_P10 34
USB20_N11 19
USB20_P11 19
+3VALW
WiMax
RP4
Card Reader
SLP_CHG_M4
USB_OC#0
SLP_CHG_M3
USB_OC#6
Int. Camera
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
8/23 PIN swap for layout request

RP5
USBRBIAS
B33
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
USBBIAS
1
R535
USB_OC#1
USB_OC#2
USB_OC#5
USB_OC#7
2
22.6_0402_1%
Within 500 mils
PME#
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
USB_OC#0
USB_OC#1
USB_OC#2
SLP_CHG_M3
SLP_CHG_M4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#0 31,35,38
USB-LEFT
HM65R1@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_PCI/USB/NAND
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
25
of
53
+3VS
+3VALW
U2F
ODD_EN#
2
R437
2
R547
2
R402
1
R328
TACH4 / GPIO68
C40
ODD_EN#
A42
TACH1 / GPIO1
TACH5 / GPIO69
B41
PCH_W L_BT_LED
T7
PCH_GPIO57
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
USB30_SMI#
2
47K_0402_5%
ISDBT_DET
PCH_GPIO6
H36
TACH2 / GPIO6
TACH6 / GPIO70
C41
LOGO_LED
EC_SCI#
EC_SCI#
E38
TACH3 / GPIO7
TACH7 / GPIO71
A40
MAXIC_SELECT
38
EC_SMI#
EC_SMI#
C10
GPIO8
USB30_SMI#
PCH_GPIO12
C4
LAN_PHY_PWR_CTRL / GPIO12
USB30_SMI#
G2
GPIO15
PCH_GPIO16
U2
PCH_GPIO17
D40
BT_DET#
32
BT_ON#
T74 PAD
31 ODD_DETECT#
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
PCH_GPIO27
E16
GPIO27
PCH_GPIO28
P8
GPIO28
BT_ON#
K1
STP_PCI# / GPIO34
PCH_GPIO35
K4
GPIO35
ODD_DETECT#
PCH_GPIO37
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
OPTIMUS_EN#
N2
SLOAD / GPIO38
CIR_EN#
M3
SDATAOUT0 / GPIO39
V13
ISDBT_DET
PECI
P4
KB_RST#
AY11
H_PW RGOOD
THRMTRIP#
AY10
PCH_THRMTRIP# 1
R416
INIT3_3V#
T14
NC_1
AH8
NC_2
AK11
NC_3
AH10
NC_4
AK10
NC_5
P37
VSS_NCTF_15
BG2
VSS_NCTF_16
BG48
PCH_GPIO57
D6
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
KB_RST# 38
H_PW RGOOD 5
2
390_0402_5%
H_THERMTRIP# 5
This signal has weak internal

pull-up, can't be pulled low
8/18 Remove PCH PECI by HW Review demand
SATA5GP / GPIO49
2 1K_0402_5% PCH_GPIO28
GATEA20 38
P5
RCIN#
SDATAOUT1 / GPIO48
PCH_GPIO27
GATEA20
PROCPWRGD
V3
PCH_GPIO37
PAD T75
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
AU16
PCH_GPIO49
On-Die PLL Voltage Regulator

H: Enable
L: Disable
R325
A20GATE
T5
GPIO28
ODD_EN# 41
38
CPU/MISC
PCH_GPIO28
BT_ON#
2
10K_0402_5%
HDMI_HPD
2
10K_0402_5%
PCH_GPIO1
2
10K_0402_5%
BT_DET#
2
10K_0402_5%
OPTIMUS_EN#
2
10K_0402_5%
ODD_DETECT#
2
200K_0402_5%
PCH_GPIO6
2
10K_0402_5%
PCH_GPIO16
2
10K_0402_5%
EC_SCI#
2
10K_0402_5%
CIR_EN#
2
100K_0402_5%
ISDBT_DET
2
10K_0402_5%
PCH_GPIO49
2
10K_0402_5%
PCH_GPIO17
2
10K_0402_5%
BMBUSY# / GPIO0
PCH_GPIO1
PCH_GPIO12
35
1
R567
1
R539
1
R540
1
R542
1
R554
1
R545
1
R546
1
R577
1
R550
1
R551
1
R552
1
R553
1
R555
HDMI_HPD
EC_SMI#
+3VS
13,30 HDMI_HPD
USB30_SMI#
GPIO
1
1K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
NCTF
2
R390
1
R558
1
R556
1
R557
1
R549
1
R106
GATEA20
1
R548
KB_RST#
1
R559
LOGO_LED
1
R436
PCH_W L_BT_LED
1
R110
H_THERMTRIP#
C896
1
@
2 220P_0402_50V7K
H_PW RGOOD
C897
1
@
2 220P_0402_50V7K
9/1
HM65R1@
Reserve C896, C897 for ESD requset
GPIO8
Integrated Clock Chip Enable (Removed)

H: Disable
L: Enable
R326 1
2 1K_0402_5%
EC_SMI#
Integrated clock enable functionality

is achieved by soft-strap
The current default is clock enable
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_CPU/GPIO
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
26
of
53
U2G
C269
C275
C289
1U_0402_6.3V6K
2
1U_0402_6.3V6K
+1.05VS_PCH
T30 PAD
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
2
+1.05VS_PCH
1U_0402_6.3V6K
C277
10U_0603_6.3V6M
C273
C279
C510
1U_0402_6.3V6K
VCCIO[17]
VCCIO[18]
AN27
VCCIO[19] 2925mA
VCCIO[20]
VCCIO[21]
1U_0402_6.3V6K
2
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
C512
0.01U_0402_25V7K
U47
AP16
+VCCA_LVDS
+VCCP_VCCDMI
AP17
AU20
0.001
0.001
2 0_0402_5%
AK37
V5REF_SUS
VCCTX_LVDS[1]
AM37
VCC3_3
3.3
0.266
VCCTX_LVDS[2]
AM38
VCCADAC
3.3
0.001
VCCTX_LVDS[3]
AP36
VCCTX_LVDS[4]
AP37
VCCADPLLA
1.05
0.08
VCCADPLLB
1.05
0.08
VCCCORE
1.05
1.3
VCCDMI
1.05
0.042
VCCIO
1.05
2.925
VCCASW
1.05
1.01
VCCSPI
3.3
0.02
VCCDSW
3.3
0.002
VCCDFTERM
1.8
0.19
VCCRTC
3.3
6 uA
VCCSUS3_3
3.3
0.97
+VCCTX_LVDS
R27
0_0402_5%
VCC3_3[6]
V33
1
VCC3_3[7]
V34
C272
0.1U_0402_10V7K
2
+1.5VS
R474
0_0603_5%
1
2
+VCCAFDI_VRM
AT16
+VCCP_VCCDMI
VCCDMI[1]
20mA
VCCIO[1]
VCCFDIPLL
R480
0_0805_5%
1
2
+VCCP_VCCDMI
AT20
R477
0_0805_5%
1
2
+1.05VS_VCC_DMI
1
AB36
VCCPNAND[1]
AG16
VCCPNAND[2]
AG17
+1.05VS_PCH
+1.05VS_VCCP
C276
1U_0402_6.3V6K
C270
1U_0402_6.3V6K
VCCDFTERM
VCCVRM[2]
VCCDMI[2]
0.001
VSSALVDS
VCCIO[27]
1.05
AK36
VCCVRM[3]
FDI
+1.05VS_PCH
BG6
S0 Iccmax
Current (A)
1
V_PROC_IO
R26 1
Voltage
C286
10U_0603_6.3V6M
+VCCAFDI_VRM
T36 PAD
Voltage Rail
V5REF
C290
0.1U_0402_10V7K
+VCCAFDI_VRM
PCH Power Rail Table
2
1
BLM18PG181SN1D_0603
VCCALVDS
1U_0402_6.3V6K
+3VS
0.1U_0402_10V7K
1
C288
+3VS
AN26
AP23
+VCCA_DAC
U48
1mA
VCCIO[16]
AP21
VCCADAC
VSSADAC
60mA
AN21
AP24
C511
1mA
10U_0603_6.3V6M
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
CRT
JUMP_43X118
C274
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
LVDS
+1.05VS_PCH
1U_0402_6.3V6K
HVCMOS
+3VS
L12
DMI
POWER
1300mA
NAND / SPI
VCC CORE
PJ31
+1.05VS_VCCP
VCCIO
+1.8VS
VCCSusHDA
1
190mA
VCCPNAND[3]
AJ16
2
VCCPNAND[4]
VCCSPI
1.5
0.16
VCCCLKDMI
1.05
0.02
VCCSSC
1.05
0.095
AJ17
VCCDIFFCLKN
1.05
0.055
VCCALVDS
3.3
0.001
VCCTX_LVDS
1.8
0.06
V1
1
0.01
VCCVRM
C278
0.1U_0402_10V7K
+3VS
20mA
3.3 / 1.5
HM65R1@
C281
1U_0402_6.3V6K
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_POWER-1
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
27
of
53
T38
P26
VCCIO[31]
P28
VCCIO[32]
T27
VCCIO[33]
T29
VCCSUS3_3[7]
T23
VCCSUS3_3[8]
T24
DCPSUSBYP
0.1U_0402_10V7K
+VCCSUS
+1.05VS_PCH
C311
C300
1U_0402_6.3V6K
@
C312
22U_0805_6.3V6M
2
2
22U_0805_6.3V6M
+1.05VS_PCH
AL29
VCCIO[14]
AL24
DCPSUS[3]
AA19
+1.05VS_VCCADPLLA
1
2
BLM18PG181SN1D_0603
L14
1
2
BLM18PG181SN1D_0603
C287
C323
1U_0402_6.3V6K
1
1
C294
C308
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
1U_0402_6.3V6K
C295
C291
1U_0402_6.3V6K
2
2
C298
1U_0402_6.3V6K
+1.05VS_PCH
R522
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
+VCCDIFFCLK
0_0603_5%
C337
1U_0402_6.3V6K
+1.05VS_PCH
+1.05VS_VCCDIFFCLKN
+VCCRTCEXT
R485
VCCASW[8]
AC27
1U_0402_6.3V6K
2
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
AC26
+1.05VS_VCCADPLLB
+1.05VS_VCCDIFFCLKN
1
1
0_0603_5%
3
C334
0.1U_0402_10V7K
C320
1U_0402_6.3V6K
+VCCAFDI_VRM
Y49
+1.05VS_VCCADPLLA
+1.05VS_PCH
R521 @
2
1
+1.05VM_VCCSUS
C316
1U_0402_6.3V6K
BD47
2
+RTCVCC
C327
C330
VCCSUS3_3[6]
P24
VCCIO[34]
T26
V5REF_SUS
M26
+PCH_V5REF_SUS
DCPSUS[4]
AN23
+VCCA_USBSUS
VCCSUS3_3[1]
AN24
R512
100_0402_5%
C332
0.1U_0402_10V7K
D8
RB751V40_SC76-2
+1.05VS_PCH
+PCH_V5REF_SUS
C326
0.1U_0603_25V7K
V5REF
P34
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
1mA
C335 1
2 1U_0402_6.3V6K
+3VALW
+PCH_V5REF_RUN
+3VALW
+5VS
+3VS
R490
100_0402_5%
D7
RB751V40_SC76-2
2
1
C293
1U_0402_6.3V6K
2
VCC3_3[1]
AA16
VCC3_3[8]
W16
VCC3_3[4]
T34
VCC3_3[2]
VCCIO[12]
AH13
VCCIO[13]
AH14
VCCIO[6]
AF14
VCCVRM[4]
C313
0.1U_0402_10V7K
+3VS
+1.05VS_SATA3
1
AF13
C304
1U_0603_10V6K
AJ2
VCCIO[5]
+3VS
+PCH_V5REF_RUN
1
+3VS
1
2
C306
0.1U_0402_10V7K
VCCADPLLA
80mA
80mA
+VCCDIFFCLK
AF17
AF33
AF34
AG34
VCCIO[7]
VCCIO[8]
VCCIO[9] 55mA
VCCIO[11]
AG33
VCCIO[10]
+VCCSST
V16
DCPSST
0.1U_0402_10V7K
+1.05VM_VCCSUS
C299
T17
V19
DCPSUS[1]
DCPSUS[2]
+V_CPU_IO
BJ8
V_PROC_IO
0.1U_0402_10V7K
+1.05VS_PCH
R516
C297
0.1U_0402_10V7K
0_0805_5%
C329
1U_0402_6.3V6K
+1.05VS_SATA3
C325
4.7U_0603_6.3V6K
C322
PAD
AK1
T43
+VCCAFDI_VRM
VCCVRM[1]
AF11
+VCCAFDI_VRM
VCCIO[2]
AC16
+1.05VS_VCC_SATA
VCCIO[3]
AC17
VCCIO[4]
AD17
+1.05VS_VCC_SATA
+1.05VS_PCH
R491
2
1
0_0805_5%
C331
1U_0402_6.3V6K
+1.05VS_PCH
1mA
C336
0.1U_0402_10V7K
VCCAPLLSATA
95mA
+1.05VS_VCCP
0_0603_5%
V24
DCPRTC
R511
1U_0402_6.3V6K
2
V23
2
1
+RTCVCC
VCCSUS3_3[9]
1mA
VCCADPLLB
+5VALW +3VALW
+3VALW
C321
0.1U_0402_10V7K
VCCSUS3_3[10]
1010mA
BF47
+1.05VS_VCCDIFFCLKN
+1.05VS_PCH
C318
1U_0402_6.3V6K
0.1U_0402_10V7K
+1.05VS_VCCADPLLB
+3VALW
0_0603_5%
N16
119mA
VCCASW[1]
AA21
L13
C328
1U_0402_6.3V6K
VCCAPLLDMI2
USB
+1.05VS_PCH
BH23
SATA
T41 PAD
C310
1U_0402_6.3V6K
C303
0.1U_0402_10V7K
2
MISC
C301
10U_0603_6.3V6M
VCCASW[22]
T21
+VCCME_22
0_0402_5% 1
2 R509
VCCASW[23]
V21
+VCCME_23
0_0402_5% 1
2 R517
VCCASW[21]
T19
+VCCME_21
0_0402_5% 1
2 R520
+3VALW
+RTCVCC
A22
VCCRTC
HDA
VCC3_3[5]
PCI/GPIO/LPC
+3VS_VCC_CLKF33
1
CPU
1
2
10UH_LB2012T100MR_20%
RTC
Clock and Miscellaneous
L18
V12
+3VS_VCC_CLKF33
VCCIO[30]
3mA
VCCDSW3_3
+PCH_VCCDSW
VCCIO[29]
VCCACLK
T16
C324
0.1U_0402_10V7K
+1.05VS_PCH
N26
AD49
+3VS
T42 PAD
@
C305
2
1
"@" Avoid leakage
POWER
U2J
+3VALW
10mA
1
VCCSUSHDA
P32
HM65R1@
C307
0.1U_0402_16V4Z
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_POWER-2
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
28
of
53
U2I
H5
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
U2H
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
HM65R1@
HM65R1@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCH_GND
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
29
of
53
+HDMI_5V_OUT
+5VS
HDMI@
R145
HDMI_HPD_U 1
2
1K_0402_5%
2
14 VGA_HDMI_TX0-
2 0.1U_0402_16V7K HDMI@
CV299
2 0.1U_0402_16V7K HDMI@
VGA_DVI_TXD0VGA_DVI_TXD1+
14 VGA_HDMI_TX1-
2 0.1U_0402_16V7K HDMI@
VGA_DVI_TXD1-
CV295
2 0.1U_0402_16V7K HDMI@
VGA_DVI_TXD2+
CV300
14 VGA_HDMI_TX2-
2 0.1U_0402_16V7K HDMI@
2
R401
14 VGA_HDMI_DATA
1
3
0_0402_5%
HDMI_SDATA
+3VS
CV298
14 VGA_HDMI_TX2+
Q19
BSH111_SOT23-3
HDMI@
VGA_DVI_TXD2-
C265
0.1U_0402_16V4Z
HDMI@
74AHCT1G125GW_SOT353-5
HDMI@
HDMI_SCLK
Q18
BSH111_SOT23-3
HDMI@
1
HDMI@
CV297
HDMI@
2
1
R391
0_0402_5%
14 VGA_HDMI_CLK
VGA_DVI_TXD0+
U9
VGA_DVI_TXC-
2 0.1U_0402_16V7K HDMI@
R185
2.2K_0402_5%
HDMI@
2
2 0.1U_0402_16V7K HDMI@
CV294
R184
2.2K_0402_5%
HDMI@
R186
100K_0402_5%
HDMI@
HDMI_HPD_R
CV293
VGA_DVI_TXC+
14 VGA_HDMI_TX1+
2 0.1U_0402_16V7K HDMI@
14 VGA_HDMI_TX0+
14 VGA_HDMI_CLK-
CV296
5
P
1
2
14 VGA_HDMI_CLK+
HDMI_HPD_C
2
For DISCRETE
C264
0.1U_0402_16V4Z
HDMI@
OE#
R452
0_0402_5%
HDMI@
+3VS
@
2
1
R570
100K_0402_5%
HDMI@
2
1
R571
2.2K_0402_5%
+3VS
@ D55
HDMI_HPD_R
HDMI_HPD 13,26
CH751H-40PT_SOD323-2
2
1
R403
0_0402_5%
HDMI@
1
4
VGA_DVI_TXC+
B
1
4
2
0_0402_5%
HDMI@
2 2
3
1
R175
L9
1
4
2
0_0402_5%
HDMI@
2 2
1 HDMI@ 2
R195
499_0402_1%
1 HDMI@ 2
R197
499_0402_1%
HDMI_R_D1- 1 HDMI@ 2
R198
499_0402_1%
HDMI_R_D1+ 1 HDMI@ 2
R202
499_0402_1%
R201
499_0402_1%
R203
499_0402_1%
R205
499_0402_1%
R206
499_0402_1%
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0+
+5VS
OCE2012120YZF
@
1
2
R180
0_0402_5%
VGA_DVI_TXD0-
HDMI_R_CK+
OCE2012120YZF
@
1
2
R173
0_0402_5%
VGA_DVI_TXD0+
HDMI_R_CK-
HDMI@
D53
+5VS
F2
+HDMI_5V_OUT_F 2
1
+HDMI_5V_OUT
1.1A_6V_MINISMDC110F-21
HDMI@
C259
HDMI@
0.1U_0402_16V4Z
2
PMEG2010AEH_SOD123
@
1
R157
L8
VGA_DVI_TXC-
2
G
Q24
2N7002_SOT23-3
HDMI@
HDMI_R_D0-
HDMI Connector
JHDMI
VGA_DVI_TXD1-
@
1
R182
L10
1
4
1
4
2
0_0402_5%
HDMI@
2 2
3
VGA_DVI_TXD2+
@
1
R187
L11
HDMI_HPD_C
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-
2
0_0402_5%
HDMI@
2 2
HDMI_R_D1-
OCE2012120YZF
@
1
2
R183
0_0402_5%
VGA_DVI_TXD1+
HDMI_R_D1+
HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D2+
HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
VGA_DVI_TXD2-
OCE2012120YZF
@
1
2
R188
0_0402_5%
20
21
22
23
HDMI_R_D2-
Issued Date
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
TAITW_PDVBR9-19FLBS4NN4N1
Compal Secret Data
.
2010/09/03
2012/12/31
Deciphered Date
3
Title
HDMI Conn.
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet

1
30
of
53
SATA HDD Conn
SATA ODD Conn
@
SW 2
Place closely JHDD SATA CONN.
1
C356
10U_0603_6.3V6M
C357
0.1U_0402_16V4Z
ODD_DA#_R
C358
0.1U_0402_16V4Z
JODD
15
14
GND
GND
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
C378 1
C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P2 21
SATA_PTX_DRX_N2 21
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
C376 1
C375 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
R561 0_0402_5%
1
2
ZODD@
+5VS_ODD
ODD_DETECT#_R
GND
A+
AGND
BB+
GND
ODD_DETECT# 26
+5VS_ODD
ODD_DA# 25
ZODD@
Place components closely ODD CONN.
1.1A
ODD_DA#_R 1
2
R562 0_0402_5%
C363
0.1U_0402_16V4Z
2 ZODD@
C352
10U_0603_6.3V6M
C353
10U_0603_6.3V6M
2
C354
@
1U_0402_6.3V6K
1
C355
0.1U_0402_16V4Z
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
C360
0.1U_0402_16V4Z
Close to JHDD
JHDD
GND
GND
SMT1-05-A_4P
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SANTA_206401-1_RV
24
23
Close to JODD
C359
0.1U_0402_16V4Z
2
6
5
1.2A
+5VS
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P0 21
SATA_PTX_DRX_N0 21
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
USB Conn
W=60mils
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
2.5A
U14
+5VALW
1
2
3
4
35,38 USB_EN#
+5VS
+USB_VCCA
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
1
R161
1
1000P_0402_50V7K
USB_OC#0 25,35,38
RT9715BGS_SO8
+5VALW
For EMI
2
C361
C362
4.7U_0805_10V4Z
2 @
2 USB_EN#
100K_0402_5%
SANTA_191201-1
W=60mils
2
1
+
C87
3
+USB_VCCA
C85
+USB_VCCA
1
+
220U_6.3V_M
C60
2
1
220U_6.3V_M
C62
1 @
0.1U_0402_16V4Z
For EMI
0.1U_0402_16V4Z
1
0_0402_5%
JUSBB
25
25
USB20_P0
USB20_N0
2
3
3
L87
1
USB20_P0_R
USB20_N0_R
1
2
3
4
5
6
1
2
3
4
5
6
1000P_0402_50V7K
W=60mils
W CM-2012-900T_0805
G7
G8
7
8
P-TW O_161021-06021_6P-T
2
R839
C61
0_0402_5%
2
1
R842
2
25
25
USB20_N1
USB20_P1
1
0_0402_5%
JUSB2
3
L86
1
2
3
4
USB20_N1_R
USB20_P1_R
2
R843
W CM-2012-900T_0805
D62 @
VCC
DD+
GND
GND
GND
GND
GND
5
6
7
8
ALLTOP C107L8-10405-L
PJDLC05_SOT23-3
R838 0_0402_5%
@
4
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
SATA-HDD/ODD/USB
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
31
of
53
Half PCIe Mini Card-WLAN/ WiMax

2
PJ27@ JUMP_43X79
2 2
1 1
+3VS
CM1
CM2
For SED
WLAN&BT Combo module circuits

BT
on module
BT
on module
Enable
Disable
BT_CRTL
BT_ON#
CM3
C253
47P_0402_50V8J
2
2
@
4.7U_0805_10V4Z
2
0.01U_0402_25V7K
PJ26@ JUMP_43X79
Short PJ27 for Wimax

Short PJ26 for WLAN
+1.5VS
BT_CTRL
CM8
CM9
C254
47P_0402_50V8J
2
2
@
4.7U_0805_10V4Z
26
Q50B
BT_ON#
2
0.01U_0402_25V7K
CM7
**If +3V_WLAN is +3VS, please

remove D24
For SED
0.1U_0402_16V4Z
1
1
40 mils
0.1U_0402_16V4Z
1
1
+3V_W LAN
+3VALW
+3V_W LAN
Q50A
2
1
5,9,41,47 SUSP
+1.5VS
22
22
CLK_W LAN#
CLK_W LAN
22 PCIE_PRX_W LANTX_N2
22 PCIE_PRX_W LANTX_P2
22 PCIE_PTX_C_W LANRX_N2
22 PCIE_PTX_C_W LANRX_P2
WLAN/ WiFi
+3V_W LAN
38
38
E51_TXD
E51_RXD
Debug card using
R16
10_0402_5%2
1
2
0_0402_5%
R17
E51_RXD_R
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
BT_CTRL
1 R327
2 E51_RXD_R
1K_0402_5%
+3VS
For isolate Intel Rainbow Peak and

Compal Debug Card.
2
G
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
+3V_W LAN
W LAN_OFF#
W LAN_OFF#
PLT_RST#
22 CLKREQ_W LAN#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
JW LAN
R1443
0_0402_5%
BT_CTRL 1
2BT_CTRL_R
2N7002_SOT23-3
PLT_RST# 5,13,25,33,35,38,39
W L_OFF# 25
Add level shift circuit for WL_OFF# to

avoide leakage from WLAN to PCH
Q36
@
W LAN_OFF# 1
R565
2
10K_0402_5%
+3V_W LAN
PM_SMBCLK 11,12,22
PM_SMBDATA 11,12,22
USB20_N9 25
USB20_P9 25
WiMax
8/30 Add R1443 for WLAN Mini PCIE Card Pin5
FOX_AS0B226-S40N-7F
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PCIe-WLAN
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
32
of
53
UL1
22 PCIE_PRX_C_LANTX_N1
CL2
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1
22
HSOP
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1
23
HSON
PCIE_PTX_C_LANRX_P1 17
PCIE_PTX_C_LANRX_N1 18
22 PCIE_PTX_C_LANRX_P1
22 PCIE_PTX_C_LANRX_N1
CLKREQ_LAN#
22 CLKREQ_LAN#
1
5,13,25,32,35,38,39
+3V_LAN
1 10K_0402_5%
CLKREQ_LAN#
RL25 2 @
1 10K_0402_5%
EC_SW I#
RTL8105E
RTL8111E
Pin14
NC
NC
Pin15
NC
Pin38
1K ohm Pull-high
23,35
EC_SW I#
2
0_0402_5%
RL7
15K_0402_5%
W OL_EN
Sx Enable Sx Disable
Wake up
Wake up
LOW
WOL_EN
HIGH
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
LAN_X1
43
CKXTAL1
PERSTB
LAN_X2
44
CKXTAL2
EC_SW I#
28
LANWAKEB
DVDD10
DVDD10
DVDD10
RL2 2
RL1 2
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
13
29
41
+LAN_VDD10
LL1
8111E@
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
+LAN_VDD10
ISOLATEB
DVDD33
DVDD33
27
39
+3V_LAN
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
+3V_LAN
33
ENSWREG
EVDD10
21
+LAN_EVDD10
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
REGOUT
36
46
2
2.49K_0402_1%
24
49
VDDREG
VDDREG
RSET
GND
PGND
Layout Note: LL1 must be

within 200mil to Pin36,
CL13,CL9 must be within
200mil to LL1
UL1
UL1
CL683 +
220U_6.3V_M_R16
@
2
8105E-VL 10/100M
8105ELDO@
CL684
10U_0805_10V6K
25MHZ_20PF_7A25000012
CL26
27P_0402_50V8J
+3V_LAN
CL17
0.1U_0402_16V4Z
8111E@
8111E@
8111E@
0.1U_0402_16V4Z
1
CL19
1
CL20
1
CL21
1
CL22
1
CL23
1
CL24
1
CL25
CL29
0.1U_0402_16V4Z
2 8111E@
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
RL4
0_0402_5%
8111E@
ENSW REG
LL3
0_0603_5%
8105ESW R@
CL28
4.7U_0603_6.3V6K
8105ESW R@
CL29
0.1U_0402_16V4Z
8105ESW R@
RL23
0_0402_5%
8105ELDO@
8105E-VL 10/100M
8105ESW R@
FOR EMI ISN TEST DEMAND.
UL3
0.1U_0402_16V4Z
CL27
27P_0402_50V8J
0.1U_0402_16V4Z
+3V_LAN
2
0_0603_5%
CL28
4.7U_0603_6.3V6K
8111E@ 2
0.1U_0402_16V4Z
+LAN_VDDREG
LAN_X2
Close to Pin 21
YL1
LAN_X1
60 mils
1
8111E@ LL3
8111E@
+LAN_REGOUT
0.1U_0402_16V4Z
CL19, CL20,CL21 close to

pin 13,29,45, respectively
CL22 close to pin 3, respectively
CL23,CL24,CL25 close to
pin 6,9,41, respectively
+LAN_VDD10
2
0_0603_5%
CL18
1U_0402_6.3V6K
HIGH
+3V_LAN
CL9
0.1U_0402_16V4Z
8105ESW R@
+LAN_EVDD10
1
LL2
0.1U_0402_16V4Z
CL9
0.1U_0402_16V4Z
2 8111E@
CL13
4.7U_0603_6.3V6K
8105ESW R@
+LAN_VDD10
CL13
4.7U_0603_6.3V6K
8111E@ 2
LL1
2.2UH +-5% NLC252018T-2R2J-N
8105ESW R@
RTL8111E-GR_QFN48_6X6
8111E@
For P/N and footprint

Please place them to ISPD page
CL3 to CL6 close to Pin 27,39,47,48

CL7 to CL8 close to Pin 12,42
1
CL3
1
CL4
1
CL5
1
CL6
1
8111E@ CL7
1
8111E@ CL8
1 10K_0402_5%
1 10K_0402_5%
26
34
35
1
RL5
S0
CLKREQB
REFCLK_P
REFCLK_N
+LAN_VDDREG
38,41
30
32
19
20
ENSW REG
1
RL433
EECS/SCL
EEDI/SDA
CLK_LAN
CLK_LAN#
RL21 2 8111E@ 1 10K_0402_5%

RL22 1
2 1K_0402_5%
+3V_LAN
HSIP
HSIN
16
1
0_0402_5%
25
10K ohm PD
1K_0402_5%
RL6
@
ISOLATE#
CLK_LAN
CLK_LAN#
31
37
40
2
RL19
PLT_RST#
ISOLATE#
1
2
22
22
RL24 2 @
+3VS
PLT_RST#
+3V_LAN
LED3/EEDO
LED1/EESK
LED0
CL1
22 PCIE_PRX_C_LANTX_P1
RL4
0_0402_5%
8105ESW R@
LAN Conn.
8/30 Add UL3 at DVT
JLAN
X'FORM_ LFE8456E
PR4+
RJ45_MIDI1-
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
MCT1
MX1+
MX1-
24
23
22
LAN_MDI3LAN_MDI3+
LAN_MDI2LAN_MDI2+
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
LAN_MDI1LAN_MDI1+
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
LAN_MDI0LAN_MDI0+
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
TCT1
TD1+
TD1-
CL39 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL11
75_0402_1%
CL40 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL12
75_0402_1%
CL41 1000P_0402_50V7K
2
1
1
2
RL13
75_0402_1%
CL42 1000P_0402_50V7K
2
1
1
2
RL15
75_0402_1%
DL1
AZC199-02SPR7G_SOT23-3
RJ45_MIDI3RJ45_MIDI3+
CL34
0.1U_0402_25V4K
SHLD2
10
AZC199-02SPR7G_SOT23-3
DL2
8/30 Reserve DL1 and DL2 for ESD request

RJ45_GND 1
CL36
2
1000P_1808_3KV7K
LANGND
2
Place CL34, CL35 colse
@
to LAN chip
CL35
0.1U_0402_25V4K
SHLD1
@
SANTA_130451-D
@
0 ohm
(Pull Down)
RL23
UL4
1
2
3
NC
RTL8105E-VC RTL8105E-VC
RTL8111E-VB
PWM Mode
LDO Mode
NC
RL4
0 ohm
(Pull High)
RJ45_MIDI1+
RJ45_MIDI1-
PR4-
RJ45_MIDI3+
RJ45_MIDI0+
RJ45_MIDI0-
16
15
14
13
12
11
10
9
TX+
TXCT
NC
NC
CT
RX+
RX-
TD+
TDCT
NC
NC
CT
RD+
RD-
LAN_MDI1+
LAN_MDI1-
1
2
3
4
5
6
7
8
LAN_MDI0+
LAN_MDI0-
10/100M transformer
8105ESW R@
RJ45_MIDI3-
UL3 8105ELDO@
CL37
220P_0402_50V6K
CL38
4
4.7U_0603_6.3V6K
SUPERW ORLD_SW G150401

8111E@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title

PCIe-LAN-RTL8105E/8111E
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
E
33
of
53
For EMI request
48MCLK_CR
RC2
6.19K_0402_1%
2
1
25
25
USB20_N10
USB20_P10
@ RC6
2
100P_0402_50V8J
10_0402_5%
2
@ CC10
1
10P_0402_50V8J
2
UC1
0_0402_5% 2
0_0402_5% 2
1 RC1
1 RC3
USB20_N10_R 2
USB20_P10_R 3
+3VS
+VCC_3IN1
CC7
+V1_8
1U_0402_6.3V6K
SDW P_MSCLK
DM
DP
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
8
9
10
11
12
SP1
SP2
SP3
SP4
SP5
GPIO0
17
CLK_IN
24
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
0620 --> remove CR_LED#

48MCLK_CR
48MCLK_CR 22
< 48MHz >
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
0620 --> remove CARD-RADER LED
SDCMD
MS_DATA2_SDCLK
SDCD#
RTS5137-GR_QFN24_4X4
25
SD_DATA1
SD_DATA0
REFE
EPAD
1
@ CC2
0715 --> change P/N to RTS5137 (SA000043500)
< 2 in 1 Card Reader >

0624 --> change CARDREADER conn.
JREAD @
D3 1
CMD 2
VSS1 3
VDD 4
CLK 5
VSS2 6
D0
D1
D2
WP
CD
7
8
9
10
11
GND1
GND2
GND3
GND4
12
13
14
15
MS_DATA1_SD_DATA3
SDCMD
+VCC_3IN1
MS_DATA2_SDCLK
1
SD_DATA0
SD_DATA1
SD_DATA2_MS_DATA5
SDW P_MSCLK
SDCD#
CC6
0.1U_0402_16V4Z
CC5
1U_0402_6.3V6K
TAITW _PSDAT3-09GLAS1N14N
For EMI request

@ RC4
MS_DATA2_SDCLK
10_0402_5%
2
@ CC8
10_0402_5%
2
@ CC9
@ RC5
SDW P_MSCLK
10P_0402_50V8J
2
10P_0402_50V8J
2
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title

PCIe-CardReader RTS5137
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
E
34
of
53
+1.5V to +1.05V Transfer
+3V
Close to U102.D7
+1.05V
UT2
5
9
6
7
VIN
VOUT
VIN
VOUT
VCNTL
POK
FB
3
4
EN
GND
2 USB30@ 1
RT2
10K_0402_1%
2
1
1
RT3
32.4K_0402_1%
USB30@
USB30@ 2
Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025
+3VA
1
0.1U_0402_16V7K
CT4
U3RXDP1_R
2
CT8 2
0.01U_0402_25V7K
USB30@
USB30@
2
4
D2
D1
F2
F1
+3V:200mA
PETXP
PETXN
SMI high active

1
USB30@
2
2
1
G
S 2N7002_SOT23-3
1
@
2 USB30_SMI_R
RT21
0_0402_5%
H2
K1
K2
J2
J1
H1
P4
P5
PERXP
PERXN
D7
U2DP2
U3RXDP2
PERSTB
PEWAKEB
PECREQB
OCI2B
OCI1B
AUXDET
PSEL
SMI
SMIB
PPON2
PPON1
PONRSTB
K13
K14
J13
SPISCK
SPISCB
SPISI
SPISO
U3TXDN1
U2DM1
U2DP1
U3RXDP1
GND
GND
GND
U3RXDN1
RREF
U2AVSS
GND
U2PVSS
N14
M14
U3AVSS
XT1
XT2
P6
2
@
RT31
2
USB30@
0_0402_5%
2
USB30@
CT38
12P_0402_50V8J
CT37
12P_0402_50V8J
RT30
0_0402_5%
USB30@ USB30@ USB30@

USB30@ USB30@ USB30@
USB30@
RT291
2
0_0402_5%
24MHZ_12PF_X5H024000DC1H
RT281
2
0_0402_5%
USB30@
YT1
1
U2D_DP1
+3V
22 48MCLK_USB30
Place as close as possibile to

UU102.N14 and UU102.M14
A1
A2
A3
A4
A5
A7
A9
A11
A13
A14
B3
B4
B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11
CSEL
2
3
USB20_DN1_L
USB20_DP1_L
@ WCM-2012-900T_0805
1
2
RT10 0_0402_5% USB30@
B6
A6
N8
P8
B8
A8
G14
H13
OCI2#
OCL1#
1 RT13
2 10K_0402_5%
+3V
USB30@
H14
J14
JUSB30
USB30PWRON
U3TXDP1_L
+USB_VCCA
B10
U3TX_C_DP1
CT32
A10
N10
U3TX_C_DN1
U2D_DN1
CT33
P10
B12
A12
U2D_DP1
U3RXDP1_R
USB30@
2 0.1U_0402_16V7K
U3TXDP1
2 0.1U_0402_16V7K
U3TXDN1
USB20_DN1_L
U3RXDP1_R_L
U3RXDN1_R_L
USB30@
W=80mils
USB_GND
0_0603_5%
0_0603_5%
RT42
P12
N12
RT22
2 1.6K_0402_1%
USB30@
2
USB30@ USB30@
USB30@
N11
D6
@
2USB_EN#
USB_EN#
31,38
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6
+USB_VCCA
DT2
U3TXDN1_L
U3TXDP1_L
U3RXDN1_R_L
U3RXDP1_R_L
1
2
3
4
RR+
TT+
VCC
GND
DD+
8
7
6
5
USB20_DN1_L
USB20_DP1_L
LXES4XBAA6-027_MSOP8
@
+3V
+3V
10K_0402_5%
2 RT43
1
USB30@
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
USB30_SMI#_IC
QT3B
2N7002KDWH_SOT363-6
USB30@
1
OCL1#
USB30_SMI#
26
QT3A
6
USB_OC#0
25,31,38
2N7002KDWH_SOT363-6
USB30@
10K_0402_5%
2 RT44
1
USB30@
UPD720200AF1-DAP-A
10
11
12
13
RT41
RT33
10K_0402_5%
USB30@
SPI_CLK_USB
UT4
1
2
3
4
CS#
SO
WP#
GND
35mA
VCC
HOLD#
SCLK
SI
1 RT34
2
0_0402_5%
@
GND
GND
GND
GND
U3RXDN1_R
+3V
SPI_CS_USB#
SPI_SO_USB
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
SANTA_371394-3
@
+3V
RT32
47K_0402_5%
USB30@
9
1
8
3
7
2
6
4
5
U3TXDN1_L
USB20_DP1_L
CSEL=0
CSEL=1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
9/2 Change CT25 from SE093106K80 (10uF_0805) to SE000005T80

(10uF_0603) by sourcer demand
USB30PWRON RT11 1
0_0402_5%
24MHz
XTAL
48MHz Clock
1
RT26
100_0402_5%
USB30@
P13
U3TXDN2
U2DM2
@
2 USB30_SMI#_R
RT40
0_0402_5%
U2D_DN1
U2AVDD10
U3TXDP2
+1.05V:800mA
U3TXDP1
M2
N2
N1
M1
C14
0.01U_0402_25V7K
0.1U_0402_16V7K
0.01U_0402_25V7K
CT15
CT14
0.01U_0402_25V7K
CT13
0.01U_0402_25V7K
0.01U_0402_25V7K
CT12
CT11
CT10
RT9 0_0402_5% USB30@

1
2
.1U_0402_16V7K
Q57
@
CLK_48M_USB
U3AVDO33
H11
K11
K12
L8
VDD10
VDD10
VDD10
VDD10
E11
E12
E3
E4
H3
H4
L5
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
C8
C9
D8
D9
VDD10
VDD10
VDD10
VDD10
C4
C5
C6
C7
D5
VDD10
VDD10
VDD10
VDD10
VDD10
N4
N5
N6
P3
VDD33
VDD33
VDD33
VDD33
L13
L14
VDD33
VDD33
L9
L10
VDD33
VDD33
F3
G3
G4
PECLKP
PECLKN
+3V
U3TXDN1_L
RT12 10_0402_5% 2 USB30_WAKE#

USB30@
RT15
1 USB30@ 2 10K_0402_5%
RT16
@
@1
2 100_0402_1%
RT17
1 USB30@ 2 10K_0402_5%
+3V
USB30_SMI_R
USB30_SMI#_IC
0_0402_5%
RT18
1
2 USB30_SMI#_R
USB30@
RT39 1
UPD720200A:
2 10K_0402_5%
+3V
USB30@
SMIB Low active
1SS355TE-17_SOD323-2
SPI_CLK_USB
1
2
1 2 DT3
SPI_CS_USB#
SPI_SI_USB
USB30@
1
USB30_SMI#_IC
SPI_SO_USB
For UPD720200:
USB30@
2 RT7
0_0402_5%
PCIE_PRX_USBTX_P6
PCIE_PRX_USBTX_N6
USB30@ USB30@ USB30@ USB30@ USB30@

USB30@ USB30@ USB30@ USB30@
CT45
0.01U_0402_25V7K
USB30@
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
USB30@
CT29 2
CT30 2
VDD33
VDD33
VDD33
USB30@
B2
B1
CLK_USB30
CLK_USB30#
D10
F13
F14
1
3
UT1
CT44
1U_0603_10V6K
U3TXDN1
+1.05V
U3RXDN2
CT24
0.01U_0402_25V7K
CT23
0.01U_0402_25V7K
0.1U_0402_16V7K
U3RXDN1_R_L
1
LT2
LT4
5,13,25,32,33,38,39
PLT_RST#
23,33 EC_SWI#
22 CLKREQ_USB30#
CT22
WCM-2012-121T_0805
1
2 RT6
@
0_0402_5%
USB30@
+3VA
22 PCIE_PTX_C_USBRX_P6
22 PCIE_PTX_C_USBRX_N6
CT21
0.01U_0402_25V7K
0.01U_0402_25V7K
CT20
CT19
0.1U_0402_16V7K
0.01U_0402_25V7K
0.1U_0402_16V7K
CT18
CT17
CT16
+3V
+3V
U3TXDP1_L
+1.05V
1 @
2 RT5
0_0402_5%
WCM-2012-121T_0805
3
4
3
22
22
10U_0603_6.3V6M 1
U3TXDP1
USB30@
CT42
0.1U_0402_16V4Z
2
USB30@
CT41
0.1U_0402_16V7K
1
USB30@
22 PCIE_PRX_C_USBTX_P6
22 PCIE_PRX_C_USBTX_N6
CT25
U3RXDP1_R_L
1 @
2 RT4
0_0402_5%
LT1 USB30@
3
4
3
Follow Vendor recommend.
RT37
100K_0402_5%
+3VA
1
2
BLM18AG601SN1D_2P
8P_0402_50V8D
CT9
1 @
U3RXDN1_R
QT1
1
2
2
AO3413_SOT23
RT38 47K_0402_5%
2
CT43
D
USB30@
0.01U_0402_25V7K
USB30@
1
+3V
S 2N7002_SOT23-3
USB30@
USB30@
LT3
C
+3VALW
+3V & +1.05V has power sequence timing:

0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms
+3V
1
0.1U_0402_16V7K
CT7
SYSON
8P_0402_50V8D
CT6
1 @
38,48
2
CT5 2
0.01U_0402_25V7K
USB30@
USB30@
+3VALW
2
G
QT2
Close to U102.P13
+3VA
+3VALW to +3V Transfer
USB30@
1A
CT3
10U_0603_6.3V6M
+3V
USB30@ USB30_POK
USB30@
APL5930KAI-TRG_SO8
USB30_POK
+1.5V
CT2
10U_0603_6.3V6M
+3V
VDD33
VDD33
VDD33
+1.5V
USB30@
1 RT1
2
4.7K_0402_5%
8
7
6
5
MX25L5121EMC-20G SOP 8P
USB30@
USB30@
1 RT35
210K_0402_5%
SPI_CLK_USB_R
CT39
1
2 0.1U_0402_16V7K
USB30@
SPI_SI_USB
SPI_CLK_USB_R 1 RT36
2010/09/17 Add Level shift to avoid +3V leakage from +3VALW_PCH

2
Close to UU37.6
CT40
0.1U_0402_16V7K
@
Issued Date
2
2010/09/03
Deciphered Date
2012/12/31
SPI_CLK_USB
0_0402_5%
http://mycomp.su - .
, ,
USB30@
.
Compal Secret Data
Title
Size
Document Number
Custom
Date:

PCIe-USB3.0 UPD720200A
Rev
1.0
PWWHA LA-7201P M/B

Sheet

1
35
of
53
Codec
600 mA
+PVDD1
RA2
1
2
0_0603_5%
0.1U_0402_16V4Z
1
1
CA57
0.1U_0402_16V4Z
1
1
CA44
C56
2
+3VS
2
RA19 0_0603_5%
+1.5VS
@
2
RA20 0_0603_5%
0.1U_0402_16V4Z
1
1
Beep sound
+5VS
CA43
2
10U_0603_6.3V6M
+DVDD_IO
2
10U_0603_6.3V6M
EC Beep
1
CA1
CA2
10U_0603_6.3V6M
2
38
place close to chip
PCI Beep
0.1U_0402_16V4Z
35 mA
21
CA13
1
2
RA8
1
2
47K_0402_5%
PCH_SPKR
+AVDD
CA8
CA7
10U_0603_6.3V6M
2
68 mA
RA3
0.1U_0402_16V4Z 1
2
0_0603_5%
10U_0603_6.3V6M
MONO_IN
0.1U_0402_16V4Z
+5VS
RA1
2
1
0_0603_1%
+3VS
RA7
1
2
47K_0402_5%
EC_BEEP#
+3VS_DVDD
4.7U_0805_10V4Z
2
MIC1_R_L
37
CA23
1
2
4.7U_0805_10V4Z
MIC1_R_R
1
CA29
Int. Mic
19 INT_MIC_DATA
19 INT_MIC_CLK
INT_MIC_DATA
INT_MIC_CLK
1
CA83
27P_0402_50V8J
RA46
FBMA-10-100505-301T
38 EC_MUTE#
EC_MUTE#
MONO_IN
2
100P_0402_50V8J
1
CA12
RA45
MIC1_L
MIC1_R
16
17
MIC2_L
MIC2_R
EC control EC_MUTE# behavior:

High-state / low-state
1
2
CA15
2.2U_0603_6.3V6K
+MIC1_VREFO_L
CA47 1
2 0.1U_0603_50V7K
CA48 1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
2 0.1U_0603_50V7K
GPIO1/DMIC_CLK
SENSE A
18
SENSE B
RA4
RA5
place close to chip
SPKL+
SPKL-
37
37
SPKR+
SPKR-
37
37
75_0402_1%
75_0402_1%
HP_L
HP_R
38
AVDD2
RA12
4.7K_0402_5%
37
37
AZ_SYNC_HD
21
BCLK
AZ_BITCLK_HD
21
SDATA_OUT
SDATA_IN
EAPD
47
48
MONO_OUT
20
MIC2_VREFO
29
MIC1_VREFO_R
LDO_CAP
30
28
AZ_SDOUT_HD 21
AZ_SDIN0_HD_R
2
RA6
1
33_0402_5%
AZ_SDIN0_HD
@
1
2
1
R746 10_0402_5%
CA80
+3VS
close to Audio Codec(UA1) for EMI

R235
4.7K_0402_5%
CA18
100P_0402_50V8J
2
22P_0402_50V8J
@
AZ_SYNC_HD
@
CA81
22P_0402_50V8J
@
21
AZ_RST_HD#
CA82
22P_0402_50V8J
place close to chip

+MIC1_VREFO_RCA28
1
CBP
35
CBN
VREF
27
AC_VREF
31
MIC1_VREFO_L
JDREF
19
AC_JDREF2 RA9
PVSS2
PVSS1
DVSS2
DVSS1
CPVEE
34
AVSS1
AVSS2
26
37
10U_0603_6.3V6M
2
+MIC1_VREFO_R
1
1
CA14
+MIC1_VREFO_L
1 20K_0402_1%
2
2.2U_0603_6.3V6K
CA17
C16
10U_0603_6.3V6M
@
2
2
0.1U_0402_16V4Z
ALC259-GR_QFN48_7X7
1
RA18
place close to chip
10
36
43
42
49
7
CA6
SYNC
SPDIFO
RESET#
13
25
HP_OUT_L
HP_OUT_R
32
33
GPIO0/DMIC_DATA
PCBEEP
AVDD1
46
39
PVDD2
SPK_OUT_R+
SPK_OUT_R-
45
44
12
SENSE_A
40
41
11
CA5
AZ_BITCLK_HD
EC_MUTE#
4 PD#
21 AZ_RST_HD#
4.7K_0402_5%
LINE2_L
LINE2_R
21
22
CA4
37
2
2
2
2
10U_0603_6.3V6M 0.1U_0402_16V4Z
SPK_OUT_L+
SPK_OUT_L-
LINE1_L
LINE1_R
CA3
Ext. Mic
14
15
PVDD1
1
DVDD
23
24
DVDD_IO
1
UA1
@
C37
1U_0402_6.3V6K
@
CA36
1U_0402_6.3V6K
place close to chip
DGND
AGND
2
0_0603_5%
RA18 CLOSE TO ALC259
Sense Pin
SENSE A
Impedance
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
5.1K
place close to chip

37
MIC_SENSE
37
NBA_PLUG
2
RA10
1
20K_0402_1%
RA21
39.2K_0402_1%
SENSE_A
(PIN 48)
39.2K
SENSE B
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 20)
Int. MIC
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
HD CODEC ALC259
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
36
of
53
Speaker Connector
Ext. Mic
placement near Audio Codec UA1
36
MIC1_R_L
36
MIC1_R_R
RA31
1K_0402_5%
2
1
2
1
1K_0402_5%
RA22
2
RA32
1
2.2K_0402_5%
MIC1_L
2
RA33
1
2.2K_0402_5%
+MIC1_VREFO_L
MIC1_R
+MIC1_VREFO_R
RA30
1
36
SPKR+
SPKR+
SPK_R1
2
1
0_0603_5%
CA25
470P_0402_50V8J
2
@
CA26
1
2
470P_0402_50V8J
2
1
0_0603_5%
@
RA35
2
1
0_0603_5%
1
CA27
1U_0402_6.3V6K
@
RA34
36
SPKR-
36
SPKL+
SPKR-
SPKL+
SPK_R2
SPK_L1
CA19
470P_0402_50V8J
2
@
CA20
36
SPKL-
SPKL-
2
470P_0402_50V8J
2
RA36
2
1
0_0603_5%
CA24
1U_0402_6.3V6K
@
SPK_L2
HeadPhone/LINE Out JACK

JLINE
JSPK
SPK_L1
SPK_L2
SPK_R1
SPK_R2
1
2
3
4
@ DA5
PJDLC05_SOT23-3
3
NBA_PLUG
36
HP_R
36
HP_L
LA6 1
2 HP_R_L
KC FBM-L11-160808-121LMT 0603
LA7 1
2 HP_L_L
KC FBM-L11-160808-121LMT 0603
1
2
3
4
3
6
2
1
ACES_85204-0400N
@
CA45
100P_0402_50V8J
CA46
100P_0402_50V8J
CA11 @
2
0.1U_0402_16V4Z
DA6 @
PJDLC05_SOT23-3
1
2
10
9
8
7
FOX_JA63331-B39S4-7F
@
1
3
1
1
2
6
3
36
PJDLC05_SOT23-3
3
7
8
GND
GND
@ DA4
For EMI
Ext.MIC/LINE IN JACK
JEXMIC
1
2
6
3
3
6
2
1
MIC1_L
LA8 1
2 MIC1_L_R
KC FBM-L11-160808-121LMT 0603
LA9 1
2 MIC1_L_L
KC FBM-L11-160808-121LMT 0603
36 MIC_SENSE
MIC1_R
7
8
GND
GND
10
9
8
7
FOX_JA63331-B39S4-7F
@
1
2
CA41
100P_0402_50V8J
CA42
100P_0402_50V8J
DA7 @
PJDLC05_SOT23-3
CA21
2
0.1U_0402_16V4Z
For EMI
4
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
AUDIO AMP/MIC/SPK/VR
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
37
of
53
0.1U_0402_16V4Z
For EMI
C438
C439
2
2
0.1U_0402_16V4Z
C440
1
1
1000P_0402_50V7K
U19
R377
10_0402_5%
@
25 CLK_PCI_EC
5,13,25,32,33,35,39 PLT_RST#
R378
47K_0402_5%
2
1
2
C444
26
EC_SCI#
12
13
37
20
38
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
ECRST#
1
0.1U_0402_16V4Z
1
2
3
4
+3VS
8
7
6
5
39
KSI[0..7]
39
KSO[0..17]
KSI[0..7]
KSO[0..17]
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
2.2K_0804_8P4R_5%
@
PLT_RST#
2
1U_0402_6.3V6K
PLT_RST#
2
100K_0402_5%
SUSP#
2
180P_0402_50V8J
1
C819
1
R3
1
C820
1
2
3
4
5
7
8
10
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
RP7
+3VL
Close to EC
43
43
13,22
13,22
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LPC_FRAME#/LFRAME#
LPC_AD3/LAD3
LPC_AD2/LAD2
LPC_AD1/LAD1
LPC_AD0/LAD0
PWM0/GPIO0F
BEEP#/PWM1/GPIO10
Output FANPWM0/GPIO12
ACOFF/FANPWM1/GPIO13
21
23
26
27
BATT_TEMP/AD0/GPI38
BATT_OVP/AD1/GPI39
ADP_I/AD2/GPI3A
AD3/GPI3B
AD Input
AD4/GPI42
AD5/GPI43
63
64
65
66
75
76
DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D
IREF/DA2/GPO3E
DA3/GPO3F
68
70
71
72
EC_MUTE#/PSCLK1/GPIO4A
USB_EN#/PSDAT1/GPIO4B
CAP_INT#/PSCLK2/GPIO4C
Interface
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
97
98
99
109
VGATE_R
W OL_EN
PW RME_CTRL#
LID_SW #_R
PWM
LPC & MISC
CLK_PCI_EC/PCICLK
PCIRST#/GPIO05
EC_RST#/ECRST#
EC_SCI#/GPIO0E
CLKRUN#/GPIO1D
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PS2
SDICS#/GPXIOA00
WOL_EN/SDICLK/GPXIOA01
ME_EN/SDIMOSI/GPXIOA02
LID_SW#/GPXIOD00
PM_SLP_S3#
SLP_S5#
EC_SMI#
6
14
15
16
VGATE_RR
17
USB_OC#0_RR
18
PCH_SUSPW RDN 19
25
FAN_SPEED1
28
29
E51_TXD
30
E51_RXD
31
ON/OFFBTN#_R
32
PW R_LED#
34
NUM_LED#
36
23 PM_SLP_S3#
26
EC_SMI#
23 PCH_SUSPW RDN
5 FAN_SPEED1
+3VALW
O
IN2
23 PM_SLP_S4#
U44
IN1
32
32
0.1U_0402_16V4Z
SLP_S5#
@
SN74AHC1G08DCKR_SC70-5
23
Q41
C518
2N7002_SOT23-3 47P_0402_50V8J
2
G
930@
CLK_EC
930@
2
R766
122
123
1
0_0402_5%
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO
GPIO0C
SUS_PWR_DN_ACK/GPIO0D
INVT_PWM/PWM2/GPIO11
FAN_SPEED1/FANFB0/GPIO14
FANFB1/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
0_0402_5%
1
9012@
R20
100K_0402_5%
930@
ACIN_R
0_0402_5%
VGATE_R
EN_DFAN1 5
IREF
44
CHGVADJ 44
2
R742
VGATE_RR
PM_SLP_S4#/GPXIOD01
ENBKL/GPXIOD02
EAPD/GPXIOD03
EC_THERM#/GPXIOD04
SUSP#/GPXIOD05
PBTN_OUT#/GPXIOD06
EC_PME#/GPXIOD07
110
112
114
115
116
117
118
ACIN_RR
VGA_ENBKL_R
ON/OFFBTN#_RR
LID_SW #_RR
SUSP#
PBTN_OUT#
USB_OC#0_R
V18R
124
R758 10K_0402_5%
1
2
@
VGATE
0_0402_5%
TP_CLK 40
TP_DATA 40
VGATE
5,23,49
LID_SW #
39
1
9012@
0_0402_5%
LID_SW #_R
2
1 LID_SW #
R749
930@
0_0402_5%
LID_SW #_RR
2
1
R748
9012@
0_0402_5%
+5VS
PH1 voltage compare function

W OL_EN 33,41
PW RME_CTRL# 21
2
R764 @
1
0_0402_5%
EC_SI_SPI_SO
EC_SI_SPI_SO 39
EC_SO_SPI_SI
EC_SO_SPI_SI 39
SPI_CLK_R
R19 930@
2
1
SPI_CLK 39
33_0402_5%
SPI_CS#
SPI_CS# 39
C19
1
2 930@
33P_0402_50V8J
PM_PW ROK_RR
EC_PECI
R461 1
930@ 2 43_0402_1%
H_PECI
FSTCHG
FSTCHG 44
BATT_FULL_LED#
BATT_FULL_LED# 40
CAPS_LED#
CAPS_LED# 39
BATT_CHG_LOW _LED#
BATT_CHG_LOW _LED# 40
PCH_RSMRST#
EC_LID_OUT#
EC_ON_R
PH1+
TP_CLK
43
1
R379
1
R381
1
R5
SYSON
VR_ON
ACIN_R
SYSON
VR_ON
SYSON
EC_ON_R
2
R750
VGA_ENBKL_R
2
R751
930@
35,48
49
2
PCH_RSMRST# 23
EC_LID_OUT# 22
+3VL
PM_PW ROK_EC
BKOFF#
VGA_ENBKL_RR
BKOFF#
SA_PGOOD
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
EC_ON
0_0402_5%
1
930@
EC_ON
40
VGA_ENBKL 13
0_0402_5%
EC_ON
0_0402_5%
1
9012@
R341 330K_0402_5%
1
2
3
D21
19
ACIN_R
2
R755
930@
SA_PGOOD 46
2
R762 @
1
0_0402_5%
1 ACIN_D 2
0_0402_5%
ACIN
23,44
RB751V40_SC76-2
ACIN_RR 2
1
R765
9012@
0_0402_5%
VS
USB_OC#0_RR
SUSP#
41,47,48,50
PBTN_OUT# 5,23
2
R756
R757
43_0402_1%
S9012@
R759
0_0402_5%
S9012@
2
1 0_0402_5%
R759 9012@
USB_OC#0_R
+EC_V18R
C448
4.7U_0805_10V4Z
VGA_ENBKL_RR
2
1
R753
9012@
0_0402_5%
support 51ON#
GPI
1H_PROCHOT#_EC
0_0402_5%
930@
2
R743
EC_MUTE# 36
USB_EN# 31,35
H_PROCHOT#_EC_R
TP_CLK
TP_DATA
100
101
102
103
104
105
106
107
108
XCLK1
XCLK0
C1
20P_0402_50V8J
930@
EN_DFAN1
IREF
CHGVADJ
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
EC_ON/GPXIOA05
EC_SWI#/GPXIOA06
ICH_PWROK/GPXIOA07
BKOFF#/GPXIOA08
GPO RF_OFF#/GPXIOA09
GPXIOA10
GPXIOA11
69
9012@
H_PROCHOT#_EC_R 2
R744
930@
73
74
89
90
91
92
93
95
121
127
+3VS
43,44
44
R752
11
24
35
94
113
R760
ADP_I
ADP_V
GPIO40
H_PECI/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
PWR_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
GPIO
2
100P_0402_50V8J
2
100P_0402_50V8J
BATT_TEMPA 43
ADP_I
ADP_V
119
120
126
128
EC_SMB_CK1/SCL0/GPIO44
EC_SMB_DA1/SDA0/GPIO45
EC_SMB_CK2/SCL1/GPIO46
EC_SMB_DA2/SDA1/GPIO47
1
0_0402_5%
BATT_TEMPA
1
C445
1
C446
ACIN_D
EC_BEEP# 36
FANPW M 5
ACOFF
44
SPIDI/MISO
SPIDO/MOSI
SPICLK/GPIO58
SPICS#
R739
R761
H_PROCHOT# 5,43
D
TP_DATA
SPI Flash ROM
GND
GND
GND
GND
GND
E51_TXD
E51_RXD
40 PW R_LED#
39 NUM_LED#
C818 @
2
1
EC_BEEP#
FANPW M
ACOFF
SPI Device I/F
SM Bus
23 PM_SLP_S5#
H_PROCHOT#_EC
0.1U_0402_16V4Z
AGND
C443
22P_0402_50V8J
@
+3VL
VR_HOT#
BATT_TEMPA
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
26
GATEA20
26 KB_RST#
21,39 SERIRQ
21,39 LPC_FRAME#
21,39 LPC_AD3
21,39 LPC_AD2
21,39 LPC_AD1
21,39 LPC_AD0
49
C442
1
2
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
CLK_PCI_EC
+3VL
C441
1000P_0402_50V7K
C437
1
0_0402_5%
67
C436
+3VL_R
2
R763
0.1U_0402_16V4Z
1
2
9
22
33
96
111
125
0.1U_0402_16V4Z
1
1
R737
0_0402_5%
2
1
+3VL
USB_OC#0
0_0402_5%
H_PECI
43_0402_1%
930@
2
R757
9012@
USB_OC#0 25,31,35
KB930QF-A1_LQFP128_14X14
USB_OC#0_RR 2 S9012@ 1
EC_PECI
Only for PWWHA
R767
0_0402_5%
R767 close U19.74
PM_PW ROK_RR
2
1
R754
9012@
0_0402_5%
1
R349
E51_TXD
2
100K_0402_5%
SUSP#
R423 2
1 10K_0402_5%
VR_ON
R462 2
1 10K_0402_5%
PM_PW ROK_EC
2
R745
930@
2
R747
U19
40
ON/OFFBTN#
ON/OFFBTN# 2
R740
930@
S9012@
U19
1H_PROCHOT#_EC
0_0402_5%
2010/09/03
Issued Date
EC KB9012 A1
Compal Secret Data
EC KB9012 A1
PM_PW ROK 5,234
0_0402_5%
9012@
ON/OFFBTN#_R
0_0402_5%
2
1 ON/OFFBTN#_RR
R741
9012@
0_0402_5%
9012@
Deciphered Date
2012/12/31
A
B

.
Title
LPC-EC-KB930
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
38
of
53
SPI Flash (256KB)
Lid SW
1
@ R21
1
R22
+3VL
2
0_0402_5%
2
0_0402_5%
+3VALW
Place the PAD under DDR DIMM.
LPC Debug Port
+3VS
+3VL
20mils
8
0.1U_0402_16V4Z
38 SPI_CS#
38
SPI_CLK
38 EC_SO_SPI_SI
VCC
HOLD
SPI_CS#
SPI_CLK
EC_SO_SPI_SI
930@
VSS
R383
47K_0402_5%
4
U21
APX9132ATI-TRL_SOT23-3
EC_SI_SPI_SO
EC_SI_SPI_SO 38
W 25X10BVSNIG_SO8
VOUT
C453
0.1U_0402_16V4Z
PLT_RST# 5,13,25,32,33,35,38
LPC_AD2 21,38
21,38
LPC_AD3
21,38
LPC_AD1
LPC_AD0 21,38
10
CLK_PCI_DDR
LID_SW #
38
21,38 LPC_FRAME#
1
C452
10P_0402_50V8J
SERIRQ
2
0_0402_5%
25
DEBUG_PAD
R393
22_0402_5%
@
VDD
21,38
1
R392
U22
930@
GND
C451
H7
6
1
+3V_LID
SPI_CLK
1 R394
2
10_0402_5%
2
1
C454
2
10P_0402_50V8J
C457
22P_0402_50V8J
1 @
For EMI
8/30 Change U22 From SA00003GK00 to SA00003GM10 due to EOL of SA00003GK00
For EMI
9/03 Change U22 change to SA00003FL10
KEYBOARD CONN.
2
Noticed: KB Connector Pin Definition

Reversed with KB Membrane Pin Definition
For EMI
KSI[0..7]
KSO[0..17]
Close to JKB
KSI[0..7]
38
KSO16
KSO[0..17] 38
KSO17
KSO2
JKB
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88170-3400
@
JKB34
KSO16
1
2
R372 300_0402_5%
+3VS
KSO1
KSO0
KSO17
KSO4
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R376 300_0402_5%
NUM_LED#
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
+3VS
CAPS_LED# 38
NUM_LED# 38
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
CAPS_LED#
NUM_LED#
1
C401
1
C402
1
C404
1
C405
1
C406
1
C407
1
C408
1
C409
1
C410
1
C411
1
C412
1
C413
1
C415
1
C416
1
C417
1
C418
1
C419
1
C420
1
C421
1
C422
1
C423
1
C424
1
C425
1
C427
1
C429
1
C431
1
C433
1
C435
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
SPI ROM/LID/Debug/KB
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
39
of
53
+3VL
51_ON#
TP Button/Conn.
ON/OFFBTN#
ON/OFFBTN# 38
TOP side
1
BTM side
Q7
2N7002_SOT23-3
2
G
R396
10K_0402_5%
LEFT
SW 1
SW _L
JTOUCH @
4
6
5
C458
0.1U_0402_25V6
@
@
SW 3
EC_ON
1
38
100K_0402_5%
R395
For debug
42
Power Button
38
38
1
2
3
4
5
6
+5VS
SMT1-05_4P
TP_CLK
TP_DATA
SW _L
SW _R
For EMI request
RIGHT
6
5
SMT1-05-A_4P
G7
G8
7
8
3
D19 @
AZ5125-02S.R7G_SOT23-3
SMT1-05_4P
0816->change JTOUCH connector

D20 @
AZ5125-02S.R7G_SOT23-3
ON/OFFBTN#
P-TW O_161021-06021_6P-T
6
5
SW _R
PWR/B to MB Conn.
D83 @
AZ5125-02S.R7G_SOT23-3
JPOW ER @
1 1
2 2
3 3
4 4
G1 5
G2 6
SW 4
1
2
3
4
5
6
ACES_85201-0405N
For EMI request

For ESD
POWER/SUSPEND LED
H10
H11
H12
H13
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H9
H_3P0
@
PW R_LED# 38
H26
H_2P7x3P2N
@
H17
H14
H_2P7N
@
H_1P0N
@
H1
HT-110UYG5_YELLOW GREEN
YG
H8
H_3P0
@
2
510_0402_5%
3
D22
1
R398
H6
H_3P0
@
H5
Vf=1.9V~2.4V
If=5mA
+5VALW
Screw Hole
1
H_3P0
@
BATT CHARGE/FULL LED
1
R404
YG
510_0402_5%
510_0402_5%
PJP1
H23
H_4P2x4P7
@
1
45@
U2
HM65R3@
H_4P7
@
H2
H3
H_2P9x3P9
@
UV1
N12MR3@
PCB Fedical Mark PAD
N12M-GE-S-B1 533P
FD1
MDC
FD2
@
B3 FCBGA 989P PCH
H_2P9
@
For Codec AGND

3G
PJP1
H4
H_2P9x3P9
@
Dummy
DAZ_PCB LA-7201P
H22
BATT_FULL_LED# 38
1
ZZZ
BATT_CHG_LOW _LED# 38
HT-210UD5-UYG5_AMBER-YEL GRN
ISPD
H_5P0N
@
FD3
@
FD4
@
H16
H_5P0N
@
H15
H_3P3
@
1
R399
H19
H_3P3
@
H18
H_4P2x4P7
@
D25
+5VALW
H21
H_4P2
@
SB
H20
MINI CARD
CPU
Vf=1.8V~2.0V
If=5mA(max)
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
A
B

.
Title
PWR&TP CON/LED/ISPD
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
40
of
53
+3VALW
1
C18
0.1U_0402_10V6K
@
2
+3VS
+5VALW TO +5VS
2
C500
0.01U_0402_25V7K
NLS@ 2
ON_MOS1 CAP_MOS1
5_VDD
ON_MOS2 CAP_MOS2
MOS2_D
MOS2_S
Q53A
ZODD@
+5VS
+5VS
ODD_EN#
6
R430
820K_0402_5%
1 R431
2
+VSB
220K_0402_5%
Q13A
2 VGA_PW ROK#
C679
4.7U_0805_10V4Z
@
+5VALW
Q13B
1
4
SUSP
SUSP
2010/09/03
Issued Date
D
38,47,48,50 SUSP#
Deciphered Date
C680
1U_0402_6.3V6K
R468
470_0805_5%
Q6
2N7002_SOT23-3
Q189
SUSP
2
G
2N7002_SOT23-3
2
G
Q60
2N7002_SOT23-3

2012/12/31
A
B

.
R421
22_0805_5%
2
G
Compal Secret Data
2
2
+1.05VS_VCCP
5,9,32,47
50 VGA_PW ROK
100K_0402_5%
Q188
2N7002_SOT23-3
2
G
R146
1
D
PJ28
JUMP_43X79
@
+5VS_ODD
+0.75VS
R422
100K_0402_5%
+5VALW
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
C217
0.01U_0402_25V7K
1 ZODD@
C489
C480
R429
1U_0402_6.3V6K
FDS6676AS_SO8
Q45
2
AO3413_SOT23
ZODD@
Vgs=-4.5V,Id=3A,Rds<97mohm
C471
0.1U_0402_16V7K
ZODD@
C481
4.7U_0805_10V4Z
470_0805_5%
CL686
1U_0402_6.3V6K
1
2
3
4
C484
S
S
S
G
3 1
2
2
1
2
1
CL685
4.7U_0805_10V4Z
@
D
D
D
D
0.1U_0402_25V6
@
CL484
0.01U_0402_25V7K
8
7
6
5
4.7U_0805_10V4Z
AO3413_SOT23
PJ33
JUMP_43X79
@
+3V_LAN
47K_0402_5%
@ QL52
2
Vgs=-4.5V,Id=3A,Rds<97mohm
@ RL434
Q43
CL485
@
0.1U_0402_16V7K
47K_0402_5%
Q53B
ZODD@
ZODD@
Vgs=10V,Id=14.5A,Rds=6mohm
33,38 W OL_EN
26
R441
10K_0402_5%
ZODD@
R440
1
2
+3VS
+1.5V_MEM_GFX
+3VALW
RL148
100K_0402_5%
@
470_0805_5%
+5VS TO +5VS_ODD
C255
2 @
@
C499
2 0.01U_0402_25V7K
C252
2 NLS@
1
+1.5V
ODD_EN#
1
0.1U_0402_16V4Z
1 SLG59M232VTR_TDFN14-10_3X2
5
+3VALW
C249
2 @
120P_0402_50V4Z
+1.5V to +1.5V_MEM_GFX
1
0.1U_0402_16V4Z
C236
2@
+3VALW TO +3V_LAN
3 1
0.1U_0402_16V4Z
11
GND
2 R419 1
0_0402_5%
NLS@
38,47,48,50 SUSP#
R457
470_0805_5%
ZODD@
PS3@
+5VS_ODD
+3VS
1
GND
Q12B
10
MOS1_S
SUSP
2
1
Q12A
2
Q44A
SUSP
R414
820K_0402_5%
+5VALW
2 0.75VR_EN 5
100K_0402_5%
MOS1_D
1
1 C496
0.01U_0402_25V7K
@
2
2
3 1
1
R158
46,47 VCCPPW RGD
0.75VR_EN# 47
Q44B
PS3@
PS3@
Q190
SUSP
2
G
2N7002_SOT23-3
1
C469
R408
1 R411
2
+VSB
220K_0402_5%
2
1
1
NLS@
U46
+3VALW
R415
0_0402_5%
R425
100K_0402_5%
PS3@
Q11B
+5VS
NLS@
SI4800BDY_SO8
@
Each 250pF on CAP_MOS1 (2) will make

Slew Rate(uS/V) increase of 100uS/V
+5VALW
+3VALW
For S3 CPU Power Saving
C821
SUSP#
+1.8VS
R470
470_0805_5%
C463
1U_0402_6.3V6K
SUSP
C822
D
D
D
D
3 1
OLS@
5
38,47,48,50
470_0805_5%
OLS@
Q11A
2
8
7
6
5
R413
200K_0402_5%
@
+VSB
For EMI
OLS@
C468
OLS@
OLS@
1 R410
2
47K_0402_5%
R407
OLS@
FDS6676AS_SO8
@
C464
0.1U_0402_16V4Z
C467
SI4800BDY_SO8
C461
1U_0402_6.3V6K
0.1U_0402_25V6
Q10B
W PS3@
S 1
S 2
S 3
G 4
C470
Q10A
2 OLS@ SUSP
1
2
3
4
S
S
S
G
4.7U_0805_10V4Z
+VSB
OLS@
D
D
D
D
0.1U_0402_16V4Z
R412
330K_0402_5%
OLS@
8
7
6
5
C466
OLS@
1 R409
2
47K_0402_5%
+1.5VS
Vgs=10V,Id=14.5A,Rds=6mohm
Q31
R406
OLS@
C465
4.7U_0805_10V4Z
0.022U_0402_25V7K
SI4800BDY_SO8
C460
C459
1U_0402_6.3V6K
0.01U_0402_25V7K
4.7U_0805_10V4Z
1
2
3
4
S
S
S
G
470_0805_5%
OLS@
D
D
D
D
1
4.7U_0805_10V4Z
3 1
Q29
Q31
4.7U_0805_10V4Z
+5VS
4.7U_0805_10V4Z
1
C462
Q30 OLS@
8
7
6
5
+1.5V
+5VS
Vgs=10V,Id=9A,Rds=18.5mohm
1
+1.5V to +1.5VS
Vgs=10V,Id=9A,Rds=18.5mohm
+5VALW
Only for PWWHA DIS unmount
+3VS
+3VALW TO +3VS
+3VALW
for EMI
Title
DC-DC INTERFACE
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
E
41
of
53
@ PD1
VIN
PL1
SMB3025500YA_2P
1
2
PF1
DC_IN_S1 1
@ PJP1
N3
B+
@ PR2
1K_1206_5%
RLS4148_LL34-2
@ PR3
1K_1206_5%
1
@
@ PR5
2.2M_0402_5%
2
1
PR38
511K_0402_1%
PR7
66.5K_0402_1%
@
VS
+3VLP
PJ332
1 1
+3VL
JUMP_43X39
(7A,280mils ,Via NO.= 14)

OCP=7.7A
@ PJ152
1 1
JUMP_43X118
(100mA,40mils ,Via NO.= 2)

2
+5VALW P
+5VALW P
PQ2 @
DTC115EUA_SC70-3
+3VALW
JUMP_43X118
1
LM393DG_SO8
22K_0402_1%
2
+
@ PU2A
PC5
0.1U_0603_25V7K
+3VALW P
1
2
0.22U_0603_25V7K
2
PC6
@ PJ333
44
N1
2
1
51_ON#
PACIN
PR11
40
2
G
S
1
PR10
100K_0402_1%
PQ1
SSM3K7002FU_SC70-3
N1
1
RLS4148_LL34-2
BATT+
PR9
68_1206_5%
2
TP0610K-T1-E3_SOT23-3
PD4
PC14
1000P_0402_50V7K
@ PR39
47K_0402_1%
2
1
@
PR8
68_1206_5%
PQ4
44
@
PR35
255K_0402_1%
@ PR36
150K_0402_1%
PC16
1000P_0402_50V7K
@ PC13
1000P_0402_50V7K
RLS4148_LL34-2
@ PR6
34K_0402_1%
LM393DG_SO8
PD3
6251VREF
ACON
EN0
44
45
VIN
@ PU2B
N1
@ PD2
RB715F_SOT323-3
2
1
3
VL
@ PR4
100K_0402_1%
1
2
PC4
100P_0402_50V8J
PC3
1000P_0402_50V7K
SINGA_2DW -0005-B03
10A_125V_451010MRL
PC2
100P_0402_50V8J
2
1
PC1
1000P_0402_50V7K
DC_IN_S2
VIN
@ PR1
1K_1206_5%
PJ352
+5VALW
+1.5VP
@ PJ153
1 1
+1.5V
JUMP_43X118
JUMP_43X118

OCP=7.9A
(16A,640mils ,Via NO.= 32)
@ PJ72
+VSBP
+VSB
JUMP_43X39
@ PJ182
2
+1.8VSP
(120mA,40mils ,Via NO.= 1)
@ PJ402
+1.8VS
JUMP_43X118
JUMP_43X118
(1.65A,70mils ,Via NO.= 4)

OCP=4.2A
@ PJ76
+0.75VSP
@ PJ403
+1.05VS_VCCPP
+0.75VS
+1.05VS_VCCP
JUMP_43X118
JUMP_43X79

+VCCSAP
@ PJ452
2
1 1
+VCCSA
JUMP_43X118
(12A,480mils ,Via NO.=24)
@ PJ602
1 1
JUMP_43X118
+VGA_COREP
@ PJ603
1 1
ACIN
Precharge detector
Min.
typ.
Max.
H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V
+VGA_CORE
JUMP_43X118
(30A,1200mils ,Via NO.=60)
Issued Date
.
A
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
C
Title
DCIN/VIN DECTOR
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
D
42
of
53
VMB
@ PJP2
1
PH1 under CPU botten side :

CPU thermal protection at 95 degree C
Recovery at 56 degree C
BATT+
1
PC7
1000P_0402_50V7K
PC8
0.01U_0402_25V7K
SUYIN_200045MR009G171ZR
@ PC15
.1U_0402_16V7K
PR14
1K_0402_1%
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
15A_65V_451015MRL
GND
GND
GND
GND
BATT_S1
1
2
3
4
5
6
7
8
9
10
11
12
13
PL2
SMB3025500YA_2P
1
2
PF2
1
2
3
4
5
6
7
8
9
PH1+
PR15
19.6K_0402_1%
1
0.1U_0603_25V7K
+3VL
PC9
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
PR22
20K_0402_1%
38,44
100K_0402_1%_NCP15W F104F03RC
BATT_TEMPA 38
VS_ON
45
G718TM1U_SOT23-8
EC_SMB_DA1 38
PR21
100_0402_1%
PR28
88.7K_0402_1%
PR20
100_0402_1%
PH1
ADP_I
PR18
8.66K_0402_1%
PU1
PR19
1K_0402_1%
PR16
6.49K_0402_1%
2
1
PD5
2
PJSOT24C_SOT23-3
3
38
VL
PD6
PJSOT24C_SOT23-3
PR27
100K_0402_1%
EC_SMB_CK1 38
D
PQ7
SSM3K7002FU_SC70-3
+3VS
@ PJ334
2
PR29
10K_0402_1%
2
G
S
5,38 H_PROCHOT#
JUMP_43X39
PQ5
TP0610K-T1-E3_SOT23-3
3
B+
Adapter
+VSBP
Throttle Watt
Recovery Watt
Throttle Point
Recovery Point
65W_UMA
71.25W
62.4W
1.48V
1.308V
75W_DIS
85.5W
72W
1.78V
1.5V
75W_QCore
85.5W
72W
1.78V
1.5V
PR24
1
PR25
100K_0402_1%
1
2
1
2
VL
PC10
0.22U_0603_25V7K
2
1
PR23
100K_0402_1%
PC11 @
0.1U_0603_25V7K
22K_0402_1%
PR26
23,45
POK
PQ6
SSM3K7002FU_SC70-3
2
G
@ PC12
.1U_0402_16V7K
0_0402_5%
Issued Date
.
A
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
C
Title
BATTERY CONN / OTP

Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
D
43
of
53
CSIP
VIN
2
1
2
ACSET ACPRN
23
EN
CSON
22
CELLS
CSOP
21
ICOMP
CSIN
20
PR2312
ACOFF
PQ213
DTC115EUA_SC70-3
ACOFF
2
PHASE
LX_CHG
VREF
UGATE
17
DH_CHG
BST_CHG 1
2
2.2_0603_1%
11
VDDP
15
6251VDDP
VADJ
LGATE
14
DL_CHG
GND
PGND
13
ACLIM
12
0.1U_0603_25V7K
PD202
RB751V-40_SOD323-2
1
2 6251VDD
PR233
PC221
4.7U_0603_6.3V6M
1
3
0.02_1206_1%
16
BOOT
BATT+
4
2
PR206
4.7_1206_5%
PC205
BST_CHGA 2
1
24K_0402_1%
PR223
20K_0402_1%
5
6
7
8
5
6
7
8
10
CHLIM
PR235
6251aclim
PL202
10UH_MSCDRI-104A-100M-E_4.6A_20%
CHG
CHG1
1
2
PQ202
AO4466L_SO8
1
6251VREF
1
2
2_0402_5%
PR205
PR222
PC206
680P_0603_50V7K
PC204
10U_1206_25V6M
2
1
ICM
18
PQ216
SSM3K7002FU_SC70-3
1 20_0402_5%
2
G
19
PACIN
4.7_0603_5%
38
PC222
PC202
10U_1206_25V6M
2
1
PR221
120K_0402_1%
PC216
ACON
42
PQ201
AO4466L_SO8
IREF
6251VREF
6251VREF
CSOP
PC220
0.1U_0603_25V7K
1
PR232
CSIP
VCOMP
CSON
PC219
0.047U_0402_16V7K
1
2
PR230
20_0402_5%
42
PR220
154K_0402_1% .1U_0402_16V7K
2
1
PR229 20_0402_5%
1
2
38
PR219
1
2
100_0402_1%
ADP_I
PC215
1
2
0.1U_0402_25V6
PACIN
10K_0402_1%
42
PR211
22K_0402_5%
1
2
0.01U_0402_25V7K
38,43
6800P_0402_25V7K
PR218
5
G
PACIN
PC214
1
2
0.01U_0402_25V7K
PQ212B
DMN66D0LDW -7_SOT363-6
PC213
1
2
PQ212A
ACPRN
VIN
1SS355_SOD323-2
3
2
1
6251_EN
PQ215
DTC115EUA_SC70-3
100K_0402_1%
200K_0402_1%
0.1U_0603_25V7K
2
G
1 PR290
PD10
DCIN 2
ACOFF
2
24
DCIN
1SS355_SOD323-2
1.26V
PR228
14.3K_0402_1%
PC218
VDD
VIN
47K_0402_1%
PD9
PR237
10K_0402_1%
ACSETIN
PC217
1000P_0402_25V8J
2
1
1 1
PR236
1 1
6251VDD
PU200
PQ211
DTC115EUA_SC70-3
PR227
10_1206_5%
PR217
PR213
150K_0402_1%
FSTCHG
38
PR216
10K_0402_1%
2
1
PR226
191K_0402_1%
PD201
RB751V-40_SOD323-2
ACSETIN
LDO 5.075V
PR212
200K_0402_1%
PC212
2.2U_0603_6.3V6K
1
2
3
PC210
0.1U_0603_25V7K
2
1
PQ210
DTA144EUA_SC70-3
1
PR210
47K_0402_1%
PC211
5600P_0402_25V7K
PC203
10U_1206_25V6M
2
1
CHG_B+
PL210
1
2
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
CSIN
B+
0.02_1206_1%
1
3
2
1
P3
8
7
6
5
PC231
4.7U_0805_25V6-K
2
1
1
2
3
1
2
3
PQ208
APM4315KC-TRG_SO8
8
7
6
5
1
2
3
PC233
4.7U_0805_25V6-K
2
1
PQ204
SI4483ADY-T1-GE3_SO8
8
7
6
5
VIN
PC232
4.7U_0805_25V6-K
2
1
PR215
PC209
10U_1206_25V6M
2
1
PQ203
APM4315KC-TRG_SO8P2
PC208
10U_1206_25V6M
2
1
PC207
10U_1206_25V6M
2
1
ISL6251AHAZ-T_QSOP24
PR224
38 CHGVADJ
15.4K_0402_1%
PR225
31.6K_0402_1%
6251VDD
1
ACIN
PACIN
CHGVADJ
0V
4.2V
1.882V
4.35V
3.2935V
CP mode
Iada=0~3.42A(65W)
.1U_0402_16V7K
47K_0402_1%
Vin Detector
4V
PC223
PR248
PR243
14.3K_0402_1%
CHGVADJ=(Vcell-4)*9.445
38
ADP_V
ACPRN
VCHLIM need over 95mV
PQ214
DTC115EUA_SC70-3
IREF=0.254V~3.048V
Vcell
PR247
10K_0402_1%
1
2
IREF=1.016*Icharge
23,38
PR246
309K_0402_1%
PR242
10K_0402_1%
PR240
47K_0402_1%
CC=0.25A~3A
PR241
10K_0402_1%
1
2
VIN
High 18.089V
Low 17.44V
1.26 / 14.3 * 205.3 = 18.089V

CP= 92%*Iada; CP=3.147A
Vaclim=1.08V(65W)
PR222=75k PR223=20k
Iada=0~3.947A(75W)
CP= 92%*Iada; CP=3.63A
Issued Date
Vaclim=0.736V(75W)
PR222=24k PR223=20k PR215=0.02
http://mycomp.su
-
. , ,
.
A
Compal Secret Data
PR215=0.02
2010/09/03
Deciphered Date
2012/12/31
C
Title
CHARGER
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
D
44
of
53
2VREF_8205
PC363
1U_0603_10V6K
PR364
30K_0402_1%
1
2
PR363
20K_0402_1%
1
2
PR365
19.1K_0402_1%
1
2
PC366
10U_1206_25V6M
5
6
7
8
1
ENTRIP1
24
4
POK
22
UG_3V
10
DRVH2
DRVH1
21
PR355
BST_5V 1
2
0_0603_5%
UG_5V
LX_3V
11
LL2
LL1
20
LX_5V
LG_3V
12
DRVL2
DRVL1
19
LG_5V
PC355
2 0.1U_0603_25V7K
VCLK
RT8205LARGER_QFN24_4X4
5
G
PR361
PC364
4.7U_0805_10V6K
RT8205_B+
Ipeak=5A
Imax=3.5A
F=245KHz
Total Capacitor 150uF
2VREF_8205
2
VL
PQ360B
+
PC356
680P_0603_50V7K
1
2
100K_0402_5%
1
G
D
PQ360A
ENTRIP2
ENTRIP1
PC362
1U_0402_6.3V6K
PQ352
IRF8707TRPBF_SO8
Ipeak=5A
Imax=3.5A
F=305KHz
PL352
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
+5VALWP
1
2
PR356
4.7_1206_5%
2
B
AO4466L_SO8
13
18
EN0
EN0
5
6
7
8
23
VBST1
VREG5
PGOOD
VBST2
VIN
VREG3
23,43
PC352
330U_6.3V_M
VO1
3
2
1
2
VFB1
VREF
VFB2
TONSEL
6
ENTRIP2
3
2
1
B+
PQ351
PR360
499K_0402_1%
1
2
IRF8707TRPBF_SO8
ENTRIP2
PR357
150K_0402_1%
1
2
17
8
7
6
5
1
PC336
680P_0603_50V7K
42
1
2
3
330U_6.3V_M
RT8205_B+
BST_3V
PR336
4.7_1206_5%
1
PC332
PQ332
VO2
16
PL332
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
1
2
GND
PR335
1
2
0_0603_5%
P PAD
SKIPSEL
1
2
3
PC335
0.1U_0603_25V7K
1
25
15
PU330
14
PQ331
AO4466L_SO8
+3VALWP
PR337
150K_0402_1%
1
2
4.7U_0805_10V6K
PC361
2
1
8
7
6
5
10U_1206_25V6M
1
PC368
1
2
PC367
1U_0805_25V7
+3VLP
PC360
10U_1206_25V6M
B+
ENTRIP1
PL331
RT8205_B+
HCB2012KF-121T50_0805
PR362
13K_0402_1%
1
2
PC365
0.1U_0603_25V7K
PR370
VL
1
1
100K_0402_1%
43
VS_ON
PR371
0.01U_0402_16V7K
PR372
2
A
PC370
2
1
2
1
1
2
100K_0402_1%
42.2K_0402_1%
VS
PQ361
DTC115EUA_SC70-3
Compal Secret Data
2009/09/03
Issued Date
Deciphered Date
2012/12/31
5
4

.
Title
3VALWP/5VALWP
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:
Sheet
1
45
of
53
HCB2012KF-121T50_0805
D
PL451
255K_0402_1%
PR460
0_0402_5%
0.1U_0402_25V6
2
1
PC475
@
0.1U_0402_25V6
2
1
PC476
PC474
@
0.1U_0402_25V6
2
1
1
2
PC473
@
0.1U_0402_25V6
2
1
PC472
@
0.1U_0402_25V6
PC471
0.1U_0402_25V6
2
1
1
PC469
0.1U_0402_25V6
2
1
PC468
10U_1206_25V6M
PC466
0.1U_0402_25V6
2
1
1
2
10K_0402_1%
ILIM
FB
VDD
PGOOD
SA_PGOOD
DL
3
2
1
DH_VCCSAP
LX_VCCSAP
11
PR457
1
2
14.3K_0402_1%
+5VALW
1
10
PR456
4.7_1206_5%
PQ452
+ PC452
330U_6.3V_M
PC462
4.7U_0805_10V6K
+VCCSAP
0.1U_0603_25V7K
1
13
12
15
14
BST
TP
LX
VCC
DH
OUT
PL452
1.8U_D104C-919AS-1R8N_9.5A_30%
1
2
PC455
1
2
2
PC456
DL_VCCSAP
TPS5117_TQFN14_3P5X3P5
BST_VCCSAP-1
680P_0603_50V7K
PR463
0_0402_5%
IRF8707TRPBF_SO8
+3VS
38
Ipeak=6A
Imax=4.2A
F=276K
Toatal Capacitor 660u
PQ451
AO4466L_SO8
PR471
4
FB
TON
PGND
AGND
VOUT
EN_SKIP
PU450
@ PC460
.1U_0402_16V7K
PR461
100_0402_1%
1
2
PC461
4.7U_0805_10V6K
PC467
1U_0805_25V7
0_0603_5%
+5VALW
B+
PR455
1
5
6
7
8
41,47 VCCPPWRGD
BST_VCCSAP
3
2
1
PC465
2200P_0402_50V7K
2
1
PR462
1
1
PC464
4.7U_0805_25V6-K
5
6
7
8
PC463
4.7U_0805_25V6-K
VCCSAP_B+
@ PR472
10K_0402_1%
VCCSA_SENSE
PR464
10_0402_5%
2
1
PR465
680_0402_1%
1
2
2
B
3
@ PR470
100K_0402_1%
2
G
S
PQ453
SSM3K7002FU_SC70-3
PR468
10K_0402_1%
PC470
.1U_0402_16V7K
PR469
10K_0402_1%
1
2
PR467
5.1K_0402_1%
+3VS
PR466
9.09K_0402_1%
PR473
0_0402_5%
1
2
VCCSAP_VID1
E
PQ454
MMST3904-7-F_SOT323-3
VID1
+VCCSAP
0.8V
0.9V
Issued Date
.
5
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
Title
+VCCSAP
Size
C
Date:
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Sheet

1
46
of
53
@ PJ75
JUMP_43X79
+1.5V
GND
NC
VREF
NC
VOUT
NC
TP
+3VALW
Ipeak=0.5A
Imax=0.35A
PC264
PR280
1K_0402_1%
VCNTL
5,9,32,41 SUSP
VIN
PC261
4.7U_0805_6.3V6K
PR282
0_0402_5%
1
2
PU75
1U_0603_10V6K
PC263
.1U_0402_16V7K
2
1
+0.75VSP
1
2
PR281
1K_0402_1%
PC262
10U_0805_6.3V6M
For shortage changed
PL401
HCB4532KF-800T90_1812
1
2
VDD
10
3
2
1
9
DL_1.05VS_VCCP
3
2
1
PC412
4.7U_0805_10V6K
DL
PQ402
PGOOD
11K_0402_1%
AON6788_DFN8-5
FB
PGND
VFB=0.75V
PC415
4.7U_0805_25V6-K
PR406
4.7_1206_5%
+5VALW
LX_1.05VS_VCCP
PR407
1
2
VCC
+1.05VS_VCCPP
12
11
OUT
PC406
680P_0603_50V7K
LX
ILIM
2
1
DH_1.05VS_VCCP
DH
PL402
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1 2
13
TON
PC402
330U_6.3V_M
Ipeak=12.5A
Imax=8.75A
F=305KHz
PR415
41,46 VCCPPW RGD
B+
AON6428L_DFN8-5
PC405
0.1U_0603_25V7K
1
2
BST
TP
14
15
PR405
0_0603_5%
BST_1.05VS_VCCP
1
2
PR411
100_0603_1%
1
2
PU400
EN_SKIP
PC410
@
.1U_0402_16V7K
PC414
4.7U_0805_25V6-K
2
1
PC416
10U_1206_25V6M
2
1
PR510
0_0603_5%
AGND
PC411
4.7U_0603_6.3V6K
PQ401
PR410
0_0402_5%
1
2
38,41,48,50 SUSP#
+5VALW
PR414
255K_0402_1%
1
2
PC413
4.7U_0805_25V6-K
2
1
1.05VS_B+
PR420
0_0402_5%
PQ260
SSM3K7002FU_SC70-3
PC260
.1U_0402_16V7K
2
G
1
41 0.75VR_EN#
G2992F1U_SO8
@ PR279
0_0402_5%
1
2
+3VS
10K_0402_1%
@ PR416
10K_0402_1%
PR421
10_0402_5%
2
1
VCCIO_SENSE
PR412
4.02K_0402_1%
1
2
PR413
10K_0402_1%
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
5
4

.
Title
+1.05VS_VCCP/+0.75VSP
Size
Document Number
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
1
47
of
53
HCB2012KF-121T50_0805
PL151
1.5_B+
PR165
PR164
255K_0402_1%
1
2
PR160
VDD
10
PGOOD
VFB=0.75V
DL
PR157
1
2
11K_0402_1%
+5VALW
DL_1.5V
4
2
+1.5VP
FB
PC162
4.7U_0805_10V6K
PR156
4.7_1206_5%
1
+ PC152
330U_6.3V_M
2
1
LX_1.5V
VCC
0.1U_0603_25V7K
PQ152
12
11
OUT
PL152
1UH_FDUE1040D-1R0M-P3_21.3A_20%
PC155
1
2
AON6788_DFN8-5
14
TP
BST
LX
ILIM
PC161
4.7U_0603_6.3V6K
DH_1.5V
PGND
100_0603_5%
13
DH
AON6428L_DFN8-5
BST_1.5V-1
TON
PC156
680P_0603_50V7K
DIS :
UMA :
Ipeak=18A
Ipeak=12A
Imax=12.6A
Imax=8.4A
------------------------------------------------F=294KHz
Total Capacitor1050(dis)uF,
720(uma)uF
PR162
1
@ PC165
680P_0402_50V7K
0_0603_5%
0_0603_5%
AGND
PR161
1
+5VALW
EN_SKIP
PU150
15
1
2
PC160 @
.1U_0402_16V7K
3
2
1
BST_1.5V
0_0402_5%
PR155
3
2
1
SYSON
35,38
B+
PC164
4.7U_0805_25V6-K
2
1
1
5
PQ151
PC163
4.7U_0805_25V6-K
2
1
1
PC166
10U_1206_25V6M
10K_0402_1%
PR163
10.5K_0402_1%
Ipeak=1.65A
ILIM = 4A
F=1MHz
0.1U_0402_10V7K
PC1810
1U_0603_10V6K
1
2
2
1
2
1
2
1
2
PR184
10K_0402_1%
PC1820
4.7U_0805_25V6-K
PU1800
FB
+1.8VSP
0.47U_0402_6.3V6K
@
PR1820
3K_0402_1%
APL5930KAI-TRG_SO8
@
@ PC1850
4
3
4
EN
POK
VOUT
VOUT
PC1840
22U_0805_6.3V6M
8
7
1
38,41,47,50 SUSP#
VCNTL
VIN
VIN
PR1810
0_0402_5%
1
2
6
5
9
PC1830
0.01U_0402_25V7K
PC185@
GND
@ PR182
499K_0402_1%
FB_1.8V
+5VALW
3
PJ1810
@ JUMP_43X39
PC182
22U_0805_6.3VAM
PC186
0_0402_5%
PR183
20K_0402_1%
PC187
68P_0402_50V8J
2
1
NC
FB=0.6Volt
2 EN_1.8V
PR181
TP
11
38,41,47,50 SUSP#
NC
FB
EN
PR186
LX
SVIN
PVIN
PC184
22U_0805_6.3VAM
JUMP_43X39
LX
LX_1.8V
+3VALW
+1.8VSP
PL182
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
2
PVIN
10
4.7_1206_5%
680P_0603_50V7K
+5VALW
PG
@ PJ181
PC183
22U_0805_6.3VAM
PU180
SY8033BDBC_DFN10_3X3
PR1830
2.4K_0402_1%
Issued Date
.
A
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
C
Title
+1.5VP/+1.8VSP
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
D
48
of
53
@ PH501
3.83K_0402_1%
470KB_0402_5%_ERTJ0EV474J
NTCG
1
@ PC556
330P_0402_50V7K
1
2
PC557
330P_0402_50V7K
2
1
ISNG
38
ALERT#
SCLK
32
LGATE2
31
VDDP+
PWM3
30
VSSP1
28
PH1
27
PHASE1
UG1
26
UGATE1
BOOT1
25
BOOT1
1000P_0402_50V7K
2
1
PR516
680P_0603_50V7K 4.7_1206_5%
PR580
ISEN2
PR581
10K_0402_1%
ISEN1
10K_0402_1%
PR582
VSUM+
3.65K_0402_1%
PR583
VSUM-
@ PC552
@PR555
@
PR555
330P_0402_50V7K 100_0402_1%
2
1
2
1
PR509
0_0603_5%
1
+
AON6428L_DFN8-5
PL504
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1
PHASE1
PC525
0.22U_0603_25V7K
BOOT1 2
1 2
1
PR525
0_0603_5%
LGATE1
4
PC569
100U_25V_M
PC566
100U_25V_M
UGATE1
VSUM-
PC568
100U_25V_M
PQ503
PH503
10K_0402_1%_ERTJ0EG103FA
PC583
4.7U_0805_25V6-K
2
1
1 2
1
PR556
11K_0402_1%
PR557
PC551
0.047U_0402_25V7K
CPU_B+
PC546
PR554
1.47K_0402_1%
2
1
+CPU_CORE
VSUM+
PQ504
330P_0402_50V7K
2
1
AON6788_DFN8-5
PC545
1_0402_5%
PC544 0.22U_0402_6.3V6K
PR551
2
1
3.32K_0402_1%
3
2
1
VSSSENSE
470P_0402_50V7K
LGATE2
B+
PL503
0.36UH_PCMC104T-R36MN1R17_30A_20%
3
2
1
VCCSENSE
2
PL501
HCB4532KF-800T90_1812
PC515
0.22U_0603_25V7K
BOOT2 2
1 2
1
PR515
0_0603_5%
+5VALW
1
8
PC562 0.22U_0402_6.3V6K
PHASE2
PC516
2
1
PR560
1.69K_0402_1%
PC553
2
1
Reserve for slow rate
@ PR550
2K_0402_1%
2
1
VSUM-
AON6428L_DFN8-5
PC549
0.22U_0603_25V7K
1
PC550
0.22U_0402_10V6K
2
1
@ PC555
100P_0402_50V8J
2
1
499_0402_1%
2
1
PC543
PR549
150P_0402_50V8J 316K_0402_1%
2
1
2
1
330P_0402_50V7K
1_0603_5%
PC559
0.22U_0402_10V6K
2
1
2
PC542
PR548
PC547
499K_0402_1%
3
2
1
ISEN1
ISEN2
22P_0402_50V8J
1U_0603_10V6K
PC548
2
1
PC540
PC541
10P_0402_50V8J
@ PR547
UGATE2
PQ508
AON6788_DFN8-5
CPU_B+
PR558
PQ505
1
2
0_0603_5%
For Turbo mode , PH502 must be

changed 470K (b value = 4700)
CPU_B+
PR508
0_0603_5%
PR559
ISEN3
1000P_0402_50V7K
PC539
PR546
1
PR545
27.4K_0402_1%
+5VALW
PU500
LGATE1
3.83K_0402_1%
8.06K_0402_1%
PR562
0_0603_5%
1
2
3
2
1
29
PROG1
VIN
LG1
24
23
VDD
ISUMP
22
13
470KB_0402_5%_ERTJ0EV474J
2
21
VW
ISUMN
12
20
NTC
RTN
VR_HOT#
11
VSEN
10
19
IMON
18
ISEN1
PGOOD
ISEN2
ISEN3/ FB2
VR_ON
16
COMP
PR540
LG2
VDDP
ISL95831CRZ-T_TQFN48_6X6
PC567
10U_1206_25V6M
2
1
PC574
10U_1206_25V6M
2
1
VR_SVID_CLK
PC565
4.7U_0805_25V6-K
2
1
VR_SVID_ALRT#
PC582
4.7U_0805_25V6-K
2
1
33
PC580
4.7U_0805_25V6-K
2
1
VSSP2
SDA
PC554
2.2U_0603_10V6K
2
1
39
37
LGG
PHG
UGG
1
40
41
PROG2
BOOTG
ISNG
NTCG
42
NTCG
44
43
.1U_0402_16V7K
ISPG
PHASE2
VR_SVID_DAT
2.61K_0402_1%
43P_0402_50V8J
PC537
ISNG
34
VDD+
1
2
@PR543
@
PR543
499_0402_1%
45
PH2
VR_HOT#
+1.05VS_VCCPP
46
PGOODG
VGATE
PH502
RTNG
UGATE2
PR544
47
BOOT2
35
15
1
PC561
0.033U_0603_16V7
2
1
PR542
29.4K_0402_1%
2
1
38
FBG
36
UG2
1.91K_0402_1%
5,23,38
VSENG
49
GND
BOOT2
IMONG
0_0402_5%
PR541
+3VS
COMPG
VWG
8 VR_SVID_CLK
+5VALW
Connect to +5V can disable GFX portion,

but PR575 need to be removed.
8 VR_SVID_ALRT#
VR_ON
48
+1.05VS_VCCPP
8 VR_SVID_DAT
1
2
PR576 0_0402_5%
@ PR567
16.5K_0402_1%
38
VSS_AXG_SENSE
@ PC558
1000P_0402_50V7K
PR534
2.55K_0402_1%
FB
@ PR533
475K_0402_1%
PC534
0.047U_0603_16V7K
PR539
24.9K_0402_1%
2
1
PC533
150P_0402_50V8J
1
PR538
54.9_0402_1%
PC585
4.7U_0805_25V6-K
2
1
PC560
.1U_0402_16V7K
2
1
PR537
130_0402_1%
VCC_AXG_SENSE
@ PC532
@PC532
680P_0402_50V7K
1
680P_0603_50V7K 4.7_1206_5%
1 2
@PR532
422_0402_1%
PC581
4.7U_0805_25V6-K
2
1
14
499K_0402_1%
PC584
4.7U_0805_25V6-K
2
1
PC531
68P_0402_50V8J
2
1
@PR564 27.4K_0402_1%
@PR564
1
2
17
@ PR531
PR526
@ PR563
2
PC526
2
1
PC530
1000P_0402_50V7K
PR530
8.06K_0402_1%
PR591
ISEN1
+CPU_CORE
10K_0402_1%
VSUM+
PR590
PR592
VSUM-
1 ISEN2
10K_0402_1%
3.65K_0402_1%
PR593
1_0402_5%
Issued Date
.
5
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
3
Title
CPU_CORE/GFX
Custom
Date:
Rev
1.0
PWWHA LA-7201P M/B
Sheet
1
49
of
53
2 B+_VCORE
B+
PQ601
PR621
3K_0402_1%
1
2
PR607
DH_VCORE
BST_VCORE
0_0603_5%
PC605
0.1U_0603_25V7K
1
2
VBST
10
TRIP
DRVH
AON6428L_DFN8-5
PL602
RT8237
PC628
2.2U_0603_6.3V6K
PR606
4.7_1206_5%
PC602
330U_6.3V_M
11
PR632
4.3K_0402_1%
1
2
PC606
680P_0603_50V7K
PR631
10_0402_5%
1
2
1000P_0402_50V7K
PC632
2
1
DL_VCORE
2
TP
+VGA_COREP
+5VALW
PR630
0_0402_5%
DRVL
PR626
1
2
0_0603_5%
VCORE_VDD
1000P_0402_50V7K
PC635
2
1
LX_VCORE
V5IN
SW
VFB
EN
0.56U_PCMC104T-R56MN_25A_20%
1
2
PQ602
AON6788_DFN8-5
RF
PR605
0_0603_5%
1
2
3
2
1
PGOOD
5
PR625
470K_0402_1%
2
1
38,41,47,48 SUSP#
20K_0402_1%
2
PC623
.1U_0402_16V7K
PR622
1
3
2
1
PU600
PR624
120K_0402_1%
1
2
PR620
1.5K_0402_1%
41 VGA_PW ROK
Ipeak=20A
Imax=14A
F=300kHZ
Output capacitor=660uF
VCORE_VDD
4.7U_0805_25V6-K
PC622
2
1
10U_1206_25VAK
PC621
2
1
10U_1206_25VAK
PC620
2
1
PL601
HCB4532KF-800T90_1812
15
VDD_SENSE
+3VS
300KHZ
350KHZ
390KHZ
400KHZ
PR633
20K_0402_1%
PR634
100K_0402_1%
PR635
3K_0402_1%
1
2
1
@ PR642
100K_0402_1%
1V
P0(cold)
PQ606
SSM3K7002FU_SC70-3
GPU_VID1 13
@ PR643
3K_0402_1%
1
2
2
G
1V
PR644
22K_0402_1%
P0
PC634
.1U_0402_16V7K
0.85V
P8/P12
N12M-GE
GPU_VID1
GPU_VID0
PC633
.1U_0402_16V7K
1
2
+3VS
VFB(0.7)=Vout*Rbottom/(Rtop+Rbottom)
Pstate
GPU_VID0 13
20K_0402_1%
@
PR640
20K_0402_1%
PR641
B
PQ605
D SSM3K7002FU_SC70-3
2
G
S
PR636
22K_0402_1%
=
=
=
=
FSW
FSW
FSW
FSW
=>
=>
=>
=>
= 470Kohm
= 200Kohm
= 100Kohm
= 47Kohm
PR625
PR625
PR625
PR625
PR632=4.3K
PR633=20K
A
PR641=20K
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
5
4

.
Title
VGA_CORE
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
1
50
of
53
EBUF!!!!!!!!QBHF!!!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
............................................................................................................................
2010/12/31(PVT) P36 Charger
add snubber PR206,PC206
EMI command
2010/12/31(PVT) P36 Charger
change boost to 2.2 ohm PR205
EMI command
2010/12/31(PVT) P35 +3VALW/+5VALW
add snubber PR336,PC336,PR356,PC336
EMI command
2010/12/31(PVT) P37 +1.5VP/+1.8VSP
Change PR155,PR165 to 0 ohm
EMI command
2010/12/31(PVT) P37 +1.5VP/+1.8VSP
Change PQ151 to POK 5*6
EMI command
2010/12/31(PVT) P37 +1.5VP/+1.8VSP
Reserve snubber PR156,PC156
EMI command
2010/12/31(PVT) P37 +1.5VP/+1.8VSP
add PC165 for MEI
EMI command
2010/12/31(PVT) P37 +VCCSA
add snubber PR456,PC456
EMI command
2010/12/31(PVT) P38 +1.05VS/+0.75
change PRQ401 to POK 5x6
EMI command
2010/12/31(PVT)
change PR405,PR510 to 0 ohm
EMI command
2010/12/31(PVT) P38 +1.05VS/+0.75
change 0.75V enable PR279 tp PR282
HW command
2010/12/31(PVT)
P39 +CPU_CORE
change PC549,PC515,PC525 to correct rating
design change
2010/12/31(PVT)
P39 +CPU_CORE
change PL503,PL504 to DCR 5%
design change
2010/12/31(PVT) P39 +CPU_CORE
change PC568 PC 566 to 5.8mmm capacitor
design change
2010/12/31(PVT) P39 +CPU_CORE
change PC551 for load line adjust
design change
2010/12/31(PVT) P39 +CPU_CORE
change PR560 for program temperture
design change
P38 +1.05VS/+0.75
2010/12/31(PVT)
P39 +CPU_CORE
change PC505,PQ503 change to POK5X6
design change
2010/12/31(PVT)
P40+VGA_CORE
change PU600 to RT8237
design change
2010/12/31(PVT)
P40+VGA_CORE
change PR605,PR607 to 0ohm
design change
2010/12/31(PVT)
P40+VGA_CORE
change PR601 to POK 5X6
EMI command
2010/12/31(PVT)
P40+VGA_CORE
Issued Date
2010/09/03
design change
change VID0 and VID1 compont chage

Compal Secret Data
Deciphered Date
2012/12/31
5
4

.
Title
Power PIR
Size
Document Number
Rev
1.0
PWWHA LA-7201P M/B

Date:

2
Sheet
51
of
1
53
HW PIR (Product Improve Record)
PWWHA LA-7201P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2010/10/29
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
10/29
17
SWAP FBA_CMD2 and FBA_CMD11
Schematic error
2
10/29
18
SWAP FBA_CMD18 and FBA_CMD11
Schematic error
3
10/29
21
Chane +3V_SPI to +3VS
Schematic error
4
10/29
22
Add R23 for CLK_REQ_VGA#
Reserve pull down for clock request

NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
11/03
25,31 Add USB20_N9 & USB20_P9
Support Wimax
2
11/03
32
Co-Lay Giga LAN
Giga LAN support
3
11/22
22
Add R584 & R564 for Panel select
For HW common design
4
11/22
5
change D86 (SC100001M00)
5
11/22
5
cancel D85 @
6
11/24
32
LAN 8105E-VC update to 8105E-VL

NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
01/15
14
Change RV48 BOM structure from @ to HDMI@.
For HDMI function
2
01/15
15
Add net name +IFPE_IOVDD & +IFPE_PLLVDD
For HDMI function
3
01/15
15
Add LV12,CV160,CV169,CV170,CV173,LV8,CV178,CV159,CV176,CV182,CV215
For HDMI function
4
01/15
38
Add U19 BOM symbol for 9012
For EC 9012
5
01/15
19
Change R120 from 10Kohm to 47Kohm.
For backlight PWM issue
6
01/15
35
Change UT2.6 & RT1 connector from +5VALW to +3V and del CT1.
For LDO leakage issue
7
01/15
41
Add Q31 BOM symbol and add BOM structure PS3@.
For power saving function
8
01/16
13
Change R25 BOM structure from @ to NHDMI@.
For HDMI function
9
01/16
38
Delete U19.123 CLK_EC_R net name
Due to duplicate net name
10
01/16
38
Change U19.104 & R745.2 & R747.2 net name from PM_PWROK_R to PM_PWROK_EC. Due to duplicate net name
11
01/18
38
Add R757 & R759 & U19 BOM symbol and add BOM structure S9012@
For EC9012 solution
12
01/18
38
Add R767 and BOM structure S9012@
For EC9012 solution
13
01/19
21~29 Change U2 P/N from SA00003P440 to SA00004EE80.
For PCH P/N update
14
01/19
21~29 Change U2 BOM structure from Q65R3@ to HM65R1@.
For BOM structure update
15
01/19
40
Add U2 BOM symbol and BOM structure HM65R3@.
16
01/19
33
Change UL3 to SP050006E00
For EMI
17
01/20
5,7,9
Change C93,R312,U10,Q14,R465,R463,C140 BOM structure to PS3@
18
01/20
41
Change Q31 BOM symbol structure from PS3@ to @
Only for PWWHA DIS unmount
19
01/20
9
Change Q46,R449,C179,C472,R420,R455,Q33 BOM structure from @ to PS3@
Only for PWWHA DIS PS3@

NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
01/31
5
Change JFAN2.2 connect FAN_SPEED1, JFAN2.3 connect GND
For FAN pin define modification
2
02/09
5,38
Change Q5,Q41 from SB570020110 to SB570020020
For common material
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
5
4

.
Title
HW-PIR 1
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
1
52
of
53
HW PIR (Product Improve Record)

NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
01/31
5
Change JFAN2.2 connect FAN_SPEED1, JFAN2.3 connect GND
For FAN pin define modification
2
02/09
5,38
Change Q5,Q41 from SB570020110 to SB570020020
For common material
3
02/17
5
Change C902,R1445,D85,D86,C900,C901,R1444 from mount to @.
For unused PWM FAN
4
02/17
5
Change R24 from @ to mount.
For use RPM FAN
5
02/17
40
Change R396,Q7 from 930@ to mount.
For EC9012 function
6
02/17
31
Add C363
For solving ODD issue
7
02/17
31
Change SW3 from mount to @
For MP phase
8
02/17
41
Change C496,C499,C236,C249,C255 from NLS@ to @
For low cost power switch
9
02/17
41
Change R415,R419 from 47Kohm to 0ohm
10
02/17
40
Change ZZZ P/N from DA60000L700 to DAZ0II00101
For MP phase
11
02/17
41
Change C252 from SE070104Z80 to SE071121J80
12
02/17
31
Change R561,R562,R457,Q53,R441,R440,C471,C217,Q45 from mount to ZODD@
For zero ODD function
13
02/18
21~29 Change U2 P/N from SA00004EE80 to SA00004EES0
For PCH B3 version
14
02/18
40
Change U2 P/N from SA00004EEA0 to SA00004EET0
For PCH B3 version
15
02/22
40
ADD UV1 BOM symbol and BOM structure N12MR3@.
For N12M R3 P/N
16
02/22
13~16 ADD UV1 BOM structure N12MR1@.
For N12M R1 P/N
17
02/23 32,35,41 Change Q50,Q53,QT3 from SB00000EO00 to SB00000EO10
For common material
18
02/23
41
Change C465,C467 BOM structure from OLS@ to always mount
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
5
4

.
Title
HW-PIR 2
Size
Document Number
Custom
Rev
1.0
PWWHA LA-7201P M/B
Date:
Sheet
1
53
of
53

Compal LA-7201P M/B Schematic and Notes

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Compal LA-7201P M/B Schematic and Notes

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A

LA-7201P REV 1.0 Schematic

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

Compal Electronics, Inc.

Compal Secret Data

PWWHA LA-7201P M/B

Fan Control Circuit

Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

1.5V DDRIII 1066/1333/1600 MT/s

USB port 0,1

NVIDIA N12M-GE-S-B1 BGA 533P

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Electronics, Inc.

Compal Secret Data

PWWHA LA-7201P M/B

Friday, February 25, 2011

DESIGN CURRENT 0.1A

DESIGN CURRENT 10A

DESIGN CURRENT 1.8A

DESIGN CURRENT 5.5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4.5A

DESIGN CURRENT 0.5A

Ipeak=53A, Imax=36A, Iocp min=70A

DESIGN CURRENT 53A

Ipeak=20A, Imax=14A, Iocp min=26A

DESIGN CURRENT 21A

DESIGN CURRENT 17A

Ipeak=12.5A, Imax=8.75A, Iocp min=21.4A

Ipeak=6A, Imax=4.2A, Iocp min=7.76A

Ipeak=16.5A, Imax=11.55A, Iocp min=21.03A

DESIGN CURRENT 20A

DESIGN CURRENT 0.7A

Compal Electronics, Inc.

Compal Secret Data

PWWHA LA-7201P M/B

Friday, February 25, 2011

BTO Option Table

S5 S4/ Battery only

MINI PCI-E SLOT

Camera & Mic

Camera & Mic

Camera & Mic

PCH SM Bus Address

Compal Electronics, Inc.

Compal Secret Data

PWWHA LA-7201P M/B

Friday, February 25, 2011

Stuff R41 and R42 if do not support eDP

FAN Control Circuit

Compal Electronics, Inc.

Compal Secret Data

FAN Control Circuit (RPM and PWM)

Routed as a single daisy chain

PU/PD for JTAG signals

DDR3 Compensation Signals

Buffered Reset to CPU

23,38 PM_PW ROK

JTAG & BPM

Remove R14(o ohm) for HW Review demand

PWWHA LA-7201P M/B

Friday, March 04, 2011