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GII THIU TI
ti ny trnh by v thit k h thng x l nh Video trn FPGA (Cyclone
II) bao gm cc thnh phn: Thu nhn v s ha tn hiu Video Analog, x l nh
Video s, hin th ln VGA.
Trong ti ny ngoi Cyclone II cc thnh phn tch hp trn Kit DE2 m ta
s s dng l: Chip m ha tn hiu Video Analog ADV7181B, SDRAM IS42S16400
lu tr v xut frame nh hp l, cng VGA (chip ADV7123) hin th nh ln
mn hnh.

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1. GII THIU V NGN NG VHDL V FPGA
1.1 NGN NG VHDL
VHDL l mt ngn ng m t phn cng (hardware description language), m
t hnh vi ca mch in hoc h thng, t mch in vt l hoc h thng c th
c thc thi.
VHDL l vit tt ca VHSIC Hardware Description Language. Bn thn
VHSIC l vit tt ca Very High Speed Integrated Circuits (mch tch hp tc
cao), ln u tin c sng lp bi United State Department of Defense trong nhng
nm 80, sau to ra VHDL. Phin bn u tin l VHDL 87, ln nng cp sau c
tn l HDL 93. VHDL l ngn ng m t phn cng nguyn gc u tin c chun
ha bi Institue of Electrical and Electronics Engineers (IEEE), ti chun IEEE 1076.
Trong IEEE 1164, c mt chun c thm vo l gii thiu h thng logic a gi tr
(multi-valued logic system).
ng c thc y c bn khi dng VHDL (hay dng Verilog) l VHDL l mt
ngn ng c lp chun ca cc nh cng ngh, cc nh phn phi do chng c
kh nng portable v k tha cao (reusable). Hai ng dng trc tip chnh ca VHDL
l trong mng cc thit b logic lp trnh c (Programmable Logic Devices) (bao
gm CPLDs Complex Programmable Logic Devices v FPGAs Field
Programmable Gate Arrays). Mi khi m ngun VHDL c vit, chng c th c
dng thc thi mch in trong cc thit b lp trnh c (t Altera, Xilinx, Almel,
..) hoc c th gi n cc xng ch to cc chp ASIC. Hin ny, rt nhiu cc chip
thng mi phc tp (v d nh cc microcontrollers ) c thit k da trn cch tip
cn ny.
Mt iu ch v VHDL l tri ngc vi cc chng trnh my tnh thng
thng c thc hin tun t th cc cu lnh c thc hin song song (concurrent).
V l do , nn VHDL thng c coi l mt m ngun hn l mt chng trnh.
Trong VHDL ch c cc cu lnh t trong PROCESS, FUNCTION, hay
PROCEDURE c thc thi tun t.
Mt trong nhng tin ch ln ca VHDL l cho php tng hp mch in hoc
h thng trong thit b kh lp trnh (programmable devide) (PLD hoc FPGA) hoc
trong mt h ASIC.
1.2 FPGA
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FPGA (Field Programable Gate Arrays) l mt thit b bn dn bao gm cc
khi logic lp trnh c gi l "Logic Block", v cc kt ni kh trnh. Cc khi
logic c th c lp trnh thc hin cc chc nng ca cc khi logic c bn nh
AND, XOR, hoc cc chc nng kt hp phc tp hn nh decoder hoc cc php
tnh ton hc. Trong hu ht cc kin trc FPGA, cc khi logic cng bao gm c cc
phn t nh. c th l cc Flip-Flop hoc nhng b nh hon chnh hn.
Cc kt ni kh trnh cho php cc khi logic c th ni vi nhau theo thit k
ca ngi xy dng h thng, ging nh mt bng mch kh trnh.
Mt s kin trc FPGA hin nay cn c th cho php cu hnh li tng phn
(partial re-configuration). C ngha l cho php mt phn ca thit k c cu hnh
li trong khi nhng thit k khc vn tip tc hot ng.
Mt u im khc ca FPGA, l ngi thit k c th tch hp vo cc b
x l mm (soft processor) hay vi x l tch hp (embedded processor). Cc vi x l
ny c th c thit k nh cc khi logic thng thng, m m ngun do cc hng
cung cp, thc thi cc lnh theo chng trnh c np ring bit, v c cc ngoi vi
c thit k linh ng ( khi giao tip UART, vo/ra a chc nng GPIO, thernet...).
Cc vi x l ny cng c th c lp trnh li (re-configurable computing) ngay
trong khi ang chy.
FPGA c ng dng in hnh trong cc lnh vc nh: x l tn hiu s, x
l nh, th gic my, nhn dng ging ni, m ha, m phng (emulation)...FPGA c
bit mnh trong cc lnh vc hoc ng dng m kin trc ca n yu cu mt lng
rt ln x l song song, c bit l m ha v gii m. FPGA cng c s dng
trong nhng ng dng cn thc thi cc thut ton nh FFT, nhn chp (convolution),
thay th cho vi x l.
Hin nay cng ngh FPGA ang c sn xut v h tr phn mm bi cc
hng nh: Xilinx, Altera, Actel, Atmel... Trong Xilinx v Altera l 2 hng hng
u. Xilinx cung cp phn mm min ph trn nn Windows, Linux, trong khi Altera
cung cp nhng cng c min ph trn nn Windows, Linux v Solaris.
1.2.1 KIN TRC FPGA
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Hnh 1.1: kin trc FPGA
Mi nh sn xut FPGA c ring cu trc FPGA, nhng nhn chung cu trc
c th hin ging nh trong hnh bn trn. Cu trc FPGA bao gm c
configuration logic blocks (CLBs), configurable I/O blocks (IOB), v programmable
interconnect. V tt nhin, chng c mch clock truyn tn hiu clock ti cc logic
block, v thm vo c cc logic resources nh ALUs, memory v c th c c
decoders. Cc phn t lp trnh c ca FPGA c 2 dng c bn l cc RAM tnh
(Static RAM) v anti - fuses.
Configurable I/O Blocks:
Configurable Logic Blocks (CLBs) bao gm cc Look-Up Tables (LUTs) rt
linh ng c chc nng thc thi cc logic v cc phn t nh dng nh l cc flip-flop
hoc cc cht (latch). CLB thc hin phn ln cc chc nng logic nh l lu tr d
liu,..
Configurable I/O Blocks:
Input/Output Blocks (IOBs) iu khin dng d liu gia cc chn vo ra I/O
v cc logic bn trong ca FPGA. N bao gm c cc b m vo v ra vi 3 trng
thi v iu khin ng ra dng open collector. Phn ln l c tr ko ln ng ra v
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thnh thong li c tr ko xung.IOBs h tr lung d liu 2 chiu (bidirectional data
flow) v hot ng logic 3 trng thi (3 state). H tr phn ln cc chun tn hiu, bao
gm mt vi chun tc cao, nh Double Data-Rate (DDR).
Programmable Interconnect:
Interconnect FPGA khc xa so vi CPLD, tuy nhin li ging vi ca gate array
ASIC. C mt line di c dng ni cc CLBs quan trng m chng li cch xa
nhau m khng gy ra qu nhiu tr. Chng c th c dng nh l cc bus trong
chip. C cc line ngn c dng lin kt cc CLBs ring r nhng t gn nhau.
V cng thng c vi ma trn chuyn i (switch matrices), ging nh trong CPLD,
ni gia cc line di v ngn li vi nhau theo mt s cch c bit. Cc chuyn i
lp trnh c (Programmable switches) bn trong chip cho php kt ni gia CLBs
ti cc interconnect line v gia interconnect line vi cc line khc v vi switch
matrix. Cc b m 3 trng thi c dng kt ni phn ln cc CLBs vi cc line
di (long line), to nn cc bus. Cc long line c bit, gi l cc line clock ton cc
(global clock lines), c thit k c bit cho tr khng thp v nh m thi gian
lan truyn nhanh hn. Chng c kt ni vi cc b m clock v vi mi phn t
c clock trong mi CLB. l cch m clock c th phn phi bn trong FPGA.
Mch ng h (Clock Circuitry):
Cc khi vo ra vi b m clock high drive gi l cc clock driver, nm ri
rc xung quanh chip. Cc b m ny c ni vi cc chn clock vo v li cc tn
hiu clock vo cc ng clock ton cc (global clock line) nh m t bn trn. Cc
ng clock c thit k sao cho thi gian thi gian lch nh nht v thi gian lan
truyn nhanh. Thit k ng b l yu cu bt buc vi FPGA, t khi lch tuyt
i v tr khng c bo m. Ch khi dng cc tn hiu clock t cc b m clock
th thi gian tr tng i v thi gian lch mi c m bo.
2. CHP M HA TN HIU VIDEO ADV7181B
2.1 CHC NNG V DNG D LIU NG RA
Ngun nh cn x l l tn hiu analog video do DVD plalyer xut ra. Kt ni
ng ra TV-Out composite ca DVD Player vi cng TV-In trn Kit DE2 th b
ADV7181B s s ha tn hiu ny sang chun ITU - RTBT 656 l chui cc frame
nh. Mi im trong frame nh thu v c biu din di dng I(x,y) trong x,y l
ta ca pixel trn frame v I l mc xm tng ng ca pixel . Nh vy 1 frame
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nh thu c s c biu din di dng mt ma trn 2 chiu 720 x 525 vi 720 l
s pixel trn 1 hng, 525 l s hng trong 1 frame.
Chun Video ITU RBT601:
Chun ITU RBT 610/656 nh ngha mt thit k cho vic m ha mt
khung bao gm 525 (hoc 625) line tn hiu video tng t thnh dng s, truyn tn
hiu vi xung clock 27MHz. Mt single horizontal line c cu trc:
EAV BLANKING SAV Active Video Data

EAV, BLANKING v SAV u l cc trng (field) phn bit ng b d
liu c truyn.
EAV v SAV u l cc trng 4 byte:
EAV: cho bit im kt thc ca Active Video Data trong line hin hnh
cng nh l im bt u ca line tip theo.
SAV: bo hiu im bt u ca Active Video Data trong line hin hnh.
FFh 00h 00h XY

Byte th t XY cha thng tin v trng c truyn, tnh trng ca khong
trng (field blanking) theo chiu dc (Vertical) hoc ca dng trng (line blanking)
theo chiu ngang (horizontal):
MSB LSB
1 F V H P3 P2 P1 P0

Bit Symbol Chc nng
7 1 Lun mc 1
6 F Field Bit: 0 => Field1; 1 => Field2
5 V
Vertical Blanking Status Bit:
- Ln mc cao khi vertical field blanking interval.
- Xung mc thp cc trng hp khc.

4 H
Horizontal Blanking Status bit:
- Nu l trng SAV th mc 0.
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- Nu l trng EAV th mc 1.
3 P3 Protection bit 3
2 P2 Protection bit 2
1 P1 Protection bit 1
0 P0 Protection bit 0
Cc Protecction bit th dng kim tra v sa li ph thuc vo cc bt
F,V,H. nhng khi nhn Video Stream ta c th b qua cc bit ny nn ta khng xt
n.
ngha ca cc bit F v V l m bo s ng b cc horizontal line trong
mt frame theo chiu dc:
TABLE 1
Field interval definitions

625 525
V-digital field blanking
Field 1 Start
(V=1)
Finish
(V=0)

Field 2 Start
(V=1)
Finish
(V=0)
Line 624 Line 1
Line 23 Line 20
Line 311 Line 264
Line 336 Line 283
V-digital field identification
Field 1 F=0
Field 2 F=1
Line 1 Line 4
Line 313 Line 266

Cch t gi tr cc bit F,V theo trng (Field 1 hoc 2) v tnh hiu dng
(Active or Blanking) s c hiu r hn qua bng m t mt frame gm 525
horizontal line sau :
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Field 1 (F=0) : 262 line t line 4 n line 265; Field 2(F=1) : 263 line t line
266 n line 3
Active or Blanking : cc Active video data v cc Vertical Blanking Interval
c sp xp xen k nhau :
Active portion (V=0) Odd Field : 244 line t 20->263; Even Field: 243 line t
283->525;
Vertical Blanking Interval (V=1): 38 line gm 19 line t 1->19 v 19 line t
266->282;

Hnh 2.1: Frame nh theo chun ITU656
Mt horizontal line tn hiu s gm cc thnh phn sau:
Blanking: trong sut thi gian truyn tn hiu Video, gia cc Active video
signal Segments s l cc horizontal blanking interval. Gi tr ca cc byte trong
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trng ny s phi ph hp vi cc cp (level) ca cc tn hiu Cb, Cr v Y tng
ng theo quy tc sau: Cb = 80h; Y = 10h; Cr = 80h ta c chui byte : 80h, 10h,
80h,80h,10h.
Ty vo s line tn hiu m chui ny s bao gm 268 byte (khung 525 line)
hoc l 280 byte (khung 625 line).
Active Video Data: C tt c 1440 byte cha ng cc thng tin v nh: 720
gi tr Y (luminace-brightness); 360 gi tr Cr (red chrominace); 360 gi tr Cb (blue
chromiance) c sp xp theo tng nhm c mt Cb v Cr th c 2 gi tr Y:
CbYnCrYn+1 to thnh chui:
Cb
0

0
Cr
0

1
Cb
1

2
Cr
1

3
Cb
359

718
Cr
359

719

Cc trng SAV v EAV: mi trng di 4 byte
Vy trong h thng 525 line th mt Horizontal line s bao gm 1716 byte.
2.2 GIAO THC CI T I2C
ADV7181B h tr mt giao din kt ni 2 dy tun t a-wire serial interface
I2C. Hai ng vo : d liu tun t SDA, xung clock tun t SCLK mang thng tin
gia ADV7181B vi b iu khin h thng I2C. Mi thit b ti (Slave) s c
nhn ra bi mt a ch duy nht.
Cc chn I2C ca ADV7181B cho php ngi dng ci t, cu hnh b m
ha v c ngc li d liu VBI (vertical blank interval) bt c. ADV7181B c 4
a ch Slave cho tt c thao tc c v ghi ph thuc vo mc logic ca chn ALSB.
ALSB iu khin bit 1 ca a ch Slave (Slave_address[1] ) bi vic thay i chn
ny c th iu khin c c 2 b ADV7181B m khng c s xung t v trng a
ch Slave. Bit thp nht ca a ch Slave( LSB hay l Slave_address[0] ) quyt nh
thao tc ghi hay c: mc 1 c v mc 0 th ghi. y ta ch s dng 1 b
ADV7123, giao thc I2C ch yu dng np d liu cho cc thanh ghi nn chn a
ch Slave cho chip m ha ny l 0x40h t bng gi tr a ch I2C Slave di y:

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iu khin thit b trn Bus th phi c mt giao thc c bit i km. u
tin Master s khi ng truyn d liu bng vic thit lp iu kin bt u (SDA
t 1 xung 0 trong khi SCLK vn mc cao) y ta gi l START, n m ch rng
theo sau l mt lung a ch hay d liu. Cc ngoi vi p tr li START v dch
chuyn 8 bit tip theo (7 bit a ch v 1 bit c/ghi), cc bit ny c truyn t bit
cao (MSB) n thp (LSB). Cc ngoi vi khi nhn ra cc a ch c truyn th
p ng bng cch gi SDA = 0 trong ton b chu k th 9 ca xung clock gi l
ACK. Cc thit b khc th s rt khi bus ti im ny v bo ton trng thi IDE
(khi c SDA v SCLK u mc cao cho cc thit b theo di 2 line ny, ch
START v a ch c truyn ng). Bit c/ghi ch ra hng ca d liu, LSB = 0/1
th master ghi/c thng tin vo/t ngoi vi.
ADV7181B hot ng nh thit b Slave tiu chun trn Bus, cha 196 a ch
con (Subaddress l lch ca a ch cn thao tc vi a ch thit b) cho php
truy cp cc thanh ghi ni. iu gii thch rng byte u tin l a ch ca thit b
v byte th 2 l a ch con u tin. Cc a ch con ny t ng tng dn cho php
truy c/ghi a ch con bt u. S truyn d liu th lun b ngt bi iu kin
dng (STOP). Ngi dng c th truy cp ti bt c duy nht 1 thanh ghi a ch
con trn c s 1-1 khi khng c s cp nht ton b cc thanh ghi. ti ny ta
khng s dng ch cp nht ton b m ch truy cp vo cc thanh ghi cn thit
cc a ch con trn c s 1-1.
START v STOP c th xut hin bt k u trong s truyn d liu, nu cc
iu kin ny c khng nh ngoi chui lin tc vi cc thao tc c v ghi
thng thng, th n tc ng lm bus tr v trng thi IDE. Nu a ch ngi dng
pht ra khng ph hp (invalid) th ADV7181B s khng gi xc nhn ACK v tr v
trng thi IDE.
Nu cc a ch con t ng tng dn ri vt qu gii hn a ch con cao
nht:
Nu ang c th nhng gi tr cha ng trong thanh ghi c a ch con cao
nht s c tip tc c cho n khi Master pht 1 NACK (SDK khng b a xung
mc thp trong ton b chu ky th 9) ch rng vic c kt thc.
Nu ang ghi th nhng gi tr ca byte khng ph hp s khng c load.
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Hnh 2.1: Truyn d liu trn bus v chui c v ghi tun t vi giao thc I2C
Truy cp cc thanh ghi : MPU c th vit hoc c cc thanh ghi ngoi tr
cc a ch con, chng ch c ghi, chng ch ra cc thanh ghi m tc v c hay ghi
tip theo truy cp n. Mi s giao tip vi phn ny thng qua Bus START vi mt
s truy cp cc thanh ghi ny. Cc thao tc ghi hay c s c thc hin t a ch
ch, ri tng ln a ch tip theo n khi mt lnh STOP trn Bus c thc thi.
Lp trnh cc thanh ghi: cu hnh cho tng thanh ghi, thanh ghi giao tip
gm 8 bit ch c ghi. Sau khi thanh ghi ny c truy cp trn Bus v mt thao tc
c/ghi c la chn, cc a ch con c ci t ch ra cc thanh ghi m tc v s
t ti.
Chn la thanh ghi: (SR n SR0) nhng bit ny c ci t ch ra a
ch bt u c yu cu.
Chui I2C : c s dng khi cn cc thng s vt qu 8 bit, v vy n
phi c phn phi trn t nht 2 thanh ghi ca I2C:
Khi mt thng s c thay i bi 2 ln ghi th n c th gi gi tr khng
ph hp (invalid) trong khong thi gian ln u v ln cui I2C c hon thnh, c
ngha l cc bit u ca n c th mang gi tr mi trong khi cc bit cn li vn gi
gi tri c.
trnh sai st ny chui I2C s gi cc bit gi tr cp nht ca cc thng s
trong b nh cc b, v cc bit ca chui I2C c cp nht vi nhau mt ln khi tc
v ghi vo thanh ghi cui cng hon thnh.
Tc v hp l trn chui I2C s da trn c s sau: cc thanh ghi dnh cho
chui I2C s c ghi theo th t tng dn a ch cc thanh ghi. V d: HSB[10:0]
th ghi ln 0x34 trc ri ngay lp tc ghi thm vo 0x35.
3. SDRAM IS42S16400
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SDRAM IS42S16400 c tt c 67180864 bit SDRAM c t chc thnh 4
di (BANK) nh, mi di c dung lng 1024576 t (Words) 16 bit vi tc truyn
d liu c th ln n 133MHz.
3.1 NGUYN TC HOT NG
Thc hin vic truyn d liu qua cc chn a ch v d liu di s chi phi
ca cc chn diu khin:
CKE cho php xung clock. Khi tn hiu ny mc thp, chip x l ging
nh l xung clock hon ton b dng li.
/CS la chn chip: mc cao, th b qua tt c cc u vo khc (ngoi
tr CKE), v hot ng nh mt lnh NOP nhn c.
DQM mt n d liu: Khi cao, nhng tn hiu ny khng ch d liu
vo/ra. Khi i km vi s vit, d liu khng tht s vit vo. Khi d liu c gi
mc trong hai chu k trc mt chu k c, vic c khng c a ra t chip. Trn
mt chip nh x16 hay DIMM, vi 1 t 8 bit th c mt hng DQM.
/RAS Row Address Strobe l bit iu khin cho qua a ch hng.
/CAS Column Address Strobe bit iu khin cho qua a ch ct.
/WE Write enable cho php ghi.
Cc tn hiu /RAS, /CAS, /WE dng la chn 1 trong 8 lnh. Ni chung th
dng phn bit cc lnh c, ghi.
SDRAM bn trong c chia thnh trong 2 hay 4 di (Bank) d liu ni c
lp bn trong. Mt hoc hai a ch vo ca di (Bank) BA0 v BA1 s la chn Bank
m lnh tc ng n.
Phn ln cc lnh u s dng a ch c a vo ng vo a ch. Nhng
c mt s lnh li khng s dng chng, hay ch biu din mt a ch ct, v vy ta
s dng A[10] la chn nhng phng n.
Bng 1: Cc ch truy cp SDRAM
/CS /RAS /CAS /WE Ban A10 An Lnh
H X X X X X X
c ch cc lnh
khc
L H H H X X X
Khng lm g
c(NOP)
L H H L X X X
Dng (hy) truyn
khi: dng lnh
c khi hay ghi
khi khi ang thc
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hin.
L H L H Bank L Column
Read: c khi d
liu t hng kch
hot hin hnh.
L H L H Bank H Column
c vi Precharge
( np li ) t ng:
khi thc hin xong
th Precharge ( tc
l ng hng li).
L H L L Bank L Column
Write: ghi khi d
liu t hng kch
hot hin hnh.
L H L L Bank H Column
Ghi vi s np li
t ng: khi thc
hin xong th np
li (Precharge) tc
l ng hng li.
L L H H Bank Row
Active (kch hot):
m mt hng vi
lnh Read v
Write.
L L H L Bank L X
Precharge (np
li): Ngng hot
ng hng hin
hnh ca bank
(di) c chn.
L L H L X H X
Precharge all (np
li ton b): Ngng
hot ng hng
hin hnh ca tt
c cc bank (di).
L L L H X X X
Auto refresh (t
ng lm ti):
lm ti tng hng
ca tng bank, s
dng b m ni.
Tt c cc di phi
c np li.
L L L L 0 0 Mode
Lode mode register
(ch np cc
thanh ghi): A[9:0]
c np cu
hnh chip DRAM.
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Trong quan
trng nht l ngm
nh CAS (2 hoc
3 chu k) v chiu
di khi (1, 2, 4,
hoc 8 chu k).

S tng tc cc tn hiu iu khin SDRAM:
Khng c lnh no lun c cho php:
Lnh ch np cc thanh ghi (load mode register command) yu cu tt c
cc di (Bank) trng thi IDE, v phi tr hon v sau cho s thay i tc ng.
Lnh t ng lm ti (auto refresh command) th yu cu tt c cc di
(Bank) trng thi IDE, v mt 1 khong thi gian lm ti a Chip v trng thi
IDE: thng l trcd + trp.
Ch c nhng lnh khc th cho php trn mt Bank IDE l cc lnh kch hot.
Cn phi mt trcd trc khi hng c m hon ton v chp nhn mt lnh c hay
ghi.
Khi mt di (Bank) c m th c 4 lnh c cho php: c, ghi, kt thc
truyn khi (Burst terminal), np li (precharge). Lnh c, ghi bt u truyn khi v
c th b ngt bi nhng ngt sau:
Ngt mt c khi d liu:
Sau mt lnh c th bt c lc no cng c th c mt trong cc lnh: c,
kt thc truyn khi, hoc l np c pht ra. V s ngt c khi ny nu c mt
ngm nh CAS c cu hnh. Nu c 1 lnh c thi im 0, 1 lnh c khc
chu k 2, ngm nh CAS chu k 3 th lnh c u tin s truyn khi d liu ra
ngoi chu k 3 v 4, v kt qu ca lnh c th 2 s bt u xut hin chu k 5.
Nu lnh chu k 2 l kt thc truyn khi hoc l np li Bank kch hot th
khng c d liu ra chu k 5.
Mc d vic ngt lnh c c th xut hin mt Bank bt k , nhng lnh
np li ch ngt vic c khi nu n tc ng trn cng mt Bank hoc tt c cc
Bank, nu lnh ny hng n mt Bank khc th vic c khi vn tip tc.
S ngt c to ra bi mt lnh ghi th cng c th nhng s kh khn hn.
Thc hin iu ny nh vo mt tn hiu DQM khng ch ng ra ca SDRAM, v
vy trong khong thi gian ny, chp iu khin b nh c th li d liu i qua chn
DQ ghi vo SDRAM. V tc ng ca DQM trn lnh c th b tr hon 2 chu k
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trong khi i vi lnh c th ngay lp tc, nn DQM phi ln mc cao (raised) sm
hn 2 chu k trc khi c lnh ghi.
thc hin iu ny trong 2 chu k th yu cu nh v thi im SDRAM
tt ng ra ti 1 cnh ln xung Clock v thi im d liu c cung cp (cho lnh ghi
) nh ng vo ca SDRAM cnh tip theo ca Clock.
Mt ngt ghi khi d liu:
Bt k lnh c, ghi, hay kt thc truyn ti mt Bank bt k s kt thc
(dng) vic ghi khi ngay lp tc, d liu trn chn DQ khi lnh th 2 c pht th
ch do lnh ny s dng.
Ngt ghi khi vi lnh precharge (n cung mt Bank) th kh phc tp. l
thi gian vit nh nht, twr phi c lt qua gia tc v ghi sau cng ti 1 Bank
(chu k khng b che (unmasked) cui cng ca ghi khi) vi lnh precharge k tip,
v vy mt ghi khi s b dng (hy) bi lnh tch np (pre-charge) nu c chu k
ko di c che i (dng DQM) to twr cn thit. Mt lnh ghi vi s tch np t
ng cha ng mt tr hon t ng.
Ngt mt lnh tch np t ng:
Vic x l s gin on ca thao tc c, ghi vi ch tch np t ng l
mt c tnh la chn ca SDRAM, v c h tr rt nhiu. Nu c s dng, s
tch np hay thi gian ch twr theo sau bi s tch np (sau khi c) bt u cng mt
chu k nh mt lnh ngt.
Sp xp truyn khi SDRAM:
Mt b vi x l hin i c b m ni chung s truy nhp b nh trong
nhng n v ca line b m. V d truyn 64 byte, line b m yu cu 8 s truy
cp lin tip ti mt DIMM (dual in-line memory module: module nh c hai hng
chn) 64bit, m ton b c th c kch khi bi mt lnh n c hay ghi ty vo
s cu hnh cc chp SDRAM.
S truy cp line m in hnh c kch khi bi mt s c t mt a ch
c bit, v SDRAM cho php " t c tnh cht quyt nh " ca line m s c
truyn u tin. ("t " y c ngha l chiu rng (ca) chp SDRAM hay DIMM,
64 bt vi mt DIMM tiu biu).
Chp SDRAM h tr hai giao thc sp xp cc t cn li trong line m:
- Ch truyn khi an xen: lm cho cc tnh ton ca con ngi thm
phc tp nhng li d dng tng hp phn cng hn v c u tin vi cc b vi x
l Intel. Ta khng s dng kiu truyn ny.
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Trang 16


- Ch truyn khi tun t: nhng t tr hn c truy cp trong vic tng
dn a ch, khi kt thc th quay tr li im bt u khi. Chng hn, vi mt tuyn
khi c chiu di l 4, v a ch ct c yu cu l 5, nhng t s truy cp theo th
t 5-6-7-4. Nu chiu di truyn khi l 8, th t truy cp l 5-6-7-0-1-2-3-4. iu
ny c thc hin bi vic thm mt b m a ch ct, v b qua s nh khi i ht
khi.
Ta c th la chn chiu di khi v kiu truy cp khi bng cch s dng ch
thanh ghi c m t phn tip theo.
Ch thanh ghi ca SDRAM:
Tc d liu n SDRAM c mt ch thanh ghi 10 bt n lp trnh
c. Sau chun SDRAM tc d liu kp SDRAM b sung thm ch thanh
ghi, nh a ch s dng nhng chn a ch Bank. Vi SDR SDRAM, chn a ch
Bank v a ch hng A[10] v cao hn th c l i, nhng phi l 0 trong khi ch
ghi vo thanh ghi. Trong chu k ca ch thanh ghi th cc gi tr np vo M[9:0]
chnh l cc bit a ch.
- M[9] ch ghi tng khi, mc 0 th ghi s dng ch v chiu di
truyn khi ch c, mc 1 th tt c cc ghi khng phi l truyn khi (nh v
n).
- M[8:7] ch vn hnh, mun ch lu tr th t gi tr 00.
- M[6:4] ngm nh CAS ch vi cc gi tr hp l l 010 (CL2) v 011
(CL3). Ch ra s chu k gia lnh c v d liu c gi ra t Chip. Chip s hon
thnh mt gii hn c bn trong nan-giy da trn gi tr ny; khi khi to, b iu
khin b nh phi s dng kin thc ca n v tn s xung Clock v dch gii hn kia
thnh nhng chu trnh.
- M[3] kiu truy cp cc t trong khi : 0 th truy cp tun t, 1 th truy cp
an xen.
- M[2:0]: chiu di khi: gi tr 000, 001, 010 v 011 ch ra kch thc khi
tng ng l 1, 2, 4 hay 8 t. Mi c ( v vit, nu m[9] l 0) s thc hin nhiu s
truy cp, tr phi c gin on bi mt s dng (hy) truyn khi hay cc lnh khc.
Gi tr 111 c t khi vi y hng (full-row Burst hoc cn gi l full page
Burst). S truyn khi vi y hng ch c cho php vi kiu tun t. i vi
SDRAM IS42S16400 th chiu di ca 1 khi ch full page Burst l 256 t. S
truyn khi th tip tc cho n khi c ngt.
Lm ti t ng:
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Dng lm ti li Chip ram nh vo s m v ng ( kch hot v tch np
) tng hng trong tng Bank. Tuy nhin, n gin ha chp iu khin b nh,
Chip SDRAM h tr lnh t ng lm ti, tc l ng thi thc hin thao tc ny ti
mt hng trong tng Bank. SDRAM cng duy tr mt b m ni c lp li trn
ton b cc hng c th. Chip iu khin b nh th n gin phi pht ra s lng
cc lnh lm ti t ng (1 lnh i vi 1 hng ) vi mi khong lm ti (mt gi
tr chung l tref = 64 ms). Tt c cc Bank phi trng thi IDE khi lnh c pht.
Ch Lover Power:
Nh cp, ng vo cho php xung Clock (CKE) c th c dng
dng xung Clock ti SDRAM. Gi tr ng vo CKE c xt ti tng cnh ln ca
xung Clock, v nu mc thp, th mi cnh ln ca xung Clock tip theo s b b
qua mi mc ch khc so vi vic kim tra CKE.
Nu CKE xung thp trong khi SDRAM ang thc hin tc v, th n n
gin ch l ng bng li ti ch cho n khi CKE ln mc cao.
Nu SDRAM trng thi IDE ( tt c cc Bank c tch np, khng c lnh
no ang hot ng) khi CKE xung thp, SDRAM t ng chn ch power-down
(tit kim nng lng), gi nng lng cc tiu cho ti khi c cnh ln ca CKE.
Khong ny th khng c di hn gi tr ti a khong lm ti tref, nu khng
nhng g b nh cha ng s b mt. y l phng php dng ton b xung
Clock trong khong thi gian ny tit kim nng lng.
Cui cng, nu CKE mc thp vo lc mt lnh lm ti t ng c gi
n SDRAM, SDRAM chn ch t lm ti ( seft-refresh mode). Tng t Power
Down, nhng SDRAM dng mt timer ni pht ra cc chu k lm ti ni khi cn
thit. Trong thi gian ny th dng xung Clock. Ch t lm ti tiu th t nng
lng hn so vi ch Power Down, nhng vn cho php b iu khin b nh
disable ton b.
4. C CH HIN TH NH LN MONITOR
4.1 NGUYN TC CHUNG.
hin th hnh nh ra mn hnh c tch hp th cn phi c mt b VGA
Grenerator vi cc tn hiu v c ch lm vic nh sau:
4.1.1 VGA COLOR SIGNALS.
C 3 tn hiu color l: red, green v blue gi tn hiu mu sc (color
information) n mn hnh VGA. Mi mt tn hiu iu khin mt sng bn in t
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(electron gun) phng cc ht electron v ln mt mu c bn ti mt im trn mn
hnh. Di ca tn hiu nm t t 0V (tng ng vi mu ti hon ton) v 0.7V (sng
hon ton) iu khin cng ca mi thnh phn mu v 3 thnh phn mu kt
hp vi nhau to ln mu ca im nh (dot) hay phn t nh (pixel) trn mn hnh.

Hnh 4.1: VGA Connection
Ty vo rng A bt ca tn hiu mu ng vo tn m mi mu analog ng
ra l mt trong 2
A
mc vi b chuyn i digital to analog A bit, 3 tn hiu analog kt
hp vi nhau to nn phn t nh (pixel) vi 2
A
x 2
A
x 2
A
= 2
3A
mu khc nhau.
4.1.2 VGA SIGNAL TIMING.
Mi mt nh (hay frame) trn mn hnh hin th l kt hp ca h dng, mi
dng c w pixel. Kch thc ca mi frame c biu din w x h di dng tiu biu
gm 640 x 480m 800 x 600, 1024 x 768 v 1280 x 1024.

Hnh 4.2: CRT Display Timing Example
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v mt frame, c nhng mch in c trch nhim di chuyn dng electron
t tri sang phi v t trn xung di dc theo mn hnh gi l deflection circuit.
Nhng mch ny yu cu phi c 2 tn hiu ng b khi ng v dng dng
electron ti ng thi im cho mt dng cc im nh c v dc theo mn hnh
v mi dng c in theo c ch t trn xung di to ln mt nh.
VGA Display Timing vi ch 640 x 480:
Symbol Parameter Vertical Sync Horizontal Sync
Time Clocks Lines Time Clocks
Ts Sync pulse time 16.7 ms 416,800 521 32s 800
TDISP Display time 15.36 ms 384,000 480 25.6s 640
TPW Pulse width 64s 1,600 2 3.84s 96
TFP Front porch 320s 8,000 10 640ns 16
TBP Back porch 928s 23,200 29 1.92s 48

4.1.3 VGA GENERATOR.
H thng bn ngoi ghi gi tr pixel vo trong thanh ghi pixel (data register).
Ni dung ca thanh ghi ny c dch sau mi xung cloch thay th pixel hin ti.
Cc bit ny c gi n b DAC chuyn sang dng tn hiu mu analog. Ri
kim tra xem gi tr trn chn Blank xut ra cng VGA.
Hai mch to xung ng b (pulse generation circuit) c dng to cc
xung ng b dc (VSYNC) v ngang (HSYNC). B hirizontal sync generator c u
ra l tn hiu gate mt chu k trng khp vi sng ln ca xugn ng b ngang
(horizontal sync pulse), tn hiu gate ny ni vi tn hiu clock enable ca b
vertical sync generator v th nn clock enable ch cp nht b n thi gian sau mi
dng pixel (line of pixels). Tn hiu gate ca vertical sync generator c dng nh
tn hiu bo kt thc mt frame, ng thi n cng reset v xa ton b ni dung ca
pixel buffer nn b VGA generator lun khi ng t trng thi xa sch hon ton
vi mi frame.
B to tn hiu ng b cng to ra cc tn hiu horizontal v vertical
blanking. Khi dng php ton OR logic ta c tn hiu blanking ton cc.
4.2 B VGA DAC ADV7123
Kit DE2 tch hp mt b VGA DAC v ADV7123 vi cu trc
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H tr tn hiu mu 10 bit ng vo, vi b DAC 10 bit s cho ra mc
mu Analog ng ra, tuy nhin trong thit k d liu mu ta cung cp cho ADV7181
ch l 8 bit nn tn hiu mu Analog ng ra c mc 3, tn hiu analog kt hp li vi
nhau to nn phn t nh (16 triu) mu, 1028224.
Cc tn hiu ng b l SYNC v BLANK: gi tr ca SYNC th khng
nh hng n qu trnh hin th, BLANK vi gi tr 0 th cht cc d liu mu ng
vo.

Hnh 4.3: S cu trc ADV7123
Cc chn ca ng ra c ni tng ng vi cc chn ca cng VGA
trn KIT DE2, v vy s dng c b VGA DAC ny ta phi to ra mt khi va
cung cp cc tn hiu BLANK, Red, Green, Blue cho ADV7123 va phi to ra 2 tn
hiu ng b VSYN v HSTNC ni trc tip vo cng VGA mt cch ng thi.
5. S LC H THNG
5.1 S THIT K

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Hnh 5.1: S h thng
5.2 NGUYN L HOT NG
Khi I2C_Video_Config: vi giao thc giao tip I2C s t gi tr cho cc
thanh ghi ca b m ha ADV7181 cu hnh hot ng cho chip m ha ny.
Khi Timer tr hon ban u: Sau chui khi ng, ADV7181 ri vo thi k
khng n nh, khi s pht hin thi k khng n nh ny ri tnh ton thi im bt
u lm vic ca cc khi khc.
Khi Disize_Horizon: Ly ra chui lin tc cc pixel trong dng d liu do
ADV7181B xut ra ng thi nh li kch thc frame nh t dng 720 x 480 sang
chun VGA 640 x 480.
SDRAM BUFFER: Nhn d liu v tnh hiu iu khin ghi t khi
Disize_Horizon ghi gi tr cc pixel vo SDRAM, ng thi cng nhn tn hiu t
VGA controller iu khin vic xut d liu, a ch ph hp (xut xen k cc line
thuc Odd field v Even field).
Khi x l nh YUV: x l d liu nh nhn c t SDRAM BUFFER ri
xut ra d liu nh cho khi Convert YUV to RGB.
Khi ConvertYUVtoRGB: ADV718B xut ra nh video dng YUV, c th
hin th lnh VGA th trc tin chuyn i thnh dng RGB.
Khi VGA_Controller: Nhn d liu nh RGB t khi ConvertYUVtoRGB
xut d liu v tn hiu ng b cho video DAC7123, ng thi cng pht ra cc tn
hiu iu khin SDRAM_BUFFER xut d liu t SDRAM.
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6. KHI I2C_VIDEO_CONFIG
6.1 S KHI

Hnh 6.1: S khi I2C_Video_Config
Tn

M t
ICLK

Xung Clock 50MHz t kit DE2
RESET

Tn hiu Reset h thng
I2C_SCLK
Ng ra cha xung Clock cung cp cho ADV7181B
I2C_DATA

Port 2 chiu cu hnh cc gi tr thanh ghi ca ADV7181B


Hnh 6.2: Dng sng truyn d liu v cu trc ghi vi giao thc I2C
6.2 M T
Vai tr ca khi ch l ghi gi tr vo cc thanh ghi ca ADV7181B nn c th
chn xung clock lm vic ca khi l 20KHz nh vo b chia tn s 50MHz. a ch
Slaver ca ADV7181B l 40h nn ta s dng cch gn mI2C_DATA l kiu d liu
cn truyn trn Bus v LUT_DATA cha a ch ca thanh ghi v gi tr cn np.
Khi reset, bt u cu hnh li cho ADV7181B bng cch xa gi tr cc b
m v c. Sau np gi tr cho cc thanh ghi ta s dng my trng thi sau:
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always@(posedge mI2C_CTRL_CLK or negedge iRST_N) begin
if (!iRST_N) begin
LUT_INDEX<= 0;
mSetup_ST <= 0;
mI2C_GO <= 0; end
else
begin
if(LUT_INDEX<LUT_SIZE)
//LUT_SIZE l s ln np gi tr cho cc thanh ghi cn thit
//LUT_INDEX l bin m nh x n a ch ca cc thanh ghi v gi tr cn np.
begin
case(mSetup_ST)
0: begin
//nhp chui d liu cn truyn t gi tr cho cc thanh ghi
mI2C_DATA <= {8h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
If(mI2C_END)
//mI2C_END l c bo khi truyn ht chui d liu
begin
//c xc nhn ACK l np xong gi tr cho mt thanh ghi t
//ADV th nhy ti trng thi 2
if(!mI2C_ACK)
mSetup_ST <= 2;
//khng c xc nhn th nhy v trng thi 0
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
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//tng LUT_INDEX ln 1 nhy n thay ghi mi ri quay v trng thi 0
LUT_INDEX <= LUT_INDEX + 1;
mSetup_ST <= 0;
end
endcase
end
end
end
Ta ch cn t gi tr cho mt thanh ghi cn thit nn khng thc hin vic
tng dn a ch thanh ghi m s nh x t LUX_INDEX n LUX_DATA nh vo
lnh case, chng hn nh khi LUX_INDEX=27 np gi tr 850 vo thanh ghi a
ch 8h00 ta c cu trc:
case(LUX_INDEX):
27: LUT_DATA <= 16h0050;
AVD7181B c th pht hin chun video NTSC th ta s np cc gi tr
cho cc thanh ghi theo bng gi tr ci t phn m t ADV7181B. Tuy nhin khi
truyn chui ny trn bus ta cn phi thm cc bit ng b: 1 bit cho trng thi IDE, 2
bit thit lp c START, 3 bit ch ACK cho ADV xc nhn, 3 bit thit lp c
STOP v bo kt thc chui, v vy thc s chui di 33 bit:
case(SD_COUNTER)
6d0 : begin ACK1=0; ACK2=0; ACK3=0;
END=0;SDO=1;SCLK=1;end
//thit lp c START
6d1 : begin SD=I2C_DATA;SDO=0;end
6d2 : SCLK=0;
//a ch SLAVER ca ADV7181B
6d3 : SDO=SD[23];
6d4 : SDO=SD[22];
6d5 : SDO=SD[21];
6d6 : SDO=SD[20];
6d7 : SDO=SD[19];
6d8 : SDO=SD[18];
6d9 : SDO=SD[17];
6d10 : SDO=SD[16];
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//th ni ng truyn nhp ACK t ADV7181B qua port 2 chiu
I2C_DATA
6d20 : SDO=1bz;
//gi tr cn ghi vo thanh ghi
6d21 : begin SDO=SD[7]; ACK2=I2C_SDAT;end
6d22 : SDO=SD[6];
6d23 : SDO=SD[5];
6d24 : SDO=SD[4];
6d25 : SDO=SD[3];
6d26 : SDO=SD[2];
6d27 : SDO=SD[1];
6d28 : SDO=SD[0];
//th ni ng truyn nhp ACK t ADV7181B qua port 2 chiu I2C_DATA
6d29 : SDO=1bz;
//thit lp c STOP v bo kt thc chui
6d30 : begin SDO=1b0; SCLK=1b0; ACK3=I2C_SDAT;end
6d31 : SCLK=1b1;
6d32 : begin SDO=1b1;END=1;end
endcase
Trong SD_COUTER thc hin m t 0 n 63, nh vy vic np cho mt
thanh ghi ch thc hin trong 33 chu k u cn 30 chu k sau th bus trng thi
IDE (SCLK=1 va SDO=1) ch chu k tip theo. ng thi m bo c yu
cu v dng sng trn chn I2C_SCLK v xc nhn (ACK) np xong thanh ghi, ta
thc hin:
wire I2C_SCLK = SCLK | (((SD_COUTER>=4) &
(SD_COUTER<=30))? ~CLOCK : 0 );
wire ACK=ACK1 | ACK2 | ACK3;
// khi xt xc nhn np xong thanh ghi ta s dng gi tr b ca //ACK
(tch cc mc thp), ch xc nhn khi c 3 xc nhn ACK1, //ACK2, ACK3
V dng sng thu c trn chn I2C_SCLK nh sau (END t 0 ln 1 ch ra
rng np xong gi tr cho mt thanh ghi):
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Hnh 6.4: dng sng m phng trn chn I2C_SCLK
7. KHI TIMER TR HON BAN U
7.1 S KHI


Hnh 7.1: S ca khi timer tr hon ban u
Tn M t
ICLK Xung clock 50Mhz t kit DE2
VS Tn hiu VS (Vertical Sync) t ADV7181B
HS Tn hiu HS (Horizontal Sync) t ADV7181B
TD_Stable Bo hiu ADV7181b hot ng n nh
RST0, RST1, RST3 Ng ra cho php cc khi khc bt u lm vic

7.2 M T
Vi cu hnh ci t phn trc, khi hot ng n nh, dng sng do
ADV7181B pht ra nh sau:


Hnh 7.2: M t dng sng ADV7181B
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V vy pht hin xem chip m ha ny hot ng n nh hay cha khi
TD_DETEC tin hnh kim tra iu kin: VS mc cao trong 9 chu k lin tip ca
HS ri chuyn xung mc thp, nu tha mn th a TD_Stable ln mc cao. Khi tn
hiu TD_Stable ln mc cao, khi RESET_DELAY bt u m ln theo xung nhp
ca ICLK (50MHz) tnh thi im xut ra mc 1 trn cc chn RST0, RST1,
RST2. Cc tn hiu ny dng khi ng cc khi khc theo trnh t nh sau:
a) Ban u xa tt c d liu trong cc khi.
b) Tnh t thi im TD_Stable ln 1 (n v l chu k clock 27MHz)
- Sau 1132461.5: tch cc RST0 kch hot khi SDRAM BUFFER.
- Sau 1698692.5: tch cc RST1 kch hot khi Desize Horizon.
- Sau 2264923.5: tch cc RST2 kch hot khi x l nh YUV v
VGA controller.
c) Gi nguyn gi tr ng ra cho n khi c tn hiu RESET h thng th lp
li.
im cn ch y l khi Desize Horizon hot ng th s xut
DATA_VALID cho php ghi d liu vo SDRAM BUFFER. Ri phi ch mt
khong thi gian ghi s liu cn thit mi kch hot VGA Controller xut d
liu t SDRAM BUFFER. Nh ta bit mt frame nh do ADV7181B xut ra bao
gm 900900 byte (525 line, mi line c 1716 byte) hay truyn ht mt frame s
mt 900900 chu k. Do xung clock trn chn LLC truyn cc byte l 27MHz nn
ta kim tra li cc thi im ny nh sau:
- Ly gc thi gian l khi bt u frame u tin.
- TD_Stable ln 1 khi Frame u tin pht c 9 line: 9 x 1716 =
15444 chu k.
- Frame th ba c bt u ti thi im 2 x 900900 = 1801800
- Khi Desize Horizon c kch hot ti thi im 1714136.5
(= 15444 + 1698692.5) tc l trc khi frame th ba bt u. m bo
rng khi s xut ra DATA_VALID = 1 ton b cc Active Pixel ca frame th 3.
- Khi VGA Controller c kch hot ti thi im 2280367.5(=15444
+ 2264923.5) nn oRequest c xut ra ti thi im 2315727.5(= 2280376.5 +
35360). Vi 35360 chu k l khong thi gian t khi khi c reset cho n khi
oRequest ln 1. Vy vic c t SDRAM BUFFER c kch hot khi frame th 3
bt u c mt khong thi gian l 513927.5(= 2315727.5 1801800). iu ny
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m bo cho vic xut ra ng tng frame t SDRAM BUFFER m ta s cp k
hn phn m t SDRAM BUFFER.
8. KHI DISIZE_HORIZON
8.1 S KHI

Hnh 8.1: S khi Disize_Horizon
Tn M t
CLK_27 Xung clock 27MHz t kit DE2
RST_N Reset h thng
TD_DATA[7:0] D liu hnh nh t ADV7181B
ACLR Tn hiu xa bt ng b do khi Timer tr hon cung cp
CLK Xung clock 27MHz t chn TD_CLK ca ADV7181B
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S chia = 9 S chia cung cp cho b chia do ngi thit k nhp vo
TV_X[9:0]
V tr ca Pixel trong hng hin hnh ng thi cng l s
b chia cung cp cho b chia
Thng[9:0] Thng ca php chia TV_X cho 9
S d [9:0] S d ca php chia TV_X cho 9
DATA_VALID ng b cho oYCbCr a vo SDRAM_Controller
oYCbCr[15:0] Chui d liu nh ng ra

DATA_VALID: mc 1 th s cho php Pixel i km c ghi vo SDRAM
thng qua SDRAM_Controller. Do frame m ADV7181B xut ra c dng 720 x 480
a v chun 640 x 480 m hnh nh khng b xn th vi mi 9 pixel lin tip ta
s loi b Pixel u tin: Khng cho php ghi vo SDRAM bng cch a
DATA_VALID xung mc 0 (ly ra 8 Pixel trong 9 Pixel: 640 =
8
9
x 720 ).
ng thi m bo c chui a vo SDRAM_Controller vn c dng
chui CbYnCrYn+1 lin tip th phi hon i gia 2 thnh phn Cb v Cr c sau 2 ln
loi b 1 Pixel.

Hnh 8.2: V tr cc Pixel trong chui
Nh hnh trn X l v tr cc Pixel b loi b (b b qua khi hin th ln mn
hnh), khi chui Pixel ti S1 l Cb4Y8Cb5Y10 v ti E1 l Cr8Y17Cr9Y19 v vy
m bo chui c dng CbYCrY lin tip th phi hon i v tr gia Cb v Cr trong
khong Cb5Y10Cr8Y17.
8.2 M T
TD_DATA l chui Pixel c pht ra theo chun Video ITU656. Ta c th
xem mt frame thc s bt u vi Odd Field khi bit F (bit 6 trong byte cui ca
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trng SAV hay EAV) chuyn t 1 v 0, vy xt iu kin bt u ca mt frame
ta phi i n trng SAV hay EAV ri mi kim tra gi tr ca bit F:
Window <= {Window[15:0],iTD_DATA};
if (Window == 24hFF0000)
//khi pht hin trng SAV (EAV) th gn gi tr bit V cho FVAL v bit F cho
//Field
begin
FVAL <= !iTD_DATA[5];
Field <= iTD_DATA[6];
end
//kim tra iu kin bit F chuyn t 1 v 0 bt u 1 frame nh sau:
Pre_Field <= Field;
if ({ Pre_Field, Field } == 2b10)
Start <= 1b1;
//khi ng b m cont xc nh s byte ca chui Pixel trong 1 hng
if (SAV)
begin
cont <= 18h0;
Active_video <= 1b0;
End
else if (cont < 1440)
cont <= cont+1b1;
//c 2 byte 1 Pixel khi xc nh v tr Pixel trong hng th phi chia cont cho 2
assign oTV_X = cont>>1;
thc hin php chia oTV_X cho 9 ta s dng b chia t th vin ca
quatus:
Phn Menu >> Tools >> MegaWizard Plug_in Manager>>Create to
custom mi t tn l DVI; chn phn Arithmetic >> LPM_DEVIDE. V oTV_X
720 nn chn rng bit ca s b chia (Numberator) l 10, rng bit ca s chia
(denominator) l 4, kiu d liu khng du. V s chia cn nhp l 9 nn ta ghp vo
khi tng th nh sau:
DIV u5 ( .aclr(!DLY0),
.clock(TD_CLK),
.denom(4h9),
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.number(TV_X),
.quotient(Quotient),
.remain(Remain));
Trong quotient, remain l thng v s d, ta nhp cc iu kin oTV_X
c chia ht cho 9 v thng l s l thng qua cc chn iSkip v iSwap_CbCr bng
cch khai bo:
Desize_Horizontal u4 ( .iTD_DATA(TD_DATA),
.oTV_X(TV_X),
.oYCbCr(YCbCr),
.oDVAL(TV_DVAL),
.iSwap_CbCr(Quotient[0]),
.iSkip(Remain==4'h0),
.iRST_N(DLY1),
.iCLK_27(TD_CLK) );
Sau ghp 1 Y vi 1 Cr hay 1 Y vi 1 Cb ng thi hon i v tr ca Cr v
Cb ti cc v tr cn thit:
if(iSwap_CbCr)
begin
case(Cont[1:0]) //hon i Cb v Cr
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cr};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cb};
endcase
end
else
begin
case(Cont[1:0]) //khng cn hon i
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cb};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cr};
endcase
end
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Sau xt thm iu kin Cont[0] m bo vic ghp 1 byte Y vi 1 byte
Cr hay 1 byte Y vi 1 byte Cb hon thnh xut DATA_VALID :
if(Start && FVAL && Active_Video && Cont[0] && !iSkip )
Data_Valid <= 1'b1;
else
Data_Valid <= 1'b0;
Nh vy Data_Valid ch ln 1 Active Pixel iu khin s ghi vo
SDRAM BUFFER.
9. KHI SDRAM BUFFER
9.1 S KHI
Gm 2 khi PLL v SDRAM Controller:


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Hnh 9.1: S khi SDRAM BUFFER
Tn M t
RESET Tn hiu reset h thng
CLK_27 Xung clock 27MHz t kit DE2

CLK
Xung clock 81MHz PLL a ra cho cc ng vo CLK ca
khi SDRAM Controller ( chnh l tn s c ca
SDRAM WRITE FIFO, ghi ca SDRAM READ FIFO1 v
SDRAM READ FIFO2)
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SDR_CLK Xut xung clock 81MHz cho SDRAM
WR_LOAD
RD1_LOAD
RD2_LOAD

Ln lt l tn hiu xa bt ng b SDRAM WRITE
FIFO, SDRAM READ FIFO1 v SDRAM READ FIFO2
ly t chn RST0 ca khi Timer tr hon ban u.

WR_DATA

D liu nh a vo SDRAM WRITE FIFO do Desize
horizon cp

WR

Cho php ghi vo SDRAM WRITE FIFO ly t chn
DATA_VALID ca khi Desize horizon

WR_CLK

Xung clock 27MHz t chn LLC(TD_CLK) ca
ADV7181B

RD_WRFIFO

Cho php c d liu t SDRAM WRITE FIFO

WRITE_SIDE[8:0]

S t (Word) hin c trong SDRAM WRITE FIFO

DATA_IN

D liu t SDRAM WRITE FIFO a vo Control Center
ghi SDRAM.

DATA_OUT[15:0]

D liu Control Center c t SDRAM xut ra ngoi
qua 1 trong 2 FIFO: SDRAM READ FIFO1, SDRAM
READ FIFO2

RD1
RD2
RD1 = ~ RD2: Ln lt cho php c d liu t SDRAM
READ FIFO1, SDRAM READ FIFO2 vi s iu khin
ca khi VGA Cotroller thng qua chn Request v
VGA_Y.
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RD1_CLK
RD2_CLK

Tn s c ca SDRAM READ FIFO1 v SDRAM READ
FIFO2 c l 27MHz t KIT DE2


READ_SIDE1[8:0]
S t (Word) hin c trong SDRAM READ FIFO1
READ_SIDE2[8:0] S t (Word) hin c trong SDRAM READ FIFO2
WR_RDFIFO1 Cho php ghi d liu SDRAM READ FIFO1
WR_RDFIFO2
Cho php ghi d liu SDRAM READ FIFO2
RD1_DATA[15:0]
RD2_DATA[15:0]
D liu ng ra cung cp cho khi x l nh YUV

Cc chn DQ[15:0], SA[11:0], CKE, CAS_N, RAS_N, SDR_CLK, WE_N,
BA[1:0], CS_N[1:0], DQM[1:0] th c ni tng ng vo chip SDRAM c sn trn
kit DE2.
9.2 M T
Nh ta bit 1 frame nh theo chun ITU656 bao gm Odd Field v Even
Field: khi xut ra mn hnh th cc line thuc Odd Field s c hin th hng l,
cn cc line thuc Even l hng chn. Nn cc line ca 2 Field ny phi c xut
xen k nhau nhng trong chui video ITU656 do ADV7181B xut ra th 2 Field c
xut lin tc: xut xong Odd Field ri mi ti Even Field (cc frame khi ghi vo
SDRAM th thnh 2 Field lin tc) nn xut ra cc line xen k th ta phi tun t
xut 1 line t a ch m Odd Field c lu gi ri li xut tip 1 line t a ch m
Even Field c lu gi.
D liu trong mt frame nh s c ghi ln lt vo SDRAM t a ch 0
n a ch 324480 (324480 = 640 x 507, 507 chnh l s line ca frame c ghi vo
SDRAM ,ta b qua 18 line c bit V =1 ), lc ny phn d liu cn xut ra t SDRAM
chia thnh 2 phn (trong 1 frame theo chun ITU656 thc s c ti 487 active line, ta
xn bt 7 active line gim s line v chun hin th l 480):
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Phn 1: T a ch 8320 (640 x 13) n 161920 (640 x 253) s l cc Pixel
thuc Odd Field. y chnh l 240 line t 23 n 262 trong frame gc.
Phn 2: T a ch 170880 (640 x 267) n 324480 (640 x 507) l cc
Pixel thuc Even Field. y chnh l 240 line t 286 n 525 trong frame gc.
SDRAM h tr ch truy cp d liu theo tng khi (Burst) vi chiu di
khi c th thay i c nh vo ci t gi tr 3 bit cui (BL) ca thanh ghi mode
register bng cch truy cp ch load mode ri nhp gi tr cho thanh ghi ny qua
cc chn a ch:

y c v ghi theo tng khi 128 word 16 bit nn nhp BL = 111: chiu
di ca Burts l full page (tc l 256 word vi vic s dng SDRAM di dng 4M
x 16); WT=0: truy xut tun t (Sequential) d liu trong khi; LTMODE = 011:
thi gian ch (latency) cho tn hiu RAS l 3 chu k;
Cc Burst d liu ca 2 phn trn s c xut xen k nhau. Ta khi to v chi
xut a ch cho cc phn ny nh sau:
if(!RESET_N)
begin
rWR_ADDR <= 0;
rWR_MAX_ADDR <= 640*507;
rRD1_ADDR <= 640*13;
rRD1_MAX_ADDR <= 640*253;
rRD2_ADDR <= 640*267;
rRD2_MAX_ADDR <= 640*507;
//chiu di ca khi cn truy xut
rWR_LENGTH <= 128;
rRD1_LENGTH <= 128;
rRD2_LENGTH <= 128;
end
else
begin
//nu thc hin xong tc v mWR_DONE, mRD_DONE v c c
bo thc hin tc v mi i vi mt khi WR_MASK[0], RD_MASK[0],
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RD_MASK[1] th tng a ch khi ln 1 khi v lp li cho n khi vt
qu a ch ti a th quay v a ch ban u.
//ghi vo SDRAM
if(WR_LOAD)
begin
rWR_ADDR <= WR1_ADDR;
rWR_LENGTH <= WR1_LENGTH;
end
else if(mWR_DONE&WR_MASK[0])
begin
if(rWR_ADDR<rWR_MAX_ADDR-rWR_LENGTH)
rWR_ADDR <= rWR_ADDR+rWR_LENGTH;
else
rWR_ADDR <= WR_ADDR;
end
//c d liu t phn 1
if(RD1_LOAD)
begin
rRD1_ADDR <= RD1_ADDR;
rRD1_LENGTH <= RD1_LENGTH;
end
else if(mRD_DONE&RD_MASK[0])
begin
if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
rRD1_ADDR <= rRD1_ADDR+rRD1_LENGTH;
else
rRD1_ADDR <= RD1_ADDR;
end
//c d liu t phn 2
if(RD2_LOAD)
begin
rRD2_ADDR <= RD2_ADDR;
rRD2_LENGTH <= RD2_LENGTH;
end
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else if(mRD_DONE&RD_MASK[1])
begin
if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
rRD2_ADDR <= rRD2_ADDR+rRD2_LENGTH;
else
rRD2_ADDR <= RD2_ADDR;
end
end
Trc ht cn to mt khi iu khin vic ghi v c SDRAM xen k nhau,
mi ln c hay ghi d liu s thao tc trn tng Burst c chiu di l 128 t (Word)
theo th t u tin (ch thao tc hin thi hon thnh ri mi thc hin thao tc tip
theo):
- c 1 khi t SDRAM ri ghi vo SDRAM READ FIFO1 xut chui
Pixel thuc Odd Frame.
- c 1 khi t SDRAM ri ghi vo SDRAM READ FIFO2 xut chui
Pixel thuc Even Frame.
- Ghi 1 khi t SDRAM WRITE FIFO vo SDRAM.
trn ta thc hin 3 thao tc xen k nhau, v vy d liu c th ng b
nhp, xut d liu vi cc khi khc th phi cung cp tn s lm vic cho SDRAM v
tn s truy xut d liu gia cc khi FIFO v SDRAM gp 3 ln tn s clock ca cc
khi khc. to cc xung clock ny ta s dng th vin ca Quartus to khi
PLL :
Phn Menu >> Tools >> MegaWizard Plug_in Manager >> Create to
mt custom mi, t tn l SDRAM_PLL, chn phn I/O >> ALTCLKILOCK, ta
khng s dng cc chn ng b m ch nhp cc thng s cho tn s ng vo v tn
s ng ra nh sau: inclk0 l 27MHz; c0 chn tn s l 81MHz vi pha ban u l 0;
c1 tn s l 81 MHz vi pha ban u tr 3ns (b tr vi khng thi gian iu khin
cc tn hiu ng b truy cp SDRAM).
Chn c0 s cung cp tn s c tn s cho SDRAM WRITE FIFO ghi d
liu vo SDRAM, tn s ghi cho SDRAM READ FIFO1 v SDRAM READ FIFO2
ghi d liu c xut ra t SDRAM. Chn c1 cung cp tn s lm vic cho
SDRAM.
ng thi khi thc hin 1 tc v ta cn phi tr hon cc tc v khc mt
khong thi gian c m t theo gin sau (cha xt tc ng ca RD1 v RD2):
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Hnh 9.2: Gin nh th cho chu k truy xut gia SDRAM v cc FIFO
V vy m bo truy xut ng d liu th cn phi c cc FIFO c chiu
di 384 ( tc l 128 x 3 ). Tuy nhin trong th vin ca Quarus ch c FIFO di 384
Word nn s to mt FIFO di 512 Word nh sau:
Phn Menu >> Tools >> MegaWizard Plug_in Manager >> Create to
mt custom mi, t tn l SDRAM_WRITE_FIFO, chn phn Memory Compiler >>
FIFO chn rng d liu l 16bit, chiu di ( deep ) l 512 Words. Lm tng t
to cc khi SDRAM_READ_FIFO1 v SDRAM_READ_FIFO2.
Khi s dng FIFO di 512 Word ta phi c 1 s thay i trong thit k, tuy
nhin cc thay i ny tng i n gin nh tng tn s xung clock ln 108 MHz,
s dng thm 1 tc v ghi trng (WR2) m bo d liu xut ra ung theo yu cu.
Thc hin ghi v xut tng khi d liu xen k t SDRAM nh sau:
//ghi vo SDRAM READ FIFO1 cc Pixel thuc line Odd frame
if( (READ_SIDE1< rRD1_LENGTH) )
begin
mADDR <= rRD1_ADDR;
mLENGTH <= rRD1_LENGTH;
WR_MASK <= 2'b00;
RD_MASK <= 2'b01;
mWR <= 0;
mRD <= 1;
end
//ghi vo SDRAM READ FIFO2 cc Pixel thuc line Even frame
else if( (READ_SIDE2< rRD2_LENGTH) )
begin
mADDR <= rRD2_ADDR;
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mLENGTH <= rRD2_LENGTH;
WR_MASK <= 2'b00;
RD_MASK <= 2'b10;
mWR <= 0;
mRD <= 1;
end
//c d liu t SDRAM WRITE FIFO v ghi vo SDRAM
else if( (WRITE_SIDE>= rWR_LENGTH)&& (rWR_LENGTH!=0) )
begin
mADDR <= rWR_ADDR;
mLENGTH <= rWR_LENGTH;
WR_MASK <= 2'b01;
RD_MASK <= 2'b00;
mWR <= 1;
mRD <= 0;
end
end
if(mWR_DONE)
begin
WR_MASK <= 0;
mWR <= 0;
end
if(mRD_DONE)
begin
RD_MASK <= 0;
mRD <= 0;
end
Xt iu kin s Word c trong cc FIFO khi to lnh c v ghi
SDRAM. Ri dng bin m ST (bt u t 0) thit lp khong thi gian cn thit
cho 1 tc v bao gm: thi gian ch bus m bo rnh hon (i vi lnh c l
SC_CL+SC_RCD+1, ghi l SC_CL-1, ph thuc vo cu trc ca SDRAM: SC_CL
= SC_RCD = 3 c khai bo trong tp tin Sdram_Params.h ), thi gian thc hin tc
v (mLENGTH = 128).To tn hiu iu khin vic ghi c cc FIFO v c bo
c hay ghi xong nh sau:
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if(Read)
begin
//OUT_VALID l tn hiu dng iu khin cho php ghi vo cc SDRAM
//READ FIFO
if(ST==SC_CL+SC_RCD+1)
OUT_VALID <= 1;
else if(ST==SC_CL+SC_RCD+mLENGTH+1)
begin
OUT_VALID <= 0;
Read <= 0;
mRD_DONE <= 1;
end
end
else
mRD_DONE <= 0;
if(Write)
begin
//IN_REQ l tn hiu dng iu khin cho php c t SDRAM WRITE
//FIFO
if(ST==SC_CL-1)
IN_REQ <= 1;
else if(ST==SC_CL+mLENGTH-1)
IN_REQ <= 0;
else if(ST==SC_CL+SC_RCD+mLENGTH)
begin
Write <= 0;
mWR_DONE <= 1;
end
end
else
mWR_DONE<= 0;
vi chu k truy xut nh gin trn th lng d liu xut ra s gp 2 ln
lng d liu ghi vo SDRAM. Tuy nhin qu trnh trn cn chu nh hng ca cc
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ng vo RD1 v RD2, (tc ng n cc gi tr READ_SIDE1 v READ_SIDE2) s
iu khin cc thao tc xut d liu t SDRAM vo SDRAM READ FIFO nh sau:
- RD1 = ~RD2 = 1: ngng tc v xut d liu t SDRAM vo SDRAM
READ FIFO2 tc l ch xut cc line ca Odd Field.
- RD1 = ~RD2 = 0: ngng tc v xut d liu t SDRAM vo SDRAM
READ FIFO1 tc l ch xut cc line ca Even Field.
Do RD1, RD2 c tch cc ln lt sau 640 chu k (tng ng vi 1 line)
nn cc line s c xut xen k nhau. Nh vy trong 1 chu k truy xut thc s ch
c 128 Word c xut vo 1 FIFO, m bo c s ng b d liu ca SDRAM
vi h thng.
Vn cui cng cn phi gii quyt l xc nh cc thi im truy xut
SDRAM BUFFER tc l tnh ton khong thi gian k t khi bt u ghi d liu
vo(WR=1) v ti khi bt u xut chng ra m bo cc pixel c xut ra l
cng thuc 1 frame:
- Nu khong thi gian ny khng ln: chn RD2 tch cc bt u truy
xut d liu ca Even Field t a ch 170880 cho n 324480, m d liu trong cc
a ch ny li cha c cp nht nn dn n cc line xut ra s khng c gi tr
hoc l cc line ca frame trc.
- Nu khong thi gian ny qu ln: do tc tng a ch ca qu trnh ghi
gp i qu trnh c (do a ch ghi c tng lin tc cn ch c ln lt l a ch
xut xen k cc line thuc Odd Field v Even Field nn cng ch c tng ln
lt), nn xy ra trng hp khi ang xut d liu thuc 1 frame th qu trnh ghi
nhp d liu ca frame tip theo vo SDRAM BUFFER, khi RD1 tch cc th c
th xut ra 1 line thuc frame mi ny ch khng phi l line ca frame hin hnh.
Nh ni trong phn m t khi Timer tr hon ban u, vic c t
SDRAM BUFFER c kch hot sau 1 khong thi gian l 513927.5 chu k tnh t
khi frame th 3 bt u: khi cc Pixel trn line th 300 ca frame gc ( 513872.5
1716; vi1716 l s byte ca 1 line trong frame gc) tng ng vi line th 282
(b qua18 line c bit V =1) ang c ghi vo SDRAM BUFFER, th bt u xut
xen k cc line. iu kin RD2 truy xut ng Even frame c tha mn, xt cc
line m RD1 xut ra:
- Khi WR ghi lin tc t line 282 n line 507 vo SDRAM BUFFER th
hin nhin l RD1 truy xut ng. Lc ny line m RD1 ang xut l 13 + (507 - 282)
2 = 125.5
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- Xt frame tip theo: phi ch ht 9 line u tin mi bt u ghi t line 0.
Lc RD1 s truy xut line th 125.5 + 9 : 2 = 130; nh vy cho n khi RD1 xut
line xong line th 253 th WR mi ch ghi ti line (253-130)2 = 246. m bo d
liu c xut vn l ca frame hin thi.
Ngoi ra trong khi Control Center cn c cc khi command, control
interface to v ng b cc lnh lm ti (refresh), tch np (Precharge), chn ch
c, ghi, truyn khi, ng thi m ha v gii m lnh cho SDRAM theo m t
cc ch truy cp SDRAM Bng 1.2 vi cu trc kh phc tp. Trong khun kh
n ny khng cp n m ch tham kho v s dng code verilog t cng ty
Altera v hng sn xut KIT DE2 l Terasic.
Khi ghp vo trong khi tng th ta s dng cu trc xut d liu nh sau:
.RD1_DATA(m1YCbCr), .RD2_DATA(m2YCbCr), ri chn d liu a vo khi
x l nh YUV : assign mYCbCr_d = !VGA_Y[0]? m1YcbCr : m2YCbCr; vi
!VGA_Y[0] l do khi VGA Controller a ra cho bit line ang xut trn mn hnh
v tr l hay chn chn d liu xut ra tng ng.
10. KHI X L NH YUV
10.1 S KHI

Hnh 10.1: S ca khi x l nh YUV
Tn M t
CLK
Xung clock 27Mhz t kit DE2.
RESET Reset h thng.
mYCbCr_d[15:0] D liu hnh nh ng vo.
oRequest
Tn hiu iu khin do VGA Controller cung cp:
yu cu xut d liu.
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iX[0]
Tn hiu iu khin do VGA Controller cung cp,
cho bit v tr ca Pixel l chn hay l (bit 0 trong gi
tr ca b m v tr Pixel)
oRequest
Tn hiu iu khin do VGA Controller cung cp:
yu cu xut d liu.
iYCbCr Pixel nh sau qua Image Process x l.
oY[7:0] Thnh phn sng (Luma) ca Pixel c tch ra.
oCb[7:0] Thnh phn Cb ca Pixel c tch ra.
oCr[7:0] Thnh phn Cr ca Pixel c tch ra.
Resgister[1..9][15:0]

9 thanh ghi tng ng vi ca s 3x3 pixels.

10.2 M T
Khi Line Buffer: l b m lu li cc gi tr cc Pixel cn thit. Xt ca
s 3x3 Pixel: trong chui d liu ng vo v tr cc pixel ny nh sau:

ca pixel ny xut hin cng lc trong 1 ca s th phi cn c cc b m
( cc thanh ghi v line buffer) lu li cc gi tr ca P1, P2, P3, P4, P5, P6, P7, P8
cho n khi P9 xut hin:

Hnh 10.2: s dng cc Line_Buferr v Regitster to ca s 3x3 pixel
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Line_Buffer c th l 1 FIFO hoc l 1 thanh ghi dch(shift register), nhng
trong th vin ca Quartus khng c FIFO vi chiu di 640 Words, nn ta s dng
thanh ghi dch:
Phn Menu >> Tools >> MegaWizard Plug_in Manager >> Create to
custom mi, t tn l Line_Buffer, chn phn Memory Compiler >> shift register
( RAM-Based). Ta chn rng d liu l 8bits, chiu di (distance between Taps) l
640, s Tap l 1, v nh du chn s dng chn clock enable. Nh vy ta c
ca s Pixel:

Khi x l nh: Ta chn 1 trong hai ch lm vic: lc trung bnh v tch
bin.
Lc trung bnh: Thc hin php tng quan ca s pixel vi mt n

Tuy nhin d liu vo l 16 bit vi 8 bit cao l thnh phn Y v 8 bit thp l
Cb hoc Cr. Nn ta s dng khai bo tch ra tng thnh phn ri x l:
Loc_trung_binh Loc_trung_binh_0 ( clock,
reset,
register1[7:0],
register2[7:0],
register3[7:0],
register4[7:0],
register5[7:0],
register6[7:0],
register7[7:0],
register8[7:0],
register9[7:0],
out2
);
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Loc_trung_binh Loc_trung_binh_1 ( clock,
reset,
register1[15:8],
register2[15:8],
register3[15:8],
register4[15:8],
register5[15:8],
register6[15:8],
register7[15:8],
register8[15:8],
register9[15:8],
out1
);
thc hin php tng quan gia ca s Pixel vi mt n lc, ta tin hnh
theo cc bc:
Nhn cc thnh phn tng ng ca 2 ca s li vi nhau: mt n lc ch
c cc h s 1, 2, 4 (d thy kt qu l cc s 10 bit )
k = 1 th gi nguyn: multi_1 <= { 2'b00, register1};
k = 2 th dch tri 1 bit : multi_2 <= { 1'b0, register2,1b0};
k = 4 th dch tri 2 bit: multi_5 <= { register5,1b00};
Ly tng cc tch va tm c (tng ny l 12 bit):
assign multi1 = multi_1 + multi_3 + multi_7 + multi_9;
assign multi2 = multi_2 + multi_4 + multi_6 + multi_8;
assign multi = multi1 + multi2 + multi_5;
Chia tng trn cho 16 tng ng vi vic ly 8 bit cao:
assign out = multi[11:4];
Tch bin: Tng t nh trn ta cng tch d liu 16 bit ra tng thnh
phn x l vi cc bc thc hin nh sau:
a) Tnh |Gx| v |Gy|: Chp ma trn ca s 33 pixels nh ca frame vi hai
mt n lc theo phng php gradient vi mt n lc Prewitt :

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Trang 47


Mat na loc ch co cac he so 0, 1, 2 , -1 va -2 ( k =1, 2 a xet phep loc
trung bnh)
k = 0 th multi <= 0;
k =-1 th ly b 2: multi = ~{3'b000,register} + 1;
k = -2 dch tri 1 bit ri ly b 2: multi = ~{2'b00,register,1'b0}+1;
Vi register [7:0] nhn vi s [1:0] -> s [9:0] thm bit du thnh s [11:0],
tc l 12 bits. Sau cng tt c cc thnh phn ca ca s thu c ri ly 8 bit cao
trong gi tr tuyt i ta c kt qu l |Gx| v |G y|
b) Tnh gi tr ng ra ca pixel theo cng thc G = 0
x
2
+ 0

2

Tnh gi tr bnh phng ca Gx v Gy vi b nhn t th vin ca Quartus:
Phn Menu >> Tools >> MegaWizard Plug_in Manager >> Create to
custom mi, t tn l MULT2, chn phn Arithmetic >> LPM_MULT. Chn rng
bit ng vo l 8 bit. Sau khi tng hp ta c mt khi vi khai bo nh sau:
module MULT2 ( dataa,
datab,
result);
ly php bnh phng ta nhp cng mt gi tr cho 2 ng vo dataa v
datab.
Dng b ly cn bc 2 t th vin ca Quartus tnh G t tng hai kt qu
trn:
Phn Menu >> Tools >> MegaWizard Plug_in Manager >> Create to
custom mi, t tn l SQUARE, chn phn Arithmetic >> ALTSQRT. Chn rng
bit ng vo l 16 bit.Sau khi tng hp ta c mt khi vi khai bo nh sau (trong
radical l d liu 17 bit ng vo, q l kt qu 9 bit ca php ly cn, ta khng s
dng chn remainder):
module SQUARE ( radical,
q,
remainder);
Thc cht khi x l nh ch l cc cp khi lc bin, lc trung bnh c
ghp song song nhau. Mi khi trong cp x l trn tng 8 bit d liu, sau ghp
chng li vi nhau (out3, out 4 tng t l cc ng ra ca cc khi lc bin)
assign out_pixel = (!reset)? 16'b0 : out;
assign out = select_process? {out1,out2} : {out3,out4};
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Khi s xut ra gi tr ca pixel nh tng ng vi gi tr pixel nh nm chnh
gia ca s. C 1 vn c t ra y l khi mt frame va bt u th ca s
cha c 9 Pixel nhng b x l nh vn thc hin lc v xut pixel s dn n sai
s bin nh. ng thi khi Image Process cn c 1 s chu k xung clock x l
xong nh. Tuy nhin vi 1 frame kch thc 640 x 480 th cc sai lch ny c th chp
nhn c.
Khi Extract YCrCb to Y, Cr, Cb : n gin ch l tch chui d liu 16 bit
dng YCrCb lin tip ra 3 thnh phn Y, Cr, Cb. Da vo tn hiu iX[0] do VGA
controller a ra bit v tr ca Pixel trong hng l chn hay l(16 bit ny l YCb
hay l YCr):
if(iX[0])
{mY,mCr} <= iYCbCr;
else
{mY,mCb} <= iYCbCr;
Nh vy d liu 16 bit ng vo c x l v tch ra 3 thnh phn Y, Cr,
Cb.
11. KHI CONVERT YCRCB TO RGB
11.1 S KHI

Hnh 11.1: S ca khi Convert YCrCb to RGB
Tn M t

CLK

Xung clock 27Mhz t kit DE2.
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RESET Reset h thng.
iY[7:0] Thnh phn sng (Luma) ca Pixel c tch ra.
iCb[7:0] Thnh phn Cb ca Pixel c tch ra.
iCr[7:0] Thnh phn Cr ca Pixel c tch ra.
Red[9:0] Thnh phn Red ca Pixel tng ng.

Green[9:0] Thnh phn Green ca Pixel tng ng.

Blue[9:0] Thnh phn Blue ca Pixel tng ng.
11.2 M T
Khi ny chuyn i t dng d liu nh YCrCb 8 bit sang dng RGB 10 bit
cho ph hp vi yu cu ng vo ca VGA DAC l ADV7123. Di y l cng thc
chuyn i sang dng RGB 8 bit:
R = 1.164 ( Y - 16 ) + 1.596 ( Cr 128 ) ;
G = 1.164 ( Y - 16) - 0.392 ( Cb - 128 ) - 0.813 ( Cr - 128 ) ;
B = 1.164 ( Y - 16 ) + 2.017 ( Cb 128 ) ;
Sau c dng RGB 10 bit th ta dch tri 2 bit ( nhn 4 ) nn c cng thc
mi:
R = 4.656 ( Y - 16 ) + 6.384 ( Cr - 128 ) ;
G = 4.656 ( Y - 16 ) - 1.568 ( Cb - 128 ) - 3.252 ( Cr - 128 );
B = 4.656 ( Y - 16 ) + 8.068 ( Cb - 128 ) ;
Do cc h s c dng thp phn, trong khi cc php ton ca phn cng
c tng hp ch thc hin trn s nguyn nn khi lm trn v tnh ton th sai s
kh ln, v vy ta phi nhn biu thc trn vi mt s nguyn H no gim bt
sai s khi lm trn cc h s, sau tnh ton biu thc ri chia li cho H. S nguyn
H ta chn c dng 2
k
th thay v thc hin php chia cho A ta ch cn dch phi k bit.
y ta chn k = 7 hay H = 128 th chnh xc ca h s s n ch s th 2 sau
du phy. Ta c cng thc cui cng ( lm trn tnh ton trn cc s nguyn) :
oR = (596 Y + 817Cr 114131) : 128 ;
oG = (596 Y 200Cb 416Cr + 69370) : 128 ;
oB = (596 Y + 1033Cb 141781) : 128 ;
thc hin cng thc trn ta tin hnh theo cc bc:
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Nhn cc thnh phn Y, Cb, Cr vi cc h s tng ng ri cng chng
li, s dng b tng hp cng nhn ( ALTMULT_ADD ) trong th vin ca Quartus :
Phn Menu >> Tools >> MegaWizard Plug_in Manager >> Create to
custom mi, t tn l MAC3; chn phn Arithmetic>>ALTMULT_ADD. Vi cc
thng s c chn nh sau:
- Tnh oG cn 3 php nhn : s lng b nhn l 3.
- Y,Cb,Cr l s 8 bit dng: rng ng vo A l 8, kiu d liu khng du
(Unsigned)
- Trong cc h s c s m nn, gi tr ln nht l 1033 (s 11 bit) : rng
ng vo B l 11, kiu d liu c du (signed)
- Chn hm gia hai b nhn u tin (first pair of multiplier) l php cng
(Add). Khi tng hp xong ta c mt khi vi khai bo nh sau :
module MAC_3 ( dataa_0,
dataa_1,
dataa_2,
datab_0,
datab_1,
datab_2,
result,
aclr0,
clock0);
Trong :
- Ng vo iu khin : xa bt ng b aclr0 v xung clock lm vic clock0.
- Cc ng vo d liu l dataa_0; dataa_1; dataa_2 l cc s 7 bit khng
du; datab_0; datab_1; datab_2 l cc s 11 bit c du;
- Ng ra l d liu 21 bit c du:
result = (dataa_0 datab_0) + (dataa_1 datab_1) + (dataa_2
datab_2).
Ch : data_b0, data_b1, data_b2 l cc h s cng thc tnh trn:
596d = 254h , 817d = 331h , -200d = F38h (s b hai), -416d = E60h (s b hai), 1033d =
409h .Vy thc hin bc ny ta s gi cc khi MAC_3 nh sau:
MAC_3 u0( iY, iCb, iCr,
11'h254, 11'h000, 11'h331,
X, iRESET, iCLK);
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MAC_3 u1( iY, iCb, iCr,
11'h254, 11'hF38, 11'hE60,
Y, iRESET, iCLK);
MAC_3 u2( iY, iCb, iCr,
11'h254, 11'h409, 11'h000,
Z, iRESET, iCLK);
Sau tr (cng) vi cc s hng cn li ri chia cho 128 bng cch dch phi
7 bit:
X_OUT <= ( X - 114131 ) >>7;
Y_OUT <= ( Y + 69370 ) >>7;
Z_OUT <= ( Z - 141787 ) >>7;
Tuy nhin khi cc gi tr R, G, B c tnh theo cng thc trn th c th l s
m hoc vt qu 1023 (10 bit ) v vy ta gii hn li gi tr vo trong khong 0 n
1023:
if(X_OUT[13])
oRed<=0;
else if(X_OUT[12:0]>1023)
oRed<=1023;
Thc hin tng t vi 2 thnh phn cn li th d liu khi xut ra s l dng
RGB ph hp vi yu cu t ra.
12. KHI VGA CONTROLLER
12.1 S KHI

Hnh 12.1: S ca khi VGA Controller
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Tn M t
CLK Xung clock 27Mhz t kit DE2.
RESET Tn hiu reset do khi Timer tr hon ban u cung cp.
oRequest
Tn hiu iu khin cho php xut d liu t SDRAM
BUFFER v lu cc gi tr ca Line Pixel vo khi Line
Buffer.
oVGA_BLANK
oVGA_SYNC
oVGA_VS
oVGA_HS
Cc chn ny c gn tng ng vo chip gii m
ADV7123 v cng VGA trn kit DE2 ng b vic xut
ra monitor cc frames nh. Do xut nh theo chun VGA
640 x 480 nn chn VGA_SYNC lun phi t mc cao
m bo vic ng b.
VGA_X[0]
Cho bit v tr ca Pixel l chn hay l iu khin vic
tch cc thnh phn Y, Cr, Cb trong khi x l nh YUV
VGA_Y[0]
Cho bit Line s hin th trn mn hnh l thuc Odd Frame
hay Even Frame chn d liu a ra t SDRAM
BUFFER

Cc chn d liu iRed, iGreen, iBlue c ni trc tip vi ng ra VGA_R,
VGA_G, VGA_B. Ng ra oVGA_CLOCK l nghch o ca ng vo CLK .
12.2 LU GII THUT
Gii thut to tn hiu ng b giao tip vi VGA l to cc b m vi cc
thng s chun to ra cc tn hiu ng b theo gin thi gian:


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Hnh 12.2: Vng hin th trong mt chu k qut vi tnh hiu reset t h thng
T cc thng s nh th cho chun VGA 640 x 480 60Hz trn, do xung
clock trong thit k c tn s 27Mhz nn ta chn cc gi tr tng ng cho cc thng
s nh sau:
a) i vi VGA_HS (tn hiu ng b quy nh thi gian hin th 1 hng
trong 1 chu k qut ngang):
H_FRONT = 16, H_SYNC = 96, H_BACK = 48, H_ACT = 640
Nh vy khi hin th xong 1 hng th phi ch 1 khong thi gian l
H_BLANK = H_FRONT + H_SYNC + H_BACK = 160
(n v l s chu k xung clock) th hin th hng mi. Lc ny thi gian qut ngang
l: H_TOTAL = H_BLANK + H_ACT = 800.
b) i vi VGA_VS(tn hiu ng b quy nh thi gian hin th 1 frame
trong 1 chu k qut ton b mn hnh):
V_FRONT = 11; V_SYNC = 2; V_BACK = 31; V_ACT = 480
Nh vy khi hin th xong 1 frame th phi ch 1 khong thi gian l:
V_BLANK = V_FRONT + V_SYNC + V_BACK = 44
(n v l chu k xung qut ngang VGA_HS) th hin th frame mi. Thi gian qut
mn hnh l:
V_TOTAL = V_BLANK + V_ACT= 524.
Lu gii thut to VGA_VS cng c thc hin tng t ch khc l
V_Cont c m ln sau mi cnh ln ca VGA_HS.
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12.3 M T
Khi s to cc tn hiu iu khin cho ADV7123 v ng b vic truy xut,
x l d liu vi cc khi khc da trn cc tn hiu nh th qut ngang v qut dc
nh sao:
To tn hiu qut ngang VGA_HS vi b m ln H_Cont :
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if( H_Cont < H_TOTAL )
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
//a VGA_HS v 0 tng ng vi khong thi gian Horizontal SYNC
if(H_Cont == H_FRONT-1)
oVGA_HS <= 1'b0;
if(H_Cont == H_FRONT+H_SYNC-1)
oVGA_HS <= 1'b1;
end
end
To tn hiu qut dc VGA_VS vi b m V_Cont theo cnh ln ca
VGA_HS:
always@(posedge oVGA_HS or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
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end
else
begin
if(V_Cont < V_TOTAL)
V_Cont <= V_Cont+1'b1;
Else
V_Cont <= 0;
//a VGA_HS v 0 tng ng vi khong thi gian Hrizontal SYNC
if(V_Cont == V_FRONT-1)
oVGA_VS <= 1'b0;
if(V_Cont == V_FRONT+V_SYNC-1)
oVGA_VS <= 1'b1;
end
end
Sau xut cc tnh hiu iu khin khc:
//tch cc tn hiu BLANK xa cc Flicker:
assign oVGA_BLANK = ~((H_Cont < H_BLANK) || (V_Cont <_BLANK));
//oRquest ln 1 thi gian hin th frame trong mt chu k qut mn hnh:
assign oRequest = ( ( H_Cont >= H_BLANK && H_Cont < H_TOTAL )
&& ( V_Cont>=V_BLANK && V_Cont<V_TOTAL ) );
//tnh ton v tr X,Y ca Pixel trong frame (X : v tr pixel trong hng v Y :
//v tr hng trong frame) :
assign oCurrent_X = (H_Cont>=H_BLANK)? H_Cont-H_BLANK : 11'h0;
assign oCurrent_X = (V_Cont>=V_BLANK)? V_Cont-V_BLANK : 11'h0;
Nh vy k t khi bt u qut 1 frame th phi ch 1 khong thi gian c
di l (V_BLANK H_TOTAL) + H_ BLANK = 35360 (chu k) th oRequest mi
c tch cc.
13. KT LUN
14. TI LIU THAM KHO
[1]. Stuart Sutherland, Simon Davidmann, Peter Flake, System
Verilog for Design.
[2]. DAVID R. SMITH, PAUL D. FRANZON, verilog styles for
Synthesis of Digital Systems.
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[3]. D. Vanden Bout, VGA Generator for the XSA Boards, XESS
Corporation, October 12, 2004.
[4]. J. BHASKER, A Verilog HDL Primer.
[5]. T. R. PADMANABHAN, B. BALA TRIPURA SUNDARI, Design
Through Verilog HDL.
[6]. FPGA Design with Verilog.
[7]. Peter J. Ashenden, Digital Design.

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