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Arithmetic Unit
Logic Unit
4x 1 MUX
4 x 1 MUX
2 x 1 MUX
Logic gates
2 x 1 MUX
Status Register
Logic gates
8 bit adder
1 bit adder
Verilog Code
module ALU (A,B,S,St,T,clk,set,clr);
input clk,set,clr;
Output Register
input[7:0] A,B;
input[3:0] S;
output [3:0] St;
output [7:0] T;
wire [7:0] G,Y,Tin;
wire [3:0] F;
arithmetic_unit au(A,B,S[0],S[2:1],G,F); //Instantiation of subunits namely arithmetic and logic units,multiplexer,status and output
register
logic_unit lu(A,B,S[2:1],Y);
mux2_1 mux1(Y,G,S[3],Tin);
output_register d1(Tin,clk,set,clr,T);
status d2(F,clk,set,clr,St);
endmodule
//Arithmetic unit
mux4_1 m2(8'b0,B,B1,B,S,Y);
adder_8bit add1(X,Y,Co,G,F[0],F[1]);
nor(F[2],G[0],G[1],G[2],G[3],G[4],G[5],G[6],G[7]);
and(F[3],G[7],1'b1);
endmodule
module logic_unit(A,B,S,Y);
//Logic Unit
//1-bit adder
//4-is-to-1 multiplexer
endmodule
//2-is-to-1 multiplexer
//Status register
input [3:0]d;
input clk,st,clr;
output reg [3:0]q;
always@(negedge st,negedge clr,posedge clk)
begin
if(!clr)
q <= 0;
else if(!st)
q <= 1;
else q <= d;
end
endmodule
//Output register
input [7:0]d;
input clk,st,clr;
output reg [7:0]q;
always@(negedge st,negedge clr,posedge clk)
begin
if(!clr)
q <= 0;
else if(!st)
q <= 1;
else q <= d;
end
endmodule
Output
I.
Arithmetic Unit
Consider A=01010111 and B=11011010 and M=1
S1
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
Output
01010111
01011000
(1)00110001
(1)00110010
01111100
01111101
(1)10000010
(1)10000011
Output Waveforms
Arithmetic Unit
II.
Logic Unit
S1
0
0
S0
0
1
C0
X
X
Function
01010010
(1)00110001
1
1
0
1
Output Waveforms
Logic Unit
Test Bench
module testalu;
wire [7:0]T;
wire [3:0]St;
reg [7:0] A,B;
reg [3:0] S;
reg clk,set,clr;
integer i;
ALU a1 (A,B,S,St,T,clk,set,clr);
initial
begin
clk =0;
S= 0000;
X
X
10001101
01110010
A=01010100;
B=11101100;
clr = 0;
set = 1;
end
always
begin
#5 clk = ~clk;
end
always @(posedge clk)
begin
clr = 1;
for (i=0;i<16;i=i+1)
begin
#20 S = i;
end
end
endmodule