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Mc lc
Mc lc.............................................................................................................................................1
Li ni u........................................................................................................................................2
Chng I: Gii thiu chung..............................................................................................................5
1) t vn ................................................................................................................................5
2) Tng quan v ng dng ca VK trong cc mch in t......................................................5
....................................................................................................................................................6
Chng II: Cu trc phn cng........................................................................................................7
I)Gii thiu chung v h avr.........................................................................................................7
II)ATMEGA32.............................................................................................................................8
1) Tng quan.............................................................................................................................9
3) Cu trc ngt ATMEGA16...............................................................................................15
4 .Cu trc b nh.............................................................................................................17
5 .Cc cng vo ra (I/O)....................................................................................................22
7. B nh thi/m timer/counter 1 16-bit ...........................................................................32
8. SPI(Serial peripheral interface)..........................................................................................41
9.B so snh tng t(Alalog Comparator)...........................................................................46
.10. h thng xung clock.........................................................................................................48
III. Cu trc cng ni tip...........................................................................................................56
1. Khi Qut............................................................................................................................56
IV. LM35....................................................................................................................................65
Mt s tnh cht c bn ca lm35...........................................................................................65
V. HS1101 .................................................................................................................................65
Chc nng:..............................................................................................................................65
Chng III: Thit k mch trn Orcad v Layout..........................................................................67
CAPTURE......................................................................................................................................67
3.1. Gii thiu v cch s dng phn mm proteus...................................................................67
3.2 Thit k phn cng...............................................................................................................68
3.2.1. Tng quan v Orcad Capture........................................................................................68
3.2.2. V mch nguyn l bng Orcad Capture.....................................................................69
5.Khi dao dng ....................................................................................................................83
6.Khi np chng trnh ...................................................................................................83
7.Khi vi iu khin...............................................................................................................83
LAYOUT........................................................................................................................................87
3.3. V mch in bng Orcad Layout.......................................................................................87
TI LIU THAM KHO..............................................................................................................94
PH LC.......................................................................................................................................95
Chng trnh...............................................................................................................................95

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Li ni u
Hin nay, t nc ang trn pht trin mnh m, khoa hc cng ngh, k
thut pht trin. i sng ngi dn nng cao dn n nhu cu tin nghi v sinh
hot i hi ng dng c v cng ngh cng tng theo. Trc kia, chng ta cng
khng ngh mt thi im tng lai sau ny chng ta khng cn phi ng tay trc
tip m vn c th iu khin mt thit b g hay khng cn phi v tn nh
gii quyt mi khi s c xy ra. Nhng vic nh vy i vi khoa hc vin thng,
in t ngy nay khng cn l chuyn kh na v mc tiu hng ti ca con ngi
l khng nhng ch iu khin thit b n thun m cn tch hp nhiu chc nng
truyn thng, a phng tin vo mt thit b in t nh xu cm tay.
Nhn y, em cng xin chn thnh cm n c Vng Lan Nhi nhit
tnh hng dn, chnh sa, to c hi cho em hon thnh bi n ny trong thi
gian ngn nht.
Sinh vin thc hin

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Danh sch hnh v

Hnh 1.1 S chn ATMEGA16
Hnh 1.2 Thanh ghi trng thi SREG
Hnh 1.3 Thanh ghi chc nng chung
Hnh 1.4 Chc nng con tr ca cc thanh ghi R26 R31
Hnh 1.5 Thanh ghi con tr ngn xp
Hnh 1.6 b nh chng trnh
Hnh 1.7 B nh d liu sram
Hnh 1.8 Thanh ghi 8 bit
Hnh 1.9 B nh d liu eeprom
Hnh 1.10 Thanh ghi port I/O
Hnh 1.11 Hot ng ca b timer/couter
Hnh 1.13 n v m
Hnh 1.13. S n v so snh ng ra
Hnh 1.14 Thanh ghi iu khin b nh thi
Hnh 1.15. Thanh ghi b nh thi
Hnh 1.16. Thanh ghi mt n ngt TIMSK
Hnh 1.17 s khi b nh thi/m timer/counter 1 16-bit
hnh 1.18 SPI(Serial peripheral interface)
Hnh 1.19 B so snh tng t(Alalog Comparator)
Hnh 1.20 Ghp ni b dao ng thch anh
Hnh 1.21 Mch dao ng R-C
Hnh 1.22 Ghp ni vi my pht xung clock bn ngoi
Hnh 2.1 S chn cng ni tip
Hnh 2.2 Kt ni n gin trong truyn thng ni tip
Hnh 2.3 Kt ni trong truyn thng ni tip dng tn hiu bt tay
Hnh 2.4 IIR(Interrupt Identification Register):
Hnh 2.5 IER (Interrupt Enable Register):
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Hnh 3.0 S mch m phng
Hnh 3.1 s nguyn l mch
Hnh3.2 Khi ngun
Hnh 3.3 Khi lcd
Hnh 3.4 Khi reset
Hnh 3.5 Khi cm bin nhit
Hnh 3.6 Khi c bin m
Hnh 3.7 Khi to dao ng
Hnh 3.8 Khi np chng trnh
Hnh 3.9 Vi iu khin atmega16
Hnh 3.10 Khi chng nhiu

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Chng I: Gii thiu chung

1) t vn
Ngy nay cng s pht trin khng ngng ca khoa hc k thut, th k thut
s em li cho con ngi nhng thnh tu to ln, gip cho con ngi d dng t
c mc ch ca mnh trong mi thit k. Ho nhp cng xu hng , vi iu
khin khng nh c v th vng chc ca mnh trong mi ng dng. in
hnh trong cng ngh o lng v iu khin bng my tnh c bit l vic o nhit
v iu khin cc h thng. vn t ng n nh nhit l yu t quan trng
hng u nng cao cht lng cuc sng , sn xut. V vy, vic ng dng vi
iu khin trong t ng iu khin nhit v hin th kt qu trn my tnh
c nghin cu v ng dng.

2) Tng quan v ng dng ca VK trong cc mch in t

Vi iu khin l mt my tnh c tch hp trn mt chp, n thng c s
dng iu khin cc thit b in t. Vi iu khin, thc cht, l mt h thng
bao gm mt vi x l c hiu sut dng v gi thnh thp (khc vi cc b vi x
l a nng dng trong my tnh) kt hp vi cc khi ngoi vi nh b nh, cc m
un vo/ra, cc m un bin i s sang tng t v tng t sang s,... my tnh
th cc m un thng c xy dng bi cc chp v mch ngoi.
Hu ht cc vi iu khin ngy nay c xy dng da trn kin trc von
Neumann, kin trc ny nh ngha bn thnh phn cn thit ca mt h thng
nhng. Nhng thnh phn ny l li CPU, b nh chng trnh (thng thng l
ROM hoc b nh Flash), b nh d liu (RAM), mt hoc vi b nh thi v cc
cng vo/ra giao tip vi cc thit b ngoi vi v cc mi trng bn ngoi - tt
c cc khi ny c thit k trong mt vi mch tch hp. Vi iu khin khc vi
cc b vi x l a nng ch l n c th hot ng ch vi vi vi mch h tr bn
ngoi

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Ngoi kin trc von neumann cn c cu trc Harvard.cu trc harvard tch
ri b nh d liu v b nh chng trnh, nn tc x l cao hn, v dung lng
ca 2 ng truyn c th khc nhau.

Hnh 1.0 Cu trc AVR

Vi iu khin thng c dng xy dng cc h thng nhng. N xut

hin kh nhiu trong cc dng c in t, thit b in, my git, l vi sng, in
thoi, u c DVD, thit b a phng tin, dy chuyn t ng.

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Chng II: Cu trc phn cng

I)

Gii thiu chung v h avr

AVR l mt h vi iu khin do hng Atmel sn xut (Atmel cng l nh sn

xut dng vi iu khin 89C51 m c th bn tng nghe n). AVR l chip vi
iu khin 8 bits vi cu trc tp lnh n gin ha-RISC(Reduced Instruction Set
Computer), mt kiu cu trc ang th hin u th trong cc b x l.
1 s chip avr thng dng
AT 90S1200
AT90S2313
AT90S2323, AT90S2343
AT90S2333, AT90S4433
AT90S4414, AT90S8515
AT90S4434, AT90S8535
AT90C8534
ATtiny10, ATtiny11, ATtiny12
ATtiny15
ATtiny22
Ttiny26
ATtiny28
ATMEGA8
ATMEGA16
ATMEGA161
ATMEGA162
ATMEGA163
ATMEGA169
ATMEGA32
ATMEGA323
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ATMEGA103
ATMEGA64/128/2560/2561
AT85RF401
II)
ATMEGA32
AVR c cu trc Harvard, trong ng truyn cho b nh d liu (data
memory bus) v ng truyn cho b nh chng trnh (program memory bus)
c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit
b ngoi vi, vi register file. Trong khi program

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Memory bus c rng 16 bits v ch phc v cho instruction registers.

Hnh 1.1 s chn ATMEGA32

1) Tng quan
Nhng Tnh Nng Chnh Ca ATmega32:
Hiu xut cao ( high performance ), l loi vi iu khin AVR 8 bit cng sut
thp
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Cu trc lnh n gin, thi gian thc thi lnh nh nhau ( tht ra l Advanced
RISC

Architecture )

130 lnh thc thi trong vng 1 chu k chip

32 x 8 thanh ghi cng dng chung ( chc l 32 thanh ghi cng dng chung 8
bit )
y cc s l tnh
H tr 16 MIPS khi hot ng tn s 16 MHz
Tch hp b nhn 2 thc hin trong 2 chu k chip
B nh chng trnh v d liu khng bay hi ( nonvolatile )
16k byte trong h thng flash kh trnh c th np v xa 1,000 ln
Ty chn khi ng phn m vi cc bit nhn c lp trong h thng bng
cch vo chng trnh khi ng chip
512 byte EEPROM c th ghi v xa 100,000 ln
1k byte ram nh tnh trong ( internal SRAM )
Lp trnh kha cho phn mm bo mp
Tnh nng ngoi vi
2 b nh thi/b m ( timers/counters ) 8 bit vi cc ch m ring r
v kiu so snh
1 b nh thi/b m ( timer/counter ) 16 bit vi cc ch m ring r,
kiu so snh v kiu bt s kin
B m thi gian thc vi my giao ng ring r
4 knh bm xung PWM
8 knh ADC 10 bit
Byte nh hng 2 ng giao tip ni tip
Giao tip USART ni tip kh trnh
Giao tip SPI ni tip ch/t ( master/slave )
B nh thi kh trnh gim st xung nhp ca chip 1 cch ring r
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Tch hp b so snh tn hiu tng t
Giao tip JTAG
Cc tnh nng t bit ca vi iu khin
Ch bt ngun reset v pht hin Brown-out kh trnh
Tch hp mch dao ng RC bn trong
Cc ngt trong v ngoi
6 ch ngh : rnh ri,gim nhiu ADC, Tit kim nng lng, ngun thp,
Standby v Extended Standby
Vo/ra v cc gi d liu
32 chn vo ra kh trnh
40-pin PDIP and 44-lead TQFP
in p s dng:
5.5V dng vi atmega16L
4.5 5.5V dng vi atmega16
Tc xung nhp dng cho chip
0 8 MHz cho atmega16L
0 16 MHz cho atmega16
Atmega16 gm c 40 chn:
chn 1 n 8 : Cng nhp xut d liu song song B ( PORTB ) n c th c
s dng cc chc

nng c bit thay v nhp xut d liu

Chn 9 : RESET a chip v trng thi ban u

Chn 10 : VCC cp ngun nui cho vi iu khin
Chn 11,31 : GND 2 chn ny c ni vi nhau v ni t
Chn 12,13 : 2 chn XTAL2 v XTAL1 dng a xung nhp t bn ngoi
vo chip

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Chn 14 n 21 : Cng nhp xut d liu song song D ( PORTD ) n c th
c s dng cc chc nng c bit thay v nhp xut d liu
Chn 22 n 29 : Cng nhp xut d liu song song C ( PORTC ) n c th
c s dng cc chc nng c bit thay v nhp xut d liu
Chn 30 : AVCC cp in p so snh cho b ADC
Chn 32 : AREF in p so snh tn hiu vo ADC
Chn 33 n 40 : Cng vo ra d liu song song A ( PORTA ) ngoi ra n
cn c tch hp b chuyn i tn hiu tng t sang tn hiu s ADC ( analog to
digital converter
2) Cu trc chung h avr
CPU ca AVR c chc nng bo m s hot ng chnh xc ca cc chng
trnh. Do n phi c kh nng truy cp b nh, thc hin cc qu trnh tnh ton,
iu khin cc thit b ngoi vi v qun l ngt.
2.1.Cu trc tng qut
AVR s dng cu trc Harvard, tch ring b nh v cc bus cho chng trnh
v d liu. Cc lnh c thc hin ch trong mt chu k xung clock. B nh
chng trnh c lu trong b nh Flash.
2.2. ALU
ALU lm vic trc tip vi cc thanh ghi chc nng chung. Cc php ton
c thc hin trong mt chu k xung clock. Hot ng ca ALU c chia lm 3
loi: i s, logic v theo bit.
2.3. Thanh ghi trng thi
y l thanh ghi trng thi c 8 bit lu tr trng thi ca ALU sau cc php
tnh s hc v logic.

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Hnh 1.2 Thanh ghi trng thi SREG
C: Carry Flag ;c nh (Nu php ton c nh c s c thit lp)
Z: Zero Flag ;C zero (Nu kt qu php ton bng 0)
N: Negative Flag (Nu kt qu ca php ton l m)
V: Twos complement overflow indicator (C ny c thit lp khi trn s b
V, For signed tests (S=N XOR V) S: N
H: Half Carry Flag (c s dng trong mt s ton hng s c ch r sau)
T: Transfer bit used by BLD and BST instructions(c s dng lm ni
chung gian trong cc lnh BLD,BST).
I: Global Interrupt Enable/Disable Flag (y l bit cho php ton cc ngt.
Nu bit ny trng thi logic 0 th khng c mt ngt no c phc v.)
2.4. Cc thanh ghi chc nng chung

Hnh 1.3 Thanh ghi chc nng chung

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Tip ghanh ghi ( register file ) : Tip 32 thanh ghi a chc nng ( $0000 $001F )
c ni trn, ngoi chc nng l cc thanh ghi a chc nng, th cc
thanh ghi t R26 ti R31 tng i mt to thnh cc thanh ghi 16 bit X, Y, Z c
dng lm con tr tr ti b nh chng trnh v b nh d liu .Thanh ghi con tr
X, Y c th dng lm con tr tr ti b nh d liu, cn thanh ghi Z c th dng
lm con tr tr ti b nh chng trnh. Cc trnh bin dch C thng dng cc
thanh ghi con tr ny qun l Data stack ca chng trnh C.

Hnh 1.4 Chc nng con tr ca cc thanh ghi R26 R31

2.5. Con tr ngn xp (SP)
L mt thanh ghi 16 bit nhng cng c th c xem nh hai thanh ghi chc
nng c bit 8 bit. C a ch trong cc thanh ghi chc nng c bit l $3E (Trong
b nh RAM l $5E). C nhim v tr ti vng nh trong RAM cha ngn xp.

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Hnh 1.5 Thanh ghi con tr ngn xp

Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu
vo ngn xp trong khi con tr ngn xp gim hai v tr. V con tr ngn xp s
gim 1 khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn
xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2.
Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp
trc khi mt chng trnh con c gi hoc cc ngt c cho php phc v. V
gi tr ngn xp t nht cng phi ln hn hoc bng 60H (0x60) v 5FH tr li l
vng cc thanh ghi
3) Cu trc ngt ATMEGA16
3.1)khi nim v ngt
Ngt l mt c ch cho php thit b ngoi vi bo cho CPU bit v tnh trng
sn sng cho i d liu ca mnh.V d:Khi b truyn nhn UART nhn c mt
byte n s bo cho CPU bit thng qua c RXC,hc khi n truyn c mt byte
th c TX c thit lp
Khi c tn hiu bo ngt CPU s tm dng cng vic ng thc hin li v lu
v tr ang thc hin chng trnh (con tr PC) vo ngn xp sau tr ti vector
phuc v ngt v thc hin chng trnh phc v ngt ch ti khi gp lnh RETI
(return from interrup) th CPU li ly PC t ngn xp ra v tip tc thc hin
chng trnh m trc khi c ngt n ang thc hin. Trong trng hp m c
nhiu ngt yu cu cng mt lc th CPU s lu cc c bo ngt li v thc hin
ln lt cc ngt theo mc u tin .Trong khi ang thc hin ngt m xut hin ngt
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mi th s xy ra hai trng hp. Trng hp ngt ny c mc u tin cao hn th
n s c phc v. Cn n m c mc u tin thp hn th n s b b qua.
B nh ngn xp l vng bt k trong SRAM t a ch 0x60 tr ln. truy
nhp vo SRAM thng thng th ta dng con tr X,Y,Z v truy nhp vo
SRAM theo kiu ngn xp th ta dng con tr SP. Con tr ny l mt thanh ghi 16
bit v c truy nhp nh hai thanh ghi 8 bit chung c a ch :SPL :
0x3D/0x5D(IO/SRAM) v SPH:0x3E/0x5E.
Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu
vo ngn xp trong khi con tr ngn xp gim hai v tr.V con tr ngn xp s gim
1 khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s
tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh
vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp
trc khi mt chng trnh con c gi hoc cc ngt c cho php phc v. V
gi tr ngn xp t nht cng phi ln hn 60H (0x60) v 5FH tr li l vng cc
thanh ghi
3.2 Trnh phc v ngt
i vi mi ngt th phi c mt trnh phc v ngt ISR (Interrupt Service
Routine)
hay trnh qun l ngt (Interrupt handler). Khi mt ngt c gi th b vi iu
khin phc v ngt. Khi mt ngt c gi th b vi iu khin chy trnh phc v
ngt. i vi mi ngt th c mt v tr c nh trong b nh gi a ch ISR ca
n. Nhm cc v tr nh c dnh ring gi cc a ch ca cc ISR c gi l
bng vc t ngt.
Khi kch hot mt ngt b vi iu khin i qua cc bc sau:
Vi iu khin kt thc lnh ang thc hin v lu a ch ca lnh k tip (PC)
vo ngn xp.
N nhy n mt v tr c nh trong b nh c gi l bng vc t ngt ni
lu gi a ch ca mt trnh phc v ngt.
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B vi iu khin nhn a ch ISR t bng vc t ngt v nhy ti . N bt
u thc hin trnh phc v ngt cho n lnh cui cng ca ISR l RETI (tr v t
ngt).
Khi thc hin lnh RETI b vi iu khin quay tr v ni n b ngt.
Trc ht n nhn a ch ca b m chng trnh PC t ngn xp bng cch ko
hai byte trn nh ca ngn xp vo PC. Sau bt u thc hin cc lnh t a ch
.
4 .Cu trc b nh
4.1 b nh chng trnh (flash)

Hnh 1.6 b nh chng trnh

L b nh Flash lp trnh c, trong cc chip AVR c (nh AT90S1200 hay
AT90S2313) b nh chng trnh ch gm 1 phn l Application Flash Section
nhng trong cc chip AVR mi chng ta c thm phn Boot Flash setion. Boot
section s c kho st trong cc phn sau, trong bi ny khi ni v b nh chng
trnh, chng ta t hiu l Application section. Thc cht, application section bao
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gm 2 phn: phn cha cc instruction (m lnh cho hot ng ca chip) v phn
cha cc vector ngt (interrupt vectors). Cc vector ngt nm phn u ca
application section (t a ch 0x0000) v di n bao nhiu ty thuc vo loi chip.
Phn cha instruction nm lin sau , chng trnh vit cho chip phi c load
vo phn ny
4.2 b nh d liu sram
1120 nh ca b nh d liu nh a ch cho file thanh ghi, b nh I/O v
b nh d liu SRAM ni. Trong 96 nh u tin nh a ch cho file thanh
ghi v b nh I/O, v 1024 nh tip theo nh a ch cho b nh SRAM ni

Hnh 1.7 b nh d liu sram

y l phn cha cc thanh ghi quan trng nht ca chip, vic lp trnh cho
chip phn ln l truy cp b nh ny. B nh d liu trn cc chip AVR c ln
khc nhau ty theo mi chip, tuy nhin v c bn phn b nh ny c chia thnh
Phn 1: l phn u tin trong b nh d liu, nh m t trong hnh 1,
phn ny bao gm 32 thanh ghi c tn gi l register file (RF), hay General Purpose
Rgegister GPR, hoc n gin l cc Thanh ghi. Tt c cc thanh ghi ny u l
cc thanh ghi 8 bits nh trong hnh 1.7.
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Hnh 1.8 thanh ghi 8 bit

Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c
a ch tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t
0 n 255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no
Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia
thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh
ghi R16 n R31. Cc thanh ghi ny c cc c im sau:
c truy cp trc tip trong cc instruction.Cc ton t, php ton thc hin
trn cc thanh ghi ny ch cn 1 chu k xung clock.
Register File c kt ni trc tip vi b x l trung tm CPU ca
chip.Chng l ngun cha cc s hng trong cc php ton v cng l ch cha kt
qu tr li ca php ton.
Phn 2: l phn nm ngay sau
register file, phn ny bao gm 64 thanh ghi c gi l 64 thanh ghi
nhp/xut (64 I/O register) hay cn gi l vng nh I/O (I/O Memory). Vng nh
I/O l ca ng giao tip gia CPU v thit b ngoi vi. Tt c cc thanh ghi iu
khin, trng thica thit b ngoi vi u nm y. Xem li v d trong bi 1,
trong ti c cp v vic iu khin cc PORT ca AVR, mi PORT lin quan
n 3 thanh ghi DDRx, PORTx v PINx, tt c 3 thanh ghi ny u nm trong vng
nh I/O. Xa hn, nu mun truy xut cc thit b ngoi vi khc nh Timer, chuyn
i Analog/Digital, giao tip USARTu thc hin thng qua vic iu khin cc
thanh ghi trong vng nh ny.
Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi
I/O. Nu s dng instruction truy xut SRAM truy xut vng nh ny th a ch

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ca chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi
I/O th a ch ca chng c tnh t 0x0000 n 0x003F.
Phn 3: RAM tnh, ni (internal SRAM), l vng khng gian cho
cha cc bin (tm thi hoc ton cc) trong lc thc thi chng trnh, vng ny
tng t cc thanh RAM trong my tnh nhng c dung lng kh nh (khong vi
KB, ty thuc vo loi chip).
Phn 4: RAM ngoi (external SRAM), cc chip AVR cho php ngi
s dng gn thm cc b nh ngoi cha bin, vng ny thc cht ch tn ti khi
no ngi s dng gn thm b nh ngoi vo chip.

4.3) b nh d liu eeprom

L mt phn quan trng ca cc chip AVR mi, v l ROM nn b
nh ny khng b xa ngay c khi khng cung cp ngun nui cho chip, rt thch
hp cho cc ng dng lu tr d liu

Hnh 1.9 B nh d liu eeprom

Atmega 16 cha b nh d liu EEPROM dung lng 512 byte, v c sp
xp theo tng byte, cho php cc thao tc c/ghi tng byte mt. y l b nh d
liu c th ghi xa ngay trong lc vi iu khin ang hot ng v khng b mt d
liu khi ngun in cung cp b ct. C th v b nh d liu EEPROM ging nh
l cng ( Hard disk ) ca my vi tnh. EEPROM c xem nh l mt b nh vo
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ra c nh a ch c lp vi SRAM, iu ny c ngha l ta cn s dng cc
lnh in, out khi mun truy xut ti EEPROM. iu khin vo ra d liu vi
EEPROM ta s dng 3 thanh ghi sau
-Thanh Ghi EEAR ( EEARH v EEARL )
-Thanh Ghi EEDR
-Thanh Ghi EECR
4.3.1 ghi d liu vo
1. Ch cho bit EEWE v 0.
2. Cm tt c cc ngt.
3. Ghi a ch vo thanh ghi EEAR.
4. Ghi d liu m ta cn ghi vo EEPROM vo thanh ghi EEDR.
5. Set bit EEMWE thnh 1.
6. Set bit EEWE thnh 1 .
7. Cho php cc ngt tr li.
Nu mt ngt xy ra gia bc 5 v 6 s lm hng qu trnh ghi vo EEPROM
bi
v bit EEMWE sau khi set ln 1 ch c gi trong 4 chu k my, chng trnh
ngt s lm ht thi gian ( time out ) duy tr bit ny mc 1. Mt ngt xut hin
cui bc 4 cng c th lm cho a ch v d liu cn ghi vo EEPROM tr nn
khng chnh xc nu trong chng trnh phc v ngt c chnh sa li cc thanh ghi
EEAR v EEDR. l l do ta cn cm cc ngt trc khi thc hin tip cc bc
3, 4, 5, 6.
Qu trnh ghi d liu vo EEPROM cng c th khng an ton nu in th
ngun
nui ( Vcc ) qu thp
4.3.2 c d liu t EEPROM:
Vic c d liu t EEPROM n gin hn ghi d liu vo EEPROM, c
d liu t EEPROM ta thc hin cc bc sau:
1. Ch cho bit EEWE v 0.
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2. Ghi a ch vo thanh ghi EEAR.
3. Set bit EERE ln 1.

5 .Cc cng vo ra (I/O)

Vi iu khinATmega16c 32 ng vo ra chia lm bn nhm 8 bit mt. Cc
ng vo ra ny c rt nhiu tnh nng v c th lp trnh c. y ta s xt
chng l cc cng vo ra s. Nu xt trn mt ny th cc cng vo ra ny l cng
vo ra hai chiu c th nh hng theo tng bit. V cha c in tr pull-up (c th
lp trnh c). Mc d mi port c cc c im ring nhng khi xt chng l cc
cng vo ra s th dng nh iu khin vo ra d liu th hon ton nh nhau.
Chng ta c thanh ghi v mt a ch cng i vi mi cng, l : thanh ghi d
liu cng (PORTA, PORTB, PORTC, PORTD), thanh ghi d liu iu khin cng
(DDRA, DDRB, DDRC, DDRD) v cui cng l a ch chn vo ca cng (PINA,
PINB, PINC, PIND)
5.1 Thanh ghi DDRx
y l thanh ghi 8 bit (ta c th c v ghi cc bit thanh ghi ny) v c tc
dng iu khin hng cng PORTx (tc l cng ra hay cng vo). Nu nh mt bit
trong thanh ghi ny c set th bit tng ng trn PORTx c nh ngha nh
mt cng ra. Ngc li nu nh bit khng c set th bit tng ng trn PORTx
c nh ngha l cng vo.
5.2.Thanh ghi PORTx
y cng l thanh ghi 8 bit (cc bit c th c v ghi c) n l thanh ghi d
liu ca cng Px v trong trng hp nu cng c nh ngha l cng ra th khi ta
ghi mt bit ln thanh ghi ny th chn tng ng trn port cng c cng mc
logic. Trong trng hp m cng c nh ngha l cng vo th thanh ghi ny li
mang d liu iu khin cng. C th nu bit no ca thanh ghi ny c set
(a ln mc 1) th in tr ko ln (pull-up) ca chn tng ng ca port s
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c kch hot. Ngc li n s trng thi hi-Z. Thanh ghi ny sau khi khi ng
Vi iu khins c gi tr l 0x00.
5.3 Thanh ghi PINx
y l thanh ghi 8 bit cha d liu vo ca PORTx (trong trng hp PORTx
c thit lp l cng vo) v n ch c th c m khng th ghi vo c.
Tm li:
1. c d liu t ngoi th ta phi thc hin cc bc sau:
a d liu ra thanh ghi iu khin DDRxn t cho PORTx (hoc bit n
trong port) l u vo (xa thanh ghi DDRx hoc bit).
Sau kch hot in tr pull-up bng cch set thanh ghi PORTx ( bit).
Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit).
2. a d liu t vi iu khin ra cc cng cng c cc bc hon ton
tng t. Ban u ta cng phi nh ngha l cng ra bng cch set bit tng ng
ca cng .v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx
5.4 M t thanh ghi ca port I/O
Port A Data Register PORTA

Port A Data Direction Register DDRA

Port A Input Pins Address PINA

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The Port B Data Register PORTB

The Port B Data Direction Register DDRB

The Port B Input Pins Address PINB

The Port C Data Register PORTC

The Port C Data Direction Register DDRC

The Port C Input Pins Address PINC

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The Port D Data Register PORTD

The Port D Data Direction Register DDRD

The Port D Input Pins Address PIND

Hnh 1.10 thanh ghi port I/O

6. B nh thi 8bit timer/counter 0
B nh thi (timer/counter0) l mt module nh thi/m 8 bit, c cc c
im sau:
B m mt knh
Xa b nh thi khi trong mode so snh (t ng np)
PWM
To tn s
B m s kin ngoi
B chia tn 10 bit
Ngun ngt trn b m v so snh

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6 .1 hot ng ca b timer/couter
Mch m ln lm thanh ghi TCNTn tng 1 n v mi khi c xung clkTn, khi
t gi tr ln nht (8bit=255), c TOVn c set (logic 1) v b m trn, gi tr b
n TCNTn tr v 00 v tip tc m.
Xung clkTn c th c la chn t nhiu ngun khc nhau. Khi chn xung
ni (system clock), Timer/Counter l mt Timer. Khi chn xung ngoi (thng qua
chn Tn) Timer/Counter l Counter.
Hot ng ny c th din t bng gin xung sau:

Hnh 1.11 Hot ng b timer/couter

Cng ging nh b timer/counter trong cc vi iu khin khc, chng ta quan
tm n 2 thanh ghi: Timer/Counter Control v Timer/Counter Value. Trong AVR,
l thanh ghi TCCRn v TCNTn.

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Clock Select Bit Description

TCNT0 - Timer/C
TCNT0 v OCR0 l cc thanh ghi 8 bit. Cc tn hiu yu cu ngt u nm
trong thanh ghi TIFR. Cc ngt c th c che bi thanh ghi TIMSK.
B nh thi c th s dng xung clock ni thng qua b chia hoc xung clock
ngoi trn chn T0. Khi chn xung clock iu khin vic b nh thi/b m s
dng ngun xung no tng gi tr ca n. Ng ra ca khi chn xung clock c
xem l xung clock ca b nh thi (clkT0).
Thanh ghi OCR0 lun c so snh vi gi tr ca b nh thi/b m. Kt
qu so snh c th c s dng to ra PWM hoc bin i tn s ng ra ti chn
OC0.
6.2 n v m
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Phn chnh ca b nh thi 8 bit l mt n v m song hng c th lp
trnh c. Cu trc ca n nh hnh di y:

Hnh 1.12. n v m
count: tng hay gim TCNT0 1
direction: la chn gia m ln v m xung
clear: xa thanh ghi TCNT0
clkT0: xung clock ca b nh thi
TOP: bo hiu b nh thi tng n gi tr ln nht
BOTTOM: bo hiu b nh thi gim n gi tr nh nht (0)
6.3 n v so snh ng ra

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Hnh 1.13. S n v so snh ng ra

B so snh 8 bit lin tc so snh gi tr TCNT0 vi gi tr trong thanh ghi so
snh ng ra (OCR0). Khi gi tr TCNT0 bng vi OCR0, b so snh s to mt bo
hiu. Bo hiu ny s t gi tr c so snh ng ra (OCF0) ln 1 vo chu k xung
clock tip theo. Nu c kch hot (OCIE0=1), c OCF0 s to ra mt ngt so snh
ng ra v s t ng c xa khi ngt c thc thi. C OCF0 cng c th c
xa bng phn mm.
6.4 M t cc thanh ghi
6.4.1 Thanh ghi iu khin b nh thi/b m TCCR0

Hnh 1.14. Thanh ghi iu khin b nh thi

Bit 7-FOC0: So snh ng ra bt buc

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Bit ny ch tch cc khi bit WGM00 ch nh ch lm vic khng c PWM.
Khi t bit ny ln 1, mt bo hiu so snh bt buc xut hin ti n v to dng
sng.
Bit 6, 3-WGM01:0: Ch to dng sng
Cc bit ny iu khin m th t ca b m, ngun cho gi tr ln nht ca
b m (TOP) v kiu to dng sng s c s dng.
Bit 5:4-COM01:0: Ch bo hiu so snh ng ra
Cc bit ny iu khin hot ng ca chn OC0. Nu mt hoc c hai bit
COM01:0 c t ln 1, ng ra OC0 s hot ng.
Bit 2:0: CS02:0: Chn xung ng h
Ba bit ny dng la chn ngun xung cho b nh thi/b m.

6.4.2 Thanh ghi b nh thi/b m

Hnh 1.15. Thanh ghi b nh thi

Thanh ghi b nh thi/b m cho php truy cp trc tip (c c v ghi) vo
b m 8 bit.
Thanh ghi ny cha mt gi tr 8 bit v lin tc c so snh vi gi tr ca b
m.
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6.4.3 Thanh ghi mt n ngt

Hnh 1.16. Thanh ghi mt n ngt TIMSK

. Bit 1-OCIE0: Cho php ngt bo hiu so snh
Bit 0-TOIE0: Cho php ngt trn b m
6.4.4 Thanh ghi c ngt b nh thi

Bit 1-OCF0: C so snh ng ra 0

Bit 0-TOV0: C trn b m
Bit TOV0 c t ln 1 khi b m b trn v c xa bi phn cng khi
vector ngt tng ng c thc hin. Bit ny cng c th c xa bng phn
mm.

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7. B nh thi/m timer/counter 1 16-bit
7.1 s khi v mt s c im

Hnh 1.17 s khi b nh thi/m timer/counter 1 16-bit

True 16-bit Design (i.e., allows 16-bit PWM)
- 2 n v ng vo so snh c lp(Two Independent Output Compare Units)
- i thanh ghi so snh ng ra m(Double Buffered Output Compare
Registers)
- 1 n v cht ng vo(One Input Capture Unit)
- B chng nhiu li vo(Input Capture Noise Canceler)
- Xa timer trong Compare Match (Clear Timer on Compare Match (Auto
Reload))
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- chng nhiu sc ngang(Glitch-free, Phase Correct Pulse Width Modulator
(PWM)
- Gi tr chu k PWM
- B pht tn s chung
-B m s kin ngoi
- 4 ngun ngt c lp (TOV1, OCF1A, OCF1B, and ICF1)
7.2 Mt s nh ngha
BOTTOM B m t ti BOTTOM khi co gi tr 0x0000
MAX B m t ti MAXimum khi khi t gi tr 0xFFFF (decimal 65535).
TOP B m t ti TOP khi n bng vi gi tr ln nht ca chui m. Gi
tr ny c th c gn bi cc gi tr c nh : 0x00FF, 0x01FF, or 0x03FF,hoc
gi tr trong b nh ca cc thanh ghi OCR1A ,ICR1 .
7.3 M t cc thanh ghi
7.3.1 Timer/Counter 1 Control Register A TCCR1A

Initial Value

0
Bit 7:6 COM1A1:0: Compare Output Mode for channel A
Bit 5:4 COM1B1:0: Compare Output Mode for channel B
COM1A1: 0 v COM1B1: 0 iu khin chn so snh trng thi ng ra (OC1A
v OC1B tng ng). Nu mt hay c hai bit COM1A1:0 c set ln 1 th ng ra
OC1A s u tin hn chc nng port I/O thng thng m n kt ni ti . Nu mt
hay c hai bit COM1B1:0 c set ln 1 th ng ra OC1B s u tin hn chc nng
port I/O thng thng m n kt ni ti . Tuy nhin ch l bit ca thanh ghi DDR
tng ng vi cc chn OC1A, OC1B, OC1C phi c set cho php ng ra.
Khi OC1A, OC1B, OC1C c kt ni ti chn th tc dng ca cc bit COM1X1:0
cn ph thuc vo la chn ca cc bit WGM3:0. Nh bng sau th hin chc nng
khi cc bit WGM13:0 l set bnh thng.
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Table 37 hin th chc nng ca bit COM1x1:0 khi cc bit WGM13:0 l set
ch PWM nhanh.

Bit 3 FOC1A: Force Output Compare for channel A

Bit 2 FOC1B: Force Output Compare for channel B
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Cc bit FOC1A/FOC1B ch hot ng khi cc bit c bit WGM13:0 khng
ch PWM.
.khi bit FOC1A/FOC1B c gi tr l 1,ngay lp tc Compare Match(Compare
Match :y l mt chc nng ca b nh thi, theo , gi tr ca b nh thi (tc
gi tr thanh ghi TCNTn (n=0,..,2)) lin tc c so snh snh vi gi tr ca thanh
ghi OCRn (n=0,..,2). Khi hai gi tr ny bng nhau s to ra s thay i mc logic
chn OCn (n=0,..,2). Nh , ta c th to ra xung PWM ng ra OCn (n=0,..,2)
ca vi iu khin.) b buc vo dng sng n v chung (waveform generation
unit). Ng ra OC1A/OC1B b thay i cho ph hp vi iu chnh cc bit
COM1x1:0.Cc bit FOC1A/FOC1Blun trng thi 0.
Bit 1:0 WGM11:0: Waveform Generation Mode
S kt hp vi cc bit WGM13:2 tm thy trong thanh ghi TCCR1B,nhng
bit ny iu khin dy m ca b m, gc gi tr ln nht (TOP) ca b m, v
nhng loi sng chung c s dng , nhn bng Table 39. Cc ch ca h thng
c h tr boier Timer/Counter l : Normal mode (counter), Clear Timer on
Compare Match (CTC) mode,v ba loi ca cc ch Pulse Width Modulation
(PWM).

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7.3.2 Timer/Counter 1 Control Register B TCCR1B

Bit 7 ICNC1: Input Capture Noise Canceler

iu chnh bit ny ln 1 kch hot Input Capture Noise Canceler. Khi noise
canceler hot ng, ng vo t chn Input Capture Pin (ICP1) c lc. Yu cu
chc nng ca b 4 gi tr k bng vi chn ca ICP1 cho s thay i ca ng ra.
Bit 6 ICES1: Input Capture Edge Select
Bit ny c chn sao cho cnh ln trong Input Capture Pin (ICP1) dng
khi ng bt gi s kin. Khi bit ICES1 set l 0, cnh xung c dng , v khibit
ICES1 set l 1, cnh ln s khi ng bt gi. Khi vic bt gi c kch hot
theo iu chnh ca ICES1 ,gi tr b m sao chp vo
Input Capture Register (ICR1). S kin cng s set c Input Capture Flag
(ICF1), v iu ny c th dng v mt Input Capture Interrupt,nu ngt ny
c kch hot. Khi ICR1 c dng vi gi tr TOP (see description of the
WGM13:0 bits located in the TCCR1A and the TCCR1B Register), ICP1 b ngt
kt ni v gi nguyn chc nng Input Capture l disable.
Bit 5 Reserved Bit
Bit ny dng trong tng lai.
Bit 4:3 WGM13:2: Waveform Generation Mode
Tng t thanh ghi TCCR1A.
Bit 2:0 CS12:0: Clock Select
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Ba bit la chn xung nhp la chn xung ngun c dng bi Timer/Counter

7.3.3 Timer/Counter 1 TCNT1H and TCNT1L

Thanh ghi b nh thi TCNT1 l thanh ghi 16 bit c kt hp t hai thanh

ghi
TCNT1H v thanh ghi TCNT1L. Thanh ghi TCNT1 c th c hay ghi. c
2 byte ca TCNT 1 c c hay ghi ng thi ngi ta dng mt thanh ghi tm 8
bit byte cao 8-bit Temporary High Byte Register (TEMP). Thanh ghi TEMP c
chia s cho tt c cc thanh ghi 16 bit khc. Khng nn chnh sa thanh ghi TCNT1
khi n ang m trnh b hng Compare Match gia TCNT1 v mt trong nhng
thanh ghi OCR1X .

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7.3.4 Output Compare Register 1 A OCR1AH and OCR1AL

7.3.5 Output Compare Register 1 B OCR1BH and OCR1BL

Thanh ghi output compare register (OCR1A/OCR1B) l thanh ghi 16 bit,

gi tr ca n c lin tc so snh vi b m (TCNT1). Khi c s bng nhau
ca hai thanh ghi ny s to ra mt ngt so snh hay mt dng sng chn ng ra so
snh OC1X. Ng ra cua thanh ghi so snh co c l 16 bit. nn c hai byte cao v
thp ca thanh ghi c ghi hay c ng thi khi CPU cn truy xut thanh ghi ny,
ngi ta dng thanh ghi tm byte cao (TEMP), thanh ghi TEMP lun lu gi byte
cao ca cc thanh ghi 16 bit khi cc thanh ghi ny cn dng ti n
Ch l khi ghi mt gi tr vo thanh ghi OCR1X trong lc b m ang
chy, th gi tr ca thanh ghi OCR1X c th cp nht tc thi, nhng cng c th
ch c cp nht khi b m t ti mt gi tr no , chn hn, gi tr TOP,
BOTTOM
7.3.6 Input Capture Register 1 ICR1H and ICR1L

Tng t nh trn! Cc bn c th tham khao k hn trong datasheet.

7.3.7 Timer/Counter Interrupt Mask Register TIMSK

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Bit 5 TICIE1: Timer/Counter1, Input Capture Interrupt Enable

Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php
th ngt bt mu ng vo b Timer/couter1 (Timer/Counter1 Input Capture
interrupt) c cho php. Vector ngt tng ng s c thc thi khi c ICF1 trong
thanh ghi TIFR c set..
Bit 4 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt
Enable
Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php
th ngt so snh ng ra 1A (Timer/Counter1 Output Compare A Match Interrupt)
c cho php. Vector ngt tng ng s c thc thi khi c OCF1A trong thanh
ghi TIFR c set.
Bit 3 OCIE1B: Timer/Counter1, Output Compare B Match Interrupt
Enable
Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php
th ngt so snh ng ra 1B (Timer/Counter1 Output Compare B Match Interrupt)
c cho php. Vector ngt tng ng s c thc thi khi c OCF1B trong thanh
ghi TIFR c set.
Bit 2 TOIE1: Timer/Counter1, Overflow Interrupt Enable
Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php
th ngt c trn b nh thi 1 (Timer/Counter1 overflow interrupt) c cho php.
Vector ngt tng ng s c thc thi khi c TOV1 trong thanh ghi TIFR c
set.

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7.3.8 Timer/Counter Interrupt Flag Register TIFR

Bit 5 ICF1: Timer/Counter1, Input Capture Flag

C ny c set khi xy ra s kin bt mu ng vo (Input Capture) ca chn
ICP1. Khi thanh ghi ICR1 (Input Capture Register) c thit lp bi cc bit
WGMn3:0 s dng nh mt gi tr TOP th c ICF1 s c set khi b m t
ti gi tr TOP. C ICF1 s t ng xa khi ngt tng ng c thc thi, hoc c
th xa hay set bng cch ghi mt gi tr logic vo v tr ca n.
Bit 4 OCF1A: Timer/Counter1, Output Compare A Match Flag
C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh
ghi OCR1A (Output Compare Register A). Ch l mt so snh cng bc
(FOC1A) s khng set c ny. C OCF1A s t ng xa khi ngt tng ng c
thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n.
Bit 3 OCF1B: Timer/Counter1, Output Compare B Match Flag
C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh
ghi OCR1B (Output Compare Register B). Ch l mt so snh cng bc
(FOC1B) s khng set c ny. C OCF1B s t ng xa khi ngt tng ng c
thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n.
Bit 2 TOV1: Timer/Counter1, Overflow Flag
Vic thit lp c ny ph thuc vo thit lp ca cc bit WGMn3:0, trong ch
bnh thng v CTC c TOV1 c set khi b nh thi trn

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8. SPI(Serial peripheral interface)
8.1 S v nh ngha
SPI l mt giao din thc hin vic trao i d liu gia cc thit b tng
thch vi khung d liu 8bit v c truyn ng b(cng xung nhp ng h).
SPI cho php truyn d liu ni tip ng b gia thit b ngoi vi v vi iu khin
AVR hoc gia cc vi iu khin AVR. SPI ca AT90S8535 c cc c im c
bit sau:
Ch song cng, truyn d liu ng b 3 dy.
C th gi vai tr Master hoc Slave.
Bit MSB hoc LSB c th c truyn trc ty vo ngi lp trnh.
Bn tc truyn c th lp trnh thng qua hai bit
C ngt bo kt thc truyn
Vn hnh t trng thi ng (c nh thc t trng thi ng).
S cu trc:

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hnh 1.18 SPI(Serial peripheral interface)

iu khin khi giao tip SPI th chng ta c 3 thanh ghi. l 1 thanh ghi
iu khin SPCR (SPI control Register), thanh ghi trang thi SPSR (SPI status
Register) v cui cng l thanh ghi d liu SPDR (SPI Data Register).
8.2 M t thanh ghi
8.2. 1.Thanh ghi SPCR:
y l thanh ghi 8 bit c a ch trong cc thanh I/O l 0x0D v trong SRAM
l 0x2D, cc bit trong thanh ghi ny u c th c hoc ghi.
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Bit 7-SPIE: SPI interrupt enable
Bit ny cho php ngt ca b truyn tin SPI (nu ngt ton cc v ngt ny
c cho php th nu c SPIF c bt th ngt s c phc v.)
Bit 6-SPE: SPI Enable
Nu bit ny c set th khi SPI s c hot ng v n phi c set trong
sut qu trnh SPI hot ng.
Bit 5-DORD: Data order
Khi m DORD c set th LSB ca byte d liu s c truyn trc v
ngc li.
Bit 4-MSTR: Master/Slave select
y l bit dng la chn ch master hay slave.Nu bit ny c set th
b SPI ny c vai tr l Master v ngc li.Nu nh SS c cu hnh l li vo v
c t xung mc thp th MSTR b xa v 0v SPIF v SPSR b t ln 1 khi
ta s phi t li MSTR v 1.
Bit 3-CPOL: Clock polarity
Khi bit ny c set th SCK mc cao trong trang thi ng v ngc lai.
Bit 2-CPHA:Clock Phase
Quy nh pha kch hot ca xung nhip.
Bit 1,0-SPR1,SPR0 :Clock rate select:
y l hai bit iu khin tc xung nhp truyn ca kt ni v c thit lp
trn Master. N khng c tc dng g nu nh ta thit lp trn slave.
V gi tr ca chng ng theo t hp cc bit nh sau:
S
PR1

S
PR0

T
n

SCK
0

F
cl/4
F
cl/16

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1

F
cl/64

F
cl/128

Nh vy y l thanh ghi iu khin ton b khi SPI t vai tr (Master/slave

n tc truyn,cho php ngt,cho php hot ng,mc logic trong trang thi ng
v pha kch hot xung nhp.
8.2.2.Thanh ghi SPSR:
y l thanh ghi 8 bit (c a ch 0x0e/0x2e)lu gi trng thi ca b truyn
nhn SPI.Nhng n ch c hai bt c nh ngha c kh nng c v ghi.Cc bit
cn li khng c nh ngha v khi c chng th c gi tr zero.
Bit 7-SPIF: SPI interrupt Flag
Khi truyn xong mt byte d liu th bit ny c set v mt ngt c to
ra.Nu bit cho php ngt SPIE trong thanh ghi SPCR c set v ngt ton cc
c cho php th ngt c thi hnh.Nu khng n s b b qua.Khi m chn ss
ca Master c nh ngha l cng vo li c thit lp mc thp th c ny cng
c set.N c xa bi phn cng hi ngt c phc v.
Bit 6-WCOL: wite collision flag
C bo xung t khi ghi:C ny c set ln 1 nu nh d liu c ghi ln
thanh ghi d liu SPI khi ang din ra mt cuc truyn.V n c xa cng vi c
SPIF khi c thanh ghi trng thi v truy nhp vo thanh ghi d liu.

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bt u mt cuc truyn th ta cn cho php b truyn nhn hot ng.Khi
truyn ta ch cn ghi byte d liu cn truyn ln thanh ghi d liu v i cho ti khi c c
SPIF bt ln ri tip tc truyn byte mi.
bt u nhn d liu cng vy.SPI c khi ng,ch khi no c SPIF bt ln th
ta c d liu (c t xa khi ta c thanh ghi trng thi).
8.2.3.Thanh ghi SPDR:
y cng l thanh ghi 8 bit (0x0f/0x2f) c th c v ghi c.N c s dng
truyn d liu gia hai bn truyn nhn SPI.Ghi d liu vo thanh ghi ny c ngha l ta
bt u cuc truyn.V c d liu t thanh ghi ny l c d liu c nhn.
8.2.4.Nguyn l hot ng:

1
y l s ghp ni gia hai b SPI song cng (nh ca 2 vi iu khin AVR).
i vi VK AVR th cc chn SCK (Serial clock) l chn PB7,y l chn xung
nhp ra trong trng hp n l Master v l chn xung nhp vo nu n l Slave.khi
ghi d liu ln thanh ghi d liu SPDR ca khi Master s khi ng b to xung v
d liu c dch v a ra chn MOSI (PB5) v vo chn MOSI ca slave (PB5
i vi AVR).Sau khi dch ht mt byte b to xung ngng hot ng,v c SPIF
c pht bo kt thc truyn.Nu nh ngt ny c php th chng trnh phc
vu ngt s c phc v v khi c s b xa.u vo la chn slave (SS v l
chn PB4) c set mc tch cc thp la chn thit b SPI slave v c dng
cho vic ghp ni nhiu VK.Hai thanh ghi dch ca hai b truyn v nhn (Master
v slave) c xem nh l mt thanh ghi dch vng 16 bit.V trong mt ln trao i
d liu th d liu thanh ghi ca Master v slave trao i cho nhau.Mt
bSIP lm ng thi c hai nhim v truyn v nhn nhng chng li ch c mt
b m khi truyn c hai b m khi nhn.Nh vy c ngha l d liu truyn i
s khng c ghi ln thanh ghi d liu truyn nu nh byte trc cha c
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truyn xong (hay c SPIF cha c bt).V khi nhn d liu cng vy d liu cn
phi c c trc khi d liu mi c nhn xong.
Bng cu hnh chn:

9.B so snh tng t(Alalog Comparator)

B so snh tng t ca AVR c u vo l hai chn PB2 v PB3 (nh hnh
v). Vi chn PB2 c ni vo cc dng ca b so snh v PB3 c ni vo
cc m ca b so snh.N to ra hai mc logic nu V+>V- th tn hiu ra l 1 v
ngc li l 0.

Hnh 1.19 B so snh tng t(Alalog Comparator)

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iu khin v qua st trng thi ca b so snh tng t ta c mt thanh ghi
l thanh ghi ACSR.Trc khi tm hiu v nguyn tc hot ng ca n ta s gii
thiu v thanh ghi ny.
Thanh ghi ACSR l mt thanh ghi 8 bit c a ch trong cc thanh ghi I/O l
0x08 v c a ch trong khng gian b nh SRAM l 0x28.Trong 8 bit th c 7 bit
c nh ngha v bit 6 khng c nh ngha.N ch c th c v lun c gi tr
logic l 0.
1.Bit 7-ACD:Analog comparator disable y l bit iu khin.
Bit ny ttrc tip iu khin hot ng ca AC(b so snh tng t). Nu nh bit
ny c set ln 1 th ngun cung cp cho AC hot ng b tt (turn off) v ng
ngha vi vic n khng hot ng.V nu n c xa th AC c cp ngun v
hot ng bnh thng.Ch :Ta c th thay i gi tr logic ca bit ny lc no
cng c ngng hot ng ca chng hoc cho chng hot ng tr li nhng
khi thay i gha tr logic ca n th ngt (ngt ca AC)cn b cm nu khng n s
sinh ra mt ngt (C th l bit ACIE cn b xa).
2.Bit 5-ACO:Analog comparator output y l bit trng thi.
Bit ny c ni trc tip vi u ra ca b so snh tng t.
3.Bit 4-ACI:Analog comparator interrupt flag y l bit trng thi.
C bo ngt ca b so sanh tng t.Nu nh c ny c set v cc ngt c
php th mt chng trnh phc v ngt c gi v chng c xa bng phn
cng khi chng trinh bo ngt c phc v. Cc trng hp lm thay i trng
thi c ny ngoi vic thay i bit ACD s c ni ti trong cc bt o v 1.
4.Bit 3-ACIE:AC interrupt enable y l bit iu khin.
Nu bit ny c set th ngt ny c php v ngc li.
5.Bit 2ACIC:Analog comparator input Capture Enable y l bit iu khin.
Khi bit ny c set ln 1 th u ra ca AC c ni trc tip vo u vo ca
chc nng bt s kin ca Timer/counter 1.( c thm timer/counter1).
6.Bit ACIS1 v ACIS0 :Ac interrupt mode select y l hai bit iu khin.

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A
CIS1

Ch ngt

0
1

Theo mc
Dnh ring(cha

CIS0
0
0
1
1

dng n)
Sn xung
Sn ln

0
1

Ch : Cc bit ny cng c th c thay i bt c khi no. Nhng khi thay

i th ngt ca n phi b cm.
Ta c th s dng lnh SBI hoc CBIU thay i trng thi cc bit trn thanh
ghi ny tr bit ACI. Bit ny sau khi c c cng s b xa (nu n c set).
Thit lp port u vo cho b so snh tng t:
Hai chn PB2 v PB3 ny cn c thit lp l u vo b in tr treo.
lp trnh cho AC ta bt u cc bc sau:
Bc 1: Thit lp cc chn u vo cho AC.
Bc 2: Chn cc ch cho AC v nh dng ngt
Bc 3: Khi ng AC bng cch xa bit ACD.
.10. h thng xung clock
cu hnh cho chip hot ng theo ch xung clock no, ngi ta dng cc
bit cu ch ( fuse bit ) CKSEL 3, CKSEL2, CKSEL 1. Ngoi ra khi vi iu khin
c nh thc t cc ch ngh sang ch hot ng bnh thng, b to dao
ng cn c mt khong thi gian n nh, khong thi gian ny gi l thi gian
khi ng ( start-up time ). CPU ch thc hin lnh khi ht khong thi gian khi
ng ny. Khi ta reset CPU cng cn mt khong thi gian tr hon (delay time )
ngun nui t mc n nh trc khi thc bt u thc thi lnh. Ngi ta dng cc
bit cu ch CKSEL 0, SUT1, SUT0 thit lp thi gian khi ng v thi gian tr
hon. Khong thi gian khi ng v thi gian tr hon c o c o bng mt
ng h ring, l b dao ng Watchdog. Tn s ca b dao ng Watchdog ph
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thuc vo in th ngun nui v nhit mi trng. Vcc = 5V v nhit
25oC th tn s ca b dao ng Watchdog l 1 MHz. Lin quan n vic thit lp
ca h thng xung clock ngi ta cn dng ti bit cu ch CKOPT m vai tr ca n
kh linh hot ty theo vic thit lp xung clock cho h thng nh th no. Hnh 18
cho thy ATmega128 c ti 7 b to xung clock c th c la chn. Di y l
m t c th cho tng trng hp cu hnh xung clock ca h thng.

10.1 b dao ng thch anh

B dao ng thch anh c mc theo hnh 19. Trong chn XTAL1 v
XTAL2 (tng ng chn s 24 , 23 ca vi iu khin ) ln lt l ng vo v ng ra
ca bkhuch i o c tch hp sn trong chip.
Gi tr ca t C1 v C2 phi bng nhau v thng c gi tr vo khong 12pF
22pF. Vi ATmega8 th tn s xung clock h thng ti a l 16MHz v t
c tn s ti a ny bit cu ch CKOPT phi c lp trnh ( ghi thnh 0 ). Nu
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bit CKOPT khng c lp trnh ( ghi gi tr 1 ) th tn s ti a ch l 8 MHz. Cc
bit CKSEL3..1 c dng la chn di tn s ti u nh trong bng 8. Cc bit
CKSEL0 v SUT1..0 c dng thit lp thi gian khi ng ( start-up ) v thi
gian tr hon ( delay time ) nh trong bng 9. Ta cng c th thay th tinh th thch
anh ( Quartz crystal ) bng gm cng hng ( Ceramic Resonator ).

Hnh 1.20 Ghp ni b dao ng thch anh

Table8 Ti u di tn s
La chn (1) ch nn dng cho gm cng hng, khng nn dng cho thch
anh

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table 9 Thit lp thi gian khi ng v tr hon

V d s dng thch anh 16 MHz lm xung clock h thng, thi gian khi
ng l 16 K ( 16384 chu k xung clock ca b dao ng watchdog ) v thi gian tr
hon l 65 ms th tacn thit lp cho cc bit cu ch l :
{ CKOPT, CKSEL3..0, SUT1..0 } = { 0, 1, 0, 1, 1, 1, 1 }
10.2 b dao ng thch anh c tn s thp
Thch anh trong trng hp ny c tn s thp 32,768 KHz c mc vo
mch nh hnh 19. Tn s thp c s dng gim cng sut tiu th ca h
thng v thch hp cho cc ng dng cn o thi gian thc. cu hnh cho h
thng xung clock theo ch ny, cn thit lp cc bit cu ch { CKSEL3..0 } = { 1,
0, 0, 1 }. Cc t C1, C2 cng c th c b i bng cch lp trnh cho bit CKOPT
cho php t bn trong chip hot ng. T bn trong chip c gi tr nh danh l
36 pF. Thi gian khi ng v thi gian tr hon c la chn nh vo cc bit cu
ch SUT1..0 theo nh bng 10.

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Bng 10. Thit lp thi gian khi ng v tr hon

10.3 b dao ng r-c bn ngoi
B dao ng R-C bn ngoi thch hp cho nhng ng dng khng i hi cao
v s
chnh xc thi gian . Mch R-C c mc nh hnh 20. Tn s dao ng vo
khong:
f=1/3RC
Trong gi tr ca C phi ti thiu l 22 pF. Tuy nhin ta cng c th b i t
C bng
cch lp trnh cho bit cu ch CKOPT cho php t bn trong chip ( mc
gia
XTAL1 v GND ) hot ng. Gi tr nh danh ca t bn trong chip l 36 pF.
Cc bit cu ch
CKSEL3..0 s cu hnh di tn s ti u nh bng 11 v cc bit cu ch
SUT1..0 s thit
lp thi gian khi ng v thi gian tr hon nh bng 12.

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Hnh 1.21 Mch dao ng R-C

Table 11. Ti u di tn s

Table 12. Thit lp thi gian khi ng v tr hon

10.4 b dao ng r-c tinh chnh c.
B dao ng ni RC cung cp cc tn s xung clock c nh 1 MHz, 2 MHz, 4
MHz, 8 MHz ( Vcc = 5V v nhit 25oC ). Ta c th dng xung clock ny nh
l xung clock ca h thng bng cch cu hnh cho cc bit cu ch CKSEL 3..0 c
ch ra bng 13. Khi s dng xung clock ca b dao ng ni lm xung clock ca
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h thng ta khng cn phi dng b dao ng bn ngoi. Khi cu hnh xung clock
h thng theo trng hp ny bit cu ch CKOPT khng c lp trnh ( ghi l 1 ).
V b dao ng watchdog c lp vi b dao ng ni RC ( xem hnh 18 ) nn khi
h thng hot ng theo xung clock ca b dao ng ni RC th b dao ng
watchdog vn c s dng cho b nh thi watchdog. Ngoi ra, ngi dng c
th tinh chnh tn s ca b dao ng ni bng cch thay i gi tr ca thanh ghi
OSCCAL. L do ca vic tinh chnh ny l bi v trong qu trnh m ( tc pht
xung clock ) ca b dao ng ni, sau 1 thi gian th s c sai s, v d b dao ng
ni c tn s 1 MHz sau 1000000 ln m th khong thi gian tng ng 1s s tri
qua. Nu thi gian m ko di s c th c sai s. Do ngi ta cn tinh chnh li
tc ca b dao ng ni bng cch lm cho n m nhanh hn hay chm i so
vi gi tr nh danh. lm c iu ny ngi ta tng hay gim gi tr ca thanh
ghi OSCCAL.

Table13. La chn tn s dao ng ni

Khong thi gian khi ng v thi gian tr hon c thit lp bi cc bit cu

ch
SUT1..0 theo bng sau

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Bng 14. Thit lp thi gian khi ng v tr hon

10.5 b to xung clock bn ngoi
Ngi dng cng c th s dng mt my pht xung clock bn ngoi lm
xung clock cho h thng. S ghp ni vi my to xung clock bn ngoi c
th hin hnh21.

Hnh 1. 22. Ghp ni vi my pht xung clock bn ngoi

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Bng 16. Thit lp thi gian khi ng v tr hon
Trong trng hp ny cc bit cu ch CKSEL3..0 phi ghi thnh 0000.
Ngi
dng cng c th cho php t bn trong chip ( gia XTAL1 v GND ) hot
ng bng cch lp trnh cho bit CKOPT ( ghi CKOPT thnh 0 ). Gi tr nh danh
ca t bn trong chip l 36 pF. Thi gian khi ng v thi gian tr hon c thit
lp bi cc bit SUT1..0 c cho bng 16.
10.6 b dao ng inh thi
Ngi dng cng c th mc trc tip b dao ng thch anh vo gia 2 chn
TOSC1 v TOSC2 ca vi iu khin ( khng cn t ) .B dao ng c ti u cho
tn s thch anh 32,768 KHz.
III. Cu trc cng ni tip
1. Khi Qut
Cng ni tip c s dng truyn d liu hai chiu gia my tnh v
ngoi vi, c cc u im sau:
Khong cch truyn xa hn truyn song song.
S dy kt ni t.
C th truyn khng dy dng hng ngoi.
C th ghp ni vi vi iu khin hay PLC (Programmable Logic Device).
Cho php ni mng.
C th tho lp thit b trong lc my tnh ang lm vic.
C th cung cp ngun cho cc mch in n gin
Cc thit b ghp ni chia thnh 2 loi: DTE (Data Terminal Equipment)
v DCE(Data Communication Equipment). DCE l cc thit b trung gian nh
MODEM cn DTE l cc thit b tip nhn hay truyn d liu nh my tnh,
PLC, vi iu khin, Vic trao i tn hiu thng thng qua 2 chn RxD
(nhn) v TxD (truyn). Cc tn hiu cn li c chc nng h tr thit lp v
iu khin qu trnh truyn, c gi l cc tn hiu bt tay(handshake). u
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im ca qu trnh truyn dng tn hiu bt tay l c th kim sot ng truyn.
Tn hiu truyn theo chun RS-232 ca EIA (Electronics Industry
Associations). Chun RS-232 quy nh mc logic 1 ng vi in p t -3V n
-25V (mark), mc logic 0 ng vi in p t 3V n 25V (space) v c kh nng
cung cp dng t 10 mA n 20 mA. Ngoi ra, tt c cc ng ra u c c tnh
chng chp mch.hun RS-232 cho php truyn tn hiu vi tc n 20.000
bps nhng nu cp truyn ngn c th ln n 115.200 bps.
Cc phng thc ni gia DTE v DCE:
- n cng (simplex connection): d liu ch c truyn theo 1 hng.
- Bn song cng ( half-duplex): d liu truyn theo 2 hng, nhng mi
thi im ch c truyn theo 1 hng.
- Song cng (full-duplex): s liu c truyn ng thi theo 2 hng.
nh dng ca khung truyn d liu theo chun RS-232 nh sau:
Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop
0

Khi khng truyn d liu, ng truyn s trng thi mark (in p -10V).
Khi bt u truyn, DTE s a ra xung Start (space: 10V) v sau ln lt
truyn t D0 n D7v Parity, cui cng l xung Stop (mark: -10V) khi phc
trng thi ng truyn. Dng tn hiu truyn m t nh sau (truyn k t A):

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Cc c tnh k thut ca chun RS-232 nh sau:

Cc tc truyn d liu thng dng trong cng ni tip l: 1200 bps,

4800 bps,9600 bps v 19200 bps.

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Hnh 2.1 s chn cng ni tip

Cng COM c hai dng: u ni DB25 (25 chn) v u ni DB9 (9 chn)
m t nh hnh 4.2. ngha ca cc chn m t nh sau:

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Cc s khi kt ni dng cng ni tip:

Hnh 2.2 k ni n gin trong truyn thng ni tip

Khi thc hin kt ni nh trn, qu trnh truyn phi bo m tc u
pht v thu ging nhau. Khi c d liu n DTE, d liu ny s c a vo b
m v to ngt.Ngoi ra, khi thc hin kt ni gia hai DTE, ta cn dng s
sau:

Hnh 2.3 kt ni trong truyn thng ni tip dng tn hiu bt tay

Khi DTE1 cn truyn d liu th cho DTR tch cc tc ng ln DSR
ca DTE2 cho bit sn sng nhn d liu v cho bit nhn c sng mang
ca MODEM (o). Sau , DTE1 tch cc chn RTS tc ng n chn CTS
ca DTE2 cho bit DTE1 c th nhn d liu. Khi thc hin kt ni gia DTE v
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DCE, do tc truyn khc nhau nn phi thc hin iu khin lu lng. Qu
trinh iu khin ny c th thc hin bng phn mm hay phn cng. Qu trnh
iu khin bng phn mm thc hin bng hai k t Xon v Xoff. K t Xon
c DCE gi i khi rnh (c th nhn d liu). Nu DCE bn th s gi k t
Xoff. Qu trnh iu khin bng phn cng dng hai chn RTS v CTS. Nu
DTE mun truyn d liu th s gi RTS yu cu truyn, DCE nu c kh
nng nhn d liu (ang rnh) th gi li CTS.
2. Truy xut trc tip thng qua cng
Cc cng ni tip trong my tnh c nh s l COM1, COM2, COM3,
COM4 vi cc a ch nh sau:

Giao tip ni tip trong my tnh s dng vi mch UART vi cc thanh ghi
cho trong bng sau:

Cc thanh ghi ny c th truy xut trc tip kt hp vi a ch cng (v d

nh thanh ghi cho php ngt ca COM1 c a ch l BACOM1 + 1 = 3F9h.
IIR (Interrupt Identification Register):

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Hnh 2.4 IIR(Interrupt Identification Register):

IIR xc nh mc u tin v ngun gc ca yu cu ngt m UART ang ch
phc v. Khi cn x l ngt, CPU thc hin c cc bit tng ng xc nh
ngun gc ca ngt. nh dng ca IIR nh trn.
IER (Interrupt Enable Register):
IER cho php hay cm cc nguyn nhn ngt khc nhau (1: cho php, 0: cm
ngt)

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Hnh 2.5 IER (Interrupt Enable Register):

FIE: FIFO Error sai trong FIFO
TSRE: Transmitter Shift Register Empty thanh ghi dch rng (=1 khi pht
1 kt v b xo khi c 1 k t chuyn n t THR.
THRE: Transmitter Holding Register Empty (=1 khi c 1 k t chuyn t
THR TSR v b xo khi CPU a k t ti THR).
BI: Break Interrupt (=1 khic s gin on khi truyn, ngha l tn ti mc
logic 0
trong khong thi gian di hn khong thi gian truyn 1 byte v b xo khi
CPU c LSR)
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FE: Frame Error (=1 khi c li khung truyn v b xo khi CPU c LSR)
PE: Parity Error (=1 khi c li parity v b xo khi CPU c LSR)
OE: Overrun Error (=1 khi c li thu , ngha l CPU khng c kp d liu
lm cho
qu trnh ghi chng ln RBR xy ra v b xo khi CPU c LSR)
RxDR: Receiver Data Ready (=1 khi nhn 1 k t v a vo RBR v b
xo khi CPU c RBR).

chia tn trong UART cho php t tc truyn mong mun.

UART dng dao ng thch anh vi tn s 1.8432 MHz a qua b chia 16
thnh tn s 115,200 Hz. Khi , tu theo gi tr trong BRDL v BRDH, ta s c tc
mong mun.
V d nh ng truyn c tc truyn 2,400 bps c gi tr chia 115,200 /
2,400 = 48d =0030h BRDL = 30h, BRDH = 00h.
Mt s gi tr thng dng xc nh tc truyn cho nh sau:

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IV. LM35
Mt s tnh cht c bn ca lm35
Bin thin 10mv/1"C
gii hn o -128"C-100"C
Quan h gia nhit v in p ng ra
Vout=0,01+T"K = 2,73+0,01t"C
T=0" Vout =2,73v
T=10" Vout =2,83v
V. HS1101
Chc nng:
c s dng trong cc vn phng t ng, cc bin oto, kim sot m trong khng kh, cc
vt dng trong gia nh, h tr trong qu trnh iu khin cng nghip .
Thng s:
- Nhit hot ng : -40 n 100C
- Nhit bo qun : -40 n 125C
- in p hot ng : 10Vac
- Khong cch m : 0-100%
Mch ng dng c bn s dng cm bin:

Gi tr chuyn i tn s: 7410, 7392, 7374, 7357, 7340, 7323, 7307, 7290, 7274, 7259 , 7243,
7228, 7213, 7198, 7183, 7169, 7155, 7140, 7127, 7113 , 7099, 7086, 7072, 7059, 7046, 7033,
7020, 7007, 6995, 6982, 6969, 6957, 6945, 6932, 6920, 6908, 6896, 6884, 6872, 6860 , 6848,
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6836, 6824, 6812, 6800, 6788, 6776, 6764, 6752, 6740 , 6728, 6716, 6704, 6692, 6680, 6668,
6656, 6643, 6631, 6619 , 6606, 6594, 6581, 6568, 6556, 6543, 6530, 6517, 6504, 6491 , 6477,
6464, 6450, 6437, 6423, 6409, 6395, 6381, 6367, 6352 , 6338, 6323, 6309, 6294, 6279, 6264,
6248, 6233, 6217, 6202, 6186, 6170, 6154, 6137, 6121, 6104, 6087, 6070, 6053, 6036, 6019

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Chng III: Thit k mch trn Orcad v Layout

CAPTURE
3.1. Gii thiu v cch s dng phn mm proteus
Proteusl phn mm ca hng Labcenter dung vs nguyn l, m
phng v thit kmch in. Gi phn mm gm c phn mm chnh :
ISIS dng v s nguyn l v m phng
ARES dng thit kmch in.
C thtm hiu thng tin v ti bn dng thchng trnh ti website ca nh
sn xut : http://www.labcenter.co.uk/
Sau khi ti vqu trnh ci t chng trnh bnh thng . Sau khi ci t
thnh
cng bn sthy chng trnh trong Start menu.
1.

Cch v mch v m phng

v s nguyn l, vo Start Menu khi ng chng trnh ISIS.

Chng trnh c khi ng.
Pha trn v pha phi ca chng trnh l cc cng c ta c th thit k s

nguyn l. Phn gia c mu xm l ni chng ta vmch.

Section mode: Chc nng nay chn linh kin
Component mode: Dng ly linh kin trong thvin linh kin
t lable cho wire
Bus:
Terminal: Cha Power, Ground,
Graph: Dng vdng sng, datasheet, trkhng
Generator Mode: Cha cc ngun in, ngun xung, ngun dng
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Voltage Probe Mode: Dng o in th ti 1 im trn mch, y l 1
dng c ch c 1

chn v khng c tht trong thc t

Curent Probe mode: Dng o chiu v ln ca dng in ti 1

im trn wire
Virtual Instrument Mode: Cha cc dng c o dng v p, cc dng
c ny c m phng nh trong thc t
T nhng dng c ta c th thit k c 1 mch nh mun

Hnh 3.0 S mch m phng

3.2 Thit k phn cng
3.2.1. Tng quan v Orcad Capture.
Orcad Capture l phn mm v mch nguyn l ca mch in, vi th vin phong ph, d
thao tc v thc hin.
Capture cho php ngi dng thay i, sa cha, thm ch l to mi cc linh kin, phc v
cho vic v mch nguyn l. Cc linh kin ca Capture c xy dng mt cch r rng, sng
sa, tnh trc quan cao.
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3.2.2. V mch nguyn l bng Orcad Capture.
3.2.2.1 Khi ng phn mm Orcad Capture.
khi ng phn mm Orcad Capture ta c 2 cch sau:
_Cch 1: Vo Start-> All programs-> Orcad Family Release 9.2-> Capture

Hnh 3.1: Khi ng phn mm Orcad Capture.

_Cch 2: Click vo biu tng
Ta c giao din ca Capture:

trn mn hnh desktop

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Hnh 3.2 : Giao din ca Capture
To mt project mi
to project chn File-> New-> Project

Hnh 3.3: Mt project mi

Hp thoi Project hin ra, ta nhp

tn trong Name v nhp ng dn
n v tr lu Location, nhp nt
Browse chn ng dn. v
mch nguyn l ta chn Schematic.

Mi trng lm vic ca orcad capture

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Hnh3.4 Mi trng lm vic ca orcad capture.

thay i kch thc bn v:
Option => Schematic Page Properties

Hnh 3.5 Thay i kch thc bn v.

Tab colors/Print:
hin cc gam mu dng gn cho tng i tng, ta c th thay i mu sc theo

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Hnh 3.6: Bng cc gam mu.

Tab Grid Display:
ty chn c hin th li (mc ch: t cc linh kin cho hp l v chnh xc) trong cc trang
thit k hoc sa i linh kin hay khng:

Hnh 3.7: Tab Grid Display

Tab Pan and Zoom:

hin th khung cha cc gi tr thay i t l (to, nh) ca i tng:

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Hnh 3.8 : Tab Pan and Zoom

Tab Select:
hin th khung thoi lin thoi lin quan n vic la chn cc thnh phn trong s nguyn l:

Tab

Miscellaneous:

cha nhng
thnh phn h tr cho vic gn cc
thuc tnh
cc i tng trong trang thit k.
Hnh
3.9:
Tabnng
selectrt quan trng l
Ngoi ra n
cn c
chc
t
ng
hin th s th t ca loi linh kin
c ly ra (Automatic reference placed part ) & bt tay cho vi Layout ( th Intertool
Communication ) rt hu dng trong vic sp t cc footprint linh kin ty thch ca ngi thit
k nhm trnh trng hp cc linh kin sp xp khng theo mun. Chc nng ny ch c tc
dng khi m c Capture & Layout v x l cng chung thit k:

Hnh 3.9: Tab Miscellaneous:

Tab Text editor:

ty chnh font ch hin th hin ti.

73

 n tt nghip

Hnh 3.10: Tab Text editor.

i tng thao tc, cc phm tt

Ca s bn tri l khong v mch cn ca s bn phi l thanh cng c cha cc thnh phn
thit k mch:
Con tr select thao tc cc linh kin
Place Part: a thm linh kin vo mch
Place wire: ni dy
Place net alias: t tn dy ni
To Bus
To im ni
Ngun
t
Cc phm v chc nng:
Phm
R
H
V
O
I
W
P
J

Chc nng
Xoay linh kin
Lt linh kin theo chiu ngang
Lt kinh kin theo chiu dc
Thu nh mn hnh
Phng to mn hnh
Ni cc ng mch
Ly linh kin
To im ni

Phm
T
F
Y
N
B
G
ESC

Chc nng
Thm vn bn cho bn v
Ly cc khi ngun
V khi ch nht
nh nhn, tn ng dn
V ng Bus
Ly cc khi mass, chn ni t
Thot ch ang chn
74

 n tt nghip
Bng 3.1: Cc phm v chc nng

K hiu cc linh kin tm kim trong th vin:

K hiu
Tn gi
R
in tr
CAP NP

T khng phn cc

K hiu
PNP
SW

FUSE
NPN
BRIDGE
RESISTOR VAR
RELAY
DIODE

Cu ch
CAP
Transistor ngc
LED
Cu diode
DIODE ZENER
Bin tr
CRYSTAL
R le
HEADER
i t
Bng 3.2: K hiu cc linh kin tm kim.
v c mch nguyn l, ta cn phi b sung thm linh kin:

Tn gi
Transistor thun
Nt nhn, chuyn
mch
T in
n led
i t n p
Thch anh
Chn cm

Hnh 3.11: B sung thm linh kin.

i khi mt s linh kin ngoi thc t khng c trong th vin, t ta phi to mi mt
s linh kin cho mch.
- to mi linh kin, ta m Capture -> File ->New -> Library -> New project ->OK.

75

 n tt nghip

in tn linh kin v v
tr lu linh kin tin
cho vic add thm vo
th vin ca capture

Hnh 3.12 cc bc to thm linh kin mi.

to chn linh kin ta c 2 cch:
+ To tng chn : ta chn Place Pin hoc
s xut hin bng Place pin ta g tn
v s ca chn linh kin ri nhn OK v t chn linh kin vo v tr.

Hnh 3.13: Cch to chn linh kin.

+ To mt dy chn: ta chn Place Pin Array hoc
Array: ta nhp cc thng s cn thit nh:
- Starting name: tn bt u ca chn linh kin
- Starting number: s bt u ca chn linh kin
76

s xut hin bng Place Pin

 n tt nghip
- Number of pins: s chn mun to
- Increment: th t sp xp ca cc chn, vi 1 l sp xp thun, -1 l sp xp
ngc, 2 l th t chn nhy cch 1.
-

Hnh 3.14: Chnh sa chn linh kin

Ngoi ra: - vng Shape chn hnh dng

Hnh 3.15: Chnh sa tn ca chn linh kin

V d i vi ATmega 32, ban u ta phi tm hiu c hnh dng v chn ca linh kin
ngoi thc t. Tra cu trn datasheet, ta c hnh dng ca AT mega32 nh sau:

77

 n tt nghip

Giao din
to mt linh
kin mi trong
capture

Hnh 3.16: V d v to linh kin mi

to tn linh kin:
Nhp vo Place Text hoc
s xut hin bng Place Text ta g tn ri OK v t
khung tn va g vo v tr thch hp:

Hnh 3.17: To tn linh kin.

78

 n tt nghip
Sau khi s dng cc cng c nh ng bao, thm chn, thm text, ta c hnh v linh
kin ATmega32 nh sau:

Hnh 3.18: Hon chnh ATmega32 trn Orcad.

S MCH O NHIT , M TRONG PHNG:

1. Khi ngun.

C chc nng cung cp ngun cho mch. Mch ngun s dng ic n p

LM2576
Ng ra OUT lun n nh 5V d in p t ngun cung cp thay i. Mch
ny dng bo v nhng mch in ch hot ng in p 5V
Nu ngun in c s c t ngt: in p tng cao th mch in vn hot
ng n nh nh c IC 2576 vn gi c in p ng ra OUT 5V khng i
Vcc=5v.

79

 n tt nghip
F2

U 15
1

D 46

3
2
1

O U T

L M 2 5 7 6 -5
3

C 8

D 14

C 9

1000u 104

F R 207

C 16
1000u

R 46

D 45

1k

LED

5V

C 18
104

C ON 3

VC C

FB
O N /O F F

BR 805D

J99

4
5

5V

FU SE

V IN

L13
100m H

NGUON
Hnh3.19 Khi ngun
2. Khi lcd

A
1 6

D B 7
1 5

D B 6
1 4
D 3

D B 5
1 3
D 2

D B 4
1 2
D 1

D B 2

D B 1

D B 0

D B 3
1 1
D 0

1 0

E
7

R /W
6
E N

V C C

R S
5

R S

V C C

G N D

1 6 x 2

V -C o n s t

L C D 1

R 2
3 3 0

B ie n t r o
1 0 k
V C C

LCD
Hnh 3.20 khi lcd
Khi hin th LCD c 16 chn
Chn 1 v chn 16 ni t
Chn 6 ni vi chn PD7 ca port D ca vi iu khin
Chn 7>>chn 14 ni vi port C th t t chn 22>>29 ca vi iu khin
Chn 5 ni vi chn 19 ca vi iu khin
Chn 4 ni vi chn 20 ca vi iu khin

3. Khi phm bm

80

 n tt nghip
VCC

R 64
1 Ck 2 5
re s e t
C
4

S W N1 u t 1
3

S W N2 u t 2
3

S W N3 u t 3
3

S W N4 u t 4
3

RESET
3

PHIM BAM
Hnh 3.21 khi phm bm
Phm bm bao gm 1 phm reset chng trnh bo 4 phm iu chnh cc ch
ca mch.

81

 n tt nghip
4. Khi cm bin

1uF
C

R 63
100

VC C

VC C

R 62
100

PA0

1
2
3
4

1
2
3

J98
M Q 2

PA3

PA2

PA1
R 53
100

VC C

J101
LM 35

1
2
3

J100
LM 35

1
2
3

J97
LM 35

1uF 2
C

VC C

R 54
100

1uF 3
C

1uF 1
C

LM35
Hnh 3.22 khi cm bin nhit
Chn s 2 ca IC LM35 c ni vi chn ADC ca vi iu khin
V C C
R 1 0

D o

4 .9 K

G N D

1 K

D IS

T H R

R 9
5 7 6 K

C V
8

T R
V C C

U 2 4
L M 5 5 5

a m

R 7

C 2 6
J 1 0 2
H S 1 1 0 1

V C C

R 1 2

C 1 0

9 0 9 K

1 7 8 p F

HS1101
Hnh 3.23 khi cm bin m
82

 n tt nghip
5. Khi dao dng
C 21
XTA L1
22pF

Y 21
8M
XTA L2

C 22

22pF

Hnh 3.24 Khi to dao ng

Thch anh c ni vo chn 12 v chn 13 ca vi iu khin to dao ng
6. Khi np chng trnh
C 4
J21
1
3
5
7
9

MO SI
R ESET
SC K
M IS O

2
4
6
8
10

VC C

1n

c h a n n a p IS P

Hnh 3.8 khi np chng trnh

Cc chn 1 3 5 6 c ni ln lt vi cc chn 6 8 9 7 ca vi iu khin
Chn 10 ni vcc chn 6 7 8 9 ni gnd
7. Khi vi iu khin
U 21

N u t4

L3
L2
L1
L0
N u
N u
D o
N u

R 1
R 0
M O S I
M IS O
S C K
1
1
1
1
1
1
2
2

t1
t2
am
t3

R E S E T
V C C

1
2
3
4
5
6
7
8

R 3
R 2

C 6
1 n

4
5
6
7
8
9
0
1

9
10
31
11

P
P
P
P
P
P
P
P

B
B
B
B
B
B
B
B

0
1
2
3
4
5
6
7

P
P
P
P
P
P
P
P

D
D
D
D
D
D
D
D

0
1
2
3
4
5
6
7

P
P
P
P
P
P
P
P

A
A
A
A
A
A
A
A

0
1
2
3
4
5
6
7

P
P
P
P
P
P
S D A /P
S C L /P

C
C
C
C
C
C
C
C

7
6
5
4
3
2
1
0

/IN T 2
/O C 0
/S S
/M O S I
/M IS O
/S C K
/R X
/T X
/IN T 0
/IN T 1
/O C 1 B
/O C 1 A
/O C 2

R E S E T
V C C
G N D
G N D

XTA L1
XTA L2
A V C C
A R E F

4
3
3
3
3
3
3
3

0
9
8
7
6
5
4
3

2
2
2
2
2
2
2
2

9
8
7
6
5
4
3
2

1 2
1 3

P
P
P
P
L
L
L
L

E
R
S
S

A
A
A
A
D
D
D
D

0
1
2
3
0
1
2
3
D
D
D
D

N
S
D A
C L

XTA L1
XTA L2

3 0
3 2

L1
C 7

C 24 103

A tm e g a 3 2 -D IP

0
1
2
3

1n

V C C
10m H

ATMEGA32

Hnh 3.25 vi iu khin atmega32

83

 n tt nghip
8. Khi chng nhiu

L1
C7
1n

VCC
10m H

Hnh 3.26 khi chng nhiu

Ngun vcc c ni qua in cm L1 10uH ri ni vo chn 30 ca vi iu
khin qua t c6 ni t.
9. Khi iu khin thit b.

Hnh 3.27: Khi iu khin relay v thc thi

10. gi mch ( L khoan 4 gc).

Hnh 3.28: gi mch.

84

 n tt nghip
Mch hon thin:
U 22

8M
XTA L2

C4

1n

PC
PC
PC
PC
PC
PC
S D A /P C
S C L /P C

7
6
5
4
3
2
1
0

29
28
27
26
25
24
23
22

7
1
2
6

0
1
2
3

D0
D1
D2
D3

3
5

13
12
11
10
9
15
14

A
B
C
D
E
F
G

LT
RBI

J3

R 55
R 56

e
d

1
2
3
4
5
6

1k
1k R 57
R 58

c
g

L3

1k
1k

12
11
10
9
8
7

1k
1k
R 61

7seg X4
VCC

7447

R 10

EN
RS
SDA
SCL

LED 7 SEG

4 .9 K
R7

10m H

1n

EN

ATMEGA32

RESET
3

VCC

R 53
100

1uF
C

F2

U 15
1

1uF 2
C

1
B T1

S Q W /O U T

V bat

SCL

GND

SDA

D1

7
6
5

R4

10k
SCL

R1

SDA

B R 805D

C8

VCC

D 14

C9

F R 207

D 45

1k

LE D

R
909K

178pF

HS1101

5V

C 16
1000u

R 46

C 10

C 18
J91

104

J92

J93

J94

NGUON

LS 1
3
1
2

m ay bom
R0

D44
D IO D E

quat

R 44 O p to 4
1
330 2

J4

5
4

LS 3

J40
LS 2

2
1

VCC

3
D 43

CON2
R ELAY SPD T

U 13
4

O p to 4
1

R 42
m ay bom
330

1
3
5
quat
R1

1
2

J41
5

Q1
M O S F E T_E N _ G D S

VCC
D 47

CON2

R2

330
D IO D E

quat

m ay bom

LS 4

2
1

VCC
D 49
CON2
R3

D IO D E

Q3 R ELAY SPD T
M O S F E T_E N _G D S

O p to 4
1

R52
330

D 48
R2

R 43

R 51

D IO D E

2
1
CON2

Q4 R ELAY SPD T
M O S F E T_E N _ G D S

R 65
10k
D 50
R3

330
LED

1
2

J43
5

U 17
4

R 50
10k

330
330

1
2

J42
5

U 16
4

Q2 R ELAY SPD T
M O SF ET_EN _G D S

R47
10k
D41

R 45

O p to 4
1

R49

1k
D 42

2
1

U 14
4

2
4
6

R 48

J2
c o n g t a c g iu
CON3

L13
100m H

R 12

D S 1307

VCC

1
2
3

OUT

FB
O N /O F F

1000u 104
CON3

VCC

10k

V IN

L M 2 5 7 6 -5

330

10k

R3

3
2
1

(3) RTC_MODULE

VCC

1uF 1
C

N guon D C

X2

R9

VCC

TH R

J102
H S 1101

VCC
R 54
100

1uF 3
C

3 2 ,76 8

J99

1n R 5
Vcc

4
5

5V

D 46 FU SE

C5
U 12
X1

R 63
100

LM35
VCC

PA0

PA3
R 62
100

PHIM BAM

Y3

CV

U 24
LM 555

1
2

LCD
2

J98
MQ2

C 26

10k

VCC

S W N4 u t 4
4
3

J101
LM 35

1K

B ie n t r o

S W N3 u t 3
4
3

R2
330

VCC

R 64
1 Ck 2 5
re s e t
S W N2 u t 2
4
3

J100
LM35

D IS

576K

VCC

S W N1 u t 1
4
3

J97
LM 35

C 24 103

TR

VCC

VCC

1
2
3
4

C7

1
2
3

30
32

A tm e g a 3 2 -D IP

VCC

16x2
L1

1
2
3

AVCC
AREF

XTA L1
XTA L2

PA2

VCC
GND
GND

12
13

VCC

1n

XTA L1
XTA L2

1
2
3

C6

VCC

RESET

PA1

10
31
11

D0
D1
D2
D3

RESET

LC D 1

c h a n n a p IS P

L0
a
f
L1
L2
b

R 59
R 60

1k

B I/R B O

D0
D1
D2
D3

a
b
c
d
e
f
g

GND
VCC
V -C o n s t
RS
R /W
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
A
K

VCC

0 /R X
1 /T X
2 /I N T 0
3 /I N T 1
4 /O C 1 B
5 /O C 1 A
6
7 /O C 2

PA0
PA1
PA2
PA3
LD 0
LD 1
LD 2
LD 3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

2
4
6
8
10

PD
PD
PD
PD
PD
PD
PD
PD

40
39
38
37
36
35
34
33

D o am

J21
1
3
5
7
9

14
15
16
17
18
19
20
21

L3
L2
L1
L0
N u t1
N u t2
D o am
N u t3

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

RS

C 22

22pF

RESET
SCK
M IS O

R1
R0
MOSI
M IS O
SCK

Y 21

PB0
PB1
P B 2 /IN T 2
P B 3 /O C 0
P B 4 /S S
P B 5 /M O S I
P B 6 /M IS O
P B 7 /S C K

GND

N u t4

22pF

1
2
3
4
5
6
7
8

R3
R2

XTA L1

MOSI

LD
LD
LD
LD

U 21

C 21

R 66
330

LE D

LED

LE D

DIEU KHIEN

Hnh 3.29. Mch nguyn l hon chnh

3.2.2. Kim tra li v to file Netlist:
Sau khi hon thnh ton b s nguyn l, chng ta tin hnh to file Netlist dng
cho vic v layout. Vo Project Manager, click vo file.DSN.
Kim tra li pht hin li mch nguyn l va hon thnh:
Click Design rules check, nhp chut vo Create DRC markers for warnings nh du
nhng v tr li trn bn v. Nhn OK, nu pht hin li n s hin ra bng thng bo li v nh
du phn b li l khong mu xanh

85

 n tt nghip

Hnh 3.34..Kim tra li

Sau khi sa li, ta c mch nguyn l hon chnh v khng c li no. Tin hnh to tp
tin Netlist bng cch vo Project Manager, chn tn project, kch chut vo biu tng Create
netlist
, hp thoi Create netlist xut hin, chn th Layout s to ra mt file.MNL. File ny
dng v mt file layout mi v tn mc nh chnh l tn project chn. Click v Run ECO
to layout, khi ny c th cp nht t file Schematic sang layout:

Hnh 3.35.. To file Netlist

86

 n tt nghip
Di y l thng bo
thc hin xong file layout:

Hnh 3.36. Thc hin Layout

Vy l c file Netlist sn sng cho vic Layout.

LAYOUT
3.3. V mch in bng Orcad Layout
3.3.1Khi ng Orcad Layout
Khi ng chng trnh: Start->All Program-> Orcad Family Release 9.2-> Layout

Hoc Click vo biu tng

trn mn hnh Desktop

Hnh 3.37. Giao din Layout

Gii thiu th vin v Footprint trong Layout
Vo Tools > Library Manager:

87

 n tt nghip

Hnh 3.38. To th vin Layout

Mn hnh lm vic ca Library Manager:

Hnh 3.39. Giao din lm vic ca Layout

Sau add cc th vin ca layout tng t nh capture:
C:\Program Files\Orcad\Layout\Library

88

 n tt nghip

Hnh 3.40.Th vin Layout

Sau khi add, ta c danh sch cc Footprint. Ban u cho in tr R1 10k. Trong th vin
ta chn Footprint ca in tr:

Hnh 3.41. Hnh dng linh kin trong th vin Layout

89

 n tt nghip
Cc lp (layer) thng dng:
TOP: Top, mc nh mu xanh dng Phm 1 (mu xanh dng)
BOT: Bottom, mc nh c mu Phm 2 (mu )
SSTOP: In ch v k hiu linh kin, mc nh mu trng Phm Shift + 1 (mu trng)
SMTOP: SolderMask Top, nh khong cch ph xanh mt Top (mu xanh l)
SMBOT: SolderMask Bottom, nh khong cch ph xanh mt Bot (mu vng)
DRILLv DRLDWG: quy nh kch thc l khoan (mu nu).
to mt footprint mi hon ton ta chn Create New footprint:

hp thoi Create New Footprint.

Nhp tn linh kin mi mc Name
of footprint. Bm chn English. Kch
c cc b phn ca linh kin c
cho h met nhng hu ht kch
thc ch to PCB vn bng n v
inches (1 mils=1/1000inch).

Hnh 3.42. To tn mi cho linh kin

dng h mt phi thay i: Vo Options-> System Settings. Xut hin hp thoi . n OK.

90

 n tt nghip

Hnh 3.43. Thay i kch c

91

 n tt nghip
3.3.2.Hnh nh ca mch sau khi thit k trn Layout:
-Mt TOP:

Hnh 3.44. Hnh dng mt TOP

-Mt Bottom:

Hnh 3.45. Hnh dng mt BOTTOM

92

 n tt nghip
-Ton mch:

Hnh 3.46. Hnh dng mch in hon chnh

93

 n tt nghip
TI LIU THAM KHO
1. Dng Minh Tr, Linh kin quang in t, Nh xut bn khoa hc k thut H Ni,
1996.
2. H Trung M, Vi x l, Nh xut bn i hc quc gia T.p H Ch Minh, 2006.
3. Xun Tin, K thut vi x l v lp trnh ASSMBLER cho h vi x l, Nh xut bn
khoa hc k thut, 2006.
4. Phan Quc Ph, Nguyn c Chin, Gio trnh cm bin, Nh xut bn khoa hc v
k thut, 2005.
5. Ng Din Tp, Lp trnh bng hp ng, Nh xut bn Khoa hc k thut, H ni 1998.
6. Introducting electronic devices circuit conventional (Robert T.Payrter).
Tc gi: Bimal K. Bose, Modern Power Electronics and AC Drives
7. Cc trang web Tailieu.vn, alldatasheet.com, datasheetcatalog.com, diendandientu.com,
dietuvietnam.net, hocavr.com, google.com.....

94

 n tt nghip
PH LC
Chng trnh.
#include <mega32.h>
#include <delay.h>
#include <alcd.h>
#define ADC_VREF_TYPE ((0<<REFS1) | (1<<REFS0) | (0<<ADLAR))
unsigned int read_adc(unsigned char adc_input)
{
ADMUX=adc_input | ADC_VREF_TYPE;
delay_us(10);
ADCSRA|=(1<<ADSC);
while ((ADCSRA & (1<<ADIF))==0);
ADCSRA|=(1<<ADIF);
return ADCW;
}
void docgiatri(unsigned int t)
{
char a,b,c;
a=t/1000;
t=t%1000;
//

lcd_putchar(0x30+a);//nghin
a=t/100;
t=t%100;

lcd_putchar(0x30+a);//tram
a=t/10;
b=t%10;
lcd_putchar(0x30+a);//chuc
95

 n tt nghip
lcd_putchar(0x30+b);//donvi
}
unsigned int demxungthucong(void)
{
PIND.6=1;
while((PIND&0x40)==0x40); //cho xung xuong
while((PIND&0x40)==0);// cho xung ln
TCNT1H=0;TCNT1L=0;// xa cc thanh ghi time 1;
while((PIND&0x40)==0x40); //cho xung xuong
while((PIND&0x40)==0);// cho xung ln
return TCNT1;
}
void main(void)
{
unsigned int i,ve;
int r,M;
char phim;
DDRA=(0<<DDA7) | (0<<DDA6) | (0<<DDA5) | (0<<DDA4) | (0<<DDA3) |
(0<<DDA2) | (0<<DDA1) | (0<<DDA0);
PORTA=(0<<PORTA7) | (0<<PORTA6) | (0<<PORTA5) | (0<<PORTA4) |
(0<<PORTA3) | (0<<PORTA2) | (0<<PORTA1) | (0<<PORTA0);
DDRB=(0<<DDB7) | (0<<DDB6) | (0<<DDB5) | (0<<DDB4) | (0<<DDB3) |
(0<<DDB2) | (0<<DDB1) | (0<<DDB0);
PORTB=(0<<PORTB7) | (0<<PORTB6) | (0<<PORTB5) | (0<<PORTB4) |
(0<<PORTB3) | (0<<PORTB2) | (0<<PORTB1) | (0<<PORTB0);
DDRC=(0<<DDC7) | (0<<DDC6) | (0<<DDC5) | (0<<DDC4) | (0<<DDC3) |
(0<<DDC2) | (0<<DDC1) | (0<<DDC0);

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 n tt nghip
PORTC=(0<<PORTC7) | (0<<PORTC6) | (0<<PORTC5) | (0<<PORTC4) |
(0<<PORTC3) | (0<<PORTC2) | (0<<PORTC1) | (0<<PORTC0);
DDRD=(0<<DDD7) | (0<<DDD6) | (0<<DDD5) | (0<<DDD4) | (0<<DDD3) |
(0<<DDD2) | (0<<DDD1) | (0<<DDD0);
PORTD=(0<<PORTD7) | (0<<PORTD6) | (0<<PORTD5) | (0<<PORTD4) |
(0<<PORTD3) | (0<<PORTD2) | (0<<PORTD1) | (0<<PORTD0);
TCCR0=(0<<WGM00) | (0<<COM01) | (0<<COM00) | (0<<WGM01) |
(0<<CS02) | (0<<CS01) | (0<<CS00);
TCNT0=0x00;
OCR0=0x00;
TCCR1A=(0<<COM1A1) | (0<<COM1A0) | (0<<COM1B1) | (0<<COM1B0)
| (0<<WGM11) | (0<<WGM10);
TCCR1B=(0<<ICNC1) | (0<<ICES1) | (0<<WGM13) | (0<<WGM12) |
(0<<CS12) | (0<<CS11) | (1<<CS10);
TCNT1H=0x00;
TCNT1L=0x00;
ICR1H=0x00;
ICR1L=0x00;
OCR1AH=0x00;
OCR1AL=0x00;
OCR1BH=0x00;
OCR1BL=0x00;
ASSR=0<<AS2;
TCCR2=(0<<PWM2) | (0<<COM21) | (0<<COM20) | (0<<CTC2) |
(0<<CS22) | (0<<CS21) | (0<<CS20);
TCNT2=0x00;
OCR2=0x00;
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 n tt nghip
TIMSK=(0<<OCIE2) | (0<<TOIE2) | (0<<TICIE1) | (0<<OCIE1A) |
(0<<OCIE1B) | (0<<TOIE1) | (0<<OCIE0) | (0<<TOIE0);
MCUCR=(0<<ISC11) | (0<<ISC10) | (0<<ISC01) | (0<<ISC00);
MCUCSR=(0<<ISC2);
UCSRB=(0<<RXCIE) | (0<<TXCIE) | (0<<UDRIE) | (0<<RXEN) |
(0<<TXEN) | (0<<UCSZ2) | (0<<RXB8) | (0<<TXB8);
ACSR=(1<<ACD) | (0<<ACBG) | (0<<ACO) | (0<<ACI) | (0<<ACIE) |
(0<<ACIC) | (0<<ACIS1) | (0<<ACIS0);
ADMUX=ADC_VREF_TYPE;
ADCSRA=(1<<ADEN) | (0<<ADSC) | (0<<ADATE) | (0<<ADIF) |
(0<<ADIE) | (1<<ADPS2) | (0<<ADPS1) | (0<<ADPS0);
SFIOR=(0<<ADTS2) | (0<<ADTS1) | (0<<ADTS0);
SPCR=(0<<SPIE) | (0<<SPE) | (0<<DORD) | (0<<MSTR) | (0<<CPOL) |
(0<<CPHA) | (0<<SPR1) | (0<<SPR0);
TWCR=(0<<TWEA) | (0<<TWSTA) | (0<<TWSTO) | (0<<TWEN) |
(0<<TWIE);
lcd_init(16);
r=0;
DDRB.2=0;
phim=0;
DDRB.2=0;
PORTB.2=1;
DDRD.4=0;
PORTD.4=1;
DDRD.5=0;
PORTD.5=1;
DDRD.7=0;
PORTD.7=1;
while (1)
98

 n tt nghip
{
if (PINB.2==0) phim=0;
if (PIND.4==0) phim=1;
if (PIND.5==0) phim=2;
if (PIND.7==0) phim=3;
if(phim==0)
{
lcd_clear();
lcd_puts("Module Do Nhiet

Do Do Am");

phim=4;
}
if(phim==1)
{
DDRB.0=1;
PORTB.0=0;
ve=0;
for(M=0; M<250;M++){
i = read_adc(1);
i=(125*i/256);
ve+=i;
}
i=ve/250;
lcd_clear();
lcd_puts("Nhiet Do ");
docgiatri(i);
if(i>35) {
if (r==0) {PORTB.0=1; r=1;}
else {PORTB.0=0; r=0;}
99

 n tt nghip
}
lcd_puts("oC");
}
if(phim==2)
{
ve=0;
lcd_clear();
for(M=0;M<100;M++)
{
i= demxungthucong();
ve+=i;
}
i=ve/100;
lcd_puts(" Do Am ");
docgiatri(i);
lcd_puts("%");
delay_ms(500);
}
if(phim==3)
{
lcd_clear();
lcd_puts("Thank You Very

Much");

delay_ms(300);
}
}
}

100