SUBJECT: FPGA AND CPLD DESIGN

Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang

REPORT
LCD_CONTROLLER CORE DESIGN AND IMPORT THE CORE TO
FPGA-BASED EMBEDDED SYSTEM INCLUDING 32-BIT SOFT
CORE MICRO-CONTROLLER ON FPGA VIRTEX-5 XILINX
OUTLINE:
A. LCD CONTROLLER DESIGN
1. FPGA DESIGN FLOW
2. REQUIREMENTS ANALYSIS
3. ARCHITECTURE DESIGN
4. HDL DESIGN ENTRY
5. TEST ENVIRONMENT DESIGN
6. BEHAVIORAL SIMULATION
7. SYNTHESIS
8. IMPLEMENTATION
9. PROGRAMMING FILE AND DEMONSTRATION
B. IMPORT LCD_CONTROLLER CORE TO FPGA-BASED EMBEDDED
SYSTEM INCLUDING 32-BIT SOFT CORE MICRO-CONTROLLER ON
FPGA VIRTEX-5 XILINX




SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
A. LCD CONTROLLER DESIGN
1. FPGA DESIGN FLOW
















FPGA design flow


Source: http://www.fpgacentral.com/docs/fpga-tutorial/fpga-design-flow-overview
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
2. REQUIREMENTS
LCD 16x2 FPGA VIRTEX-5 XILINX












SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
3. ARCHITECTURE DESIGN












clk: clock 33MHz
rst_n: reset states of FSM
select_lin: button for selecting the 1
st
or 2
nd
line to display
but_clear: button for clearing LCD
but_line: button for changing the state to the display state
but_string: button for choosing the string to display
- 2 strings can be changed in the HDL code



DB(3)
DB(2)
DB(1)
DB(0)
select_lin
rst_n






LCD CONTROLLER
clk
but_clear
but_line
but_string
LCD_RW
LCD_RS
LCD_E
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
INITIALIZATION OF LCD 16x2 FOR 4-BIT INTERFACE





















Prefer to Dot Matrix Liquid Crystal Display Controller/Driver HD44780U for more details.
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang

FINITE-STATE MACHINE FOR LCD_CONTROLLER





















delay = 15ms

CLEAR_LCD
FUNCT_SET_1


FUNCT_SET_2
FUNCT_SET_3
Power on
reset

RETURN_HOME
INTERFACE_4_BIT
CURSOR_MOVE
WAIT_15MS
SELECT_LINE
DISPLAY_STRING
IDLE
but_line
but_clear
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang




TIMING CHARACTERISTICS FOR WRITING DATA TO LCD













Prefer to Dot Matrix Liquid Crystal Display Controller/Driver HD44780U for more details.





SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang


FINITE-STATE MACHINE
FOR WRITING DATA TO LCDS REGISTER



















E_high_1

E_low_1
wait_for_next_4bit
write_4bit_low
write_4bit_high
E_high_2

E_low_2
Power on
Reset

Waiting time
for execution
E_low_2 sub
state of previous
state

write_4bit_high
sub-state of
next-state
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang

























Prefer to Dot Matrix Liquid Crystal Display Controller/Driver HD44780U for more details.

Follow the above table to get the binary data and write to the DDRAM of
LCD:
o S(0x53), T(0x54), A(0x41), R(0x52)etc

SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
SUB-STATES INSIDE THE DISPLAY_STRING STATE






















DISPLAY_CHAR1
DISPLAY_CHAR2
DISPLAY_CHAR3
DISPLAY_CHAR4
DISPLAY_CHAR14
DISPLAY_CHAR15
DISPLAY_CHAR16



.
IDLE
From the state
SELECT_LINE
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
4.HDL DESIGN ENTRY
LCD_FSM.vhd: - LCD_states, LCD_subsates data type
- LCD_array, LCD_display_string data type
LCD_Library.vhd: - Procedure of sub-FSM (writing data to LCDs regs)
- Function for converting a character to
std_logic_vector(7 downto 0)
LCD_Controller.vhd: - Top module VHDL
5.TEST ENVIRONMENT DESIGN
LCD_testbench.vhd: - Behavioral Simulation.
6.BEHAVIORAL SIMULATION
Run ISIM on ISE Xilinx.












SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
7.SYNTHESIS
Observe the synthesis report on ISE Xilinx.
Synthesizing Unit <LCD_Controller>.
Related source file is
"C:/Users/Loile/LCD_Controller_FPGA/LCD_Controller/LCD_Con
troller.vhd".
Found finite state machine <FSM_0> for signal
<cur_state>.
------------------------------------------------------
| States | 27
| Transitions | 230
| Inputs | 13
| Outputs | 26
| Clock | clk (rising_edge)
| Reset | rst_n(negative)
| Reset type | asynchronous
| Reset State | wait_15ms
| Power Up State | wait_15ms
| Encoding | automatic
| Implementation | LUT
------------------------------------------------------
Found finite state machine <FSM_1> for signal
<substate>.
------------------------------------------------------
| States | 7
| Transitions | 357
| Inputs | 32
| Outputs | 7
| Clock | clk (rising_edge)
| Reset | rst_n (negative)
| Reset type | asynchronous
| Reset State | write_4bit_high
| Power Up State | write_4bit_high
| Encoding | automatic
| Implementation | LUT
------------------------------------------------------
-----------------
Found 1-bit register for signal <LCD_RS>.
Found 1-bit register for signal <LCD_E>.
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Found 4-bit register for signal <DB>.
Found 32-bit register for signal <clock>.
Found 32-bit adder for signal <clock$share0000>
created at line 67.
Summary:
inferred 2 Finite State Machine(s).
inferred 38 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
Unit <LCD_Controller> synthesized.
==========================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
32-bit adder : 1
# Registers : 4
1-bit register : 2
32-bit register : 1
4-bit register : 1

==========================================================
* Advanced HDL Synthesis
*
==========================================================
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <substate/FSM> on signal <substate[1:7]>
with one-hot encoding.
--------------------------------
State | Encoding
--------------------------------
write_4bit_high | 0000001
e_high_1 | 0000010
e_low_1 | 0000100
wait_for_next_4bit | 0001000
write_4bit_low | 0010000
e_high_2 | 0100000
e_low_2 | 1000000
--------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <cur_state/FSM> on signal <cur_state[1:27]>
with one-hot encoding.
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
------------------------------------------------
State | Encoding
------------------------------------------------
wait_15ms | 000000000000000000000000001
funct_set_1 | 000000000000000000000000010
funct_set_2 | 000000000000000000000000100
funct_set_3 | 000000000000000000000001000
return_home | 000000000000000000000010000
interface_4_bit | 000000000000000000000100000
display_on_off | 000000000000000000001000000
cursor_move | 000000000000000000010000000
clear_lcd | 000000000000000000100000000
select_line | 000000000000000100000000000
display_char1 | 000000000000000010000000000
display_char2 | 000000000000001000000000000
display_char3 | 000000000000010000000000000
display_char4 | 000000000000100000000000000
display_char5 | 000000000001000000000000000
display_char6 | 000000000010000000000000000
display_char7 | 000000000100000000000000000
display_char8 | 000000001000000000000000000
display_char9 | 000000010000000000000000000
display_char10 | 000000100000000000000000000
display_char11 | 000001000000000000000000000
display_char12 | 000010000000000000000000000
display_char13 | 000100000000000000000000000
display_char14 | 001000000000000000000000000
display_char15 | 010000000000000000000000000
display_char16 | 100000000000000000000000000
idle | 000000000000000001000000000
------------------------------------------------
==========================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Adders/Subtractors : 1
32-bit adder : 1
# Registers : 38
Flip-Flops : 38
==========================================================
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
* Low Level Synthesis
*
==========================================================
Optimizing unit <LCD_Controller> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block
LCD_Controller, actual ratio is 0.
==========================================================
Final Register Report
Macro Statistics
# Registers : 72
Flip-Flops : 72
Device utilization summary:
---------------------------
Selected Device : 5vlx110tff1136-2

Slice Logic Utilization:
Number of Slice Registers: 72 out of 69120 0%
Number of Slice LUTs: 216 out of 69120 0%
Number used as Logic: 216 out of 69120 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 217
Number with an unused Flip Flop: 145 out of 217 66%
Number with an unused LUT: 1 out of 217 0%
Number of fully used LUT-FF pairs: 71 out of 217 32%
Number of unique control sets: 3
IO Utilization:
Number of IOs: 13
Number of bonded IOBs: 13 out of 640 2%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%








SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
8.IMPLEMENTATION
Run implementation on ISE.


# CONSTRAINT FILE FOR LCD_CONTROLLER
NET "clk" LOC="AH17"; # clock 33MHz
NET "LCD_RS" LOC = "J17";
NET "LCD_RW" LOC = "AC10";
NET "LCD_E" LOC = "AC9";
NET "DB<3>" LOC = "T11";
NET "DB<2>" LOC = "G6";
NET "DB<1>" LOC = "G7" ;
NET "DB<0>" LOC = "T9";
NET "rst_n" LOC ="U25";
NET "select_lin" LOC ="AG27";
NET "but_clear" LOC ="AF25";
NET "but_line" LOC ="AF26";
NET "but_string" LOC ="AE27";





SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
9.PROGRAMMING FILE AND DEMONSTRATION
Run generating programming file and in-circuit verification.
Demonstration on FPGA Virtex-5 Xilinx.




















SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
B. IMPORT THE CORE TO FPGA-BASED EMBEDDED SYSTEM
INCLUDING 32-BIT SOFT CORE MICRO-CONTROLLER ON FPGA
VIRTEX-5 XILINX
- Previous project : XUPV5-LX110T with system.xmp
- Task: Convert LCD_Controller.vhd with string START on 1
st
line and
LOI-09DT1 on 2
nd
line of LCD into an IP core and add the core to the
above project, program and observe results.
- Firstly, open the project and click Hardware, choose Create and Import
Peripherals Wizard:







SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Click Next,
Then click Import existing peripheral and press Next
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Next











Enter LCD_Controller.




SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Next,









Next, then add LCD_Controller.vhd file and click Next
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Uncheck select bus interface(s), then Next


Continue to uncheck select and configure interrupt(s), then Next










SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Next,















Then finish creating the IP core.






SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang
Now, add the IP to the project

Then click OK and choose the connection of the LCD_Controller










SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang

Because the minimum frequency of Clock in previous project is 62.5 MHz and clk
of LCD_Controller is 33MHz, we change values of delay in LCD_Controller.vhd
file.

Then add new location for LCD pin to system.ucf file:
# LCD_FPGA_DB4
Net LCD_Controller_0_DB_pin<0> LOC = T9 | IOSTANDARD=LVCMOS33
| PULLDOWN | SLEW=SLOW | DRIVE=2;
# LCD_FPGA_DB5
Net LCD_Controller_0_DB_pin<1> LOC = G7 |
IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
# LCD_FPGA_DB6
Net LCD_Controller_0_DB_pin<2> LOC = G6 |
IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
# LCD_FPGA_DB7
Net LCD_Controller_0_DB_pin<3> LOC = T11 |
IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
# LCD_FPGA_RW
Net LCD_Controller_0_LCD_RW_pin LOC = AC10 |
IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
# LCD_FPGA_RS
Net LCD_Controller_0_LCD_RS_pin LOC = J17 |
IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2;
# LCD_FPGA_E
Net LCD_Controller_0_LCD_E_pin LOC = AC9 |
IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;

Then Generate bit stream and download bit stream into Virtex-5 FPGA and get the
same string START on the first line and LOI-09DT1 on the 2
nd
line.
SUBJECT: FPGA AND CPLD DESIGN
Students name: Le Van Loi Class 09DT1 Lecturer: Dr. Huynh Viet Thang


Demonstration on FPGA Virtex-5 Xilinx:

References:
[1] Hitachi, Dot Matrix Liquid Crystal Display Controller/Driver,1998
[2] HARDI Electronics AB, VHDL Handbook ,1997-2000
[3] Surin Kittitornkun and Charles R. Kime, FPGA Design Tutorial, Fall 2001
[4] http://www.fpgacentral.com/docs/fpga-tutorial/fpga-design-flow-overview