N CU TRC MY TNH

THIT KT B X L
MIPS 32-BIT SINGLE-
CYCLE


A 32 bit single cycle cpu c thit k v kim tra,nh l 1 i tng ca project.Cu trc thit k ca
CPU c s dng cng c the CAD t Mentor Graphichs.The CPU cn 1 tp hp ca cc cu lnh MIPs
thit t v cu trc cu lnh sao chp nhng MIPs rt n . Nhng cu lnh c h tr nh sau :
-Thut ton: add ,addi,sub
-Logic : and,or,sll
-Chuyn d liu: lw,sw
-iu kin r nhnh: beq,bne,slt
-NOP: nop
c trng mu hnh ca CPU
-cha 1 32 bit ALU,vi hai ci 32 bt ng vo,1 ci 32 bt ng ra ,v ng ra bt ging nh Carryout, Zero,
v Overflow h tr chi tit thm cho ng ra.
-Phn t b nh l 32 bit m rng( b rng d liu) v c truy cp bi 32 bit a ch ( b rng a ch )
-

Section1-ALU
The 32 bit ALU c xy dng bi cascading 32 bit n ALUs .N c s dng n gin nh 1 ng v
ti LSB ca the 32 bit ALU is fed vi a 1 trong thp ca ton hng a Sub or slt.0 l nhng th khc .
Carryout bit cp cho the Carry in bt ca khi block tip theo .
Over flow c thc hin bi php xor ca the Carry in v the Carry out ca the 1-bit ALU
Instr Regdest ALUsrc MemtoReg Regwrite Mem
Read
Mem
Write
Banch Jump Sign
Extend
ALUop
ADD 1 0 0 1 X 0 0 0 X And
SUB 1 0 0 1 X 0 0 0 X Sub
SLT 1 0 0 1 X 0 0 0 X Slt
AND 1 0 0 1 X 0 0 0 X And
XOR 1 0 0 1 X 0 0 0 X Xor
ANDI 0 1 0 1 X 0 0 0 0 And
XORI 0 1 0 1 X 0 0 0 0 Xor
SLTI 0 1 0 1 X 0 0 0 0 Slt
LW 0 1 1 1 1 0 0 0 1 Add
SW X 1 X 0 X 1 0 0 1 Add
BEQ X 0 X 0 X 0 1 0 1 Sub
BLTZ X 0 X 0 X 0 1 0 1 Xor
J X x X 0 X 0 0 1 X xx

ALUOp Funct Operation Instr
ALUOp2 ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0 0 0 1 0 0 0 0 0 000 ADD
0 0 0 1 0 0 0 1 0 010 SUB
0 0 0 1 0 1 0 1 0 011 SLT
0 0 0 1 0 0 1 0 0 100 AND
0 0 0 1 0 0 1 1 0 001 XOR
0 0 1 X X X X X X 100 ANDI
0 1 0 X X X X X X 001 XORI
0 1 1 X X X X X X 011 SLTI
1 0 0 X X X X X X 000 LW
X X X X X X X X X XXX SW
0 1 0 X X X X X X 001 BEQ
0 1 0 X X X X X X 001 BLTZ
X X X X X X X X X XXX J