STM32F4

STM32F4
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1

STMicroelectronics

STM32F4

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#01 : GPIO STM32F4

@01. Gii thiu GPIO:
GPIO (General-Purpose Input/Output) hiu nm na l u vo - u ra s dng chung:
i vi cc dng STM32 th mi port c 16 chn IO.
Ngoi chc nng IO mun s dng ngoi vi phi thit lp chn l Alternate hoc Analog.
Mi chn IO bn trong chip u gn thm in tr ni pull up v pull down.
Chi tit bn c th tham kho Reference manual trang 185, v s chn, kiu chn tham kho datasheet.
@02. Kt ni phn cng:

Bi vit s c thc hnh trn
board MiniTestF4. S nguyn l
v mch in v bng Altium c
nh km bn trn.
Trong bi lp trnh ICViet khai
bo chn PA0 l input, chn PB0-
PB1 l output. Bn c th kt ni
nh s bn di. Ring phn
mch np bn c th s dng mch
np bt k cho ARM chun SWD
hoc ST-LinkV2 ca ICViet.

STM32F4

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@03. Lp trnh GPIO c bn:
Trc ht ICViet xin thng nht vi cc bn phng php hc v tip cn ARM khng ging nh cc loi vi
iu khin trc bn tng hc, cc bn khng nn can thip su vo bn trong cc thanh ghi, v rt nhiu thanh
ghi cu thnh mt ngoi vi. Rt may mi hng u support sample code v th vin ngoi vi chun bn tin lp
trnh m khng cn kin thc chuyn su hay hiu r datasheet ca chip. in hnh ST s dng th vin chun
CMSIS.
Ti s c gng gii thch y cc dng lnh trong cc bi vit nhng nhng on code gii thch ri th
ti s khng gii thch li trong bi sau, nhng on code thiu ti liu hay gii thch cha r rng ca ST ti cng s
rt gn hoc b qua bt khng gii thch, hoc do trnh chuyn mn ti cha cao i vi nhng lnh ny ti cng
s lc b gii thch mong bn c thng cm. Nu bn mun tm hiu su hn nhng code lc b phn gii thch
ny bn c th tr n ngun gc ca n, tm thanh ghi v tra datasheet c gii thch tt nht.
Mt nn tng rt cn thit l bn phi nm vng cu trc C khng phi ng ngng trc mt s dng
code nng cao.
u tin bn ti sample code c nh km bn trn sau vo ng dn GPIO\EWARM m file
Project.eww (IAR IDE Workspace) cho IAR hoc vo ng dn GPIO\MDK-ARM m file Project.uvproj (Vision4
Project) cho Keil.
D nhin khi xem mt chng trnh ti khuyn bn nn xem hm main trc v trong mt chng trnh C th
main lun thc thi trc. Bt u chng trnh main th dng th 9 s c thc hin trc n s nhy n hm
GPIO_Configuration(). Hm GPIO_Configuration() nm t dng 23 -> 39.

23 void GPIO_Configuration(void)
24 {
25 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOA,ENABLE);
26
27 /* Configure PB0 PB1 in output pushpull mode */
28 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
29 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
30 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
31 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
32 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
33 GPIO_Init(GPIOB, &GPIO_InitStructure);
34 /* Configure PA0 in input mode */
35 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
36 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
37 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
38 GPIO_Init(GPIOA, &GPIO_InitStructure);
39 }

V d nhin l trong bt k vi iu khin no th lnh s chy lin tc t trn xung di nn ti s gii thch
cc on code trn theo th t t trn xung di, mt lu l bn s thc mc tn bin hay hm ny l g, c nh
ngha nh th no?, nm u? mi trnh bin dch iu gip bn iu ny, bn c th click chut phi vo
bin(hm) cn tm chn tr n thng tin , ty vo trnh bin dch s c cch chn khc nhau. Ti c hng dn khi
qut cc bi gii thiu c bn v trnh bin dch IAR, Keil.
dng 25: dng lnh ny c ngha l bt clock ca khi GPIOA, GPIOB. Trong mi chip STM32 th iu
ny rt cn thit, mi ngoi vi u c mt cng tc bt nh trn, nu bn qun bc ny th chc chn bn s khng
th lm g c na. Sau ny khi bn lp trnh ngoi vi khc chng hn UART, SPI, I2C th bn u phi bc clock
khi ln chip mi c th cp xung nhp hot ng cho khi .
Dng 28: do phn cng ti chn s dng chn PB0, PB1 nn dng ny ti phi khai bo, nu thm nhiu
chn na th bn ch du "|", hoc nu mun s dng tt c cc chn cng lc bn c th dng GPIO_Pin_All s
STM32F4

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ngn gn hn rt nhiu. Ch l bn s dng chn no th khai bo chn , khng nn khai bo trn lang, nhiu khi
bn s lp trnh chn mt cng vic khc, hoc bn c th khai bo nhm ln chn np SWD th bn s khng np
c chip na m phi tm cch khc cu chip.
Dng 29: chn mode out.
Dng 30: chn ch pushpull, ch ny hay c s dng iu khin GPIO nht. cn mt mode khc
l Open drain mode ny s mc mt cp Fet thun nghch trc u ra ca chip, bn c th xem Reference manual
Figure 17 trang 186 hiu r.
Dng 31: chn tc u ra ca chn out, bn nn chn tc cao nht.
Dng 32: ch u ra nopull c ngha l khng c in tr ni ko ln mc cao v mc thp. Trn thc t
mode output th in tr ni khng c ngha g c.
Dng 33: bn ch "GPIO_InitStructure" l mt kiu cu trc trong C, kiu ny c khai bo dng th 3.
Hm GPIO_Init(GPIOB, &GPIO_InitStructure); truyn 2 i s xung thit lp thanh ghi cho phn cng.
T dng 35 -> 38 tng t nh cc bc trn. Ring dng 37 khai bo in tr treo mc cao. iu ny c
ngha l sao ???? Bn xem chn PA0 c ni vi nt nhn, vy trng thi khng nhn (thng h) th s khng xc
nh c trng thi ca n, nn phi thm in tr treo mc cao chn c treo ln mc cao, khi c treo ln
mc cao ri bn nhn nt xung mi c tc dng c, ngay lp tc ko chn PA0 xung mc thp do in tr ca
dy dn phi nh hn in tr treo mc cao.
Sau khi kt thc hm GPIO_Configuration() chng trnh quay tr li hm main. dng 12 bn thy hm
GPIO_ReadInputDataBit() c chc nng tr v 0 hoc 1, ty vo trng thi chn PA0 c v. Cu lnh if s nhn gi
tr ng-sai ny nhy vo dng 14 hoc 18, trng thi khng nhn c ngha l chn PA0 mc cao th chng trnh
nhy vo dng 14 set hai chn PB0-PB1 ln mc cao, theo nh trn s test bn trn th ch c LED-D2 sng, ngc
li trng thi nhn nt th LED-D1 sng.
Ngoi ra trong th vin stm32f4xx_gpio cn rt nhiu hm bn tham kho, ti trch ra t
stm32f4xx_gpio.h

/* GPIO Read and Write functions
**********************************************/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);

Bn trn cc hm nm trong file stm32f4xx_gpio.c u c ch thch y cng dng v chc nng, bn c th th
tng hm bit r cch hot ng ca chng.

@04. Code trong bi vit:
main.c:
01 #include "stm32f4xx.h"
STM32F4

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02
03 GPIO_InitTypeDef GPIO_InitStructure;
04 void GPIO_Configuration(void);
05 void Delay(__IO uint32_t nCount);
06
07 int main(void)
08 {
09 GPIO_Configuration();
10 while (1)
11 {
12 if(GPIO_ReadInputDataBit(GPIOA , GPIO_Pin_0))
13 {
14 GPIO_SetBits(GPIOB ,GPIO_Pin_0 | GPIO_Pin_1 );
15 }
16 else
17 {
18 GPIO_ResetBits(GPIOB ,GPIO_Pin_0 | GPIO_Pin_1 );
19 }
20 }
21 }
22
24 {
25 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOA, ENABLE);
26
39 }
40 void Delay(__IO uint32_t nCount)
41 {
42 while(nCount--)
43 {
44 }
45 }
46
47 #ifdef USE_FULL_ASSERT
48 void assert_failed(uint8_t* file, uint32_t line)
49 {
50 /* User can add his own implementation to report the file name and line number,
51 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
52
53 /* Infinite loop */
54 while (1)
55 {
56 }
57 }
58 #endif

STM32F4

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#02 : INTERRUPT STM32F4

@01. Gii thiu khi qut ngt v ngt ngoi:
Thut ng ngt (Interrupt) c dng rt nhiu trong vi iu khin, rt quan trng trong lp trnh tng tc vi
ngoi vi, vy ngt l g ??? ng dng lm g ??? Nh cc bn bit trong lp trnh vi iu khin lun phi tun th
quy tc tun t t trn xung di, v ch thc hin trong chng trnh chnh. Vy bn c bao gi thc mc nu nh
chng trnh chnh ca bn ngn qu nhiu thi gian thc hin, vy lm sao bn thc hin mt vic khc ngay tc thi
c. Ti v d mt chng trnh c bn sau:
void main(void){
while(1){
LED1 = 1;
delay_ms(1000);
LED1 = 0;
delay_ms(1000);
if(button)
LED2 = 1;
else
LED2 = 0;
}
}

Trong chng trnh ny LED1 s sng 1s v tt 1s c nh vy m lp li chu trnh. Ti mt thi im no
khi bn nhn nt nhn xung v chc chn l LED2 s khng sng lin ngay lc bn nhn, m phi i cho n khi
bng LED1 tt sau 1s dng chng trnh mi nhy n lnh if(). iu ny s lm bn kh chu, nhng chc chn l
cc lp trnh vin i trc s c cch gii quyt, v ti chn s dng ngt ngoi cho bi vit hm nay.
Ngt c ngha l mt s gin on chng trnh chnh, ngng thc thi chng trnh chnh m nhy n mt
a ch no gii quyt vn , sau khi x l xong s quay v chng trnh chnh ngay ti ni m ban ny n
thot khi chng trnh chnh. Ngt ngoi th ta s dng mt tn hiu bn ngoi to ra ngt, chng hn input trn
GPIO.

@02. Kt ni phn cng:

Bn vui lng kt ni phn cng nh bn
di tin cho bi vit hm nay.

STM32F4

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@03. Lp trnh ngt ngoi:
i vi s dng ngt dng STM32 ny bn cn lu l tuy ngt ngoi c th s dng trn bt k chn IO
nhng bn ch s dng c ti a 16 chn ngt ngoi. Gi s nu chn PA0 s dng ri th trn line0 bn
khng c s dng chn PB0 hay PC0... g na, l l do ch gii hn 16 ngt ngoi.
Dng 51 : l kt ni chn IO vi khi ngt, mt ngoi vi nu c lin quan n mi trng th mt iu chc
chn l bn phi to mt s lin kt ngoi vi vi chn IO bng cu lnh ny.
Dng 54 : bn trn c gii thiu, ngt trong STM32 c 16 line, khai bo line0 trng vi chn IO PB0.
Dng 55 : chn mode interrupt.
Dng 56 : chn ngt Falling (ngt xy ra khi tn hiu chuyn t mc cao xung mc thp), bn nn lu
ch ny mt tn hiu ngt xy ra trong thi im gi l tc thi, ngay thi im tn hiu chuyn t mc cao xung
mc thp (Falling) hay t mc thp ln mc cao (Rising). VD ngt ngoi c ly t nt nhn th ngt xy ra ngay
khi bn bm nt nhn t xung v thi im bn nh tay ra khi nt nhn. Trong STM32 c 3 mode ngt cho bn chn
la l Rising, Falling hay c Rising-Falling.
Sau khi khai bo xong cc dng trn xem nh bn hon tt cc th tc lin quan n ngt nhng vn t
ra l khi ngt chng trnh s nhy n u, nh trong hp ng bn d dng nh hng c ngt s nhy n a ch
ngt v thc hin chng trnh a ch vy trong C a ch s nm u??? S khng c a ch nhng c
thay th bng hm v cc hm lin quan n ngt ny s nm file stm32f4xx_it.c, file ny nm cng th mc vi
main.c cc hm ngt ny u c tn chun v c qun l bi phn cng NVIC interrupts (IRQ).
Dng 61 : khai bo ngt EXTI0_IRQn vi NVIC. Vi khai bo ny th hm ngt chc chn phi c tn l
EXTI0_IRQHandler, hm ny khng c i s truyn v nhn nn tn ca n trong stm32f4xx_it.c l void
EXTI0_IRQHandler(void) hm ny do bn to ch trnh bin dch khng t sinh ra. Bn nn ch ch n khai
bo v Handler hm ngt cn EXTI0_IRQ tn chung.
Hai dng 62 & 63 l khai bo u tin ngt s cng nh u tin cng ln. Trong trng hp bn s dng
rt nhiu ngt v chng trnh bn cn hm ngt no nn lm vic trc m bo tnh thi gian thc th hai dng
ny rt cn thit. bn c th tham kho chi tit ti hm misc.c ch thch gii thch rt r rng. Cha khai bo group th
mc nh l group0 (NVIC_PriorityGroup_0).
Hm EXTILine9_Config() cng tng t nh trn nn ti s khng gii thch thm, c mt im nh bn cn
lu dng 93 ti khai bo EXTI9_5_IRQn dng lnh ny c ngha l ngt t line5 -> line9 phi nhy chung n
mt hm ngt, tng t cho EXTI15_10_IRQn line 10 -> 15.
Trong hm main() ti cho bng LED D1 lin tc chp tt, khi xy ra mt s kin ngt VD nh bn nhn nt
S1 th LED D2 s thay i trng thi hin ti ca n. Nt nhn S1 ti chn mode falling nn thi im bn nhn xung
bng LED D1 s ngay lp tc thay i trng thi, cn nt S2 S3 ti chn mode rising nn khi bn nhn xung v nh
tay ln LED D3 D4 mi thay i trng thi. Trong qu trnh nhn bn s cm thy nhn khng nh l thuyt cho lm
v lc n lc khng, iu do nt nhn l tip im c kh khi bn nhn hay nh s gy nhiu tip im, trnh tnh
trng ny bn c th dng mt gii thut g gii quyt vn nhiu ny.

main.c
002
004 NVIC_InitTypeDef NVIC_InitStructure;
005 EXTI_InitTypeDef EXTI_InitStructure;
006
STM32F4

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008 void EXTILine0_Config(void);
009 void EXTILine9_Config(void);
011 int main(void)
012 {
014 EXTILine0_Config();
015 EXTILine9_Config();
016 while (1)
017 {
018 GPIO_ToggleBits(GPIOB,GPIO_Pin_1);
019 Delay(10000000);
020 }
021 }
022
023
025 {
027 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
028
029 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_4;
035 }
036
037 void EXTILine0_Config(void)
038 {
039 /* Enable GPIOB clock */
041 /* Enable SYSCFG clock */
042 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
043
044 /* Configure PB0 pin as input floating */
049
050 /* Connect EXTI Line0 to PB0 pin */
051 SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOB, EXTI_PinSource0);
052
053 /* Configure EXTI Line0 */
054 EXTI_InitStructure.EXTI_Line = EXTI_Line0;
055 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
056 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
057 EXTI_InitStructure.EXTI_LineCmd = ENABLE;
058 EXTI_Init(&EXTI_InitStructure);
059
060 /* Enable and set EXTI Line0 Interrupt to the lowest priority */
061 NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;
062 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
063 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
064 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
065 NVIC_Init(&NVIC_InitStructure);
066 }
067
STM32F4

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068 void EXTILine9_Config(void)
069 {
070 /* Enable GPIOB clock */
072 /* Enable SYSCFG clock */
073 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
074
075 /* Configure PB5 PB6 pin as input floating */
080
081 /* Connect EXTI Line5, Line6 to PB5,PB6 pin */
084
085 /* Configure EXTI Line5, Line6 */
086 EXTI_InitStructure.EXTI_Line = EXTI_Line5 | EXTI_Line6;
087 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
088 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
089 EXTI_InitStructure.EXTI_LineCmd = ENABLE;
090 EXTI_Init(&EXTI_InitStructure);
091
092 /* Enable and set EXTI Line5, Line6 Interrupt to the lowest priority */
093 NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
098 }
099
100
101
103 {
104 while(nCount--)
105 {
106 }
107 }
108
109
112 {
115
116 while (1)
117 {}
118 }
119 #endif

stm32f4xx_it.c
01 #include "stm32f4xx_it.h"
02
03 void NMI_Handler(void)
04 {
05 }
STM32F4

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06
07 void HardFault_Handler(void)
08 {
09 /* Go to infinite loop when Hard Fault exception occurs */
10 while (1)
11 {}
12 }
13
14 void MemManage_Handler(void)
15 {
16 /* Go to infinite loop when Memory Manage exception occurs */
17 while (1)
18 {}
19 }
20
21 void BusFault_Handler(void)
22 {
23 /* Go to infinite loop when Bus Fault exception occurs */
24 while (1)
25 {}
26 }
27
28 void UsageFault_Handler(void)
29 {
30 /* Go to infinite loop when Usage Fault exception occurs */
31 while (1)
32 {}
33 }
34
35 void DebugMon_Handler(void)
36 {}
37
38 void SVC_Handler(void)
39 {}
40
41 void PendSV_Handler(void)
42 {}
43
44 void SysTick_Handler(void)
45 {}
46
47 void EXTI0_IRQHandler(void)
48 {
49 if(EXTI_GetITStatus(EXTI_Line0) != RESET)
50 {
52 EXTI->PR = EXTI_Line0;
53 }
54 }
55
56 void EXTI9_5_IRQHandler(void)
57 {
59 {
62 }
64 {
STM32F4

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67 }
68 }

#03 : SYSTEM TICK STM32F4

@01. Gii thiu system tick:
System tick l b nh thi timer c lp vi cc timer ngoi vi, system tick c phn gii ti a 24bit v
khng c lnh c thanh ghi t system tick.
Ti cho bn mt v d c bn d hnh dung, nu bn mun lm mt ng h m thi gian th bn s d
dng kt hp lnh for v delay nhng khi vit trong chng trnh chnh thi gian m ca bn s khng phi l hng
s do mi khi bn thm mt dng lnh th thi gian trong chng trnh chnh ca bn dn ra. Trong trng hp ny
system tick s pht huy tc dng, nh cp bn trn system tick l mt timer m thi gian, mi khi ci t cho
system tick th system tick s nh thi khong bao lu nhy vo ngt , con s thi gian ny l hng s, vic nhy vo
ngt cng hon ton t ng.

@02. Kt ni phn cng:
Bn vui lng kt ni theo s bn di

STM32F4

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@03. Lp trnh system tick:
Vic ci t system tick ht sc n gin, ch gm 1 bc.
Dng 10 : ti mun c 1ms th nhy vo ngt mt ln c ngha l tn s l 1 Khz con s 1000 m ti in vo.
i s truyn vo cho hm SysTick_Config() l SystemCoreClock / 1000 = 168000 khng ln hn s 24bit
(SystemCoreClock c nh ngha l 168000000), c ngha l c 168000 ln m m mi ln m thi gian bng
1 chu k my, s nhy vo ngt thc hin mt ln (1 chu k my : 1/168000000 = 0.00595 us). Do l thuyt trn nn
ti rt gn li thnh mt cng thc n gin
SysTick_Config(SystemCoreClock / F)
Trong F l tn s hm ngt ca bn tnh bng n v Hz.
Bn quan st t dng 51 -> 59 hm ngt SysTick_Handler() trong file stm32f4xx_it.c cha chng trnh m ti s
thc hin mi 1ms/1 ln.

52 {
53 static uint32_t time=0;
54 if(++time>1000)
55 {
56 GPIO_ToggleBits(GPIOB ,GPIO_Pin_1);
57 time = 0;
58 }
59 }

Cc dng code trn c ngha l nu time > 1000 th s vo hm if thc hin thay i trng thi chn PB1 1 ln, mi ln
thay i trng thi chn PB1 = 1s. Khai bo kiu static lm cho bin time vn gi nguyn gi tr mi khi hm ngt
thc hin xong v thot ra ngoi.
Ngoi ra trong chng trnh chnh file main.c ti cho chn PB0 thay i trng thi tn s thp hn, rt d dng
quan st hai chn PB0 PB1 c hai tn s khc nhau.

main.c
02
06
07 int main(void)
08 {
10 SysTick_Config(SystemCoreClock / 1000);
11 while (1)
12 {
14 Delay(50000000);
15 }
16 }
STM32F4

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13

17
19 {
20 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOA, ENABLE);
21
34 }
36 {
37 while(nCount--)
38 {
39 }
40 }
41
44 {
47
49 while (1)
50 {
51 }
52 }
53 #endif
54
55

stm32f4xx_it.c
02
04 {
05 }
06
08 {
10 while (1)
11 {
12 }
13 }
14
16 {
18 while (1)
STM32F4

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14

19 {
20 }
21 }
22
24 {
26 while (1)
27 {
28 }
29 }
30
32 {
34 while (1)
35 {
36 }
37 }
38
40 {
41 }
42
44 {
45 }
46
48 {
49 }
50
52 {
54 if(++time>1000)
55 {
57 time = 0;
58 }
59 }

STM32F4

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#04 : TIMER STM32F4

@01. Gii thiu c bn v timer trong STM32F4:
Timer trong STM32F4 c rt nhiu chc nng chng hn nh b m Counter, PWM, Input Capture ngoi ra
cn mt s chc nng t bit iu khin ng c nh Encoder, Hall Sensors.
Trong STM32F4 Timer 1 v Timer 8 c cng tn s vi xung clock h thng, cc Timer cn li ch bng mt
na. Ring Timer 2 v Timer 5 l Timer 32bit, cc Timer cn li 16bit. Timer 6 v Timer 7 l 2 Timer vi cc chc
nng c bn khng giao tip c vi mi trng.

@02. Kt ni phn cng:
Bn vui lng kt ni nh s bn di.

@03. Lp trnh timer c bn:
Trong bi vit ny ti s thit lp ngt nh thi cho Timer 4, mi 1ms s nhy vo ngt mt ln, tng t nh
bi vit system tick. V Timer 2 ti s dng n o thi gian cc lnh x l chng trnh chnh sau quan st
bng STMStudio.
Ti s gii thch hm TIMbase_Configuration() bt u t dng 48 dng ny tham s TIM_Prescaler hiu
n gin nh mt b chia tn s. Tn s cao nht m clock timer 4 t c l 84Mhz sau khi qua b chia ny s ra
tn s clock timer(Fc_timer). Nh VD trn ti chn Fc_timer = 1Mhz <=> Fc_timer = 84000000/84. V
TIM_Prescaler c cng thc l: ((SystemCoreClock/2)/1000000)-1 = 83 , c l bn s thc mc ti sao khng phi l
con s 84 m li l 83, do h m bt u t 0 ch khng phi l 1 nh chng ta vn hay dng m s, bt u m
t 0 -> 83 s l 84 gi tr.
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Dng 49 : Period c ngha l chu k ca timer (khng phi l chu k ca 1 xung clock timer). Mt chu k gm
1000 xung clock m mi xung clock = 1us ta s c period l 1ms. Ti tr i cho 1 l v h m bt u t 0 nh
gii thch bn trn.
Dng 50 : TIM_ClockDivision c s dng trng hp nng cao c lin quan n dead-time v filters nn
ti s khng gii thch thm, bn nn gn TIM_ClockDivision = 0 nh mc nh.
Bn ch l do timer 4 l timer 16bit nn cc i s TIM_Prescaler v Period bn khng th gn gi tr ln
hn 65535(0xFFFF).
Dng 51 : chn mode counter m tng, c ngha l mi xung nhp timer, b m counter s t tng ln mt
gi tr theo chiu dng cho n khi no bng gi tr period s m li t u, ngi ta thng gi trng hp ny l
trn b m.
Dng 53 : ti thit lp ngt khi trn b m c thng s TIM_IT_Update, cn rt nhiu kiu ngt khc ty vo
nhu cu ca lp trnh vin, bn c th tr n nh ngha c r hn.
Ti xin nh km cho bn hnh bn di bn d hnh dung hn.

hm TIM2_Configuration() dng t 63 -> 74 ti thit lp mt cu hnh c bn khng ngt, ch timer 2 l
timer 32bit.
Quay li chng trnh chnh dng 22 ti dng bin lasttime c gi tr t counter timer 2 ngay thi im
lc . Tip ti thc hin 2 lnh GPIO_ToggleBits v Delay v ti tip tc c gi tr counter timer 2 lu vo bin
nowtime. Hiu ca hai bin trn s ra c s clock m 2 lnh trn thc hin, t bn c th suy ra thi gian thc
hin ca 2 lnh trn. Ti to bin debug bn quan st trn phn mm STMStudio, bn cn phi tham kho bi vit
v phn mm ny trc.

main.c
02
05 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
06
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08 void TIMbase_Configuration(void);
09 void TIM2_Configuration(void);
11
12 volatile int32_t debug;
13
14 int main(void)
15 {
16 int32_t nowtime,lasttime;
18 TIMbase_Configuration();
19 TIM2_Configuration();
20 while (1)
21 {
22 lasttime = TIM_GetCounter(TIM2);
24 Delay(1000);
25 nowtime = TIM_GetCounter(TIM2);
26 debug = nowtime - lasttime;
27 }
28 }
29
31 {
40 }
41
42
43 void TIMbase_Configuration(void)
44 {
45 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
46
47 /* Time base configuration */
48 TIM_TimeBaseStructure.TIM_Prescaler = ((SystemCoreClock/2)/1000000)-1; //
frequency = 1000000
49 TIM_TimeBaseStructure.TIM_Period = 1000 - 1;
50 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
51 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
52 TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
53 TIM_ITConfig(TIM4,TIM_IT_Update,ENABLE);
54 TIM_Cmd(TIM4, ENABLE);
55
56 NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
61 }
62
63 void TIM2_Configuration(void)
64 {
66
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68 TIM_TimeBaseStructure.TIM_Prescaler = 0;
69 TIM_TimeBaseStructure.TIM_Period = 0xFFFFFFFF;
74 }
75
76
78 {
79 while(nCount--)
80 {
81 }
82 }
83
84
87 {
90
91 while (1)
92 {}
93 }
94 #endif
95

stm32f4xx_it.c
02
04 {
05 }
06
08 {
10 while (1)
11 {}
12 }
13
15 {
17 while (1)
18 {}
19 }
20
22 {
24 while (1)
25 {}
26 }
27
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29 {
31 while (1)
32 {}
33 }
34
36 {}
37
39 {}
40
42 {}
43
45 {}
46
47
48 void TIM4_IRQHandler(void)
49 {
51 if (TIM_GetITStatus(TIM4, TIM_IT_Update) != RESET)
52 {
53 if(++time>1000)
54 {
56 time = 0;
57 }
58 TIM_ClearITPendingBit(TIM4, TIM_IT_Update);
59 }
60 }
STM32F4

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20

#05 : PWM STM32F4

@01. Gii thiu c bn v PWM:
PWM iu ch rng xung (Pulse-width modulation) l ngoi vi ph bin c h tr hu ht trong cc loi vi
iu khin, ng dng rng ri v nht l trong lnh vc iu khin ng c. n gin nht hiu PWM ti VD cho
bn nh sau : cu hnh output cho chn GPIO iu khin bng LED, nu bn mun lm sng bng LED theo hiu ng
m hay t, gii php l bn s cho bng LED sng tt tn s cao sao cho mt bn mt kh nng phn tch s sng
tt ca mt bng LED. Bn mun bng LED sng t th thi gian sng s nhiu hn thi gian tt, v ngc li. Trn
y ch l v d c bn nht bn hiu nh th no l PWM, bn vui lng xem hnh nh bn di hiu r hn.

Nh trn hnh rt r
- Duty cycle l t l phn trm mc cao.
- Period l chu k xung.
- Pulse width l gi tr mc cao so vi period.
Da trn nguyn l bn trn m trong STM32 hay cc loi vi iu khin khc iu h tr b to rng xung t
ng m bn khng phi tn thi gian bt tt chn IO, c th thit lp chu k, tn s, rng xung v mt s chc
nng c bit. PWM thuc khi timer.

@02. Kt ni phn cng:
Bn vui lng kt ni phn cng nh hnh bn di, nu c th bn thay cc bng LED bng oscilloscope hiu
r hn v qu trnh pht xung, chu k, tn s ca PWM.

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@03. Lp trnh PWM c bn:
Trong bi ti thit lp PWM1-2-3 v 3 knh o ca n tng cng 6 knh PWM xut ra mi trng.
Ti s gii thch hm TIM_PWM_Configuration() dng 19 -> 71
Trong bi Timer c bn vi STM32F4 ti thit lp timer c bn, PWM cng thuc khi timer nn PWM s s
dng period, prescaler, counter ca timer v cc khi nim ny ti gii thch rt k bi trc.
Dng 25 : chn s dng Mode AF (mode tnh nng ph tr) cho chn IO, mode ny khng phi l mode In hay
Out m do ngoi vi t ng thit lp In-Out.
Dng 34 -> 39 bn phi kt ni chn IO n khi timer 1 cho ng, bn xem datasheet phn Table 6.
STM32F40x pin and ball definitions trang 45 r s b tr chn ca STM32F405RGT(64 Pin)

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Dng 49 : Chn mode PWM1, trong timer c nhiu mode m ty theo ng dng bn la chn mode cho ph hp.
T OC m bn thy trong dng khai bo l vit tt ca t Output Compare.
Dng 50 : Cho php chn PWM hot ng.
Dng 51 : Chn cc mc cao cho u ra, nu bn chn mc thp th n s b o ngc hnh dng ca u ra,
Chu k, tn s u nh nhau.
Dng 52 - 53 : tng t nh dng 50-51 nhng khai bo cho knh o c ngha l chn c k hiu thm ch
N. Bn cn lu do vn d knh PWM v knh o ca n c nh ngha trong chip l trng thi o ca nhau
nn dng 50-51 v 52-53 ti khai bo ging nhau v n s t o khng cn bn phi can thip o li cc cc ca
PWM knh N.
Sau khi thit lp xong cc thng s bn phi truyn bin cu trc xung cho hm TIM_OC1Init() thit lp cho
knh PWM1, vn gi li cc thng s , tng t truyn cho PWM2 v PWM3.
Dng 58-61-64-66 : bt chc nng preload cho OC1, OC2 v OC3.
Bc cui cng trong hm TIM_PWM_Configuration() bn phi bt counter bt u hot ng timer.
dng 70 do ti s dng timer1 l timer c bit nn bn phi thc hin bc ny. S dng cc timer khc tr
timer1 v timer8 th bn khng cn bc ny.
Quay li chng trnh chnh t dng 12 -> 14 ti gn gi tr vo thanh ghi cha Pulse width ca PWM1-PWM2-
PWM3 tng ng vi 10-50-90% duty cycle.
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main.c
02
03 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
04 TIM_OCInitTypeDef TIM_OCInitStructure;
06
07 void TIM_PWM_Configuration(void);
08
09 int main(void)
10 {
11 TIM_PWM_Configuration();
12 TIM1->CCR1 = 10 * 65535 / 100; // 10% Duty cycle
15 while (1)
16 {}
17 }
18
19 void TIM_PWM_Configuration(void)
20 {
22 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB, ENABLE);
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23
24 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
25 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
28 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
30
33
34 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_TIM1);
38 GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_TIM1);
39 GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_TIM1);
40
42 TIM_TimeBaseStructure.TIM_Prescaler = 0;
43 TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // 65535
46
48
49 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
50 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
51 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
52 TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
53 TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
54 TIM_OCInitStructure.TIM_Pulse = 0;
55 //TIM_OCStructInit(&TIM_OCInitStructure);
56
57 TIM_OC1Init(TIM1, &TIM_OCInitStructure);
58 TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
59
62
65
66 TIM_ARRPreloadConfig(TIM1, ENABLE);
67
68 /* TIM1 enable counter */
70 TIM_CtrlPWMOutputs(TIM1, ENABLE);
71 }
72
74
75 /**
76 * @brief Reports the name of the source file and the source line number
77 * where the assert_param error has occurred.
78 * @param file: pointer to the source file name
79 * @param line: assert_param error line source number
80 * @retval None
81 */
83 {
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86
87 while (1)
88 {}
89 }
90 #endif
91
92

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#06 : ADC & DMA STM32F4

@01. Gii thiu ADC & DMA:
Cc tn hiu m bn thng gp trong t nhin chng hn nh in p, nh sng, m thanh, nhit u tn ti
di dng tng t c ngha l tn hiu lin tc v mc chia nh v hn. VD nh trong khong in p t 0 -> 5V
th bn s c v s khong gi tr in p, nh sng s tn ti t m cho ti sng t, m thanh t nh cho n ln.
Ngc li trong vi iu khin ch c khi nim s (digital), cu trc t nhn cho n b nh hot ng da trn cc
bng bn dn ch gm mc 0-1 nn bn mun giao tip vi chip th bn phi s ha trc khi a vo chip. Qu trnh
s ha c th thc hin bng nhiu cch v nhiu cng on nhng mc ch cui cng l vi iu khin hiu c
tn hiu tng t .
ADC (analog-to-digital converter) b chuyn i tn hiu tng t-s l thut ng ni n s chuyn i mt tn
hiu tng t thnh tn hiu s ha dng trong cc h s(digital) hay vi iu khin. Trong STM32 c h tr ADC
chuyn i tn hiu in p thnh tn hiu s vi phn gii 12bit. Ti s cho bn mt VD bn hiu qu trnh s
ha trong STM32 din ra nh th no, gi s ti cn o in p ti thiu l 0V v ti a l 3.3V, trong STM32 s chia
0->3.3V thnh 4096 khong gi tr (t 0 -> 4095), khi que o t chn IO c c 0 th tng ng 0V, c c
2047 tng ng 1.65V v c c 4095 tng ng 3.3V. y ch l mt v d c bn, trn thc t ADC l mt
ngoi vi thit yu ca dng STM32 nn gm rt nhiu chc nng, bn cn kin thc nn tn c th c hiu cc
chc nng ny.
Ngoi ra h tr qu trnh chuyn i ca ADC mt cch lin tc ti xin gii thiu vi bn khi nim v DMA.
DMA (Direct memory access) l mt k thut chuyn d liu t b nh n ngoi vi hoc t ngoi vi n b nh
m khng yu cu n s thc thi ca CPU, c ngha l CPU s hon ton c lp vi ngoi vi c h tr DMA m
vn m bo ngoi vi thc hin cng vic c giao, ty vo tng loi ngoi vi m DMA c s h tr khc nhau.

@02. Kt ni phn cng:
Bn vui lng kt ni nh hnh bn di
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@03. Lp trnh ADC c bn:
Ti s gii thch cho bn hm ADC_Config() t dng 22 -> 85, trong hm ny ti thit lp DMA v ADC cho 3
chn PC0-PC1-PC2.
Dng 29 : chn mode analog cho chn IO.
tip cn v hiu c cch hot ng ca DMA bn cn phi bit mt s khi nim c bn trong DMA, bn
c th tham kho khi qut trong ti liu Reference manual trang 211. Bi vit s dng ADC1 m ADC1 ch c h
tr bi DMA2, nm stream 0 channel 0, bn tham kho bng 34 DMA2 request mapping trang 217.
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Dng 33 : da vo bng trn channel c h tr l channel 0.
Dng 34 : bin DMA_Memory0BaseAddr s cha a ch ca bin ADCValue m ti khai bo dng 8 bn
trn. Ngoi ra ti cn p kiu bin ADCValue cng kiu vi bin DMA_Memory0BaseAddr . Mc ch dng ny
l mi khi c mt s truyn nhn d liu ca DMA d liu lp tc c gn t ng vo bin ny, hoc t ng
truyn bin ny n ngoi vi.
Dng 35 : gn a ch ca thanh ghi cha gi tr chuyn i ADC vo bin DMA_PeripheralBaseAddr ca DMA.
Dng 36 : chn hng chuyn d liu t ngoi vi n b nh.
3 dng bn s hot ng nh sau, khi c mt s kin chuyn i ADC xy ra, ngay lp tc DMA s ly d liu
t thanh ghi cha d liu ADC v gn vo bin ADCValue, vic lm ny hon ton t ng v c lp vi x l ca
CPU, hng d liu chuyn c chn dng 36.
Dng 37 : kch thc ca mng d liu, y c ngha l s phn t ca mng ADCValue.
Dng 38 : bn disable mode ny do nu bn bt mode ny th mi ln chuyn d liu th a ch ngoi vi s tng
dn, iu ny l khng cn thit v rt nguy him nu nh bn khng nm r a ch tr n tip theo.
Dng 39 : bn cn enable mode ny, mi khi chuyn i xy ra bn cn tng a ch b nh ca bn do bn trn
bin ADCValue c n 3 phn t, nu khng tng a ch ln th ch duy nht c bin ADCValue[0] l c d liu.
Dng 40 : chn kch thc thanh ghi cha d liu ca ngoi vi l HalfWord (kiu 16bit), ngoi ra cn c kiu
Byte (8bit), kiu Word(32bit).
Dng 41 : chn kch thc mng d liu ADCValue l HalfWord.
Dng 42 : chn mode DMA ch vng trn, c ngha l vic chuyn i lin tc lp li.
Dng 43 : thit lp ch u tin cao.
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Dng 55 : chn mode cho ADC, mode ny l mode n c bn khng s dng chc nng c bit, c rt nhiu
mode trong ADC, nhng bi vit hm nay th bn s dng mode ny.
Dng 56 : thit lp b chia 2, do ti s dng DMA nn khng xy ra ngt, s khng tn thi gian thc thi CPU
nn tt nht cho ADC ly mu tn s cao nht.
Dng 58 : thi gian tr gia 2 ln ly mu.
Dng 61 : chn phn gii ADC l 12bit.
Dng 64 : khng s dng ch convert bng tn hiu bn ngoi.
Dng 65 : canh l d liu lch phi, do thanh ghi ADC l 16bit nhng phn gii ch 12bit nn 12bit d liu
ny s c canh l v bn tri hoc bn phi ty ngi s dng.
Dng 66 : s knh ADC chuyn i.
Dng 70 - 72 : i s th 2 trong hm ADC_RegularChannelConfig bn tham kho datasheet trang 46, i s th
3 ti sp xp theo th t tng dn 1-2-3 c ngha l mi ln xy ra chuyn i cc knh s theo th t m chuyn i
bt u t s 1. i s th 3 chnh l thi gian ly mu ca ADC, s cng ln thi gian ly mu cng lu.

Quay li chng trnh chnh, bn cn s dng phn mm STMStudio debug quan st c 3 phn t ca mng
ADCValue. Qu trnh ly mu ADC hon ton c lp vi CPU, c xy ra s kin chuyn i th DMA t ng gn
gi tr chuyn i vo mng ADCValue.
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main.c
002
003 DMA_InitTypeDef DMA_InitStructure;
004 ADC_InitTypeDef ADC_InitStructure;
005 ADC_CommonInitTypeDef ADC_CommonInitStructure;
007
008 volatile uint16_t ADCValue[3]={0};
009
010 void ADC_Config(void);
011
012 int main(void)
013 {
014 ADC_Config();
015 while (1)
016 {
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017
018 }
019 }
020
021
022 void ADC_Config(void)
023 {
024 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
025 RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
026 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
027
028 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2;
029 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
030 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
031 GPIO_Init(GPIOC, &GPIO_InitStructure);
032
033 DMA_InitStructure.DMA_Channel = DMA_Channel_0;
034 DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADCValue;
035 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&(ADC1->DR));
036 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
037 DMA_InitStructure.DMA_BufferSize = 3;
038 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
039 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
040 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
041 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
042 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
043 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
044 DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
045 DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
046 DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
047 DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
048 DMA_Init(DMA2_Stream0, &DMA_InitStructure);
049
050 /* DMA2_Stream0 enable */
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051 DMA_Cmd(DMA2_Stream0, ENABLE);
052
053
054 /* ADC Common Init **********************************************************/
055 ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
056 ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2;
057 ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
058 ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
059 ADC_CommonInit(&ADC_CommonInitStructure);
060
061 ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
062 ADC_InitStructure.ADC_ScanConvMode = ENABLE;
063 ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
064 ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
065 ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
066 ADC_InitStructure.ADC_NbrOfConversion = 3;
067 ADC_Init(ADC1, &ADC_InitStructure);
068
069 /* ADC1 regular channels configuration */
070 ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_3Cycles);
073
074 /* Enable ADC1 DMA */
075 ADC_DMACmd(ADC1, ENABLE);
076
077 /* Enable DMA request after last transfer (Single-ADC mode) */
078 ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE);
079
080 /* Enable ADC1 */
081 ADC_Cmd(ADC1, ENABLE);
082
083 /* Start ADC1 Software Conversion */
084 ADC_SoftwareStartConv(ADC1);
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085 }
086
087
089 {
090 while(nCount--)
091 {
092 }
093 }
094
095
098 {
101
102 while (1)
103 {}
104 }
105 #endif
106

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#07 : USART STM32F4

@01. Gii thiu USART trong STM32:
USART (Universal synchronous asynchronous receiver transmitter) truyn nhn ni tip ng b v khng ng
b. Trong truyn thng ni tip d liu truyn s ni ui nhau trn mt hay vi ng truyn. u im ca truyn
thng ni tip l vi iu khin c kh nng truyn-nhn nhiu d liu, tit kim ng ng IO, nhng nhc im
l khng c nhanh nh truyn song song v d b mt, li d liu, phi c k hoch phng nga cc tnh hung ny.

Chun truyn thng ny tng thch vi RS232 ca PC nu c mt thit b chuyn i in p giao tip. Nu my
tnh bn khng c cng COM bn c th s dng thit b chuyn i USB to COM hoc USB to USART.
Di y l khung truyn chun ca USART v RS232.
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@02. Kt ni phn cng:
giao tip vi my tnh ta cn mt thit b kt ni vi my tnh qua chun RS232 hoc USB to USART, ti gii
thiu vi bn mch "usb to uart breakout board" S nguyn l, layout, driver ti nh km bn trn. Bn cng c
th mua sn phm mt s trang cung cp linh kin in t tit kim c thi gian lm mch.

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Sau khi lp rp board v ci driver hon chnh, bn vui lng kt ni nh s bn di. Ch kt ni theo kiu u
cho TX ny vo RX kia.

@03. Lp trnh USART c bn:
Trong bi vit ngy hm nay ti kt hp th vin chun ca C vi UART truyn nhn d liu, nn dng 2 ti
khai bo th vin stdio.h, nu bn no tng lp trnh C trn PC chc hn th vin ny rt quen thuc s dng cc
hm lin quan n xut nhp (printf, scanf).
Tip n ti s gii thch cho bn hm USART_Configuration() t dng 39 -> 69
Dng 57 : BaudRate l i s ti truyn t khai bo u hm USART_Configuration(), n c ngha l tc
baud (s bit truyn i trong 1s). Chng hn ti cho i s BaudRate l 9600 vy trong 1s truyn i 9600 bit v chu k
mi bit l c thi gian l 1/9600 = 1.04^-4s. i s ny cng cao thi gian truyn d liu cng nhanh nhng an
ton li cng gim, ngoi ra bn nn s dng tc baud vi mt quy chun quc t (chng hn 4800, 9600, 19200,
38400 )
Dng 58 : di khung truyn l 8bit.
Dng 59 : 1 stop bit.
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Dng 60 : khng kim tra chn l.
Dng 62 : chn ch truyn v nhn.
Dng 65-66 : kt ni chn IO n khi USART1.
Dng 68 : cho php USART1 bt u hot ng.
Quay li vi chng trnh chnh dng 30 ti s dng hm printf hm ny l hm xut d liu nn s lin quan
n th vin phn cng ca USART trong STM32.
Mi khi hm printf hot ng s nhy n hm PUTCHAR_PROTOTYPE dng 96 m c khai bo s
dng dng 16 bn trn.
Dng 100 : hm USART_SendData() s gi i 1 k t UART.
Dng 103 : ti thc hin mt vng lp m khi kt thc qu trnh truyn i 1 k t s t ng thot khi vng lp
ny.
Quay li dng 34-35 chng trnh chnh : ti s nhp mt s thc kiu float t my tnh v gn vo bin a bng
hm scanf, sau li tip tc truyn bin a ln my tnh bng hm printf.
Bi vit c ti build trn trnh bin dch IAR, trong trnh dch Keil hm scanf khng nhp k t vo c, hin
ti ti vn cha c hng gii quyt vi hm scanf ca Keil mong phin bn sau Keil s fix li ny.
Phn thit lp chun USART trong hm USART_Configuration() nh th no th phn mm trn PC bn phi
thit lp tng t c hai pha c ng b vi nhau

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Bn di y l video demo qu trnh truyn nhn t my tnh bng phn mm Terminal n board MiniTestF4.
Bn ch , trn video lc ti nhp d liu vo s d ra 1 s 0 ng trc mi s nhp vo, do li trnh dch lm mt k
t u khi nhn. Vd mun nhp vo s 0.12345 th bn phi thm trc s ny mt s bt k nh ti l 00.12345.

main.c
002 #include <stdio.h>
003
004 USART_InitTypeDef USART_InitStructure;
006
007 void USART_Configuration(unsigned int BaudRate);
008 void SendUSART(USART_TypeDef* USARTx,uint16_t ch);
009 int GetUSART(USART_TypeDef* USARTx);
010 /* Private function prototypes -----------------------------------------------*/
011 #ifdef __GNUC__
012 /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
013 set to 'Yes') calls __io_putchar() */
014 #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
015 #else
016 #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
017 #define GETCHAR_PROTOTYPE int fgetc(FILE *f)
018 #endif /* __GNUC__ */
019
021 {
022 while(nCount--)
023 {
024 }
025 }
026
027 int main(void)
028 {
029 USART_Configuration(38400);
030 printf(" Test\r");
031 while (1)
032 {
033 float a;
034 scanf("%f",&a);
035 printf("%3.5f\r",a);
036 }
037 }
038
039 void USART_Configuration(unsigned int BaudRate)
040 {
041 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
043
044 /* Configure USART Tx as alternate function */
STM32F4

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051
052 /* Configure USART Rx as alternate function */
056
057 USART_InitStructure.USART_BaudRate = BaudRate;
058 USART_InitStructure.USART_WordLength = USART_WordLength_8b;
059 USART_InitStructure.USART_StopBits = USART_StopBits_1;
060 USART_InitStructure.USART_Parity = USART_Parity_No;
061 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
062 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
063 USART_Init(USART1, &USART_InitStructure);
064
065 GPIO_PinAFConfig(GPIOB,GPIO_PinSource6,GPIO_AF_USART1);
066 GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);
067
068 USART_Cmd(USART1, ENABLE);
069 }
070
071 void SendUSART(USART_TypeDef* USARTx,uint16_t ch)
072 {
073 USART_SendData(USARTx, (uint8_t) ch);
074 /* Loop until the end of transmission */
075 while (USART_GetFlagStatus(USARTx, USART_IT_TXE) == RESET)
076 {}
077 }
078
079 int GetUSART(USART_TypeDef* USARTx)
080 {
081 while (USART_GetFlagStatus(USARTx, USART_IT_RXNE) == RESET)
082 {}
083 return USART_ReceiveData(USARTx);
084 }
085
086 /**
087 * @brief Retargets the C library printf function to the USART.
088 * @param None
089 * @retval None
090 */
091 GETCHAR_PROTOTYPE
092 {
093 return GetUSART(USART1);
094 }
095
096 PUTCHAR_PROTOTYPE
097 {
098 /* Place your implementation of fputc here */
099 /* e.g. write a character to the USART */
100 USART_SendData(USART1, (uint8_t) ch);
101
102 /* Loop until the end of transmission */
103 while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET)
104 {}
105
106 return ch;
107 }
108
110
111 /**
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112 * @brief Reports the name of the source file and the source line number
113 * where the assert_param error has occurred.
114 * @param file: pointer to the source file name
115 * @param line: assert_param error line source number
116 * @retval None
117 */
119 {
122
124 while (1)
125 {
126 }
127 }
128 #endif
129

STM32F4

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#08 : SPI STM32F4

@01. Gii thiu truyn thng SPI:
SPI (ting Anh: Serial Peripheral Interface, SPI bus Giao din Ngoi vi Ni tip, bus SPI) l mt chun ng
b ni tip truyn d liu ch song cng ton phn full-duplex (hai chiu, hai pha), do cng ty Motorola thit
k nhm m bo s lin hp gia cc vi iu khin v thit b ngoi vi mt cch n gin v gi r. i khi SPI cn
c gi l giao din bn-dy (ting Anh: four-wire).

Trong giao din SPI c s dng bn tn hiu s:
MOSI hay SI cng ra ca bn ch ng, cng vo ca bn b ng (ting Anh: Master Out Slave In), dnh cho vic
truyn d liu t thit b ch ng n thit b b ng.
MISO hay SO cng vo ca bn ch ng, cng ra ca bn b ng (ting Anh: Master In Slave Out), dnh cho
vic truyn d liu t thit b b ng n thit b ch ng.
SCLK hay SCK tn hiu ng h tct ni tip (ting Anh: Serial Clock), dnh cho vic truyn tn hiu ng h
tct dnh cho thit b b ng.
CS hay SS chn vi mch, chn bn b ng (ting Anh: Chip Select, Slave Select).
Trong nu l chip master s c quyn quyt nh xung nhp SCK (hay ch ng ngun xung nhp SCK).
ch song cng ton phn th trong cng mt thi im c hai thit b u c th pht v nhn d liu, y l
mt u th rt ln ca chun truyn thng ny.

Ngoi ra chip master c th giao tip vi nhiu chip slave trong cng mng v c nhiu phng php khc nhau.
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phng php ny chip master cn nhiu ng SS, c th thay th bng ng IO thng thng. Trong mt thi
im ch nn giao tip vi mt chip slave trnh trng hp cc chip slave y d liu v cng lc s gy li d liu
trn ng MISO.
Bn c th tham kho phng php nh hnh bn di c gi l "Daisy chain".

@02. Kt ni phn cng:
Bn vui lng kt ni nh s bn di
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@03. Lp trnh SPI c bn:
Trong bi hm nay ti s dng 2 b SPI, mt cho master v mt cho slave. Phn master th ti s dng ch
thng thng, khng ngt, khng DMA. Ring slave ti s dng ngt nhn, do thi im truyn d liu ca master l
khng bit trc nn cn dng ngt trnh mt d liu.
Bt u ti xin gii thch hm SPI_Configuration(), trong hm ny thit lp SPI cho c master v slave.
Dng 54 : chn ch truyn d liu song cng full-duplex, iu ny c th khng cn thit do trong v d ny
ti ch dng master truyn m khng nhn d liu, nhng bn cng c th nguyn nh trn v khng quan tm
n ch nhn.
Dng 55 : chn mode master cho SPI1.
Dng 56 : chn kch thc ca khung truyn l 8bit.
Dng 57-58 : hai dng lnh ny bn cn tham kho hnh bn di nm r d liu c ly mu cnh v
pha nh th no.
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Dng 59 : chn s dng chn SS bng phn mm, trn thc t bn c th khng cn quan tm do bn trn ti khai
bo mt chn IO (PA4) lm chc nng SS.
Dng 60 : b chia tn s ca SPI, sau khi qua b chia ny ta s suy ra c xung nhp trn chn SCK. Do ta s
dng SPI1 thuc khi APB2 nn tc ti a m ngoi vi trn khi ny t c l 84MHz. Ti chn b chia 256 vy
tn s ti a m chn SCK t c l 84MHz/256 = 328.125KHz.
Dng 61 : bit truyn i u tin l bit MSB c ngha l bit c trng s cao nht bit th 8.
phn khai bo cho slave cng tng t nh khai bo cho master, nhng mode hot ng l mode slave v thit
lp thm ngt khi qu trnh nhn d liu hon tt nh dng 95.
Kt thc hm ny bn cho c hai khi SPI ny hot ng.
chng trnh chnh dng 25 ti s dng 1 macro SS_DIS c ti nh ngha dng 9, vic lm ny ca ti
s rt tin li nu nh bn hay thay i cc chn IO, bn ch vic thay i bn trn m khng cn thay i ton b
chng trnh ca bn ang vit.
Dng 26 : ti s dng hm SPI_I2S_SendData() gi d liu t master ln ng truyn SPI, i s
SPI_data_send chnh l bin d liu cn truyn i, bn cn s dng b phn mm STMStudio quan st bin ny.
Dng 27 : vng lp ny by chng trnh, khi kt thc qu trnh truyn th s thot khi vng lp. Vic ny
trnh trng hp tc vi iu khin qu nhanh, d liu c cn cha truyn i ht th d liu mi c gi tip.
Mc ch s dng delay dng 29 l tr hon khon mc cao m master to ra trn SS, nu khng tr hon th
chng trnh quay li dng 25 lm slave cha kp pht hin ra tn hiu mc cao.
Khi c s kin nhn d liu trn slave lp tc chng trnh s nhy n hm ngt SPI2_IRQHandler() dng 59
trong file stm32f4xx_it.c.
Ti tip tc gii thch trn file stm32f4xx_it.c
dng 4 ti khai bo thm t kha extern main.c v stm32f4xx_it.c s dng chung bin SPI_data_get.
Dng 63 : khi c mt tn hiu ngt do qu trnh nhn hon tt ti s dng hm SPI_I2S_ReceiveData() ly d
liu trong thanh ghi ra v gn vo bin SPI_data_get.
Tip theo bn m phn mm STMStudio v quan st 2 bin SPI_data_send, SPI_data_get. Bin SPI_data_send s
c bn gn gi tr truyn i vo v bin SPI_data_get bn kim tra xem ng nh bin mnh truyn i cha.
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main.c
002
003 /* MASTER SLAVE
004 PA4 --- CONTROL_SS PB12 --- SPI2_SS
005 PA5 --- SPI1_SCK PB13 --- SPI2_SCK
006 PA6 --- SPI1_MISO PB14 --- SPI2_MISO
007 PA7 --- SPI1_MOSI PB15 --- SPI2_MOSI
008 */
009 #define SS_DIS GPIO_ResetBits(GPIOA, GPIO_Pin_4)
010 #define SS_EN GPIO_SetBits(GPIOA, GPIO_Pin_4)
011
012 volatile uint8_t SPI_data_send,SPI_data_get;
014 SPI_InitTypeDef SPI_InitStructure;
016
017 void SPI_Configuration(void);
019
020 int main(void)
021 {
022 SPI_Configuration();
023 while (1)
024 {
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025 SS_DIS;
026 SPI_I2S_SendData(SPI1, SPI_data_send);
027 while(SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE)==RESET);
028 SS_EN;
029 Delay(1000);
030 }
031 }
032
033 void SPI_Configuration(void)
034 {
035 /* SPI_MASTER configuration ------------------------------------------------*/
036 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
037 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
038
045 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
049
050 GPIO_PinAFConfig(GPIOA,GPIO_PinSource5,GPIO_AF_SPI1);
053
054 SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
055 SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
056 SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
057 SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
058 SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
059 SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
060 SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
061 SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
062 SPI_InitStructure.SPI_CRCPolynomial = 7;
063 SPI_Init(SPI1, &SPI_InitStructure);
064
065 /* SPI_SLAVE configuration ------------------------------------------------*/
067 RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
068 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
GPIO_Pin_15;
072
073 GPIO_PinAFConfig(GPIOB,GPIO_PinSource12,GPIO_AF_SPI2); // only connect to
077
078 SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
079 SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
080 SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
081 SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
082 SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
083 SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
084 SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
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085 SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
086 SPI_InitStructure.SPI_CRCPolynomial = 7;
087 SPI_Init(SPI2, &SPI_InitStructure);
088
089 NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
094
095 SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
096
097 /* Enable SPI_SLAVE */
098 SPI_Cmd(SPI2, ENABLE);
099 /* Enable SPI_MASTER */
100 SPI_Cmd(SPI1, ENABLE);
101 }
102
104 {
105 while(nCount--)
106 {
107 }
108 }
109
112 {
115
117 while (1)
118 {
119 }
120 }
121 #endif

stm32f4xx_it.c
03
04 extern uint8_t SPI_data_get;
05
07 {
08 }
09
11 {
13 while (1)
14 {
15 }
16 }
17
19 {
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21 while (1)
22 {
23 }
24 }
25
27 {
29 while (1)
30 {
31 }
32 }
33
35 {
37 while (1)
38 {
39 }
40 }
41
43 {
44 }
45
47 {
48 }
49
51 {
52 }
53
55 {
56
57 }
58
59 void SPI2_IRQHandler(void)
60 {
61 if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_RXNE) != RESET)
62 {
63 SPI_data_get = SPI_I2S_ReceiveData(SPI2);
64 //SPI_I2S_ClearFlag(SPI2, SPI_I2S_IT_RXNE);
65 }
66 }

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#09 : I2C STM32F4

@01. Gii thiu truyn thng I2C:
I2C (inter-integrated circuit) l chun truyn thng ni tip 2 dy gm 1 dy xung clock(SCL) v 1 dy d liu
(SDA). Cc chip ch-t c ni chung vi nhau trn hai ng dy ny v c ni vi in tr treo.

@02. Kt ni phn cng:
Bn vui lng kt ni nh bn di
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@03. Lp trnh I2C c bn:
Trong bi vit hm nay ti s dng 2 b I2C, I2C1 vai tr l chip master, I2C2 l chip slave. Master truyn d
liu theo kiu thng thng khng thit lp ngt v DMA, ring slave thit lp ngt s kin.
u tin ti s gii thch hm I2C_Configuration() t dng 35 ->102.
Dng 37 > 43 : y l cc on m tin x l trong C, in hnh dng 37 #ifdef FAST_I2C_MODE c ngha l
nu nh macro FAST_I2C_MODE c nh ngha th s thc hin 2 dng 38-39, nu FAST_I2C_MODE cha c
nh ngha th s thc hin 2 dng 40-41. dng 8 ti nh ngha s dng FAST_I2C_MODE.
Dng 51 : s dng I2C th bn phi chn mode OD (open drain) cu hnh cho GPIO.
Dng 52 : do kt ni phn cng ti khng s dng in tr treo ln mc cao nn ti phi cu hnh in tr treo ni
ln mc cao.
Dng 63 : lnh ny dng reset li cc thanh ghi ca khi I2C a v mc nh.
Dng 64 : chn mode hot ng l I2C, ngoi ra cn mt s chun khc da trn chun I2C nh SMBus.
Dng 65 : chn t l mc thp/mc cao ca xung clock. Macro I2C_DUTYCYCLE ny c nh ngha pha
bn trn dng 37.
Dng 66 : a ch ca thit b I2C, chip master c th khng cn thit do chip master l chip ch ng, chip
mun c giao tip vi chip khc. Ging nh khi bn mun gi n mt ngi no th bn cn s in thoi ca
ngi c gi m bn khng cn quan tm n s in thoi ca bn.
Dng 67 : bt xc nhn ACK.
Dng 68 : thit lp tc xung clock trn chn SCL, macro c nh ngha dng 37.
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Dng 69 : chn ch a ch 7 bit, mng I2C ca bn s c ti a l 128 thit b.
Phn thit lp cho slave tng t nh master, dng 81 thit lp a ch ca thit b slave, iu ny l rt quan
trng, trong giao tip I2C master giao tip vi slave th master phi bit c a ch ca thit b slave , ti
nh ngha a ch ny l 0x68. Dng 89 ti thit lp ngt li v ngt s kin trn slave, mi khi c mt hot ng g
trn ng truyn th slave s phn tch cc s kin ny hm ngt.
Kt thc hm I2C_Configuration(), ti tip tc gii thch phn u chng trnh.
Dng 12 : ti to mng MasterTxBuffer[] cha d liu m master truyn i, ti cng khi to sn d liu bn
trong mng ny l 1, 2, 3.
Dng 13 : mng cha d liu m master s nhn v.
Dng 14 : mng cha d liu slave pht i.
Dng 15 : mng cha d liu m slave nhn v. Mng ny s c hm ngt update d liu.
chng trnh chnh ti s dng hm I2C_ByteWrite() pht d liu ca mng MasterTxBuffer[] n slave, v
hm I2C_BufferRead() c d liu t slave pht n master, d liu nhn v s c gn vo mng
MasterRxBuffer[]. Hai hm ny c ti vit trong th vin MY_I2C.h.
Bn vui lng m file stm32f4xx_it.c. Qu trnh slave x l ch yu nm trong y.
dng 74 : mi khi c mt s kin truyn nhn d liu, a ch, ca slave s xy ra mt ngt v s c tr
n hm ny.
Ti xin xt trng hp slave truyn d liu, hon tt qu trnh ny s sinh ra rt nhiu ngt, ti s khi qut cc
bc m ngt ln lc thc hin:
Bc 1 : khi pht hin ra mt s kin trn ng truyn u tin n s nhy vo ngt
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED li dng vic ny ti gn Tx_Idx = 0 bin ny l
mt bin m th t d liu gi i.
Bc 2 : nu master mun slave gi d liu th ln ngt tip theo s nhy vo y, ngt ny ti s gi d liu
trong mng SlaveTxBuffer[] n master. Ngt ny s c thc hin nhiu ln, ti thc hin php tng bin Tx_Idx
mi ln xy ra ngt. Qu trnh xy ra cho n khi master khng mun nhn d liu na n s pht ra mt tn hiu kt
thc.
Bc 3 : bc cui trong qu trnh truyn d liu ca slave, n s nhy n ngt
I2C_EVENT_SLAVE_STOP_DETECTED dng 113.
Qu trnh nhn d liu ca slave cng xy ra tng t nh 3 bc trn nhng cc s kin c khc ph hp vi
qu trnh nhn. Bn tham kho dng t 101 -> 106.
chc chn s truyn nhn hon ton thnh cng bn c th s dng phn mm STMStudio kim tra li cc
bin nhn nh hnh bn di.
STM32F4

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main.c
002 #include "MY_I2C.h"
003
004 /* MASTER SLAVE
005 PB8 --- I2C1_SCL PB10 --- I2C2_SCL
006 PB9 --- I2C1_SDA PB11 --- I2C2_SDA
007 */
008 #define FAST_I2C_MODE
009 #define Slave_Address 0x68
010 #define BufferSIZE 3
011
012 volatile uint8_t MasterTxBuffer[BufferSIZE] = {1 , 2 , 3};
013 volatile uint8_t MasterRxBuffer[BufferSIZE];
014 volatile uint8_t SlaveTxBuffer[BufferSIZE] = {4 , 5 , 6};
015 volatile uint8_t SlaveRxBuffer[BufferSIZE];
016
018 I2C_InitTypeDef I2C_InitStructure;
020
021 void I2C_Configuration(void);
023
024 int main(void)
025 {
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026 I2C_Configuration();
027 while (1)
028 {
029 I2C_ByteWrite(I2C1, Slave_Address, (u8*)MasterTxBuffer,3);
030 I2C_BufferRead(I2C1, Slave_Address, (u8*)MasterRxBuffer,3);
031 while(1);
032 }
033 }
034
035 void I2C_Configuration(void)
036 {
037 #ifdef FAST_I2C_MODE
038 #define I2C_SPEED 400000
039 #define I2C_DUTYCYCLE I2C_DutyCycle_16_9
040 #else /* STANDARD_I2C_MODE*/
041 #define I2C_SPEED 100000
042 #define I2C_DUTYCYCLE I2C_DutyCycle_2
043 #endif /* FAST_I2C_MODE*/
044
046 RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
047 RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
048
049 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
GPIO_Pin_11;
051 GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
052 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // enable pull up resistors
055
056 GPIO_PinAFConfig(GPIOB,GPIO_PinSource8,GPIO_AF_I2C1); // only connect to
060
061 /************************************* Master ******************************/
062 /* I2C De-initialize */
063 I2C_DeInit(I2C1);
064 I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
065 I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE;
066 I2C_InitStructure.I2C_OwnAddress1 = 0x01;
067 I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
068 I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
069 I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
070 I2C_Init(I2C1, &I2C_InitStructure);
071 /* I2C ENABLE */
072 I2C_Cmd(I2C1, ENABLE);
073 /* Enable Interrupt */
074 //I2C_ITConfig(I2C1, (I2C_IT_ERR ) , ENABLE);
075 //I2C_ITConfig(I2C1, (I2C_IT_ERR | I2C_IT_EVT | I2C_IT_BUF) , ENABLE);
076 /************************************* Slave ******************************/
077 /* I2C De-initialize */
078 I2C_DeInit(I2C2);
079 I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
080 I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE;
081 I2C_InitStructure.I2C_OwnAddress1 = Slave_Address;
082 I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
083 I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
084 I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
085 I2C_Init(I2C2, &I2C_InitStructure);
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086 /* I2C ENABLE */
088 /* Enable Interrupt */
089 I2C_ITConfig(I2C2, (I2C_IT_ERR | I2C_IT_EVT | I2C_IT_BUF) , ENABLE);
090
091 NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
096
097 NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
102 }
103
105 {
106 while(nCount--)
107 {
108 }
109 }
110
113 {
116
118 while (1)
119 {
120 }
121 }
122 #endif

stm32f4xx_it.c
002
004 {
005 }
006
008 {
010 while (1)
011 {
012 }
013 }
014
016 {
018 while (1)
019 {
020 }
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021 }
022
024 {
026 while (1)
027 {
028 }
029 }
030
032 {
034 while (1)
035 {
036 }
037 }
038
040 {
041 }
042
044 {
045 }
046
048 {
049 }
050
052 {
053 }
054
055 void I2C2_ER_IRQHandler(void)
056 {
057 /* Check on I2C2 AF flag and clear it */
058 if (I2C_GetITStatus(I2C2, I2C_IT_AF))
059 {
060 I2C_ClearITPendingBit(I2C2, I2C_IT_AF);
061 }
062 }
063
064 /**
065 * @brief This function handles I2Cx event interrupt request.
066 * @param None
067 * @retval None
068 */
069 volatile uint32_t Event = 0;
070 volatile uint8_t Tx_Idx;
071 volatile uint8_t Rx_Idx;
072 extern uint8_t SlaveTxBuffer[];
073 extern uint8_t SlaveRxBuffer[];
074 void I2C2_EV_IRQHandler(void)
075 {
076 /* Get Last I2C Event */
077 Event = I2C_GetLastEvent(I2C2);
078 switch (Event)
079 {
080 /* ****************************************************************************/
081 /* Slave Transmitter Events */
STM32F4

u o@thanhduongvs
56

082 /* */
083 /* ****************************************************************************/
084
085 /* Check on EV1 */
086 case I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED:
087 Tx_Idx = 0;
088 I2C_ITConfig(I2C2, I2C_IT_BUF , ENABLE);
089 break;
091 case I2C_EVENT_SLAVE_BYTE_TRANSMITTING:
092 case I2C_EVENT_SLAVE_BYTE_TRANSMITTED:
093 I2C_SendData(I2C2, SlaveTxBuffer[Tx_Idx++]);
094 break;
095
096 /* ****************************************************************************/
097 /* Slave Receiver Events */
098 /* */
099 /* ****************************************************************************/
100
101 /* check on EV1*/
102 case I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED:
103 Rx_Idx = 0;
104 break;
105
106 /* Check on EV2*/
107 case I2C_EVENT_SLAVE_BYTE_RECEIVED:
108 case (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_SR1_BTF):
109 SlaveRxBuffer[Rx_Idx++] = I2C_ReceiveData(I2C2);
110 break;
111
113 case I2C_EVENT_SLAVE_STOP_DETECTED:
114 I2C_GetFlagStatus(I2C2, I2C_FLAG_STOPF);
116 break;
117
118 default:
119 break;
120 }
121 }

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