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Chng 1: Tng quan v h thng thng tin s




CHNG 1

TNG QUAN V H THNG THNG TIN S
1.1 V tr ca m ha knh trong h thng thng tin s
M ha knh l mt khu rt quan trng trong h thng thng tin s khng dy
cng vi m ha ngun, ghp knh, iu ch, to ra mt tn hiu ph hp cho
vic truyn dn v tuyn v tn hiu c kh nng iu khin c s sai bit v
sa cc li xy ra nu c c th khi phc li gn nh nguyn dng tn hiu tin
tc m mnh truyn i.


Hnh 1.1: V tr ca m ha knh truyn trong h thng thng tin s


M ho knh: mc ch l lm gim xc sut sai thng tin khi truyn qua knh
truyn.
Vic gim thiu xc sut sai da vic pht hin sai v sa sai c th dn n vic
gim t s tn hiu trn nhiu (SNR) cn thit nh gim c cng sut, tit kim
nng lng. Vic sa sai hu hiu cho tn hiu SNR nh s thun li cho vic bo
mt, tri ph v tng chnh xc ca thng tin nhn- mc ch quan trng nht ca
truyn thng.
1.2 Khi nim m ha knh v phn loi
1.2.1 Khi nim
M ha knh l vic a thm cc bit d vo tn hiu s theo mt quy lut no
y, nhm gip cho bn thu c th pht hin v thm ch sa c c li xy ra trn
knh truyn.
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Mt s h thng c th khc phc li bng cch gi mt yu cu cho bn pht
gi li tn hiu nu pht hin li, l ch ARQ. Nhng vic ny ch thch hp
cho cc h thng truyn dn hu tuyn v mt s h thng v tuyn khng yu cu
v thi gian tr. Thay vo , vi cc h thng thng tin khng dy ngy nay, ngi
ta hay s dng mt loi m c th pht hin v khc phc li mt cch t ng.
Vic ny gim thiu thi gian tr so vi cc h thng yu cu truyn li. B m ny
thng c gi l m iu khin li (ECC), hay chnh xc hn l FEC.
Mc ch ca l thuyt M ha trn knh truyn l tm nhng m c th truyn
thng nhanh chng, cha ng nhiu t m t hp l v c th sa li hoc t nht
pht hin cc li xy ra. Cc mc ch trn khng ph thuc vo nhau, v mi loi
m c cng dng ti u cho mt ng dng ring bit. Nhng c tnh m mi loi
m ny cn cn tu thuc nhiu vo xc sut li xy ra trong qu trnh truyn thng.
i vi mt a CD thng thng, li trong m thanh xy ra ch yu l do bi
v nhng vt xc trn mt a. V th, cc m c lng vo vi nhau. D liu
c phn b trn ton b mt a. Tuy khng c tt cho lm, song mt m ti
din n gin c th c dng lm mt v d d hiu. Chng hn, chng ta ly mt
khi s liu bit (i din cho m thanh) v truyn gi chng ba ln lin. Bn my
thu, chng ta kim tra c ba phn lp li trn, tng bit tng bit mt, ri ly ci no
c s bu cao nht. im khc bit y l, chng ta khng ch truyn gi cc bit
theo th t. Chng ta lng n vo vi nhau. Khi d liu ny, trc tin, c chia
ra lm 4 khi nh. Sau chng ta gi mt bit khi u tin, tip theo mt bit
khi th hai v.v tun t qua cc khi. Vic ny c lp i lp li ba ln phn b
s liu ra trn b mt a. Trong ng cnh ca m ti din n gin trn, vic lm
ny hnh nh khng c hiu qu cho lm. Song hin nay c nhng m c hiu
ng cao, rt ph hp vi vic sa li xy ra t ngt do mt vt xc hay mt vt
bi, khi dng k thut lng s liu ni trn.
Mi m thng ch thch hp cho mt ng dng nht nh. Vin thng trong v
tr b gii hn bi nhiu nhit trong thit b thu. Hin trng ny khng xy ra mt
cch t pht bt thng, song xy ra theo mt chu trnh tip din. Tng t nh
vy, modem vi di tn hp b hn ch v nhiu m tn ti trong mng li in
thoi. Nhng nhiu m ny c th c biu hin r hn bng mt m hnh tp m
tip din. in thoi di ng hay c vn do s suy sng nhanh chng xy ra. Tn
s cao c dng c th gy ra s suy sng tn hiu mt cch nhanh chng, ngay c
khi my nhn ch di ch vi phn Anh. Mt ln na, ngi ta hin c mt loi
m ha trn knh truyn c thit k i u vi tnh trng suy sng.
1.2.2 Phn loi m ha knh
L thuyt m ha i s c chia ra lm 2 loi m chnh
1. M khi.
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2. M trellis.
Chng phn tch ba c tnh sau ca m (ni chung) l:
Chiu di ca m.
Tng s cc t m hp l.
Khong cch Hamming ti thiu gia hai t m hp l.


Hnh 1.2: S phn chia m ha knh thnh hai nhnh ring bit
Trong mi loi m li c phn tch thnh 2 nhnh na l m tuyn tnh v
m khng tuyn tnh.
Thng th cc m khng tuyn tnh khng c ng dng trong thc t v cc
nhc im ca n, nn y chng ta ch cp n cc m tuyn tnh.
Trong phn tip theo chng ta s khi qut s lc v m khi v m trellis.
1.3 Khi qut v m khi v m trellis
1.3.1 M khi
M khi tuyn tnh mang tnh nng tuyn tnh, chng hn tng ca hai t m no
y li chnh l mt t m; v chng c ng dng vo cc bit ca ngun trn
tng khi mt; ci tn m khi tuyn tnh l v vy. C nhng khi m bt tuyn
tnh, song kh m chng minh c rng mt m no l mt m tt nu m y
khng c c tnh ny.
Bt c m khi tuyn tnh no cng c i din l (n,m,d
min
), trong
1. n, l chiu di ca t m, trong k hiu,
2. m, l s k hiu ngun c dng m ha tc thi,
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3. d
min
, l khong cch hamming ti thiu ca m.
C nhiu loi m khi tuyn tnh, nh
1. M vng (M Hamming l mt b phn nh ca m tun hon).
2. M chn l.
3. M Reed-Solomon.
4. M BCH.
5. M Reed-Muller.
6. M hon ho.
M khi c gn lin vi bi ton ng gi ng xu l bi ton gy mt s
ch trong nhiu nm qua. Trn b din hai chiu, chng ta c th hnh dung c
vn mt cch d dng. Ly mt nm ng xu, nm trn mt bn, ri dn
chng li gn vi nhau. Kt qu cho chng ta mt mu hnh lc gic tng t nh
hnh t ong. Cc m khi cn da vo nhiu chiu khc na, khng d g m hnh
dung c. M Golay c hiu ng cao, dng trong truyn thng qua khong khng
v tr, s dng nhng 24 chiu. Nu c dng l m nh phn (thng thy), cc
chiu m ch n chiu di ca t m nh nh ngha trn.
1.3.2 M trellis
M trellis hay cn gi l m chp (kt hp) c s dng trong cc modem di
tn m (V.32, V.17, V.34) v trong cc in thoi di ng GSM, cng nh trong cc
thit b truyn thng ca qun i v trang v trong cc thit b truyn thng vi v
tinh.
Mc ch ca vic to ra m chp l nhm lm cho tt c cc k hiu t m tr
thnh tng trng s ca nhiu loi k hiu thng ip trong nhp liu. N tng t
nh ton kt hp c dng trong cc h tuyn tnh bt bin dng tm xut liu
ca mt h thng, khi chng ta bit nhp liu v cc p ng xung.
Ni chung chng ta tm xut liu ca b m chp h thng, tc s kt hp ca
nhp liu bit, i chiu vi trng thi ca b m ha kt hp, hoc trng thi ca cc
thanh ghi.
V c bn m ni, m chp khng gip thm g trong vic chng nhiu hn mt
m khi tng ng. Trong nhiu trng hp, chng ni chung cho chng ta mt
phng php thc thi n gin hn, hn hn mt m khi c hiu qu tng ng.
B m ha thng l mt mch in n gin, c mt b nh, mt vi bin php
truyn thng tin phn hi bo tnh hnh, thng l cc cng loi tr XOR. B m
ha c th c thc thi trong phn mm hay phn sn.
Thut ton Viterbi l mt thut ton ti u nht c dng gii m cc m
chp. Hin c nhng phng php gim c gip vo vic gim khi lng tnh
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ton phi lm. Nhng phng php ny phn ln da vo vic tm tuyn ng c
kh nng xy ra cao nht. Tuy khng ngn gn, song trong mi trng nhiu thp
hn, ngi ta thng thy chng cho nhng kt qu kh quan. Cc b iu hnh vi
x l hin i c kh nng thc hin nhng thut ton tm gim c ni trn vi t
l trn 4000 t m trong mt giy.
ti ch yu nghin cu v thut ton gii m Viterbi thy c u im
ca thut ton trong vic gim ti thiu sai s khi m ha v gii m tn hiu. Do
, trong cc phn tip theo ca n, chng ta ch tm hiu vic m ha tin tc
dng m chp v gii m da trn thut ton Viterbi cng nh nhng u khuyt
im ca chng. ng thi ta tin hnh m phng thut ton trn Matlab v trn
Kit FPGA kim chng thc t hn. Cn i vi cc m trellis cn li th ta s
khng phn tch trong phm vi cun n ny.
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CHNG 2
THUT GII M VITERBI
2.1 Khi nim m chp
M chp l mt k thut m ha sa sai. M chp thuc h m li (m ha
theo Trellis) v c xy dng da trn mt a thc sinh hoc mt s chuyn
trng thi (trellis m) c trng. Qu trnh gii m ca m chp phi da vo trellis
m thng qua cc gii thut khc nhau, trong ni ting nht l gii thut Viterbi.
Ti sao gi l m chp v cu trc m ha c th biu din di dng php tnh
chp gia a thc sinh m v chui tn hiu c m ha.
M ha chp v thut ton gii m Viterbi c s dng trong khong hn mt
t in thoi, c th l ln nht trong cc loi thut ton c ng dng. Tuy nhin,
hin ti th thut ton x l viterbi c ng dng nhiu nht trong cc thit b m
thanh v hnh nh k thut s. Ngy nay, chng cn c s dng trong cc thit b
bluetooth.
Mc ch ca m ha knh truyn l nhm tng dung lng knh truyn, bng
cch cng thm vo tn hiu nhng d liu d tha c thit k mt cch cn thn
trc khi truyn ln knh truyn. M ha chp v m ha khi l 2 dng chnh ca
m ha knh truyn. M ha chp th da trn d liu ni tip, 2 hoc mt vi bit
c truyn mt lc, cn m ha khi th da trn mt khi d liu ln tng quan
(c trng l khong vi trm bytes). V d, m Redsolomon l mt m ha khi.
S khc nhau c bn gia m ha khi v m ha chp l m ha khi l m
ha khng nh. Cho mt chui d liu K bit, th ng ra ca b m ha khi l mt
khi d liu n bit duy nht. M ha chp khng kt ni cc khi bit ring vo trong
mt khi t m, thay vo n s chp nhn mt chui bit lin tc v ta thnh mt
chui ng ra. Hiu qu hay tc d liu ca m ha chp c nh gi bng t l
ca s bit ng vo k, v s bit ng ra n. Trong m ha chp l c mt vi b nh
dng ghi nh dng bit vo. Thng tin ny c s dng m ha cc bit tip
theo.
2.2 Biu din m chp
C ba phng php biu din m chp l: s li, s trng thi, v
s hnh cy. lm r phng php ny ta tp trung phn tch da trn v d
hnh 2.1 vi b m (2,1,3), a thc sinh (7,5).

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* S hnh cy:
Gi thit trng thi ban u ca cc thanh ghi dch trong b m u l trng thi
ton 0. Nu bit vo u tin l bit 0 th u ra ta nhn c chui 00, cn
nu bit vo u tin l bit 1 th u ra ta nhn c chui 11. Nu bit vo
u tin l bit 1 v bit vo tip theo l bit 0 th chui th nht l 11 v
chui th hai l chui 10. Vi cch m ho nh vy, ta c th biu din m
chp theo s c dng hnh cy (xem hnh 2.1).Vi hng ln l hng ca bit
0 i vo b m, nhnh i xung biu hin cho bit 1 c dch vo. T s
hnh cy ta c th thc hin m ho bng cch da vo cc bit u vo v thc
hin ln theo cc nhnh ca cy, ta s nhn c tuyn m, t ta nhn c
dy cc chui u ra.


*S hnh li:

Do c tnh ca b m chp, cu trc vng lp c thc hin nh sau: chui n
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bit u ra ph thuc vo chui k bit u vo hin hnh v (N-1) chui u vo trc
hay (N-1) k bit u vo trc . T v d hnh 2.1 ta c chui 2 bit u ra ph
thuc vo 1 bit u vo l 1 hoc 0 v 4 trng thi c th c ca hai thanh ghi
dch, l 00; 01; 10; 11. T s hnh cy trn, ta thy rng ti tng th 3,
c mi trng thi 00, 01, 10, 11 u c 2 nhnh n t cc trng thi trc ty
thuc vo bit c dch vo b m l bit 0 hay bit 1. Vi tnh cht ta c th biu
din m chp bng s c dng hnh li gn hn, trong cc ng lin nt
c k hiu cho bit u vo l bit 1 v ng t nt c k hiu cho cc bit
u vo l bit 0 (xem hnh 2.9). Ta thy rng t sau tng th hai hot ng ca
li n nh, ti mi nt c hai ng vo nt v hai ng ra khi nt. Trong hai
ng i ra th mt ng vi bit u vo l bit 0 v ng cn li ng vi bit u
vo l bit 1.

*S trng thi:
S trng thi c thc hin bng cch n gin s 4 trng thi c th
c ca b m (00, 01, 10 v 11) v trng thi chuyn tip c th c to ra t trng
thi ny chuyn sang trng thi khc, qu trnh chuyn tip c th l:


Next State/output symbol, if
Current State Input = 0: Input = 1:
00 00/00 10/11
01 00/11 10/00
10 01/10 11/01
11 01/01 11/10
Kt qu ta thu c s trng thi trong hnh 2.10 nh sau:

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Hnh 2.10: S trng thi ca b m chp (2,1,3)
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T s trng thi hnh 2.10, cc ng lin nt c k hiu cho bit u vo
l bit 0 v ng t nt c k hiu cho cc bit u vo l bit 1. So vi s
hnh li v s hnh cy th s trng thi l s n gin nht.
2.3 u nhc im ca m chp
2.3.1 u im
Cng nh cc m sa sai khc, m chp cho php chng ta c th sa li d liu
b sai lch khi truyn qua knh truyn khi phc chnh xc tn hiu gc.
Vic thc hin m ha dng m chp tng i n gin hn cc loi m sa sai
khc m cht lng m ha li tt.
Vic thc hin m ha dng m chp c th c thc hin bng phn cng v
phn mm.
Da trn hnh thc m ha m chp cng thut gii Viterbi cho n, cc b m
ha sau ny u k tha nhng c tnh u vit ca n.
2.3.2 Nhc im
Vic m ha v gii m lin quan n m chp ch gii quyt c cc li mt
bit cn i vi cc knh truyn xut hin nhiu bit lin tip th thut ton m ha v
gii m ny s khng cn hon ho na.
Knh truyn y phi l knh truyn t nhiu, v nu knh truyn nhiu qu
ln, m ha chp s khng cn tt na. Khi ta phi cn ti tri ph tn hiu
a tn hiu xung di mc nhiu gim thiu nh hng.


2.4 nh ngha thut ton Viterbi
Thut ton Viterbi l mt gii php c s dng ph bin gii m chui
bit c m ha bi b m ha tch chp. Chi tit ca mt b gii m ring ph
thuc vo mt b m ha tch chp tng ng. Thut ton Viterbi khng phi l
mt thut ton n l c th dng gii m nhng chui bit m c m ha bi
bt c mt b m ha chp no.
Thut ton Viterbi c khi xng bi Andrew Viterbi nm 1967 nh l mt
thut ton gii m cho m chp qua cc tuyn thng tin s c nhiu. N c s
dng trong c hai h thng CDMA v GSM, cc modem s, v tinh, thng tin v
tr, v cc h thng mng cc b khng dy. Hin nay cn c s dng ph bin
trong k thut nhn dng ging ni, nhn dng t m, ngn ng hc my tnh.
Thut ton gii m Viterbi l mt trong hai loi thut ton gii m c s
dng vi b m ha m chp- mt loi khc l gii m tun t. u im ca gii
m tun t so vi Viterbi l n c th hot ng tt vi cc m chp c chiu di
rng buc ln, nhng n li c thi gian gii m bin i.
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Cn u im ca thut ton gii m Viterbi l n c thi gian gii m n nh.
iu rt tt cho vic thc thi b gii m bng phn cng. Nhng m yu cu v
s tnh ton ca n tng theo hm m nh l mt hm ca chiu di rng buc, v
vy, trong thc t, ngi ta thng gii hn chiu di rng buc ca n K = 9 hoc
nh hn. Stanford Telecom to ra mt b gii m Viterbi K = 9 hot ng tc
n 96 kbps, v mt b gii m vi K = 7 hot ng vi tc ln n 45 Mbps.
Cc k thut khng dy nng cao c th to ra mt b gii m Viterbi vi K = 9
hot ng tc ln n 2 Mbps. NTT tuyn b rng h to c b gii m
Viterbi hot ng tc 60 Mbps, nhng tnh kh thi ca n vn cha c kim
chng.
2.5 Phn tch thut gii Viterbi
Chng ta s ly v d v m chp c tc m l k/n =


Hnh 2.11: B m chp tc
FF: thanh ghi dch. Ti mi xung clock, ni dung ca thanh ghi dch c dch qua
phi 1 bit. Bit u tin s l ng vo, v bit cui cng s l ng ra. Mt thanh ghi
dch c th s xem xt vic cng tr vo ng vo. Cc thanh ghi dch c th c
hiu nh l b nh ca b m ha. N ghi nh nhng bit u ca chui.
Thanh ghi dch c khi u vi tt c gi tr l 0.
Thut ton XOR: 1 1= 0; 1 0=1; 0 1=1; 0 0=0
Nu chng ta lm vic trn mt chui ng vo l 01011101, ng ra l 00 11
10 00 01 10 01 00
2
. B m ha ny cng c th c m hnh bi mt bng trng
thi hu hn. Mi mt trng thi c quy nh bi 2 bit nh phn- trng thi ca 2
thanh ghi dch. Mi mt s chuyn trng thi c quy nh bi w/v1v2 vi w i
din cho bit ng vo, v v1v2 l i din cho 2 bit ng ra, trong trng hp ny
chng ta lun lun c w = v1.
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Bng 2.1: Trng thi ng vo v ng ra ca b m ha tc


Next State/output symbol, if
Current State Input = 0: Input = 1:
00 00/00 10/11
01 00/11 10/00
10 01/10 11/01
11 01/01 11/10


Hnh 2.12: hnh trng thi ca m chp
By gi chng ta c th m t thut ton gii m, phn chnh l thut ton
Viterbi. C l, khi nim quan trng nht h tr cho vic hiu c thut ton
Viterbi l s Trellis. Hnh bn di cho chng ta thy s trellis cho v d
ca chng ta tc , m ha chp vi chiu di rng buc K = 3 vi bn tin 8
bit.

T=0 T=1 T=2 T=3 T=4 T=5 T=6 T=7 T=8 T=9 T=10

State 00






State 01






State 10







State 11

Hnh 2.13: Cc nhnh trong b m ha
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Bn trng thi c th ca b m ha c m t nh 4 hng ca nhng du
chm theo chiu ngang. C mt ct ca 4 chm cho trng thi khi u ca b m
ha v mt mi thi im ca bn tin. Cc ng in m kt ni cc im trong
s biu din cho s chuyn trng thi khi ng vo l mt bit 1. ng chm
chm l biu din cho s chuyn trng thi khi ng vo l bit 0. Ta c th thy r s
ph hp gia s trellis v hnh trng thi ni trn.
Hnh v bn di cho ta thy trng thi trellis cho ton b 8 bit ng vo. Cc bit
ng vo b m ha v k hiu ng ra c th hin bn di ca hnh.




State 00





State 01





State 10





State 11
T=0 T=1 T=2 T=3 T=4 T=5 T=6 T=7 T=8 T=9 T=10

ENC IN = 0 1 0 1 1 1 0 1 0 0
ENC OUT =
00 11 10 00 01 10 01 00 10 11

Hnh 2.14: ng i hon chnh khi phc chnh xc tn hiu ti ng ra.
Cc bit ng vo v cc k hiu ng ra ca b m th c th xem di cng ca
hnh trn. Ch s ph hp gia cc k hiu ng ra v bng ng ra chng ta
cp trn. Hy xem xt mt cch chi tit hn, s dng phin bn m rng ca s
chuyn i t mt trng thi tc thi n mt trng thi k tip nh hnh bn di:


State
00



State
01



State
10



State
11

Gi chng ta s xem xt cch thc gii m ca thut ton Viterbi. By gi
chng ta gi s l chng ta c mt mu tin m ha (c th c vi li) v chng ta
mun khi phc li tn hiu gc.
Gi s chng ta nhn c mu tin m ha trn vi 1 bit li.
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State 00




State 01




State 10





State 11
T=0 T=1 T=2 T=3 T=4 T=5 T=6 T=7 T=8 T=9 T=10

ENC IN = 0 1 0 1 1 1 0 1 0 0
ENC OUT =
00 11 10 00 01 10 01 00 10 11
RECEIVED =
00 11 11 00 01 10 01 00 10 11

ERRORS =

X


Hnh 2.15: Tn hiu nhn c 1 bit sai ti t =2
mi thi im chng ta nhn c 2 bit trong k hiu. Chng ta s tnh ton
thng s metric o khong cch gia nhng g m chng ta nhn c vi tt
c cc cp bit k hiu knh truyn c th m chng ta c th nhn c. i t thi
im t=0 n t=1, ch c 2 trng thi m chng ta c th nhn c l 00 v 11.
l bi v chng ta bit c b m ha tch chp bt u vi trng thi tt c u l
0 v cho 1 bit vo l 0 hay 1 th ch c 2 trng thi m chng ta c th i n v 2
ng ra ca b m ha. Nhng ng ra ny c trng thi l 00 v 11.
Thng s metric m chng ta s s dng l khong cch Hamming gia cp bit
ca k hiu nhn c v cp bit c th ca knh truyn. Khong cch Hamming
c tnh mt cch n gin bng cch m c bao nhiu bit khc gia cp bit nhn
c t knh truyn v cp bit so snh. Kt qu ch c th l 0, 1, 2. Gi tr ca
khong cch Hamming (hay thng s metric) m chng ta tnh ton mi khong
thi gian cho ng dn ca trng thi ti thi im trc v trng thi hin ti
c gi l metric nhnh (branch metric). thi im u tin, chng ta s lu
nhng kt qu ny nh l thng s metric tch ly, c lin kt n cc trng
thi. thi im th 2, thng s metric tch ly s c tnh ton bng cch cng
thm thng s metric tch ly trc vo metric nhnh hin ti.
thi im t=1, ta nhn c 2 bit 00. Ch c mt cp k hiu knh truyn
m chng ta c kh nng nhn c l 00 v 11. Khong cch Hamming gia
00 v 00 l bng 0. Khong cch Hamming gia 00 v 11 l 2. Do , gi
tr thng s metric nhnh cho nhnh ng vi s chuyn trng thi t 00 n 00
l 0 v cho nhnh t 00 n 10 l 2. Khi m thng s metric tch ly trc l
0 th thng s metric tng s chnh bng thng s metric ca nhnh va xt. Tng
t ta tnh c thng s metric cho 2 trng thi kia. Hnh bn di minh ha kt qu
ti thi im t= 1
Thc hin b gii m Viterbi trn FPGA Trang 28
Chng 1: Tng quan v h thng thng tin s














State
00



State
01



State
10



State
11

ENC IN =
ENC OUT =


T=0












0

00


T=1
Accumulated
Error Metric =
0







2
RECEIVED = 00


Hnh 2.16: Ti thi im t = 1
iu g s xy ra thi im t=2, chng ta nhn c mt cp k hiu knh
truyn l 11, trong khi cp k hiu knh truyn m chng ta c th nhn c
l 00 nu chuyn t trng thi 00 sang trng thi 00 v 11 khi chuyn t
trng thi 00 n trng thi 10, 10 khi chuyn t trng thi 10 n trng
thi 01, 01 khi chuyn t trng thi 10 n trng thi 11. Khong cch
Hamming gia 00 v 11 l 2, gia 11 v 11 l 0, gia 01 hoc 10 vi 11 l 1.
Chng ta cng cc thng s metric mi nhnh li vi nhau. thi im t=1 th
trng thi ch c th l 00 hoc 10, thng s metric tch ly s c cng vo l 0
hoc l 2 mt cch tng ng. Hnh bn di th hin s tnh ton thng s metric
tch ly thi im t=2.



State
00



State
01



State
10



State
11

ENC IN =
ENC OUT =


T=0














0

00


T=1


T=2



















1

11

Accumulated
Error Metric =
0 + 2 = 2



2 + 1 = 3



0 + 0 = 0



2 + 1 = 3
RECEIVED = 00 11

Hnh 2.17: Ti thi im t = 2
l tt c s tnh ton cho thi im t=2. ng nt m l metric nhnh
c la chn v theo cc nhnh , thng s metric l nh nht. Gi chng ta s
tnh thng s metric tch ly cho mi trng thi ti thi im t=3.
Gi chng ta hy nhn vo hnh minh ha cho thi im t=3. Chng ta s gp
phi mt t phc tp hn y, ti mi trng thi trong 4 trng thi ti t=3 s c 2
Thc hin b gii m Viterbi trn FPGA Trang 29
Chng 1: Tng quan v h thng thng tin s





















ng n t 4 trng thi ca thi im t=2. Chng ta s xoay s th no? Cu tr
li l, chng ta s tnh ton thng s metric tch ly lin quan ca mi nhnh, v
chng ta s b i gi tr metric ln hn, tc l s loi b nhnh i. Nu cp thng
s metric mi trng thi l bng nhau th chng ta s gi li c 2 trng thi. Chng
ta s k tha nhng tnh ton thc hin thi im t=2. Thut ton cng thng
s metric tch ly trc vo nhnh mi, so snh kt qu v chn thng s metric
nh hn (nh nht) tip tc dng cho thi im k tip, c gi l thut ton
cng-so snh-chn. Hnh bn di cho thy kt qu ca vic x l ti thi im t=3.




State
00



State
01



State
10




State
11

ENC IN =
ENC OUT =


T=0























0

00


T=1


T=2























1 0

11 10


T=3

Accumulated
Error Metric =
2+2 , 3+0 : 3



0+1 , 3+1 : 1



2+0 , 3+2 : 2



0+1 , 3+1 : 1
RECEIVED = 00
11 11

Hnh 2.18: Ti thi im t = 3
Ch l cp k hiu knh truyn th 3 m chng ta nhn c s c mt li.
Thng s metric nh nht hin ti l 1.
Chng ta hy xem iu g xy ra thi im t=4. Tin trnh x l cng ging
nh thi im t=3. Kt qu xem hnh bn di




State
00



State
01



State
10




State
11

ENC IN =
ENC OUT =


T=0






















0

00


T=1


T=2






















1 0

11 10


T=3






















1

00


T=4

Accumulated
Error Metric =
3+0 , 1+2 : 3



2+1 , 1+1 : 2



3+2 , 1+0 : 1



2+1 , 1+1 : 2
RECEIVED =
00

11 11 00

Hnh 2.19: Ti thi im t = 4
Thc hin b gii m Viterbi trn FPGA Trang 30
Chng 1: Tng quan v h thng thng tin s


00
00 00 00 00
11 11 11
11 11 11 11 11
00 00 00
10 10 10 10
01 01 01
01
01 01 01
10 10 10


Ch l thi im t=4, ng trellis ca tin tc thc s truyn i c xc
nh bng ng in m, vi thng s metric tch ly l nh nht. Hy xem xt
thi im t=5:




State
00



State
01



State
10



State
11


T=0


T=1


T=2


T=3


T=4


T=5

Accumulated
Error Metric =
3+1 , 2+1 : 3



1+2 , 2+0 : 2



3+1 , 2+1 : 3



1+0 , 2+2 : 1

ENC IN = 0 1 0 1 1
ENC OUT =
00 11 10 00 01
RECEIVED =
00 11 11 00 01

Hnh 2.20: Ti thi im t = 5
thi im t=10, s trellis s nh th ny, cc nhnh ko c chn c
b i:




State 00





State 01





State 10





State 11
T=0 T=1 T=2 T=3 T=4 T=5 T=6 T=7 T=8 T=9 T=10

ENC IN = 0 1 0 1 1 1 0 1 0 0
ENC OUT =
00 11 10 00 01 10 01 00 10 11

RECEIVED =
00 11 11 00 01 10 01 00 10 11

ERRORS =

X


Hnh 2.21: Tt c d liu c gii m v sa sai chnh xc
Kt qu y cho thy chng ta gii m ng chui d liu gc. Nu chng
ta nhn li con ng chng ta tm ra d liu gc l bng cch so snh d liu
nhn c vi d liu so snh ca b gii m c c t bng trng thi. iu ny
cho thy chng ta ang s dng thut ton gii m da trn s ging nhau ln nht.
Thc hin b gii m Viterbi trn FPGA Trang 31
Chng 1: Tng quan v h thng thng tin s




Vic x l gii m bt u vi xy dng mt thng s metric tch ly cho mt s
cp k hiu knh truyn nhn c, v lu gi trng thi mi thi im t m
thng s metric l nh nht. Mt khi thng tin ny c dng ln th b gii m
viterbi sn sng khi phc li chui bit a vo b m ha chp, khi mu tin
c m ha truyn i. iu ny t c bng nhng bc sau:
o u tin, chn mt trng thi c thng s metric nh nht v lu li s trng
thi ca trng thi .
o S dng lp li cho nhng bc k tip mi cho n khi bt u ca trellis
t c: da vo bng ghi nh trng thi cho trng thi c chn, chn
mt trng thi mi c lit k trong bng ghi nh trng thi khi chuyn t
trng thi trc n trng thi . Lu s trng thi ca mi trng thi c
chn. Bc ny c gi l truy hi (traceback).
o Chng ta lm vic tip vi danh sch nhng trng thi c chn c
lu trong bc x l trc . Chng ta tra xem bit ng vo no ph hp vi
s truyn dn t mi trng thi trc n trng thi k tip. y l bit m
phi c m ha bng m tch chp.
Bng sau cho chng ta thy ma trn tch ly ca y 8 bit (cng vi 2 bit ph
thm) ca bn tin mi thi im t:
Bng 4.2: Bng ma trn tch ly ca c 8 bit ca bn tin




Ch rng v d v b gii m Viterbi ng vo quyt nh cng ny, thng
s metric tch ly nh nht trng thi cui ch ra c c bao nhiu li k hiu
knh truyn xy ra.
Bng lch s trng thi bn di cho thy trng thi tn ti trc cho mi trng
thi ti thi im t:
Thc hin b gii m Viterbi trn FPGA Trang 32
Chng 1: Tng quan v h thng thng tin s




Bng 2.3: Bng lch s trng thi


Tng ng 0,1,2,3 l cc v tr 00,01,10,11
2
.
Bng sau cho thy trng thi c la chn khi truy hi ng dn t bng trng
thi tn ti trn:


Bng 2.4: Bng cc trng thi c la chn khi truy hi


S dng bng ta thy c s chuyn i trng thi n cc ng vo gy ra chng,
gi chng ta c th to li bn tin gc. Bng ny rt ging vi v d ca chng ta
b m ha chp tc v K= 3.
Bng 2.5: Bng trng thi k tip


Ghi ch: trong bng trn, x ch ra l mt s chuyn trng thi khng th xy ra
t mt trng thi n mt trng thi khc.
Thc hin b gii m Viterbi trn FPGA Trang 33
Chng 1: Tng quan v h thng thng tin s












By gi chng ta c tt c cc cng c cn thit ti to li bn tin gc t bn
tin m chng ta nhn c.
Bng 2.6: Bng cha cc d liu ca bn tin gc c khi phc


Hai bit ph c b qua.
Lm th no m thut ton truy hi cui cng cng tm ra con ng i ng
nht ca n thm ch nu n chn trng thi ban u l sai. iu ny c th xy ra
nu c hn mt trng thi c thng s metric tch ly l nh nht. Chng ta s dng
li hnh 2.18 lm sng t iu ny:



State
00



State
01



State
10



State
11

ENC IN =
ENC OUT =


T=0





















0

00


T=1


T=2





















1 0

11 10


T=3

Accumulated
Error Metric =
2+2 , 3+0 : 3



0+1 , 3+1 : 1



2+0 , 3+2 : 2



0+1 , 3+1 : 1
RECEIVED = 00
11 11

thi im t=3, c 2 trng thi 01 v 11 u c thng s metric l 1.
ng i ng i n trng thi 01, ch l ng in m l ng i thc s
ca bn tin n trng thi ny. Nhng gi s chng ta chn trng thi 11 bt
u qu trnh truy hi ca chng ta. Trng thi trc ca trng thi 11 l trng
thi 10, cng l trng thi trc ca trng thi 01. iu ny l bi v thi
im t=2, trng thi 10 c thng s metric tch ly l nh nht. V vy, sau trng
thi bt u sai, chng ta c th ngay lp tc tr li vi tuyn ng ng.
Vi v d v bn tin 8 bit, chng ta tin hnh xy dng mt s trellis cho
ton b bn tin trc khi bt u qu trnh truy hi. Vi cc bn tin di hn hoc
cc chui d liu lin tc, iu ny l khng thc t, bi v b nh chiu di rng
buc v s tr hon trong gii m. Nghin cu cho thy l su truy hi ca Kx5
ch cho vic gii m viterbi vi loi b m m chng ta ang tho lun. Bt c
mt s truy hi su hn s lm tng thi gian delay gii m v b nh yu cu cho
Thc hin b gii m Viterbi trn FPGA Trang 34
Chng 1: Tng quan v h thng thng tin s




vic gii m v cng ko lm tng hiu qu vic gii m, ngoi tr b m ha thng
(punctured code) m chng ta s ni sau.
thc thi mt b gii m Viterbi bng phn mm, bc u tin l phi xy
dng mt vi cu trc d liu xoay quanh thut gii m s c thc thi. Nhng
cu trc d liu ny c thc thi tt nht khi l cc mng. Su mng chnh m
chng ta cn cho b gii m viterbi l:
- Mt bn sao ca Bng tri thi k tip ca b m ha m chp, bng
chuyn trng thi ca b m ha. Kch c ca bng ny (hng x ct) l 2
(K-1)
x 2
K
. Mng ny phi c khi u trc khi bt u tin trnh gii m.
- Mt bn sao ca bng ng ra ca b m ha m chp. Kch c ca bng
ny l 2
(K-1)
x 2
K
. Mng ny cng cn phi c khi u trc khi bt u
tin trnh gii m.
- Mt mng lu tr trng thi hin ti v trng thi k ca b m ha m
chp, vi gi tr ng vo (0 hoc 1) s cho ra trng thi k tip v trng thi
hin ti. Chng ta s gi bng ny l bng ng vo. Kch thc ca bng l
2
(K-1)
x 2
(K-1)
. Mng ny cng cn phi c khi u trc khi bt u tin
trnh gii m.
- Mt mng lu tr lch s cc trng thi trc cho mi trng thi ca b
m ha cho Kx5 + 1 cp k hiu knh truyn nhn c. Chng ta s gi
bng ny l bng lch s trng thi. Kch thc ca mng ny l 2
(K-1)
x
(Kx5 +1). Mng ny khng cn khi ng trc khi bt u tin trnh gii
m.
- Mt mng lu tr thng s metric tch ly cho mi trng thi c tnh
ton s dng nguyn tc cng- so snh- la chn. Mng ny s c gi l
mng thng s metric tch ly. Kch thc ca mng ny l 2
(K-1)
x 2.
Mng ny khng cn khi ng trc khi bt u tin trnh gii m.
- Mt mng dng lu tr danh sch cc trng thi c quyt nh trong
sut qu trnh truy hi. N c gi l mng chui trng thi. Kch thc
ca mng ny l (Kx5 + 1). Mng ny khng cn khi ng trc khi bt
u tin trnh gii m.
Gi chng ta hy ni v tc ca nhng b m ha chp m c th c gii
m bi cc b gii m Viterbi. trn chng ta cp n b m ha thng, l
mt hng chung ca b m ha tc cao, tc ln hn t k n n. Punctured
code c to ra bi d liu m ha u tin s dng mt b m ha tc 1/n
nh l b m ha th d c m t trc y v sau xa b mt vi k hiu
knh truyn ng ra ca b m ha. Qu trnh ny c gi l puncturing. V d,
to ra m tc t m tc , th n gin l s xa k hiu knh truyn
theo mu punctured sau y:
Thc hin b gii m Viterbi trn FPGA Trang 35
Chng 1: Tng quan v h thng thng tin s




Bng 2.7: V d v punctured code


Trong , bit 1 ch ra rng mt k hiu knh truyn s c truyn, v bit
0 ch ra rng mt k hiu knh truyn s c xa. xem lm th no m
vic ny c th to ra b m tc . Hy ngh l mi ct ca bng trn tng ng
vi mt bit ng vo n b m ha v mi mt bit 1 trong bng tng ng vi
mt k hiu knh ng ra. C 3 ct trong bng v 4 bit 1. Thm ch bn c th
to ra b m tc 2/3 s dng mt b m ha vi mu puncturing sau:


vi 2 ct v 3 bit 1.
gii m mt punctured code, bit 1 phi thay th nhng k hiu rng cho
nhng k hiu b xa ng vo ca b gii m Viterbi. K hiu rng c th l k
hiu c lng t n mc 1 yu v mc 0 yu hoc hn na c th l mt k
hiu c c bit, m khi c x l bng mch ACS trong b gii m, kt qu l
khng thay i thng s metric tch ly t trng thi trc.
D nhin, n khng phi bng 2. V d, mt m tc 1/3 v K=3 (7,7,5) c
th c m ha s dng b m ha nh bn di:


Hnh 2.22: B m tc 1/3 v K= (7,7,5)
Thc hin b gii m Viterbi trn FPGA Trang 36
Chng 1: Tng quan v h thng thng tin s




B m ha ny c 3 b cng modulo, v vy vi mi mt bit ng vo, c th to
ra 3 ng ra k hiu knh truyn. D nhin, vi mu puncturing ph hp, bn c
th to ra nhng m tc cao hn s dng b m ha ny.
2.6 Gii m quyt nh cng v gii m quyt nh mm
Gii m quyt nh mm v quyt nh cng da vo loi lng t ha c
s dng cc bit nhn c. Gii m quyt nh cng s dng loi lng t ha
1 bit trn cc gi tr knh nhn c. Gii m quyt nh mm s dng loi lng
t ha nhiu bit trn cc gi tr knh nhn c. i vi gii m quyt nh mm
l tng (lng t ha khng xc nh), cc gi tr knh nhn c c s
dng trc tip trong b gii m ha knh. Hnh 2.23 biu din gii m quyt
nh cng v quyt nh mm.

Hnh 2.23: Gii m quyt nh cng v mm

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