16-bit Segmented Type Current Steering DAC for Video Applications
Gaurav Raja† & Basabi Bhaumik‡
Department of Electrical Engineering,
Indian Institute of Technology, Delhi, INDIA.
Abstract
In this paper, 16-bit, 50 MHz Current Steering DAC is
designed. This DAC is implemented using TSMC 0.35 µm
technology. An optimum segmentation is done of 16-bits
into binary and thermometric bits. The integral non-
linearity (INL) and differential non-linearity (DNL) is
less than 0.3 LSB and 0.1 LSB respectively. It occupies
only 0.06 mm2 area. The average total power
consumption is 165 mW. A novel technique has been
applied to reduce the glitch energy. The design is
implemented with the matching requirements, required
for current sources.
Index Terms – Digital-to-Analog Conversion,
Segmentation, Matching.
1. Introduction
Wireless and wired line communication systems,
such as cellular base stations and cable modems, video
signal processing, computer graphics, require high speed
and high resolution digital-to-analog converters. Current
steering DACs, in which an array of current sources are
steered to the output resistive load directly depending on
the digital input code, are commonly used for these high
speed applications.
Thermometer architectures of current-steering
DACs, have guaranteed monotonicity. Also, the matching
requirement is significantly less, as 50% matching of the
unit current source results in a DNL of under 0.5 LSB.
Also, glitches do not contribute to non-linearity in
thermometer case because the size of the glitch in
thermometer-coded DACs is proportional to the number
of switches that switch at a given sample time. But, the
major drawback of thermometer architecture is that as the
number of bits increases, the area increases significantly.
On the other hand, in binary architecture, the output can
change by substantially more than 1 LSB, causing a
potentially substantial glitch, because during midcode
transitions, the MSB source varies in one direction and
†
Gaurav Raja is presently working with Intel India Pvt Ltd,
Bangalore, India. (Email: gauravraja07@rediffmail.com)
‡
Basabi Bhaumik is a professor in Department of Electrical Engg,
IIT Delhi, INDIA. (Email: bhaumik@ee.iitd.ernet.in)
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Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
the LSB sources vary in another direction. Also, the
severity of the matching problem is determined by the
weight of the bit. So, the matching of the MSB current
source transistor must be extremely accurate. But, for
high bit resolution, binary architecture requires
significantly less area than thermometer architecture.
So, there are many trade-offs between thermometer and
binary architectures.
In this design, an optimum segmentation of
bits is done into binary and thermometer type, to have
the minimum area requirement, maintaining INL < 1.0
LSB, and DNL < 0.5 LSB. Also, the thermometer bits
are split into two groups to reduce area requirement. In
this design, the current source dimensions are designed
taking all these process mismatches into consideration.
Major problem associated with current steering
architecture is that if the current required is large, then
the dimension of switch, SW1 & SW2 [Fig. (1)] becomes
so large, that a glitch of significant height occurs. In
this design, a novel technique has been implemented to
reduce this glitch height.
VA
VB
in SW1 SW2
in bar
out out bar
Fig. 1 : Current Steering Cell
Section II discusses about the optimum value
of segmentation for a segmented architecture. Section
III deals with the current source mismatch variation
with respect to yield. Section IV deals with the circuit
architecture and obtained results.
2. Optimum Segmented Architecture for
minimum Area
The major issue in current steering segmented
architecture is of optimum segmentation. For a given
 INL and DNL requirement, Lin and Bult [2] have done
the area analysis for 10-bits resolution. In this paper, an
analysis for 16-bits resolution is done. This issue is
analyzed via a MATLAB simulation. First an analysis is
done for only binary coded and only thermometer coded
DAC. If same analog area is taken for both the
architecture, and if thermometer coded architecture gives
DNL of σ, then binary weighted gives 2 N σ, where N
is the total number of bits, and σ is standard deviation of
current source value. Also, for this same area, both
architectures give INL of 0.5* 2 N σ [2].
Since, area α (1/σ2), so a calculation is done for
both the architectures, assuming that Aunit is the minimum
area required by the thermometer architecture to obtain
DNL = 0.5 LSB. The results are summarized in Table 1.
Table 1. Area requirements for specific INL/DNL
Requirement Thermometer Binary
Coded Weighted
Area (DNL = Aunit 216* Aunit
0.5 LSB)
Area (INL = 214* Aunit 214* Aunit
0.5 LSB)
Area (INL = 212* Aunit 212* Aunit
1.0 LSB)
Notice that to achieve a given INL the analog
area is the same for the two topologies, while to achieve a
given DNL specification, the analog area for the binary-
weighted device is 216 times as large as the thermometer-
coded area. To have the optimized area required for 16-
bit segmented DAC, a MATLAB simulation is done. For
the thermometer -coded architecture, 2M individual
current cells were created, each with one current source,
while for the binary-weighted architecture, (16-M)
current cells were created. The MSB current cell of
binary architecture had 2(16-M) current sources, the next
MSB had 2(16-M-1), and so on. The value of M is varied
from 0 to 16, i.e. from total binary to total thermometer.
Then simulations were run for different values of INL,
and for DNL = 0.5 LSB to calculate the analog area
required for 16-bit resolution segmented DAC, for every
value of M from 0 to 16. A curve for digital area required
is also plotted for 0 to 100% segmentation. Note that 0%
segmentation corresponds to complete binary and 100%
segmentation corresponds to complete thermometer
architecture. A plot of “Area” versus “segmentation” for
16-bits resolution is shown in Fig 2. This plot allows us
to determine the optimal degree of segmentation. In this
plot, normalized term is used to represent Aunit as unity.
Straight lines 1, 2, and 3 in the plot represent required
area for INL = 0.5, 1.0 and 2.0 LSB, respectively, as
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calculated in Table 1. Line 4 shows the required analog
area variation for DNL = 0.5 LSB with segmentation.
The two extremes of this line are in accordance with
the calculated values of area requirement for binary
and thermometer coded architecture, as shown in Table
1. Line 5 represents the digital area required. Here it is
assumed that digital area required per current cell is
approximately 0.35 times of required analog area for
that current cell. This assumption is taken in
accordance with the available Lin & Bult Plot for 10-
bit resolution [2]. The bold curve, (line 6) in the plot
represents the total required area variation with
segmentation for INL = 1.0 LSB, and DNL = 0.5 LSB.
1
6 A
2
3
4
5
Fig. 2: Area required versus percentage of
segmentation for 16-bit DAC
Any point on the straight portion of the line 6
can be taken for having minimum area required, but the
corner point, A of this straight portion gives the
maximum portion of thermometer type in the
segmented architecture. Thus, optimal degree of
segmentation occurs at the rightmost part of the
horizontal line (point A) in the plot, which is still a
minimum area (limited by INL requirements), meets
the DNL specification, and has the smallest Total
Harmonic Distortion. From the graph, this optimum
value of the segmentation comes out to be 84 %, which
in turn gives the optimum value of segmentation as 13-
bits of thermometer type and 3-bits of binary type.
3. Current Source Mismatch Variation
with Yield
To obtain an accurate estimation of the yield,
the Monte Carlo simulation is done with Matlab. Each
 of the current sources is given a random value that has
been derived from a gaussian distribution with mean
value I and a standard deviation σI. For every digital code
the output current of the D/A converter is calculated and
compared to the ideal value. If the difference is larger
than an LSB, even for only one digital code, the D/A
converter is regarded as not functional and is therefore
rejected. This procedure is repeated for every σI , for 100 Yield
times to obtain reliable results. The yield is given by the (%)
ratio of the number of functional D/A converters (INL <
1.0 LSB and DNL < 0.5 LSB) to the total number of try-
outs. Fig 3 shows the yield variation with σI for 16-bit
segmented resolution for 100 Monte Carlo runs. This
curve shows that yield is 97 % for σI / I equal to 0.26 %.
This value of σI / I is used in the calculation of W and L
of current source transistor (discussed in section IV-B).
Using this value of σI / I, INL and DNL plots have been
plotted for 16-bit Resolution (13-bits Thermometer coded σI/I (%)
3-bits Binary weighted) from 100 Matlab simulations, as
shown in Fig 4 (a) and (b). From these curves, the
maximum INL and maximum DNL comes out to be 0.8 Fig 3. Yield variation with σI for 16-bit
LSB, and 0.03 LSB respectively, which satisfies the INL resolution (for 100 Monte Carlo simulations)
& DNL requirement.
4. Circuit Architecture & Results
0.8

0.6 A. Complete Architecture of 16-bit DAC

0.4

0.2
The complete circuit with all the blocks is
shown in Fig 5. In this architecture, 13-bits of
INL 0
( in LSB) Thermometer coded have been splitted into two groups
-0.2 of 7-bits and 6-bits, to reduce the area. But this
-0.4 introduces a glitch when output jumps from 6-bit block
to 7-bit block. Fig 6 shows the circuit of one unit
-0.6
current cell. It consists of an analog part and a digital
-0.8 part. The analog part consists of a differential switch
-1.0 and a cascoded current source. The digital part consists
0 1 2 3 4 5 6 7
4
input code ( x 10 ) of a decoding logic and a latch. The decoding logic is
0.04 equivalent to an AND–OR gate function and the latch
is essential for timing synchronization, as all the
0.03
current cells should switch at the same time.
0.02
Basic architecture of this Decoding Logic
0.01 block is shown in Fig. 7(a). With this structure, there
DNL
(in LSB)
occurs one problem. When one column is completely
0
selected, and one more cell is to be added in the output
-0.01 current, then requirement is that the value of all ROW
should become ‘0’, and the value of next COL should
-0.02
become ‘1’, and these two actions should occur
-0.03 simultaneously, where ROW & COL are the outputs of
-0.04
row and column decoder. But if there is little bit delay,
0 1 2 3 4 5
4
6 7 then a glitch will occur. In the modified structure, some
input code ( x 10 )
delay is added to ROW and COL input, as compared to
COL+1 input (next adjacent COL value). Also, COL is
more delayed than ROW. This causes COL +1 to be ‘1’
Fig 4. (a) INL & (b) DNL Plots for σI / I = 0.26% earlier, which maintain the current status of the total
current, and then ROW input goes to ‘0’, so that output

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Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
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 of (ROW ∩ COL) doesn’t give ‘1’, which removes the current cell, the current source transistor is cascoded by
problem of glitch Fig 7(b). If the switches interrupt the the transistor MCD.
current flow at any time point, then the current source B. Mismatch Analysis
charges the common source point of both the switches
towards VDD. And then current source and cascoding As defined by Pelgrom, mismatch “is the
transistor may enter into linear region, which may process that causes time-independent random
deteriorate the dynamic -performance considerable. variations in the physical quantities of identically
Therefore the controlling signals must not cross in the designed devices” [1]. Essentially, this means that
middle of the supply voltage. So, the PMOS transistor each current source in the matrix generates a current
size of both inverters (Inv_1 & Inv_3) should be larger that varies slightly from the desired current, IREF.
than the NMOS transistors to decrease the rise time. Therefore the current sources have to be designed in
Inverters (Inv_5 & Inv_6) are used between digital and such a way that random variations do not degrade the
analog part to change the analog value of logic ‘0’ at the performance of the circuit below its desired
input of switches, to increase the dynamic range of output specifications. Pelgrom’s paper has become the
voltage. standard for analysis of transistor matching, and thus
The critical transistor in the whole analog part is his formula for the standard deviation of saturation
the current source transistor (MC). A little bit change in current for two identically sized devices was used for
VT and β can cause a drastic change in the output current. the design. This formula is:
So, VT and β mismatch effects have been taken into the
consideration in the W & L calculation of current source σ 2 (Id ) 4σ 2 (VTo ) σ 2 ( β )
= + ,
(section IV-B). To increase the output impedance of the I d2 (VGS − VTo ) 2 β2

Fig 5. The complete circuit of 16-bit Current Steering DAC

CLK

Inv 1 Inv 2 MC
COL s V1
ROW M1
COL+1 B1 s bar V2 MCD
Inv 5
SW1 SW2

Inv 6
out out bar
M2 Inv 4
Inv 3

Fig 6. Internal Structure of a basic current cell

COL s COL
ROW s
COL+1 ROW
s_bar COL+1
s bar
(a) (b)
Fig 7. Decoding Logic Structure

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1063-9667/06 $20.00 © 2006 IEEE
 400
400
300
300
200
200
Current
(µA) 100 Current
(µA) 100

0
0
-100
-100
-200
0 100 200 300 400 500 600 -200
30 40 50 60 70
Time (ns)
Time (ns)

(a) (b)
Fig 8. Glitch problem in 384 µA current cell during transition

where, The values of R and C decide the settling time of the

2 output, after filtration. The corresponding output is
A2
σ (β ) Aβ
2
σ 2 (VTo ) = VTo
and = shown in Fig 11(a), for 50 MHz clock frequency. Its
WL β2 WL zoomed view is shown in Fig 11(b). INL & DNL
AVTo and Aβ are the technology dependent parameters. comes out to be within 0.3 and 0.1 LSB respectively.
Note that here variation with spacing is neglected. The The average power dissipation comes out to be 165
transistor current in saturation is given by: mW.
1 W
I LSB = µ * COX * * (VGS − VT ) 2
2 L V1
So, using above mismatch and current equations,
calculation for the W and L can be done. The expression V2
derived from these equations can be written as:
2 2 I LSB Aβ2 4 AV2T
W = ( + )
σI 2 4
µ * COX ( ) 2 (VGS − VT ) (VGS − VT )
I
µ * COX in
L2 = ( Aβ2 * (VGS − VT ) 2 + 4 AV2T )
σI
2 I LSB ( )2 in_bar
I
Since the current of each cell of 7-bit block is of
sufficiently high value, which requires a relatively large
size of the switch, SW1 & SW2 to pass this large current.
But due to overlap capacitance, there occurs a glitch,
when any current cell is added. This is shown in Fig 8(a),
which represents the output of one current cell, when it
changes from off to on state. Fig 8(b) shows the zoomed
view of this glitch. To reduce this glitch, a novel
approach is used. We call this approach as Finger
Approach. In this approach, the large dimension of switch
out out_bar
is split into different small switches. The gate inputs of
these switches are progressively delayed by an optimum
delay (Fig 9). This reduces the height of the glitch, as Fig 9. Finger Approach
shown in Fig 10(a), because it splits the big glitch into
different small glitches (Fig 10(b)). So, effectively the
total height of glitch is reduced. Finger approach
definitely reduces the glitch height, but does not
completely remove this glitch. So, at the output RC low
pass filter is used, to further decrease the height of glitch.
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 400 400

300 300

200 200
Current Current
(µA) 100 (µA) 100

0 0

-100 -100

-200
0 100 200 300 400 500 -200
30 40 50 60 70
Time (ns) Time (ns)
(a) (b)
Iout
Iout -+ Fig 10. Glitch variation with Finger concept
49

48
Current
(mA) 47

46
0 10 20 30 40 50 60
Iout - Time
Time(µs)
(ns)
48.854 Iout - (a)
(a (a)
48.849
Current
(mA)
48.844

48.839

48.834

0 100 200 300 400 500

Fig 11.(a) Simulation Result of Current Output (b) zoomed view, of 16-bit Current Steering DAC for
decreasing input
5. Conclusion
The designed digital-to-analog converter is of 16-bit
resolution (13 bits thermometric & 3 bits binary), and is
tested using cadence-spectre simulator at 50 MHz clock
frequency. The INL & DNL comes out to be 0.3 LSB and
0.1 LSB respectively. The power supply voltage in this
design is 3.3 V. This digital-to-analog converter is
designed in 0.35 µm TSMC technology. If the 14-bit
20mW DAC in [6] is redesigned for 3.3V supply voltage
and 0.35 µm technology and extended to 16bits, it will
dissipate (4*(3.3/1.8)2*(0.35/0.18)2*20 mW = 1.02 W,
whereas the DAC designed in this paper consumes only
165 mW power. The area involved in this 16-bit DAC is
0.06 mm2, which is very small. The reason behind this
small area for 16-bit resolution is because of split of 13
thermometric bits into two groups of 7 bits and 6 bits. A
novel approach of Finger concept is used to reduce glitch.
Time (ns)
(b)
References
[1] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.
Welbers, “Matching properties of MOS transistors,” IEEE
J. Solid-State Circuits, vol. 24, pp. 1433–1440, Oct. 1989.
[2] Chi-Hung Lin and Klass Bult, “A 10-b, 500-MSample/s
CMOS DAC in 0.6 mm2”, IEEE J. Solid-State Circuits, vol.
33, pp. 1948-58, Dec. 1998.
[3] Van Den Bosch, M. Steyaert, andW. Sansen, “An accurate
statistical yield model for CMOS current-steering D/A
converters,” Analog Integrated Circuits Signal Process.,
vol. 29, pp. 173–180, 2001.
[4] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland,
“Characterization and modeling of mismatch in MOS
transistors for precision analog design,” IEEE J. Solid-State
Circuits, vol. SC-21, pp.1057–1066, June 1986.
[5] Bastos, A. M. Marques, M. S. I. Steyaert. W. Sansen,"A 12-
Bit Intrinsic Accuracy High-speed CMOS DAC", IEEE
JSSC, Vol. 33, No. 12, pp. 1959-1969, Dec. 1998.
[6] Mika P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2
CMOS DAC”, IEEE JSSC, Vol. 36, No.7, July 2001.

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Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
 A 1 .2-V, 600-MS/s, 2.4-mW DAC
802.11 and 802.16
Nicola Ghittoril, Andrea Vignal, Piero Malcovati2 Stefano D'Amico3, Andrea Baschirotto3
'Dept. of Electronics, 2Dept. of Electrical Engineering, University of Pavia, Pavia, Italy
3Dept. of Innovation Engineering, University of Lecce, Lecce, Italy
Email: [nicola.ghittori,andrea.vigna,piero.malcovati] @unipv.it; [stefano.damico,andrea.baschirotto] @unile.it
Abstract- For the present and up-coming WLAN applications
(802.11a/g, 802.11n, 802.16), a transmission baseband architec-
ture uses a 600-MS/s current-steering DAC with a passive output
load to perform the baseband signal processing, avoiding the use
of any active reconstruction filter. In a 0.13-tm CMOS technology
the DAC consumes 2.4 mW from a single 1.2-V supply voltage.
The DAC exhibits a full-scale SFDR of 68 dB for an input
signal frequency of 12 MHz and a full-scale dynamic range of
9.7 bits between 0 and 10 MHz. These data correspond to the
best reported Figure of Merit, if compared with state-of-the-art
digital-to-analog converters.
I. INTRODUCTION
Present baseband sections for telecom standards transmitters
consist of the cascade of a digital-to-analog converter (DAC)
receiving the digital signal processor (DSP) bit-stream and
an analog reconstruction (or smoothing) filter, which has to
suppress the DAC spectral images. A digital interpolator filter
is required between the DSP (which typically operates at
Nyquist frequency) and the DAC to enhance the data-rate to
the desired value. This architecture is shown in Fig. 1. The
design of this baseband section has to optimize the trade-off
between two possible approaches:
. a low DAC conversion frequency, which implies a
low-power interpolator filter between the DSP and the
DAC, but requires also a high-order, power-hungry analog
reconstruction filter;
* a high DAC conversion frequency, which implies a digital
filter with a high interpolation factor, but relaxes the
required performance of the analog smoothing filter.
This trade-off is presently optimized with a DAC data-rate
about 8-to-10 times the signal bandwidth and a 4th-to-6th
order analog reconstruction filter. For instance, in the case
of the WLAN standard (whose signal bandwidth is equal to
10 MHz), the DAC data-rate is around one hundred MHz [1,2].
Looking at future implementations, the above structure
will have to face several critical points due to the CMOS
technology scaling and to the improved standards under def-
inition (802.16 and 802.11n, for instance). The technology
DSP N
~~U DAC 9 MHzf i _ Active
: 100
8-10bit <t_ 4th6th
filter
@, secio
orde ~~~~section
digital section baseband analog section
Fig. 1. Traditional baseband analog section for wireless transmitters
1-4244-0303-4/06/$20.00 C2006 IEEE.
for WLAN
Wireless Transmitters
scaling will allow the use of higher-speed and lower-power
(proportional to FSCV2D) digital part. On the other hand the
same trend implies analog sections with poorer performance,
due to the limited linearity achievable with the available supply
voltage (which can be 1.2 V or lower).
As the new standards will present a larger signal bandwidth
(14 MHz for the upcoming WLAN 802.16 for instance), the
use of traditional TX baseband architectures will result in
a more and more critical design of the analog filters, since
their cut-off frequency has to be increased (with an increasing
sensitivity to the lower CMOS gain and to the non-dominant
poles). Moreover they have to guarantee the required dynamic
range and linearity at the lower supply voltage imposed by
the scaled technologies. These points would determine an
increasing power consumption of the analog filtering blocks.
Thus, maintaining the ratio between the conversion fre-
quency and the signal bandwidth equal to about 10 would
result in a digital part underperforming its effective possibility,
without exploiting the benefits of the reduced supply voltage,
and in a power-consuming analog part introducing distortion
and noise. As a consequence, the scheme of Fig. 1 will be
very disadvantageous if implemented with future technologies
and/or if used for future communication standards.
II. PROPOSED TRANSMITTER ANALOG BASEBAND CHANNEL
The considerations given in the previous section lead to
a novel TX baseband channel design approach. The solution
proposed in this paper is shown in Fig. 2. In this case the
input bit-stream at Fc is interpolated to a kFc rate, with k
equal to 30. This operation will require lower and lower power
consumption in scaled technologies, and the circuit portability
will be immediate, due to its digital nature. On the other hand,
this increase of the data-rate/signal-bandwidth ratio would
require a lower smoothing filter order. In this way the system
is becoming more digital, as the general SoC trend is, since
the analog filter simplification is exchanged with a digital part
complication.
The baseband section architecture of Fig. 2 consists of a
digital interpolator filter from 100 MHz to 600 MHz and
an 8-bit DAC operating at 600 MHz. In this way the use
of an analog active reconstruction filter is avoided, result-
ing in a significant power consumption reduction. A single
pole filtering (provided by the DAC passive load), combined
with the "sinc" attenuation inherently provided by the DAC,
404
 To RF DAC Output Stage
DSP N * -M 1 st order
* DAC 6008 MHz _ passive f lter
Isection VDD
digta section baseband analog section

Fig. 2. Proposed high-frequency baseband analog section for wireless

transmitters

ToRF
suitably suppresses the images around the multiples of a 1.section
conversion frequency as high as 600 MHz. Considering for
example the signal bandwidth of 10 MHz and 14 MHz for
WLAN 802.1 la/g and 802.16 respectively, a DAC output pole
frequency set to 40 MHz gives a total attenuation of the first
signal replica greater than 55 dB. This ensures that all the DAC GND Unit cell
images lie under the emission mask. Moreover the resulting
large oversampling ratio determines an improvement in the Fig. 3. Architecture of the implemented DAC
linearity performance due to the reduced amplitude of the
transitions between successive codes.
The main drawback of this architecture may be the dis- voltage swing of 260 mVpp on each output node does not affect
tributed noise due to the high operating frequency. However the linearity of the DAC thanks to the high output impedance
this is mitigated by three considerations: the low number of of the current cells. This is achieved by the cascoding action
output bits determines a very small interpolator section, the of the switches in the on state.
large OSR reduces the number of cells effectively switching IV. EXPERIMENTAL RESULTS
at 600 MHz, and the technology shielding reduces crosstalk.
Moreover, differently than in the receiver, in the transmitter a The DAC system is realized in a standard 0.13-[tm CMOS
significant signal level is present, reducing the dynamic range technology. The chip microphotograph is shown in Fig. 4. The
requirements. The experimental results demonstrate that this DAC consumes 2.4 mW from a single 1.2-V supply voltage
distributed noise is not critical. and occupies 0.27 mm2. The 100-MHz to 600-MHz interpo-
lator filter has been designed and it can be implemented by
III. DAC ARCHITECTURE means of a 2-kgate block with two 10-stages FIR digital filters
to suppress the baseband images under the emission mask. The
Fig. 3 shows the architecture of the proposed DAC system, interpolator filter area is evaluated in about 0.2 mm2, while
operating from the challenging 1.2 V supply voltage. A fully the estimated power consumption is 2.3 mW. The proposed
thermometric differential current-steering structure guarantees solution achieves an improvement of more than 50% in power
high static and dynamic linearity performance. The low reso- consumption with respect to the typical solutions [3].
lution implies a negligible area of the binary-to-thermometric In the chip of Fig. 4 a dedicated digital part used for
decoder. The unit cell, with a current of 5 [tA, is sized to high-frequency testing has been included in the device, and it
reduce the effect of random mismatch. A relative standard occupies the largest amount of area (24 kgate). The crosstalk
deviation in the current value equal to 0.7% ensures an INL between the digital and the analog part is kept as low as
yield of 99% with a 0.5LSB limit. The overall dimensions of possible using a shielding triple well, separated power supplies
the current sources matrix (0.05 mm2) are such that systematic and multiple bonding wires to reduce parasitic inductances.
errors due to process variations do not affect the device The achieved performance immunity to the crosstalk demon-
linearity. The switches, which deviate the unit current towards strates the robustness of the proposed structure with respect to
the positive or negative output, are driven with low-swing
signals (from 300 mV to 800 mV) to limit the energy of
glitches. Their sizes are kept to minimum values to reduce
the charge injection effects during the switching phase. Two
drivers, placed after the synchronization latches, are used to
generate the desired voltage levels. Each driver is biased with
a current of 100 [A.
The passive load converts the output currents into a voltage
signal and filters the signal replicas. In Fig. 3, a resistance R
equal to 220 Q in parallel with a capacitance C of 17.5 pF
implements the required 40-MHz single pole transfer function.
A common-mode feedback circuit, which acts on the two fixed
PMOS current sources, adjusts the voltage of the common
node A of the two impedances to 600 mV. The single-ended Fig. 4. Chip microphotograph

405
 70-
68
66
64
62
> 60
m 58
D 56
54
52
50
48-
0
-

5 10 15
Input signal frequency (MHz)
20

Fig. 5. Measured HD3 vs input signal frequency, measured IMD3 vs center

frequency of the two input tones

coupling disturbs.
The proposed DAC operates with a conversion frequency of
600 MHz. For a full-scale (FS) single tone with a frequency
Fin up to 20 MHz (which accounts also for the WLAN
802.11n standard under development) Fig. 5 shows that the
third harmonic distortion (HD3) is higher than 59 dB over the
whole input frequency range. In the same Fig. 5, the measured
IMD3 performance, for two -6-dBFS input tones with AF
equal to 1MHz and center frequency up to 20 MHz, is given.
The integrated power spectral density (evaluated with a
static code at the DAC input) results in -57 dBm. Conse-
quently, the FS dynamic range (DR) of the system, obtained
adding the contribution of the 8-bit quantization noise filtered
by the DAC single pole, is equal to about 52.9 dB (8.5 bits).
Fig. 6 shows the output spectrum of a 9-MHz FS tone. The
measured attenuation deriving from the DAC "sinc" filtering
-=20

_|1_ f

0i
--2
0

--3
l11l 0

-
0 _ rX*1|
Inpu

-4

en-5
28C0
ton

1_idB,,

4
u

}5NH
Att

1lllI_ * W111 11111l_ *

-_
--40 _ _ _ MtlZA a;E>

bC 61 ;, t * I .. _ _ igna

60 t 11 = = oP§ls41W 30 kT-I:

L i1&1 b*ilE . r _2100

30_dB

____-_*
SliT

Fig. 7. Spectrum of two -6-dB FS tones at 13.6 MHz and 15.4 MHz

and the single pole filtering at the frequency of the first replica performs the baseband digital-to-analog processing with the
corresponds to the one expected from design. Fig. 7 shows the highest efficiency. Moreover it is the one operating with a
output spectrum for an intermodulation test with the two tones supply voltage as low as 1.2 V, while guaranteeing the standard
center frequency set to 14.5 MHz. Fig. 8 shows the output requirements.
spectrum when one component of a WLAN 802.1 la signal
is applied at the DAC input. As expected, the first replica of V. CONCLUSION
3
_lvi kH.
rXasmai m-s

1 /

_
l,-

|
r- _li_

_
9

p:l79IU
|11

the signal around the conversion frequency remains under the A DAC system to be embedded in WLAN 802.11 and
level indicated by the standard emission mask. 802.16 transmitters is presented. The circuit exploits the over-
The performance summary is reported in Table I. A com- sampling ratio to avoid the use of the analog reconstruction
parison with other recent published DACs can be made using filter following the DAC. The DAC is fabricated in a standard
the Figure of Merit reported in [4]: 0.13-[tm CMOS technology and operates with a conversion
frequency of 600 MHz, consuming 2.4 mW from a 1.2 V
Vswing
FOM = .Fin 10SFDR/20 (1) power supply. The measured SFDR is greater than 59 dB for
an input frequency up to 20 MHz, which accounts also for
where Vswing is the output differential peak-to-peak swing next generation wireless protocols, as WLAN 802.11n and
expressed in V, P is the power consumption expressed in mW, 802.16. The IMD3 is higher than 50 dB in the same frequency
Fin is the frequency in kHz at which the SFDR (expressed in range. The dynamic range in a band of 10-MHz is 60.6 dB,
dB) is measured. Fig. 9 shows that, for signal frequencies corresponding to an effective resolution of 9.7 bits. These data
of 10 MHz and 14 MHz, which account for the WLAN correspond to the highest efficiency baseband digital-to-analog
802.1 la/g and 802.16 targets respectively, the proposed block conversion if compared with state-of-the-art DACs.

406
 x 106
.
o
=., | WLAN baseband signal * FOM at 1OMHz
6 this work
-1 El FOM at 14MHz
10 --- - --- --1 '- -- ------ -- --- -- --
20 5 * -this work
-;
30-- -:- :--:- :-::N
:-::----m-i
-W -m
-a
\4\WLAN emission mask- Cong. (ISSCC3)
Go
4n
4u [ :::::\ :-::------
a)33-
:E ...
Clara' (ISSCC05)
.. ....
O' Sullivan (JSSCC04)
-50
.O2. * Clara (ISSCC05) 0

-60 Schofield
C:l Deveugele (ISSCC04) * ISSCCO3)
' Doris. (iSiSCCO}5). IS
-70 * Hyde (JSSCC03)
r_ Huang (ISSCC04)
Chen (ESSCIRC04)
-80 L II
10 100 700 15 18 5.5 33
Frequency (MHz) knalog supply voltage [V]

Fig. 8. Spectrum of a component of a WLAN 802.1la signal Fig. 9. Figure of Merit vs analog supply voltage for recently published DACs

TABLE I TABLE II

PERFORMANCE SUMMARY. PARAMETERS USED FOR THE EVALUATION OF FOM FOR RECENTLY PUBLISHED
DACS AND FOR THE IMPLEMENTED ONE.
Parameter ] Value
Technology CMOS 0.13 tm P Vswing SFDR [dB] SFDR [dB]
Supply voltage 1.2 V [mW] I[V] @14MHz @10MHz
Core area 0.27 mm2 This work 2.4 0.52 65.5 67
Maximum conversion rate 600 MS/s Cong [5] 16.7 1 72 76
Power consumption 2.4 mW Clara [6] 45 1.536 76 76
Differential FS output swing 520 mVpp O'Sullivan [7] 82 2 77 80
INL/DNL <0.25LSB Doris [8] 160 1.5 80 80
SFDR @ FS, Fin = 12 MHz 68 dB Schofield [9] 400 1 90 95
F, = 600 MHz Deveugele [10] 22 0.5 70 73
IMD3 @ -6dBFS, F,enter = 12 MHz, 57 dB Hyde [11] 53 1 72 72
AF 1MHz, F, = 600 MHz Huang [12] 97 0.8 72 73
DR @ FS 52.9 dB (8.5 bits) Chen [13] 103 5 45 49
DR @ FS, 0-10 MHz 60.6 dB (9.7 bits)

ACKNOWLEDGMENT
This research has been partially supported by the Italian
National Program FIRB, Contract n° RBNEOlF582.
REFERENCES
[1] S. Mehta et al., "An 802.11g WLAN SoC," ISSCC Dig. of Tech. Papers,
pp. 94-95, February 2005.
[2] H. Darabi et al., "A Fully Integrated Soc for 802.1 lb in 0.18 rm CMOS,"
ISSCC Dig. of Tech. Papers, pp. 96-97, February 2005.
[3] N. Ghittori et al., "A Low-Power, Low-Voltage (1lmW/8.4mW, 1.2V)
DAC+Filter for Multistandard (WLAN/UMTS) Transmitters," VLSI Dig.
of Tech. Papers, pp. 334-337, June 2005.
[4] D. Giotta et al., "Low-Power, 14-bit Current Steering DAC, for
ADSL2+/CO Applications in 0.13 Ftm CMOS," Proc. of ESSCIRC, pp.
163-166, September 2004.
[5] Y Cong and R. L. Geiger, "A 1.5V 14b IOOMS/s Self-Calibrated DAC,"
ISSCC Dig. of Tech. Papers, pp. 128-129, February 2003.
[6] M. Clara et al., "A 350MHz low-OSR AY Current-Steering DAC with
Active Termination in 0.13 Ftm CMOS," ISSCC Dig. of Tech. Papers, pp.
118-119, February 2005.
[7] K. O'Sullivan et al., "A 12b 32OMsample/s Current Steering CMOS D/A
Converter in 0.44 mm2," IEEE Journal of Solid-State Circuits, pp. 1064-
10722, July 2004.
[8] K. Doris et al., "A 12b 500MS/s DAC with >70dB SFDR up to 120MHz
in 0.18 Ftm CMOS," ISSCC Dig. of Tech. Papers, pp. 116-117, February
2005.
[9] W. Schofield et al., "A 16b 400MS/s DAC with <-8OdBc IMD to 300MHz
and <-l6OdBm/Hz Noise Power Spectral Density," ISSCC Dig. of Tech.
Papers, pp. 126-127, February 2003.
[10] J. Deveugele and M. Steyaert, "A 10b 250MS/s Binary-Weighted
Current-Steering DAC," ISSCC Dig. of Tech. Papers, pp. 362-363, Febru-
ary 2004.
[11] J. Hyde et al., "A 300-MS/s 14-bit Digital-to-Analog Converter in Logic
CMOS," IEEE Journal of Solid-State Circuits, pp. 734-740, vol. 38, no.
5, May 2003.
[12] Q. Huang et al., "A 200MS/s 14b 97mW DAC in 0.18km CMOS,"
ISSCC Dig. of Tech. Papers, pp. 364-365, February 2004.
[13] T. Chen et al., "A 14-Bit 130-MHz CMOS Current-Steering DAC with
Adjustable INL," Proc. of ESSCIRC, pp. 167-170, September 2004.

407
 A 1.8V 20mW 1mm² 14b 100MSample/s CMOS DAC
Mika Tiilikainen
Nokia Mobile Phones, Helsinki, Finland
mika.p.tiilikainen@nokia.com
Abstract
A binary weighted current steering DAC is a power-
efficient architecture, because almost all the current
taken from the supply is used for the output signal.
Typically, the architecture suffers from poor linearity
characteristics, but the problem can be prevented with a
new calibration method, where the currents generated
for the most-significant bits are fine-tuned. As a result, a
very compact and low-power solution can be
implemented by using a low-voltage digital technology.
1. Introduction
The current steering DACs can be implemented by
using binary weighted and/or unweighted current
sources. At the moment, the focus has been on the
segmented structures, where a few least-significant bits
(LSBs) have the binary weighting and the rest of the bits
are switched according to the thermometer code [1],[2].
The unweighted currents give better linearity, because
the matching requirement is set between the LSB and the
unweighted bits. In other words, if the four LSBs are
implemented with binary weighted current sources, a
current matching ratio of 1:25 must be guaranteed. For a
14-bit binary weighted DAC a matching ratio of 1:214 is
required. In practice, a ratio of 1:210 is implementable
with careful layout design and a reasonable current cell
size. The nature of the binary weighted DAC does
neither guarantee the monotonicity, as the unweighted
structures do.
Typically, the problems of nonlinearity are solved by
taking care of symptoms, but not of their causes. For
example the digital input signal is manipulated to obtain
the correct output signal from the DAC. The correction
words are stored into a memory and they are dynamically
mapped according to the input signal. On the other hand,
the currents can be calibrated by adding extra current
sources in parallel with the DAC, but it increases the
number of glitching elements in the circuit. In [3] a
trimmable MOSFET is introduced, but the area of the
analog parts increases significantly, as in the worst case
the LSB-sized transistor has the same gate bias voltage
as the MSB transistor. In addition, such biasing is not
very reliable, because in principle it requires a matching
ratio of 1:214.
A new solution for the current source calibration
problem is introduced in [4], where the drain current of a
MOSFET can be fine-tuned with a low resolution
calibration DAC without significantly increasing the
current consumption, area or circuit complexity. The
method is considered more thoroughly in the next
section.
2. DAC with the calibration
The topology of the DAC is represented in Fig. 1. The
current source matrices are divided into three parts. Four
trimmable most-significant bits (MSBs) are generated in
the first matrix, five middle bits in the middle matrix, and
five LSBs in the last matrix. Current scalers are needed
to bias the matrices, and the main bias current of 256µA
is supplied externally. That is a trade-off between a LSB
current of 0.5µA and a MSB current of 4096µA. The
output currents are driven to external 50Ω loads,
resulting in a full-scale output voltage of 0.8Vpp.
A new method to compensate mismatching, interdie
and temperature variations is introduced in [4]. The main
idea is that the effective channel width or the
transconductance of a current source transistor can be
adjusted by driving a control current ICAL through the
resistive element (MR) placed between the diode (MD)
and the current source transistor (MN) in a current mirror,
as shown in Fig. 2. The control current or the calibration
current through the resistive element gives rise to a
voltage difference between the gates. The voltage
difference is superimposed on the bias voltage given by
the diode transistor. An adjustment in the calibration
current ICAL therefore slightly changes the drain current
of the current source transistor. The technique enables an
accurate trimming of the output current with an almost
arbitrary precision.
IOUT+ IOUT-
SWITCHES SWITCHES SWITCHES
MSB MID LSB
SCALER1 SCALER2
SOURCES SOURCES SOURCES
IB=256µA
Figure 1. Block diagram of the DAC.
 IB1 IB2 IOUT
VB
ICAL
MD
M1 MN-1 ICAL MR
Figure 2. Calibratable current source.
As the calibration is applied on the MSBs of the
DAC, where the currents are in the range of
milliamperes, MN cannot be biased with the same diode
as the other transistors, because the offset current
between the calibration current sink and the source
would disturb too much the bias condition, and
consequently the output current. The mismatch between
the bias currents is not an issue, if there is enough margin
in the calibration range to compensate the difference.
The channel width of the MN is purposely slightly
smaller than the channel widths of the other current cells
to guarantee that the calibration range covers all the
nonidealities. In practise, the calibration is a linear
operation, because the average drain current of the
calibratable transistor is 128µA and the adjustment range
is only a few microamperes.
3. Calibration procedure
A state machine is implemented to run the calibration.
The procedure used here is the same as the bottom-up
self-calibration scheme in [3], but the implementation is
different. In this case, only the four MSBs are calibrated
and no additional reference currents are needed. The
total area is also reduced, because the sizes of the MSB
transistors can be smaller, as a matching ratio of 1:214 is
not needed. The use of deep-submicron technology does
not reduce the area of the analog parts significantly,
because the matching requirements do not shrink with the
channel length.
The simplified calibration circuit is presented in Fig.
3. In practise, the simple pmos current mirror is a high-
swing cascode current mirror. At first, the higher MSB
currents are turned off, and the lowest trimmable MSB
current (MSB1) is compared to the LSB currents (LSB1-
LSB10), including also an additional LSB current. The
current steering calibration DAC generates the
calibration current ICAL for the MSB1 current source. In
phase A, the LSBs are mirrored to the current
comparator and the MSB current sink is shorted to node
P. The calibration current is swept from the highest value
towards zero. The sweep is stopped, when the
comparator changes its state and the result is stored into
a register. In phase B, the currents are compared the
other way around and the sweep starts from zero. The
change in the direction of the sweep between the two
phases is one way to maintain the symmetry in the
calibration process. The final calibration code is the
mean value of the two results.
In the next phase, the trimmed MSB1 is switched into
the LSB current set and the comparison with MSB2
starts from phase A etc. If there is no mismatch, and 6-bit
calibration DACs are used, 256 clock cycles are needed
MN to run the calibration.
The current comparator with a low input impedance
[5] is used. The comparator is very simple and small;
however, it sets the limit for the calibration speed.
The impedances of the current sources and the
comparator determine the voltage VP at the node P. Thus
the voltage slightly drifts during the calibration resulting
in the Early effect. However, the error caused by the
Early effect is insignificant, as the current sources have
high output impedances and the current comparator has
low input impedance. The main problem is the mismatch
m introduced in the pmos current mirror, which results in
an offset error in the current comparison. That can be
prevented by running the calibration sweep twice, and by
changing the routing of the LSBs and MSB currents. In
both phases, the VP is practically the same, when
LSBs=MSB. That also reduces the error caused by the
Early effect.
The previous considerations can be also presented
with exact formulas. If the mismatch and the Early effect
are described by coefficient εp for pmos current source,
and the Early effect by εn for nmos current source, the
calibration equations for phases A and B are given by
ε nA (I MSB + ICA ) = ε pA I LSBS
(1)
ε pB (I MSB + I CB ) = ε nB I LSBS
where ICA and ICB are the respective correction currents
resulted from the comparisons, and they have respective
calibration codes CA and CB stored into the registers in
the state machine. IMSB represents the MSB current given
by the current source in Fig. 3, when ICAL=0.
Respectively, ILSBS represents the LSB currents with the
additional LSB current. As the MN in Fig. 2 is a narrower
transistor than the M1-MN-1, IMSB<ILSBS is valid. In this
case, the current comparator has no offset, but if there
was any, it could be also handled with the calibration.
VDD
1:(1+m)
∆I
P
CAL
A B B A LOGIC
ICAL 6
CAL
DAC
LSBs MSB
VSS
Figure 3. Calibration circuit.
 As the calibration sweeps are practically linear in the curves show that there is no extra dynamics, as the
operations, the desired correction current IC is given by calibration is only applied on the four MSBs. The
the mean value of ICA and ICB linearity curves could be suppressed more by trimming
also the higher LSBs of the DAC.
1  ε pA ε nB  
IC =  + I LSBS − 2 I MSB  (2) The SFDR of 84dB can be achieved with 100kHz
2  ε nA ε pB   input signal frequency and 100MSample/s update rate, as
shown in Fig. 8.
Because the Early effect can be ignored, εpA≈εpB=εp and The even-order distortion dominated the
εnA≈εnB=εn hold. In addition εn=1, because no mismatch measurements at higher signal frequencies, because it
is needed to be modelled for the nmos sources. As was not compensated. The second- and third-order
εp=1+m is approximately equal to one, the following harmonic distortions (HD2 and HD3) are presented in
equation holds Fig. 9. In general, the mismatch in the binary weighted
1 current sources causes only odd-order harmonics. The
lim ε p + = 2 ⇒ I C ≈ I LSBS − I MSB (3)
even-order harmonics results from the unbalance in a
ε p →1 εp
differential structure. Therefore, an excellent static
The operation of the calibration is illustrated in Fig. linearity does not guarantee a good dynamic
4, where the mismatch m is a small positive number. The performance, which is dependent on glitches and timing
dark lines describe the actual currents seen by the errors. However, by adding e.g. a simple track and
comparator. As a result, the mean value of the codes CA attenuate circuit to the output of the DAC as in [1], the
and CB corresponds to the required correction current IC problem of HD2 could be reduced significantly.
given by Eq. (3). Simultaneously, also a part of the HD3 should be slightly
more suppressed.
I
ep A
swe
←
mismatch
ILSBS
→ mismatch
ep B
swe LOGIC
IMSB SCALERS

0 CB mean(CA,CB) CA code
Figure 4. Principle of the two-phase calibration. The CALDACS
dark lines represent the actual currents seen by the
LSB MID MSB
current comparator.

SWITCHES
4. Experimental results CALMIRRORS

LATCHES
A 14-bit DAC was implemented in a digital CMOS
process and the full linearity was achieved with the
Figure 5. Layout of the DAC.
calibration. The layout of the DAC is presented in Fig. 5.
The micrograph of the chip would be useless, because
the deep-submicron process is equalized by covering the
4
whole chip with dummy metal plates. The 6-bit
INL [LSB]

2
calibration DACs are oversized and could be reduced
0
significantly resulting in a smaller die area. As a result,
−2
the calibration increases the area of the DAC
−4
approximately 50%. It is not significant, because the area
1 4096 8192 12288 16384
of the DAC itself is relatively small for many code
applications. The floorplan is basically the same as used 2
e.g. in [2], where the latches are isolated from the analog 0
DNL [LSB]

parts. −2
In this study, the main emphasis was on the static
−4
linearity problems of a binary weighted DAC. As shown
in Fig. 6, the effective number of bits (ENOB) would −6
1 4096 8192 12288 16384
have been approximately ten without the calibration. code
After trimming, the nonlinearities were reduced to less Figure 6. Static linearity without the calibration.
than half a LSB, as can be seen in Fig. 7. The variations
 5. Conclusion
1
A 14-bit binary weighted current steering DAC was
0.5 implemented in a digital process without using any
INL [LSB]

0 analog options, and the full linearity was achieved with

−0.5
the calibration. By using the binary weighted structure,
the die area and current consumption can be significantly
−1
1 4096 8192 12288 16384 reduced, as compared to the published segmented DACs,
code
where unweighted parts require more analog and digital
1
components. The measured DAC characteristics are
0.5
DNL [LSB]

summarized in Table 1.
0 The use of a deep-submicron technology does not
−0.5 reduce the analog area of the DAC significantly, as the
size of the analog components cannot be shrunk
−1
1 4096 8192 12288 16384 appreciably because of the matching requirements. Thus
code
the results are valid also for technologies with larger
Figure 7. Static linearity with the calibration. minimum gate lengths.

0 Table 1. Measured DAC characteristics.

SFDR=84dB Technology 0.18µm CMOS
fs=100MS/s
fin=100kHz Resolution 14 bits
−20
INL < 0.5 LSB
DNL < 0.5 LSB
amplitude [dBc]

−40 Update Rate 100 MS/s

Full-Scale Output Range (RL=50Ω) 0.8Vpp
−60 SFDR @ 100kHz 84 dB
SFDR @ 1MHz (limited by HD2) 64 dB
Power Consumption 20 mW
−80
Supply Voltage 1.8 V
Die Area 1 mm²
−100
0.2 0.4 0.6 0.8 1
frequency [MHz]
Figure 8. Output spectrum for the 100kHz input 6. Acknowledgements
signal with the 100MS/s update rate resulting in
SFDR of 84dB. The DAC has been designed in Nokia Research
Center. The author thanks Jari Patana, Tom Ahola and
Sami Kallioinen for their support during the project.
90
fs=100MS/s
85 7. References
80 [1] A.R. Bugeja, B.-S. Song, "A Self-Trimming 14b
HD2, HD3 [dBc]

75 100Msample/s CMOS DAC", ISSCC Dig. Tech. Paper,

HD3
February 2000, pp. 44-45.
70 [2] J. Vandenbussche, et al., "A 14b 150Msample/s Update
65 Rate Q² Random Walk CMOS DAC", ISSCC Dig. Tech.
HD2 Papers, February 1999, pp. 146-145.
60 [3] A. Tang, C. Toumazou, "Novel Self-Calibrated High-
Speed D/A Converter using Trimmable Current Sources",
55
Proceedings of ISCAS, June 1994, vol. 5, pp. 469-472.
50 [4] M. Tiilikainen, "A Novel High Precision Adjustment
Method for the Transconductance of a MOSFET", CICC Dig.
0.1 1 10 Tech. Papers, May 1999, pp. 525-528.
output signal frequency [MHz] [5] H. Träff, "Novel approach to high speed CMOS current
Figure 9. SFDR for higher output frequencies is comparators", Electronics Letters, 1992, vol. 28, no. 3, pp.
dominated by the HD2 (100MS/s update rate). 310-312, January 1992.
 8-I
A 1Ob, 400 MS/s Glitch-Free CMOS D/A Converter
K. Khanoyan, F. Behbahani, and A.A.Abidi
Electrical Engineering Department
University of California
Los Angeles, CA 90095-1 594
Introduction
Recent reports on high-speed CMOS D/A Converters
(DACs) demonstrate clock rates and effective bandwidths
of the well-known current-steering DAC architecture of
loo’s of MHz [l,21. In this work, new circuit design and
layout methods are applied to a glitch-free 10b DAC based
on the pipelined charge redistribution architecture [3,4].
Transients in the output current as codes change are
called glitches, and because glitch characteristics depend
nonlinearly on codes, they result in spurious tones in the
output frequency spectrum. In the glitch-free DAC, on the
other hand, the analog voltages are sampled and held at
each clock cycle. The 0.6-pm CMOS prototype described
here clocks at up to 400 MS/s, and delivers a superior
spurious-free dynamic range (SFDR) over the Nyquist
band compared to other CMOS DACs. This circuit is
part of digitally based agile frequency synthesizer for a
fast-frequency hopping wireless transmitter, and is
intended to drive on-chip capacitor loads.
The core of the DAC successively bisects charge in an
array of equal unit capacitors (Figure l(a)). Switches
driven by a three-phase clock force charge to move from
the LSB towards the MSB capacitors. Each data bit
precharges the corresponding capacitor to one of two
reference voltages, and in the next clock cycle the charge
is bisected. The charge on the MSB capacitor constitutes
the final converted value. An op amp at the end of the
capacitor array converts this into a buffered voltage
(Figure l ( b ) ) .Latches with appropriate pipeline delays
supply data to the cells.
Design Considerations
Overall DAC linearity is limited by mismatch in the unit
capacitors, stray capacitance bypassing the series switch
between cells, and slew-rate limited response of the op
amp buffer [4]. The capacitors are implemented here as
poly over gate oxide over n + diffusion. Published match-
ing data shows that the plate area of a 0.5 pF unit capaci-
tor is large enough to guarantee 1Ob matching [ 5 ] .
Matching of the MSB capacitors is most important. The
MSB and MSB-1 capacitors are close together and not
expected to suffer gradient-induced mismatch. Accuracy
of charge bisection depends only on capacitor matching,
This research was supported by DARPA and an industrial
consortium under the State of California MICRO program.
73 4-930813-95-6199 1999 Symposium on VLSl Circuits Digest of Technical Papers
and is not affected by capacitor voltage-coefficient. When
the switch connecting adjacent cells is OFF, charge leaks
through the inter-wire stray capacitance across the
switch. This error charge produces spurious tones in a
synthesized sinewave, which get worse as the sinewave
frequency rises. To lower this critical capacitance to
about 0.2 fF,the switch FET is laid out with interconnect
metal at diagonally opposite ends, and a farther separa-
tion than normal between the metal contacts to the
source and drain (Figure 2).
The RC settling time at each unit capacitor imposes an
upper limit to the highest clock rate. The two series
switches precharging each unit capacitor in an earlier
prototype [3] are replaced here by a single switch con-
trolled by an AND gate lying outside the analog signal
path (Figure 3). This also eliminates an undesired inter-
line capacitance, which injects stray charge into the cell.
The settling time constant at each node is now 65 ps,
which gives almost 10-12.t settling accuracy.
The DAC reference voltages (Vrefl, Vref2) are supplied
off-chip. The O N resistance of the FET switch only
lightly damps the resonant circuit comprising wirebond
and leadframe inductance and DAC capacitors (Figure 4).
The natural frequency is several times the clock fre-
quency The resultant ringing in the DAC capacitor
voltage produces errors as large as 5 LSBs at the end of
precharge phase. After considering various ways to
dampen the ringing, the solution adopted was to decouple
the reference voltage pads to ground with a 0.5 nF on-
chip capacitor. The capacitor occupies otherwise vacant
area on the die. It guarantees that the reference voltage
settles to an accuracy of better than 1 LSB at the end of
the precharge phase. Furthermore, as inaccuracy in
precharge of the MSB cells contributes proportionally
larger DAC error, the voltage reference pads for the three
MSBs are separated from the common reference pad
supplying the remaining cells.
Clock skew must be considered when interfacing to the
DAC input. The DAC operates on a three-phase clock,
and receives inputs from an integrated ROM-based direct
digital frequency synthesizer (DDFS) clocked by a single
phase. If the pipeline registers use the same clock as the
DDFS, a clock skew can result in the incorrect precharge
on every 31d DAC cell (Figure 5(a)). Instead, the pipeline
registers are clocked by the three phases of the DAC, such
that the DDFS output is sampled on $2. Clock phases $1
and $3 are assigned to the subsequent register stages in
such a way that the precharge of each DAC cell can
tolerate clock skews as large as the interval of one clock
phase (Figure 5(b)).This scheme uses ten more flip-flops
compared to a conventional implementation of the
pipeline register [3].
A single cascode op amp with capacitor feedback (Figure
6(a)) acts as a charge-to-voltage buffer a t the output of
the quasi-differential DAC. Long-channel PMOS pull-up
FETs raise the buffer’s D C gain. This o p amp settles
faster than a gain-boosted cascode, and in this applica-
tion linear, fast settling is paramount. To avoid slew-rate
limiting, the input FETs are biased such that the linear
range of the differential input, J2(VG,-Vt), encompasses
the 0.5V ptp differential full-scale voltage swing at. the
last DAC stage. A continuous-time common-mode
feedback circuit is used because it settles faster than a SC
circuit (Figure 6(b)). The simulated D C gain of the op
amp is 50 dB. Voltage coefficient of the feedback capaci-
tor, which transforms the final D/A converted charge to
voltage, will contribute to the overall DAC INL. The o p
amp is reset to zero after each amplifying phase, which
has important consequences for SFDR flatness versus
frequency, as discussed below.
Experimental Results and Discussion
The prototype consists of a 10b DAC, integrated with a
DDFS and a very linear transconductance buffer to drive
off-chip measuring instruments (Figure 7(a)). The DAC,
pipeline registers, and multi-phase clock generation
circuits together consume 1.2 mmz chip area, and dissi-
pate 90 mW from 3.3V when clocked a t 300 MS/s. Of
this, the op amp consumes 25 mW, logic circuits the rest.
The area and power are comparable to a very compact
10b current-steering DAC [l]. Careful board layout with
low inductance grounds was important in obtaining the
reported performance (Figure 7(b)).
The DDFS and DAC can be clocked up to 400 MS/s.
Sinewaves are synthesized from low frequencies up t o
Nyquist a t various sample rates, and the resulting worst-
case SFDR is plotted versus normalized frequency (Figure
8(a)).At low clock rates with high oversampling, the
SFDR is almost 63 dB dominated by the 3rdharmonic.
The most likely cause is nonlinearity in the op amp
feedback capacitor, which is specified with a voltage
coefficient of 0.1 %/I! As the synthesized frequency
approaches Nyquist, SFDR falls by only about 3 dB. It is
noteworthy that at all sample rates the SFDR declines by
only 3 dB over the Nyquist band. The most likely cause
of decline in SFDR is the tiny fringing capacitance that
remains between adjacent cells in the DAC core. As the
op amp is reset t o zero after every sample, as long as it
settles fully its dynamics are the same whether a sinewave
is synthesized at a low frequency o r a t Nyquist. Although
the op amp is designed to settle to 77 a t 300 MS/s, the
1999 Symposium on VLSl Circuits Digest of Technical Papers
portion of the settling transient arising from nonlinear
transconductance becomes more significant in the
waveform of the discrete sinewave (Figure 8(b)).Owing to
this effect the SFDR a t all synthesized frequencies drops
by about 8 dB when the clock rate is raised from 50 to 300
MS/s. Representative spectra show that only two spurious
tones are important (Figure 9).
As DAC performance benefits directly from technology
scaling, this circuit can only be fairly compared with
others fabricated in a comparable CMOS technology The
comparison circuits are a O.5pm CMOS version of a 10b
current-steering DAC [ l ] (detailed SFDR data in [6]), and
a 12b current-steering DAC also in O.5pm CMOS [2]. In
both cases (Figure 10) this DAC outperforms the compari-
son circuits a t high sinewave frequencies, significantly in
the case of [2]. The SFDR of current-steered DACs falls
steeply with synthesized frequency due to the increasing
significance of code-dependent glitches, whereas in this
glitch-free DAC the SFDR remains relatively flat. Both
comparison current steered DACs are highly segmented,
which accounts for the larger SFDR a t low frequencies
compared to this non-segmented DAC. However, this
feature is of little value in a wideband frequency synthe-
sizer, where constant SFDR is desirable. This DAC
overtakes the best comparison current-steered DAC in
worst-case SFDR across the Nyquist band a t clock rates
above 100 MS/s (Figure 11).
The current-steered DAC has been used for many years in
high-speed applications. This work shows that the glitch-
free CMOS DAC is superior in such uses as digitally
synthesized sinewave generators, which have only recently
become interesting as integrated components of wireless
transceivers.
111 C.-H. Lin and K. Bult, “A lob, 250 MS/s CMOS DAC in
lmm’,” in Int’l Solid-state Circuits Conf., San Francisco,
CA, pp. 214-215, 1998.
[2] A. Marques, J. Bastos, A. Van den Bosch, J. Vandenbussche,
M. Steyaert, and W. Sansen, “A 12 b Accuracy 300
Msample/s Update Rate CMOS DAC,” in Int’l Solid-state
Circuits Conf., San Francisco, CA, pp. 216-217, 1998.
[3] G. Chang, A. Rofougaran, M. K. Ku, A. A. Abidi, and H.
Samueli, “A Low-Power CMOS Digitally Synthesized 0-13
MHz Agile Sinewave Generator,” in Int’l Solid State
Circuits Conf., San Francisco, pp. 32-33, 1994.
[4] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M.
Rofougaran, I? J. Chang, M. Djafari, M. K. Ku, E. Roth, A.
A. Abidi, and H. Samueli, “A Single-Chip 900 MHz Spread-
Spectrum Wireless Transceiver in 1-pm CMOS (Part I:
Architecture and Transmitter Design),” IEEE J. of Solid-
State Circuits, vol. 33, no. 4, pp. 515-534, 1998.
[5] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic
Capacitance Matching Errors and Corrective Layout
Procedures,” IEEE I. of Solid-state Circuits, vol. 29, no. 5,
pp. 611-616, 1994.
[6] C.-H. Lin, A 10b 500MSamples/s CMOS DAC in 0.6mm2,
PhD Thesis in Electrical Engineering. University of Califor-
nia, Los Angeles: 1998.
74
 U 01 I'
Vref

p,.
D'Acap T"
I
Off Chip On Chip

LSB * * - MSB
InitializingCapacitor (a)
Other half of
differentialcircult

Figure 4. Ringing during precharge of DAC capacitors

causes error. Large on-chip decoupling capacitor damps

mz
ringing.

Correct sampling Effect of skew

(a)
I
I
I I
I T'- Pipeline Register with DAC cell prechargesla unknown voltage
(b) single-phase clack

Figure 1. (a) Three adjacent unit cells at the LSB end of DDFS Output Word

the DAC. (b) MSB end of the DAC, showing charge-to-

voltage buffer.

' \ \
'\\ I!, \l l
(1
I
$2
I I - f + + +
'\\ l

$1
Figure 2. Layout of switch Figure 5. (a) Illustrating the problem caused by clock
FET to lower the stray skew when DAC samples DDFS output. (b) Skew tolerant
capacitance across the OFF clock scheme in pipeline register.
switch.

T
Previous design Faster design
Vcmfb

vref'pi?
*
CMFB

Figure 3. Improved switch and logic which lowers node

capacitance, and removes a path of stray charge injection. Figure 6. (a) Cascode op amp. (b) Common-mode feed-
back circuit.

75 4-930813-95-6199 1999 Symposium on VLSl Circuits Digest of Technical Papers

 -110

Figure 7 . DAC layout and close up of test board.

70 70 70

65 65

60
m 60
60 m
-U

m
2 * 55
a
2
=-55
cn

e
m 50
50

50 45
45
40
40 0 30 60 90 120 150
0 25 50 75 100 125
40 SynthesizedFreq, MHz Synthesized Freq, MHz
0.0 0.1 0.2 0.3 0.4 0.5
fsidfclk Figure 10. Comparison of SFDR vs. synthesized sinewave
frequency
(4

(b)
Figure 8. (a) Measured SFDR vs. Normalized synthesized
Clock Rate, MS/s
sinewave frequency (fsin) at various sample rates (fclk).
(b) Non-exponential settling transient arising from Figure 11. Comparison of SFDR (worst-case over Nyquist
nonlinear I-V characteristic of OTA. band) versus sample rate.

1999 Symposium on VLSl Circuits Digest of Technical Papers 76

ISSCC 2004 / SESSION 20 / DIGITAL-TO-ANALOG CONVERTERS / 20.2
20.2 A 10b 250MS/s Binary-Weighted
Current-Steering DAC
Jurgen Deveugele, Michiel Steyaert
ESAT-MICAS, Katholieke Universiteit Leuven, Belgium
The presented 10-bit binary weighted current-steering DAC has
over 60dB SFDR at 250MS/s for signals from dc to Nyquist. The
chip draws 4mW from a dual 1.5/1.8V supply plus load currents.
The active area is less than 0.35mm2 in a standard 1P-5M 0.18µm
1.8V CMOS process. Both INL and DNL are below 0.1 LSB.
The degree of segmentation of a current-steering DAC has a
major influence on both the structure of the converter and on its
performance. Segmented rather then binary weighted architec-
tures are often used for improved DNL, glitch, and SFDR per-
formance [1]. This however comes at a price. An increase in the
number of unary decoded bits has an exponential influence on
the area and increases the complexity of the decoder. This
increases the power consumption and the required design time.
The additional benefit of decoding one extra unary bit gets small
if the number of decoded bits is high. Even worse, as the digital
noise increases and time skews get bigger in large decoders, the
dynamic performance may drop. It is clear that a good segmen-
tation choice is important. Yet this choice is often based on expe-
rience rather than on founded decisions. We have carefully stud-
ied this trade-off and pushed our design to a binary weighted
structure. The DAC has a highly regular structure, good dynam-
ic performance and low power consumption.
In a segmented structure the DNL is often big at the boundaries
of the unary and the binary decoded parts. In [2], the linearity
problem is solved by using calibration. It can be solved also if all
current sources are composites of the same unit cell. This
removes the systematic error typically caused by using different
structures for the MSB and the LSB parts. Therefore the source
array consists of 1023 identical sources plus the current mirror
and dummies. The DNL specifications are met if one designs for
the correct INL yield (99.7% yield for INL < 0.5 LSB) [3]. The
measured INL and DNL plots can be seen in Fig. 20.2.1.
For good dynamic performance, it is essential to use equal struc-
tures whenever possible, and switching must be identical for all
big current sources. The chip presented here uses a pseudo-seg-
mented structure with 6 pseudo-unary bits and 4 binary bits.
Therefore the structure is identical to that of a 10-bit 6+4 seg-
mented DAC. The inputs are, however, not decoded but buffered
locally. The MSB consists of parallel connected pseudo-unary
cells distributed over the switching core.
When it comes to dynamic performance, there are two main dif-
ferences between a pseudo-segmented (binary) DAC and a seg-
mented converter. The first is the lack of a decoder. Since the
buffering requires little power, less digital noise is injected into
the output. The second difference is that in a binary DAC a lot of
undesirable switching of sources occurs. For example, at major
code transitions in a 10b DAC y = 0 to 511 extra switches are
switched on, while a similar number of switches are switched off.
However, if the sum of the differential output currents IL an IR
remains constant during switching, then this switching is not
seen at the output, and the performance of the binary DAC is
then equal to that of the unary DAC. The deviations from the
ideal must be minimized.
One way to state this problem is to say that the glitch energy has
to be minimized. Then the area of the positive deviations equals
• 2004 IEEE International Solid-State Circuits Conference
the area of the negative deviations. Reducing the glitch energy to
zero does not eliminate all spurious responses in the Nyquist
band, but pushes most of the energy out of the band. Fast tran-
sitions push the spurious outputs to even higher frequencies,
further reducing the impact in the Nyquist band. In addition,
fast switching can decrease the transition energy. The charge
injected by the capacitive coupling of the digital signals to the
output is independent of the switching speed, but the time of
unbalanced switching is reduced. Therefore we designed this
DAC for minimal glitch energy and as fast as possible switching.
The latch composed of transistors M1-M6 and inverters I1-I2 can
be seen in Fig. 20.2.2. Transistors M2-M5 and inverters I1-I2
form a David-Goliath latch. It is fast and gives good control over
the glitch energy in all process corners. The latch has one pitfall.
During switching, nodes 1 and 2 are shorted, as are nodes 3 and
4. A large glitch occurs at these nodes if the logic values differed
before switching. A buffer designed to drive the capacitances on
nodes 2 and 3 has too small a capacitance, and extra capacitance
is added at nodes 1 and 4. This increases the power consumption
a little, but significantly improves the SFDR. It is essential that
all buffers are scaled identically. This ensures that the glitch at
nodes 2 and 3 is signal independent. This is also important for
segmented structures in which each decoder stage has a differ-
ent structure and capacitance, leading to code dependency.
Adding a deglitch stage can have the same effect, but at an extra
cost, and the ratio of the capacitances must still be optimized
theretoo. Note that many other latches have comparable critical
nodes.
Transistors M7-M8 set the voltages on nodes 5 and 6. The node
above the on switch is set by bias voltage Bias3 and the current.
The influence of the output voltage is reduced by the gain of the
cascode device. The node above the off switch is charged expo-
nentially until the transistor on top of the switch enters sub-
threshold. This charging is complete at the end of one clock peri-
od at 250MS/s. The cascode thus shields the switches from the
output voltage variation, and simplifies the design of the driver-
switch-latch combination for low glitch energy.
All measurements are done at 250MS/s with 10mA load current
unless explicitly stated. Figure 20.2.3 shows the spectrum for a
122.5MHz signal for which the SFDR is 62.3dB. Figure 20.2.4
summarizes the spectral performance. The SFDR is over 60dB
for all measured frequencies. The DAC was also characterized
with a load current of 5mA. For this condition, the SFDR
dropped by less than 3dB over the Nyquist band. Figure 20.2.5
shows a two tone test with sine waves at 100 and 102.5MHz. The
SFDR in a 17.5MHz wide band is 67.8dB. Figure 20.2.6 summa-
rizes the specifications. Of the power, 2mW out of 4mW is used
by the clock buffering and buffering at the bondpaths. Figure
20.2.7 shows a die photograph. The chip is bondpath limited, and
the active area is less than 0.35mm2. Due to the highly regular
binary structure, the drivers, switches and latches consume very
little area.
Acknowledgments:
We thank Robert Taft and Chris Menkus from National Semiconductor.
This work has been sponsored and manufactured by National
Semiconductor.
References:
[1] C. H. Lin and K. Bult, “A 10-b, 500-MSamples/s CMOS DAC in
0.6mm2,” IEEE J. Solid-State Circuits, vol. SC-33, no. 12, pp. 1948-1958,
Dec 1998.
[2] M. P. Tiilikainen, “A 14-bit 1.8-V 20 mW 1- mm2 CMOS DAC,” IEEE J.
Solid-State Circuits, vol. SC-36, no. 7, pp. 1144-1148, Jul 2001.
[3] M. Borremans, A. V. D. Bosch, M. Steyaert, and W. Sansen, “A Low
Power 10-bit CMOS D/A Converter for High Speed Applications,” IEEE
CICC Digest, pp. 265-268, May 2000.
0-7803-8267-6/04 ©2004 IEEE
 ISSCC 2004 / February 18, 2004 / Salon 8 / 9:00 AM

Figure 20.2.1: Measured INL and DNL plot. Figure 20.2.2: Schematics of a single buffer-latch-switch cell.

Figure 20.2.4: SFDR plot for measured frequencies. The sample rate is
Figure 20.2.3: Measured SFDR plot for a 122.5 Mhz signal at 250MS/s. 250MS/s.

Resolution 10 bit
Decoding binary
Nyquist update rate 250 MS/s
INL < 0.1 LSB
DNL < 0.1 LSB
Differential signal, Iload = 10 mA 500 mVpp
Active area < 0.35 mm2
SFDR up to Nyquist, Iload = 10 mA > 60 dB
SFDR up to Nyquist, Iload = 5 mA > 57.8 dB
Glitch energy, Iload = 10 mA 2.64 pV.s
Power@Nyquist 4 mW + Iload x 1.8 V
Voltage supply 1.5 V and 1.8 V
Technology 0.18 Pm CMOS 1P 5M
Figure 20.2.5: Two tone measurement. Tones at 100 and 102.5MHz. The
SFDR in the shown band is 66.76dB. Figure 20.2.6: Performance specifications.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.7: Chip photograph. The die is bondpath limited.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.1: Measured INL and DNL plot.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.2: Schematics of a single buffer-latch-switch cell.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.3: Measured SFDR plot for a 122.5 Mhz signal at 250MS/s.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.4: SFDR plot for measured frequencies. The sample rate is 250MS/s.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.5: Two tone measurement. Tones at 100 and 102.5MHz. The SFDR in the shown band is 66.76dB.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

 Resolution 10 bit
Decoding binary
Nyquist update rate 250 MS/s
INL < 0.1 LSB
DNL < 0.1 LSB
Differential signal, Iload = 10 mA 500 mVpp
Active area < 0.35 mm2
SFDR up to Nyquist, Iload = 10 mA > 60 dB
SFDR up to Nyquist, Iload = 5 mA > 57.8 dB
Glitch energy, Iload = 10 mA 2.64 pV.s
Power@Nyquist 4 mW + Iload x 1.8 V
Voltage supply 1.5 V and 1.8 V
Technology 0.18 Pm CMOS 1P 5M

Figure 20.2.6: Performance specifications.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.2.7: Chip photograph. The die is bondpath limited.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

320
A 10-bit 250-MS/s Binary-Weighted
Current-Steering DAC
Jurgen Deveugele, Member, IEEE, and Michiel S. J. Steyaert, Fellow, IEEE
Abstract—This paper studies the impact of segmentation on cur-
rent-steering digital-to-analog converters (DACs). Segmentation
may be used to improve the dynamic behavior of the converter
but comes at a cost. A method for reducing the segmentation
degree is given. The presented chip, a 10-bit binary-weighted
current-steering DAC, has 60 dB SFDR at 250 MS/s from DC
to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we
operated the device in 9-bit unary, 1-bit binary-weighted mode.
The obtained 60 dB SFDR in this measurement demonstrates
that the binary nature of the converter did not limit the SFDR.
The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load
currents. The active area is less than 0.35 mm2 in a standard
1P-5M 0.18- m 1.8-V CMOS process. Both INL and DNL are
below 0.1 LSB.
Index Terms—Binary weighted, digital-to-analog converters,
low power.
I. INTRODUCTION
C URRENT-STEERING digital-to-analog converters
(DACs) are well suited to generate broadband signals for
single-hop transmitters. They are fast and able to offer high
spurious-free dynamic range (SFDR) up till high frequencies.
This high level of performance can be achieved since no
internal nodes with large capacitances must be charged or dis-
charged. It has been shown that segmentation, that is, weighting
the MSB current-sources unary and the LSB current-sources
binary, is important for dynamic performance. In [1] and [2],
for example, two similar structures are used for the DAC. The
main difference between both is that the converter in [1] uses
5-bit unary plus 5-bit binary-weighted segmentation, while [2]
uses full binary-weighted decoding. The segmented converter
achieves 10-bit dynamic accuracy up to the Nyquist frequency
for a sample rate of 1 GS/s. The binary-weighted converter,
however, achieves 10-bit dynamic accuracy up to the Nyquist
frequency for only a sample rate of 30 MS/s. However, high
degrees of segmentation do come at a price. Segmentation adds
to the power consumption, complexity and size of the converter.
Too much segmentation can worsen the performance rather
than improve it; the big dynamic core deteriorates timing and
increases the digital noise. The correct timing of a converter
with a big dynamic core can become challenging as the dis-
tances between the various segments is increased and the large
portion of logic adds more load to the clock line. Therefore,
making the assumption that increasing segmentation is the best
Manuscript received December 16, 2004; revised August 19, 2005. This work
was supported and manufactured by National Semiconductor.
The authors are with ESAT-MICAS, Katholieke Universiteit Leuven, 3000
Leuven, Belgium (e-mail: Jurgen.Deveugele@gmail.com).
Digital Object Identifier 10.1109/JSSC.2005.862342
0018-9200/$20.00 © 2006 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
way to boost dynamic performance [3] may ignore better ways
of dealing with dynamic nonlinearities.
Reducing the segmentation degree may thus be advantageous
for the overall performance of the converter. Although some
papers discuss the importance of segmentation [3], it is still
poorly understood. Rather than assuming that extra segmenta-
tion improves the performance, we tried to separate the effects
caused by segmentation from the effects caused by other mech-
anisms. Soon we realized that very few mechanisms for gen-
erating spurious signals are strongly related to the segmenta-
tion. Addressing these mechanisms could thus yield a binary-
weighted DAC with high SFDR at high signal and clock fre-
quencies. So, we designed a binary-weighted converter rather
than a segmented one. We see that the binary-weighted con-
verter is still less tolerant to poor design than the segmented
one, so we chose, for simplicity, to use generous margins on all
parameters.
II. STATIC PERFORMANCE
An -bit binary-weighted converter has only current
sources with sizes ranging from one times the LSB current
to 2 times the LSB current. This can lead to large linearity
errors at the major code transitions. It is important to limit the
linearity errors at these major code transitions, otherwise they
can reduce the obtained SFDR. Therefore, we take a closer
look at this. Our design specifications are as follows:
• INL LSB
• DNL LSB.
A DNL smaller than 1 LSB ensures that the converter is
monotonic: every increase of the digital input code leads to an
increase of the analog output value. The DNL is always smaller
than 1 LSB if the INL is smaller than 0.5 LSB. An INL smaller
than 0.5 LSB guarantees that the maximum linearity error is
smaller than the maximum quantization error. We thus design
for an INL smaller than 0.5 LSB, a common specification
for DACs. Via Monte Carlo simulations, we obtain the plot
of Fig. 1, which shows the yield in function of the standard
deviation for both unary and binary decoding. We aim for a
yield, meaning that 99.7% of the converters must have an INL
smaller than 0.5 LSB. For a yield, the required area is com-
parable in both cases. Simulations show that the expected DNL
is higher for a binary-weighted converter than for a segmented
one. However, our simulations and calculations indicate that
this does not pose a problem for reaching 10-bit accuracy as
long as we meet the mentioned INL and DNL specifications.
Fig. 1 is only correct if all basic current sources have the same
physical dimensions. In many segmented converters this is not
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC
Fig. 1. Yield as a function of the standard deviation  on the current sources
for both unary and binary-weighted converters.
the case. The use of different basic types of current-source tran-
sistors, e.g., transistors with widths equal to 1 m and transistors
with widths equal to 16 m, often leads to systematic errors and
hence reduces static performance. We will take a look at the dif-
ferent options for the current-source array.
A. Unary-Weighted Current Sources
An -bit converter can generate 2 1 different output
codes. In a pure unary implementation of the current-source
array, 2 1 equal current sources are used. Only identical
current sources are used, as one transistor with double the
width will behave slightly differently than two transistors in
parallel. The segmentation level of the current-source array
can be shielded from the segmentation level of the decoder by
putting the correct number of unary-weighted current sources
in parallel, as is explained below.
B. Split Structures for MSB and LSB Current Sources
The current-source array of a 10-bit converter needs 1023
basic current sources in a pure unary implementation. This
amount of current sources requires more area and interconnects
than an implementation with fewer individual current sources.
Therefore, many designers use two different structures for
the MSB and LSB parts. This adds an additional matching
requirement between the biasing currents. Also, care must be
taken to cancel out the differences in systematic errors between
the two structures, to avoid further matching errors.
C. Division of the Current of One MSB Current Source in
LSB Currents
In this case, the current-source array consists of MSB units
only. The current of one unit is further split into smaller cur-
rents. This guarantees that the total current of all LSB sources
matches well to the rest of the structure, as in [4]. The transis-
tors that split this MSB current have relatively relaxed matching
specifications. They require extra voltage to maintain adequate
headroom, so this technique is less suited for low-voltage de-
sign.
321
Fig. 2. One quarter of the switching scheme used. Current sources with
numbers 1 to 15 are used for the pseudo-segments. Current sources with
number 0 are used for the LSB part. The scheme is tolerant to gradient errors
and reduces the impact of the edges of the current-source array.
D. Implementation of the Current-Source Array
We opted for unary-weighted basic current sources. These
basic current sources are connected in parallel to weight them
binary. There is no distinction between MSB and LSB basic
sources, eliminating this systematic error. The large number of
basic sources is used to reduce the gradient errors [5]. It is also
used to reduce the influence of the errors on the current sources
close to the edge of the array [6]. Dummies around the current-
source array further reduce the linearity degradation caused by
the edges.
One quarter of the switching sequence is shown in Fig. 2. Our
converter is binary-weighted, but we design it as if it were a 4-bit
unary, 6-bit binary segmented converter. Then we replace the
4-bit thermometer decoder by a binary-weighted decoder. We
call this approach “pseudo-segmentation.” The pseudo-segmen-
tation is reflected in the switching scheme. The current sources
with numbers 1 to 15 form the 15 pseudo-unary current sources.
The current sources with number 0 are used to form the LSB cur-
rent sources. This pseudo-segmentation is mainly used for the
dynamic behavior and will be discussed later.
The measurements of our binary-weighted DAC show that the
current-source array has good static linearity. We have an INL
and DNL both smaller than 0.1 LSB. As we stated in the begin-
ning of this section, an INL smaller than 0.5 LSB is sufficient
for the dynamic performance.
III. DYNAMIC PERFORMANCE
In the previous section, we have shown that the static be-
havior is not responsible for the low dynamic performance of
most binary-weighted DACs; the difference in performance be-
tween segmented and binary-weighted converters must be found
somewhere else. We track it by comparing the difference in
structure between a unary-weighted and a binary-weighted con-
verter.
A. Pseudo-Segmentation
Segmented current-steering DACs perform well at high fre-
quencies, but the published binary-weighted converters in the
literature do not. Ideally, the only difference between both struc-
tures is located in the digital part: the bits are decoded in another
322
Fig. 3. Scheme for a segmented converter. The converter has a decoding stage,
a switching core with the switches, cascodes and latches, and a current-source
array.
Fig. 4. The thermometer decoder seen in Fig. 3 is replaced by a
binary-weighted one, shown here, in order to obtain a fully binary-weighted
converter.
way. We believe, therefore, that the best way to design a bi-
nary-weighted converter is to design a segmented one, replacing
the 4-bit thermometer decoder by a binary-weighted decoder.
In this way, we modify the converter just enough to make it bi-
nary-weighted. We call this approach “pseudo-segmentation”.
It is indeed very tempting to scale some parts of the design if
they seem to be oversized. This scaling, however, may for ex-
ample generate different delays for the different bits. We also
narrow the design space. Fig. 3 shows the outcome of the first
step, the design of a general segmented converter. Then, we re-
place the thermometer decoder by the decoder shown in Fig. 4.
The “switching core” holds all the switches, latches, cascodes
and cascodes above the switches.
B. Glitch Energy
The glitch energy is the energy difference between the ideal
transition and the real transition, as Fig. 5 shows. The major
code transitions have the biggest glitch energies. Fig. 5 shows
that most of the energy is due to the slower-than-ideal transition.
This is not an issue to most designers, as this happens for all tran-
sitions and does not affect linearity. Therefore, most glitch mea-
surements show the major transi-
tion.
However, for time-domain applications such as video DACs,
such waveform distortion from transitions is undesired. This
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
Fig. 5. The glitch energy equals to the energy difference between the ideal
transition and the real transition. Most of the energy is due to the slower than
ideal transition.
distortion shows up in the video image. For frequency-domain
applications, the effect of transitions on the SFDR and SNDR in
the frequency-band of interest is more important. In this work,
we focus on DACs with high SFDR.
C. Glitch Energy and Unary Decoding
In a unary-decoded DAC, exactly
switches are switched on or off for a code transition from
to . Ignoring the quantization, the code
change is the derivative of the signal to the time.
The signal can be represented by its frequency components.
Each frequency component is a sine wave with a certain ampli-
tude and phase. The derivative of each sinusoidal component is
a sinusoid with the same frequency. If all transitions are equal
and proportional to the code change, then the code transitions
generate spurs at the signal frequencies themselves, creating no
distortion components [3].
However, the condition that all transitions are equal is often
not fulfilled; the up-transitions may differ from the down-transi-
tions. The transitions are also dependent on the output voltage.
Both effects lead to signal dependencies of the glitch and
thus cause dynamic nonlinearities even for unary-decoded
converters.
D. Glitch Energy and Binary Decoding
In a binary-decoded DAC, at least
switches are switched on or off for a code transition from
to . Another switches are switched si-
multaneously on and off. During switching we have thus a
superposition of (a) the transient effect of the unary-decoded
converter, and (b) the transient effect of the switches that are
switched simultaneously on and off. Therefore, the dynamic
nonlinearities are a superposition of the dynamic nonlinearities
of a unary-decoded converter and the additional dynamic non-
linearities of the binary-decoded converter. This is in line with
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 323

Fig. 6. Basic buffer-latch-switch structure.

the common belief that binary-weighted converters produce

more spurs than segmented ones.
Fig. 6 shows the basic buffer-latch-switch structure. If the
sum of the currents through the switches M7–M8 remains
constant at all times, then the additional dynamic nonlinearities
from the binary switching are not seen. For example, in the
transition from code 511 to code 512, there are 511 switches
switched off and 512 switches switched on. If the sum of the
currents through the switches M7–M8 remains constant at all
times, then the 511 currents that are switched off are perfectly
compensated by another 511 currents that are switched on.
These 511 simultaneous up and down transitions are then not
seen. Only the one additional switch that is switched on is seen
at the output. The converter then behaves as a unary-decoded
one. Note that this condition requires that all transitions are
equal and signal independent. In other words, if we can make
a binary-weighted DAC that performs as well as a segmented Fig. 7. Exponential up and down transitions with different time constants.
converter, then we can control the additional nonlinearities.
This can only be achieved by reducing the signal dependencies differences often are smaller in the binary-weighted converters
during switching, making the binary-weighted DAC the ideal as these devices are simpler and smaller structures.
test case to verify if the switching is well controlled or not.
A. Different Up and Down Transitions
We define both transitions to be exponential functions with
IV. MODELING THE BINARY-WEIGHTED CONVERTER different time constants. They are plotted in Fig. 7. Example
time waveforms for a unary and a binary-decoded 16-bit con-
In the previous section, we qualitatively discussed the glitch verter are shown in Fig. 8. The input code is a step function
energy and its relation to segmentation. Here, we model it to with a step size of 2048 LSB.
get quantitative results. We only model two effects: the effect of Fig. 9 shows the simulated SFDR as a function of the rela-
the different up and down transitions, and the influence of the tive frequency for both unary and binary-weighted converters,
output voltage on the switching time. In [7], the impact of time single-ended. At the in-band distortion
skew and jitter on binary and unary-weighted structures is mod- caused by these effects is located at the same frequency as the
eled. The models show that the binary-weighted architectures signal, explaining the irregularity in the plot. We see that the dif-
have slightly smaller SFDR due to timing differences than the ferent up and down transitions have more impact at low frequen-
unary architectures. We agree with this, but add that the time cies in the binary-weighted converter. At high frequencies, the
324
Fig. 8. Example waveforms for unary and binary-decoded 16 bit converters.
Between times 4000 and 5000, a major glitch is seen in the binary-decoded
signal due to the transition of the MSB.
Fig. 9. Simulation of the SFDR as a function of frequency with different up
and down transitions, single-ended. (upper plot) Unary-weighted converter.
(lower plot) Binary-weighted converter.
unary-decoded converter is more susceptible to this effect. The
effect of the different up and down transitions has even-order
distortions only. Therefore, it is not necessary to simulate the
differential case.
B. Influence of the Output Voltage on the SFDR
A high output voltage is preferred as it increases the signal
power. The output voltage, however, is likely to influence the
transitions from one code to another. Transistors M7–M10 in
Fig. 6 are operated in the saturation region. They act as cas-
codes between nodes N7, N8, and N9. Due to the finite gain of
the transistors some part of the output voltage is seen on node
N5–N6 and N9. This influences the timing of the switching. In
our model, we define the transition waveforms to be exponen-
tial functions that have time constants that are dependent on the
output voltage. If the input code is increasing, then the rise time
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
Fig. 10. Simulation of the influence of the output voltage on the
SFDR, single-ended. (upper plot) Unary-weighted converter. (lower plot)
Binary-weighted converter.
Fig. 11. Simulation of the influence of the output voltage on the SFDR,
differential-ended. (upper plot) Unary-weighted converter. (lower plot)
Binary-weighted converter.
is modeled to be dependent on the mean value of the output be-
fore and after switching. We make this assumption because we
believe the rise time is dependent on both the output voltage
at the beginning of the transition and on the output voltage at
the end of the transition. If the code is decreasing, we make the
fall time dependent on the output voltage of the complementary
output in order to keep the fully differential nature of the struc-
ture.
Fig. 10 shows the influence of the output voltage on the SFDR
for the single-ended case. The spurious signals caused by the
output voltage are even and odd order. The results for the dif-
ferential case are shown in Fig. 11. Here again, we see that the
unary-decoded converter outperforms the binary-decoded at low
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC 325

frequencies, but has poorer worst-case performance over the en-

tire Nyquist range.

C. Influence of the Transition Time

In the previous subsection, we modeled the transition time
to be dependent on the output voltage. In this subsection, we
make the assumption that slow transitions align with larger time
differences due to the output voltage. In other words, we assume Fig. 12. Simplified schematics of the basic buffer-latch structure.
that the influence on the transition time is relative to the total
transition time.
We resimulated the influence of the output voltage with twice
as large time constants and equal relative impact on these time
constants. On average, the SFDR is over 8 dB worse. It is thus
important to have transitions that are as fast as possible.

V. IMPLEMENTATION
Our analysis (and the analysis in [7]) both indicate that there
is no clear reason why a unary (or segmented) converter outper-
forms a binary-weighted converter by an order of magnitude in
published designs. We also showed that transition times must
be as fast as possible. We therefore opt to make a pseudo-seg-
mented converter with as fast as possible transition times. A
pseudo-segmented converter is identical to a segmented one, ex-
cept that the bits at the input of the segments are decoded binary
instead of unary. Fig. 13. Example simulated waveform when the clock turns high.

A. Differences Between Segmented and Pseudo-Segmented

Structures
The converter can be split into two parts. The decoder trans-
forms the binary input code into a number of bits used by the
analog part. The analog part takes these digital signals as inputs
and generates the appropriate output current. The only differ-
ence between a segmented and a pseudo-segmented converter
is how the digital part decodes the input code. This difference
has been modeled in the previous section and does not seem to
reduce the SFDR over the Nyquist range. However, the interface
between the digital and the analog structure is often carried out
differently.
For example, the same driver is used for the MSB as for the
smaller bits. More subtle differences do exist. The digital part
of the segmented converter often has a large driving capability
whereas the binary-weighted converter often has a minimum-
size digital connection to the analog part.
B. Basic Structure
The basic schematic for a pseudo-segment is depicted in
Fig. 6. The input buffer, latch, the David–Goliath inverters, and
parasitic capacitances are depicted in Fig. 12. Note that we
transform the differential schematic from Fig. 6 to an equivalent
single-ended schematic in Fig. 12. Inverters I1 and I2 are the
differential David inverters, and transistors M2 to M5 form the
differential Goliath inverters. Nodes N10 and N11 in Fig. 12
match with nodes N1 and N2 for the left side of the differential
structure seen in Fig. 6, and with nodes N4 and N3 for the right
side of the schematic. Inverter I3 is composed by transistors
M11 and M12 for the left part of the differential circuit and by
transistors M13 and M14 for the right part. Inverter I3 acts as
an inverting buffer, buffering the digital input. Capacitance C2
holds the current state of the segment. Capacitance C1 holds the
next state. The David–Goliath structure is used to regenerate
the node while the clock is low.
If the clock is switched to high, then nodes N10 and N11
are shorted. If both states differ, then the two nodes with dif-
ferent voltages are shorted. A capacitive division between C1
and C2 occurs. This can temporarily flip the digital value stored
on node N10. This transition can take a long time depending
on the driving strength of inverter I3, the parallel capacitance
of C1 and C2 and the strength of the David inverter. Example
waveforms are shown in Fig. 13 when the clock turns high. Note
that this simulation still assumes a reasonably big capacitance
C1 and driving inverter I3. Increasing the driving strength of in-
verter I3 and the capacitance on node N10 from minimum sizes
to 30 times the minimum size increases the simulated SFDR in
Spice by roughly 20 dB. This increase in SFDR is mainly at-
tributed to the increased switching speed. To be more precise,
we increased the dimension of the nMOS transistor from min-
imum size to 30 times the minimum size. We increased the di-
mension of the pMOS transistor from 2 times the minimum size
to 60 times the minimum size. This increases the power con-
sumption, but the total power consumption still remains small.
The waveforms plotted in Fig. 13 are simulated with an inverter
I3 that has four times the minimum dimensions.
C. Power Savings of the Design
It is clear that a binary-weighted converter has a very simple
decoder. This far less complex decoder consumes only a small
amount of power. Furthermore, we have a very regular structure.
In the layout, we only use parallel instances of the switching
326 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006

Fig. 14. Unoptimized layout of parallel inverter instances.

Fig. 15. Mirrored layout of parallel inverter instances reduces the area requirements and the parasitic capacitances.

core segments. Fig. 6 shows the schematic of the switching core

segments together with the current source. For the 4 MSB, the
blocks are identical, that is, for the MSB 8 of those blocks are
placed in parallel. For the second MSB 4 of those blocks are
used in parallel. For the 6 LSB, the switching core segments are
almost identical. They only differ in the sizing of the switches,
the cascodes and the cascodes above the switches. As these tran-
sistors have smaller sizes, they still fit in the same area as the
basic layout.
The “binary decoder” is just a number of parallel buffers. We
call these buffers the decoder buffers. These buffers are simple
blocks that fit easily in a very regular layout. Combining the
switching core segments and the decoder buffers we have a
very regular basic block and layout instance. We place these in-
stances in a mirrored fashion on the layout. We then can share Fig. 16. Measured INL and DNL.
power supplies, wells and sources of the transistors connected
to the power supplies. Sharing these layout features reduces the
pitch of the instances quite a bit.
An example layout for a simple inverter is given in Fig. 14 be-
fore and in Fig. 15 after sharing the layout features. The result
of using very regular, layout-optimized and mirrored basic in-
stances is that we have a very regular and compact decoder and
switching core with a high fill factor. We use only very short
connections between all devices. This results in minimal para-
sitic capacitances. Due to these small connections, it is easy to
control the delay differences. This reduces the need to oversize
the devices driving these lines. Furthermore, the clock line is
small and has a small load. This decreases the power consump-
tion of the clock, maintaining the desired sharp clock edges.
The removal of the thermometer decoder requires precaution.
Our simulations showed that two things are critical to make
high-performance binary-weighted DACs: all segments must be
as close to equal as possible, and the switching must be as fast
as possible. As explained in Section V-B, the switching speed
Fig. 17. Measured spectrum for a 122.5-MHz signal at 250 MS/s.
is strongly increased if we increase the size of the buffer. We
thus traded the accuracy of the latch for speed. Compared to
the latch presented in [1], our latch is simpler, faster, and con- eraging [10] of the current sources, again reducing power con-
sumes less power. Because we traded accuracy for speed, we do sumption. In the entire converter, we do not use power-hungry
not need any correction on the operating point [8]. We there- operational amplifiers nor gain-boosting [4]. All the simplicity
fore avoid the associated power consumption. Because we used in the design thus allowed us to have low power consumption
a good switching sequence for reducing the systematic errors while the optimization of the latches allowed us to have good
[6], we did not need background calibration [9] or dynamic av- dynamic performance.
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC
Fig. 18. SFDR plot for measured frequencies. The sample rate is 250 MS/s.
Fig. 19. Two-tone measurement. Tones are at 100 and 102.5 MHz. The SFDR
in the shown band is 66.76 dB.
VI. MEASUREMENT RESULTS
All measurements are done at 250 MS/s with 10-mA load cur-
rent unless explicitly stated otherwise. Fig. 16 shows the mea-
sured INL and DNL, which are both within 0.1 LSB. Fig. 17
shows the spectrum for a 122.5-MHz single-tone signal. The
SFDR is 62.3 dB in the Nyquist band. The measurements are
differential, but still we have large parts of second-order distor-
tion in the measurement results. Fig. 18 summarizes the spectral
performance for the full-scale single-tone signals. The SFDR is
over 60 dB for all measured frequencies. We also measured the
DAC with a load current of 5 mA, because many published re-
sults stress that it is important to have a good crossing point
[8]. By using only half of the current that the converter is de-
signed for, we operate it far from the optimal crossing point.
This leads to a less than 3-dB SFDR drop over the Nyquist
band. This demonstrates that our buffer-latch combination is in-
sensitive to the exact crossing point. We have thus successfully
traded precision for speed in the latch, easing deep-submicron
integration.
327
Fig. 20. Measured spectrum for a 0.01 2 full-scale signal around the midcode.
2
Fig. 21. Measured SFDR for 0.01 full-scale signals +40 dB. The SFDR for
full-scale signals is plotted for comparison.
Two-tone tests and small-signal tests around the middle code
are important for a binary-weighted converter. Fig. 19 shows
a two-tone test with sine waves at 100 and 102.5 MHz. The
SFDR in a 17.5-MHz wide band is 67.8 dB. Fig. 20 shows the
spectrum for a small signal that has only codes ranging from
506 to 517 around the middle code. So, we positioned the signal
around the major transition, the
worst possible location. Fig. 21 shows the measured SFDR for
the 0.01 full-scale signals plus 40 dB. The plot shows that the
spurious do not get worse for smaller signals. Therefore, the
dynamic range is not compromised by the binary structure.
We also measured the
sequence.
With this dataset, the converter actually works as if it were
a 9-bit unary 1-bit binary segmented converter. This one se-
quence allows us to have an idea about the performance that
an equivalent segmented converter would have. The measured
328
TABLE I
SPECIFICATIONS
Fig. 22. Chip photograph. The current-source array and the drivers, switches,
and latches are indicated. The chip is bond-path limited. Most of the area is filled
with dummies.
SFDR here is also 60 dB, indicating that the binary weighting of
the converter did not limit the SFDR and that the two modeled
effects in Section IV are not dominant.
Table I summarizes the specifications. The clock buffer and
the buffers that we placed at the bond-paths for regenerating
the signal strength of the input signals consume 2 mW out of
4 mW. Fig. 22 shows a die photograph. The chip area is bond-
path limited. The active area is less than 0.35 mm . Due to the
highly regular binary structure, the drivers, switches, and latches
require only a minimal amount of area. They are denoted as the
switching core in Fig. 22.
VII. COMPARISON WITH OTHER BINARY-WEIGHTED DACS
In [11], a 14-bit binary-weighted and calibrated DAC is pre-
sented. It has 84 dB of SFDR at low signal frequencies but it
drops fast as the signal frequency is increased. The converter
in [2] had the highest SFDR at high frequencies for a binary-
weighted converter known to the authors. Our converter has
60 dB SFDR at 5 times higher sample rate and at 8 times higher
signal frequencies. The frequency behavior of each design is
shown in Fig. 23 and Table II compares specifications.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006
Fig. 23. SFDR of published binary-weighted converters.
TABLE II
COMPARISON WITH OTHER BINARY-WEIGHTED DACS
VIII. CONCLUSION
In the presented work we studied the differences between
unary-weighted and binary-weighted converters. The work pre-
sented in [2] and in [7] and our modeling here indicated that it
had to be possible to build binary-weighted DACs with high dy-
namic performance. We discovered that the boundary between
the decoder and the latch is critical as the signals there are both
analog and digital. This problem can be alleviated by increasing
the capacitance on this node and by making all buffer-latch
structures identical. Using this approach, we managed to de-
sign and measure a 250-MS/s 10-bit binary-weighted current-
steering DAC with over 60 dB SFDR over the entire Nyquist
bandwidth. Specific codes exist where the spectral behavior is
identical to the one of a highly segmented converter. At these
codes, the performance did not increase. The binary nature of
the converter thus did not pose limits to the SFDR. The perfor-
mance drop while operating the device far outside the nominal
operating point was limited, showing that the accuracy in the
latch can be traded with speed. These new insights allow for
DEVEUGELE AND STEYAERT: A 10-bit 250-MS/s BINARY-WEIGHTED CURRENT-STEERING DAC
fast and compact current-steering converters that scale well in
deep-submicron technologies.
ACKNOWLEDGMENT
The authors thank R. Taft and C. Menkus for their support at
tape-out.
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[1] A. V. den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit
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[2] M. Borremans, A. V. den Bosch, M. Steyaert, and W. Sansen, “A low
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[3] C.-H. Lin and K. Bull, “A 10 b, 500 M sample/s CMOS DAC in 0.6
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[4] A. Bugeja, B. Song, P. Rakers, and S. Gillig, “A 14-b, 100-MS/s CMOS
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[5] G. V. der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G. Gielen,
“A 14-bit intrinsic accuracy Q random walk CMOS DAC,” IEEE J.
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[6] J. Deveugele, G. V. der Plas, M. Steyaert, G. Gielen, and W. Sansen,
“A gradient-error and edge-effect tolerant switching scheme for a high-
accuracy DAC,” IEEE Trans. Circuits Syst. I: Fund. Theory Appl., vol.
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[7] K. Doris, C. Lin, and A. van Roermund, “Synchronization distortion and
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(ProRISC), The Netherlands, Nov. 2000, pp. 259–266.
[8] B. Schafferer and R. Adams, “A 3 V CMOS 400 mW 14 b 1.4 GS/s
DAC for multi-carrier applications,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, vol. 47, Feb. 2004, pp. 360–361.
[9] Q. Huang, P. A. Francese, C. Martelli, and J. Nielsen, “A 200 Ms/s 14
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[10] K. O’Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, “A 12-bit
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[11] M. P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm CMOS DAC,” IEEE
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Jurgen Deveugele (S’01–M’05) received the
Master’s degree in electronic engineering and the
Ph.D. degree in electronics from the Katholieke Uni-
versiteit Leuven (K.U.Leuven), Heverlee, Belgium,
in 1999 and 2005, respectively.
His main research interests are in low-power
and high-speed current-steering digital-to-analog
converters.
Michiel S. J. Steyaert (S’85–A’89–SM’92–F’04)
received the Master’s degree in electrical-mechanical
engineering and the Ph.D. degree in electronics from
the Katholieke Universiteit Leuven (K.U.Leuven),
Heverlee, Belgium, in 1983 and 1987, respectively.
From 1983 to 1986, he obtained an IWNOL fel-
lowship (Belgian National Fundation for Industrial
Research) which allowed him to work as a Research
Assistant at the Laboratory ESAT at K.U.Leuven.
In 1987, he was responsible for several industrial
projects in the field of analog micropower circuits
at the Laboratory ESAT as an IWONL Project Researcher. In 1988, he was a
Visiting Assistant Professor at the University of California, Los Angeles. In
1989, he was appointed by the National Fund of Scientific Research (Belgium)
as a Research Associate, in 1992, as a Senior Research Associate, and in 1996,
as a Research Director at the Laboratory ESAT, K.U.Leuven. Between 1989 and
1996, he was also a part-time Associate Professor. He is now a Full Professor
at the K.U.Leuven. His current research interests are in high-performance and
high-frequency analog integrated circuits for telecommunication systems and
analog signal processing.
Prof. Steyaert received the 1990 and 2001 European Solid-State Circuits Con-
ference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-
Bell-Telephone award for innovative work in integrated circuits for telecommu-
nications. He received the 1995 and 1997 IEEE ISSCC Evening Session Award
and the 1999 IEEE Circuit and Systems Society Guillemin–Cauer Award.
A 1-V 2.5-mW Transient-Improved Current-Steering DAC
using Charge-Removal-Replacement Technique
Ka-Hou Ao leong, Seng-Pan U 1 and R.P. Martins 2
Analog and Mixed-Signal VLSI Laboratory, FST, University of Macau, Macao, China
1-Also with Chipidea Microelectronics (Macao) Ltd., 2-On leave from Instituto Superior Tecnico (IST)/UTL, Lisbon, Portugal
Abstract - A charge-removal-replacement (CRR) technique is
proposed to realize a low-voltage low-power current-steering
digital-to-analog converter (DAC) for minimizing transition time
in current switching. Implemented in a 0.18-pm CMOS process,
the 10-bit 120-MS/s DAC focused on WLAN applications
consumes only 2.5 mW from a single 1-V supply. The simulated
monotonic performances achieve a mean value of IINLI < 0.14
LSB and IDNLI < 0.18 LSB, respectively. The averaged SFDR
obtains 67.23/62.45 dB with/without the CRR technique.

I. INTRODUCTION
The demand for high performance digital-to-analog converters
(DACs) has obviously increased for the fast development of (a) (b)
Fig. 1 (a) Cascoded-current-source and (b) cascoded-switch topology.
advanced telecommunication systems, e.g., wireless local area
networks (WLANs). In view of that, most of data converters are
desired to be fully integrated into a CMOS System-On-a-Chip
(SoC) wireless transceiver with including RF transceiver, digital
physical layer (PHY), corresponding media access controller Vm+rnt CRR , OFF
(MAC) and all other analog baseband building blocks [1]. To
avoid any supply-voltage constraints for the technology scaling,
low-voltage building blocks with low-power consumption is Ml' - ONH
highly required. vssvss ~~~~~~~~~~~~Time
In practice, current-steering DAC is preferred for wireless
communications due to its high sample rate, capability of driving
resistive loads and relatively low-power consumptions. The
current cells with cascoded topologies as shown in Fig. 1 are
satisfactory for static and dynamic output-impedance requirements
[2]-[3]. Alternatively, the cascoded-switch topology [4] presents as
additional digital signal feedthrough isolation and output influence nVwell nAwell A VSSTime
reduction through the insertion of two cascoded transistors (M,a,+ (a) (b)
and M, -). However, asymmetry in rising-falling transitions and Fig. 2 (a) Operational principles of CRR technique and (b) the
long settling time will degrade the dynamic performance directly, corresponding control signals.
especially applied in high speed and high resolution DAC which
unit current is small. This paper proposes a charge-removal- cascoded switch (Me.,lVLa) enters in the subthreshold region. As
replacement (CRR) technique that fixed those transient problems. a result, an amount of current leaks into the path even if the
For demonstrated purposes, a 1-V 10-bit 120-MS/s DAC with less corresponding switch is in the off stage. Such current is given by
than 1.3-jtA unit current was designed and simulated, the current the subthreshold expression of the drain current (ID),
switching transient is highly reduced and the dynamic
performances of the DAC are dramatically enhanced. ID =Io exp V><(1)
After this introduction, the proposed CRR technique will be where ;>I is a nonideality factor and VT=- kT q. Moreover, with
presented in section II. In section III, it will be applied to a low- parasitic capacitance present in the source terminal of cascoded-
voltage current-steering DAC with a detailed description of each transistor Mc,. Mc,. , the transition will be further extended.
building block. In section IV, simulation results will be presented.
Finally, the conclusions will be summarized in section V. Operational Principles The CRR technique is depicted in
Fig. 2(a), where a capacitor (CcR) driven by an inverter is inserted
II. CHARGE-REMOVAL-REPLACEMENT TECHNIQUE between the gate and drain terminals of the switched transistor.
The main disadvantages of the conventional cascoded-switch When the desired switch is turning off, the inverter generates an
current source (CSCS) topology are the long settling time and inverted control signal to draw out the positive ((IqD)
charge from
asymmetry settling time (falling settling time is slower than that in the inversion layer and the ubiquitous parasitic capacitance at node
rising), which distorting output current of the DAC. The tarry Xb such that any lengthy discharge procedure can be eliminated.
falling settling time is caused by the node voltage, which below To avoid current sources from being turned off simultaneously,
the off switch (MA,,1M,), is discharged exponentially until the digital control signals with lower crossing point apply to the switch

183
1-4244-0387-1/06/$20.00 (@2006 IEEE
 1

LU)

0
a)

(a)
1
5
-o
< settle ,,wl CRR
CRR
a *
'a 1

LU, n0.5

D. o -1. \ ,~~~~~~~~,
settle

- 5 10 15 20 25 30 35 40 45
I
50
0 20M 40M 60M 80M 1 OOM 120M
Input Code Rate of Unit Current Cell (Hz)
Time (ns)
Fig. 4 Input code rate vs. instantaneous node voltage vx settling level, and
(b) rising/falling delay of differential output current.
05 a-- settle C
5n
0.4- ..R
not settle |_ .................
(L RR
0)
.................
|0 fl j=j ~~~~~~~~~~.
...
0.3 settle

tt......
0.2._
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.......

0 5 10 15 20 25 30 35 40 45 50
o
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[1

. . . . . . . . . . . . . . . . .~ . . . . . . . .
Time (ns) ......... V rio _C8
tion ..

(c)
Fig. 3 (a) Single-ended output current, (b) differential-ended output .. C ........ ........... ............................

current and (c) node voltage vx of unit current cell.

inputs [Fig. 2(b)]. If the switching control signals directly cross-

couple to the capacitor CCRR, the charge Aq+ will draw
continuously when the path is turned off Thus, the inverter is
necessary required to generate a delayed control signal to balance
the falling and rising transitions.
Timing Benefits - Two advantageous features are summarized Fig. 5 Rising/Falling delay with capacitor variation

[different] I[average]
below: (t: Calculated by in the range of input code rate.)

(a) Balanced Speed and Advanced Transition: The CRR

technique improves the rising transition by replacing some positive thus, requires different charging time in every clock cycle,

charge, given that the node voltage vx is faster settling to its resulting in a non-constant rising delay for switching on the current

steady-state value while the current path is turning on. On the other path. As shown in Fig. 4, the CRR technique reduces the variation

hand, when the current path is desirable turned off, the CRR of vx from the steady-state voltage for different switching rates,

technique removes the residual charge and prompts the node and it also leads the rising/falling delays of the differential output

voltage vx to steady state (i.e., vx is leaded to reduce). Therefore, currents to be more independent of the input code rate. In fact, the

the cascoded switches no longer suffers from the critical difference between rising/falling delays is dependent on the

exponential discharge problem, establishing balanced falling and capacitance of CCRR. With capacitor variation, the performance is

rising speeds. As illustrated in Fig. 3(a), the falling transition of a slightly degraded as shown mn Fig. 5. However, the tmprovement is

single-ended output current is enhanced in terms of speed to still significant when comparing with the performance of

achieve more balanced rising-falling characteristic. Even though a conventional structures. Furthermore, pushing the cascoded

differential-ended output signal [Fig. 3(b)] can suppress even- switches to the deep subthreshold region can eliminate the induced

harmonic distortion in the conventional CSCS structures, the current, such that the accuracy of the D/A conversion will not be

transient nonlinear problem still exists, which can be solved by the degraded.

CRR technique presented. Output-Impedance Influence -The output impedance of the

(b) Recovered Synchronization for Each Current Source: In the current source affects both the static and dynamic linearity of the
current-steering DAC, the digital control input signals switch the DAC. The output resistance of CSCS is given by [3],
correspondent current paths on/off Delay differences among
active current paths create an input-data-dependent nonlinearity Rout = maGstoatstc (2)

and increase the susceptibility to asynchronous glitches. The and the output impedance (Z0ut) has two poles and two zeros as:

conventional CSCS endures input-data-dependent delay even the

clock nets are perfectly synchronized. The reason is the node Pi P2 = mc=as (3 )
2Zcr0csCo 2ZcrosC1 hcC0 2zcC1
voltage vx requires a long settling time, even though the output
current has already settled [Fig. 3(b) and (c)]. The node voltage vx,

APCCAS 2006
184
 0.1k 10k IM 1O0M 1 OG
Frequency (Hz)
Fig. 6 Output impedance with and without CRR.
where gm, and ro are the transconductance and output resistance of
the corresponding transistors, respectively, as noted in Fig. 6.
The CRR technique inserts an additional capacitor CCRR into
the current cell, which is equivalent to an increase of the
capacitance C1 and a frequency shifting of the pole P2 to a lower
value. As illustrated in Fig. 6, this effect can be neglected (i.e.,
only 1-kHz difference) because the add-on capacitor CC is
typically small in size.
III. DESIGN EXAMPLE
A 1-V 10-bit 120-MS/s fully binary-weighted current- steering
DAC with the CRR technique was designed for WLAN
applications. The floor plan is shown in Fig. 7, where the circuit
consists of a set of digital input buffer, a clock driver, a biasing
circuit, a switch & latch array (SWATCH), and a current-source
array (CSA). Utilizing a transimpedance output stage [5], which
has a lower input impedance node, improves static and dynamic
linearity concurrently. However, this current-to-voltage buffer is
normally required to drive a smaller feedback resistor, imposing
large power dissipation. For power saving, instead of using the
transimpedance output buffer, the designed DAC drives a resistive
load (RL) directly [6].
Current Source Array (CSA) - In the conventional current-
steering DAC, the segmented architecture improves the DNL and
glitch performance by using more unary decodes. However,
increasing the use of unary decoding occupies large chip area,
increases power, digital noise, time skews and design complexity.
In the design of a 10-bit DAC with an equal structure and a fully
binary decode [7] is more attractive to achieve low power, high
accuracy, linearity and speed, as well as size compaction.
The matching is critically determined by the area of the unit
current source. In the behavioral-level simulation, a maximum
relative standard deviation (alIl) of a unit-current source is 0.2%
for correct INL and DNL yields (99.7% yield for INLI and IDNLI<
0.5 LSB). In fact, aqJ, of a binary-weighed DAC is normally
determined from the DNL yield. The minimum area (WL)m,n of the
unit current source is estimated by [8],
(W L)min )2 L D
where AA and A vTare the matching parameters, and (VGS-VT) is the
overdrive voltage of the current source transistor.
APCCAS 2006
clk BO B9
Fig. 7 Floor plan of the designed fully binary-weighted DAC.
Switch + Latch (SWATCH) - The switch array of the DAC
is constructed by cascoded switches to enhance the output
impedance of the current sources. In practice, the length of the
input (L,) and cascoded (Lca,) switches is chosen at minimum
length to further reduce the digital feedthrough. Beside the effect
of finite output impedance, the dynamic performance of a current-
steering DAC is mainly limited by the imperfect synchronization
of the control signals and the drain-voltage variation of the current
source. For lowering the glitch errors as the current is switched to
the desired output, it is essential that the driving signals exhibit a
lower crossing point. The rise/fall-time-based latch [9] has been
exploited for its high-speed capability [Fig. 7], and NMOS positive
feedback loop exhibits a faster fall than rise time of the latch.
Moreover, an additional feedback using small inverters (IH and I2)
reduces the clock-feedthrough (CFT).
The CRR technique is embedded into the swatch array, and the
PMOS capacitor (Mc) is utilized instead of capacitor CCRR for area
saving. In this way, not only the charge injection is reduced
(similar to a dummy switch), but also removed/replaced the
positive charge while improving the transient characteristic and
dynamic performances.
In the designed DAC, the full-scale current is 1.25 mA and the
resistive load RL is 200 Q. The resulted differential peak-to-peak
output voltage is 0.5 V.
IV. SIMULATION RESULTS
A 1-V 10-bit DAC simulated using 0.18-ptm CMOS
technology was designed to demonstrate the above technique. To
evaluate the static linearity performance of the DAC, 300-time
INL and DNL Monte-Carlo simulations are illustrated in Fig. 8(a)
and (b), respectively. The statistical histograms show that the JINLI
and IDNLI exhibit a [mean, standard deviation] of [0.134, 0.049]
and [0.178, 0.081] LSB, respectively. The scatter plot obtained
from the same Monte-Carlo simulations [Fig. 8(c)] clearly shows
that the required specifications are met with the appropriate margin.
As mentioned, the CRR technique can improve the switching
behavior of the current cells. In order to compare the dynamic
performance between the conventional and the proposed technique,
185
 60. 60. 0.5 .

N = 300 N = 300 0.45

Mean = 0.134 Mean = 0.178
50 Sta Div= 0.049
50 Sta Div= 0.081 0.4
0.35
40 40
a
CO 0.3

30 30 2 0.25

02
20 20
0.15
0.1
10 10
0.05

00_ 0.3 0.35 0.4 0.45 0.

OL 5 0.5
0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
,B) JINLI (LSB)
(a) (b) (c)
Fig. 8 Histogram of (a) INL, (b) DNL and (c) scatter plot of INL vs. DNL from a 300-time Monte-Carlo simulation.
0 0 76
O-----------O/P signal wfo CRR ----------O-
-VP signal w CRR Desired Signal Band
-20 -20f
72-
-40 -40
: ~~~~~56.30 dB 63.72 dB 70
-60 -60 m68
m \.

a -80 a 80 L66
bn nCD
-100 0
10

-120 -120
6
Output..Signa Fre. ....

-140 -140 Conventional

avg SFDR 6245 dB

-1 60' '

0 1OM 20M 30M 40M 50M 60M 0 1OM 20M 30M 40M 50M 60M :::M 1M
Frequency (Hz) Frequency (Hz)
(a) (b) (c)
Fig. 9 Simulated output spectrum at 5 MIHIz, 120 MS/s (a) without and (b) with CRR technique. (c) SFDR vs. output signal frequency.

the output spectrums are presented in Fig. 9 (a) and (b), chip area overheads. In average, 4.78-dB improvement in SFDR is
respectively. With the new technique, the averaged SFDR is achieved within the Nyquist band.
improved by 4.78 dB within the Nyquist band [Fig. 9(c)]. A
summary ofthe simulation performances is listed in Table 1. ACKNOWLEDGMENT
This work was financially supported by the University of
V. CONCLUSION Macau under the research grant with Ref No RG069/02-03S/
This paper presented a charge-removal-replacement (CRR) MR/FST.
technique for improving the transient performances of current- REFERENCES
steering DACs. Adopted in a 1-V 10-bit 120-MS/s fully binary-
weighted current-steering DAC, the technique removes (replaces) [1] S. Mehta, et al., "An 802.11g WLAN SoC," in IEEE ISSCC, Digest of
the node charge when the desired current path is turned off (on). Technuical Papers, pp. 94-96, Feb. 2005.
[2] B. Razavi, Principles of Data Conversion System Design. IEEE Press,
The discharging (charging) time is reduced leading to a higher 1995.
speed in D/A conversion. Compared with the conventional [3] A. V. D. Bosch, et al., "SFDR-Bandwidth Limitations for High Speed
cascoded-switch current source (CSCS) topology, the switching High Resolution Current Steering CMOS D/A Converters," in Proc. of
transition, asymmetry rising-falling settling and synchronization ICECS, VOL. 3, pp. 1193-1196, Sept. 1999.
problems are minimized with negligible power (< 0.15 mW) and [4] H. Takakura, et al., "A 10 bit 80MHz Glitchless CMOS D/A Converter,"
in Proc. of CICC, pp. 26.5.1-26.5.4, May 1991.
Table 1 Summary of the DAC performance. [5] K. -H. Ao leong, et al., "A Frequency Up-Conversion and Two-Step
Channel Selection Embedded CMOS D/A Interface," in Proc. ofISCAS,
Specification Unit Value pp. 392-395, May 2005.
Technology 0.1 8-,tm CMOS [6] N. Ghittori, et al., "A Low-Power, Low-Voltage (1 1mW/8.4mW, 1.2V)
Number ofbits 10 DAC+Filter for Multistandard (WLAN/UMTS) Transmitters," in Proc.
Sample rate MS/s 120 of VLSI Circuits, pp. 334-337, Jun. 2005.
Supply voltage (Analog & Digital) V 1 [7] J. Deveugele, et al., "A 10b 250MS/s Binary-Weighted Current-Steering
Differential output signal V 0.5 DAC," in IEEE ISSCC, Digest of Technical Papers, pp. 362-532, Feb.
Load (RL) Q 200 2004.
JINLI [Mean, Sta Div] LSB [0.134, 0.049] [8] M. J. M. Pelgrom, et al., "Matching properties of MOS transistor", IEEE
IDNLI [Mean, StaDiv] T LSB [0.178,0.081] JSSC, VOL. 24, NO. 5, pp. 1433-1439, Oct. 1989.
SFDR @ Desired signal band j dB > 63 [9] A. V. D. Bosch, et al., "A 10-bit 1-GSample/s Nyquist Current-Steering
Glitch energy pV-s 0.4 CMOS D/A Converter," IEEE JSSC, VOL. 36, NO.3, pp. 315-324, Mar.
Power consumption mW l_ 2.51 l 2001.
t: Power Breakdown: 1.3 mW (Analog), 1.2 mW (Digital).

186 APCCAS 2006

 A DIGITAL CALIBRATION FOR A 16-BIT, 400-MHZ CURRENT-STEERING DAC
Jussi Pirkkalaniemi, Marko Kosunen, Mikko Waltari1 , Kari Halonen
Helsinki University of Technology, Electronic Circuit Design Laboratory
P.O. Box 3000, FIN-02015
email: jussi.pirkkalaniemi@hut.fi
ABSTRACT
A digital calibration for current-steering D/A converters is
presented. The calibration corrects errors originating from
mismatched thermometer decoded MSB current sources. The
calibration principle is to measure the mismatches and skip
over transfer function discontinuations. Four redundant MSB
sources compensate for reduced input range caused by the
skipping action. The mismatches are measured by using a
simple comparator. Manners for extending the calibration
range, thus enhancing linearity, are straightforward. Simu-
lations show that the errors caused by the MSB sources are
cancelled resulting in clear improvement in static linearity.
1. INTRODUCTION
Development of wired and wireless telecommunications sys-
tems has created a need for high-speed, high-resolution
DACs. Used in typical applications, such as digital-IF radio
transmitters, a DAC has to provide large dynamic range to
a low impedance load, the most important performance cri-
terion being spectral purity. Because of these demands the
current-steering architecture is often considered the most
suitable structure.
Even though spectral purity is the key performance para-
meter, the static linearity must be taken into account as well
since it contributes to dynamic performance. The most im-
portant static linearity errors (INL, DNL) in current-steering
DACs exist due to mismatched current sources. Mismatches
originate basically from process and temperature variations
on the silicon die. Current source mismatch can be com-
pensated to some extent by means of special layout tech-
niques [1], but over 12-bit intrinsic static linearity is elusive
without considerable silicon area cost. Thus some calibra-
tion or trimming is obligatory if the resolution is very high.
Traditionally current sources are calibrated either by laser-
trimming [2] or adjusting bias voltages of individual tran-
sistors [3]. However, the feasibility of these methods is lim-
This work was supported by the Finnish National Technology Agency
(TEKES) and Nokia Networks.
1 Currently with Conexant Systems Inc., San Diego, CA, USA.
;‹,((( ,
ited because laser trimming requires special process tech-
niques and cause harmful thermomechanical stress. Ana-
log biasing schemes becomes impractical as supply voltages
scale down and they may suffer from long term stability
problems without regular recalibration.
Another way of performing calibration is to measure
current source mismatches and store them digitally into mem-
ory registers. After calibration period one or several calibra-
tion DACs can be used for mismatch correction [4, 5]. Stor-
ing mismatch information digitally is advantageous since
recalibration is needed relatively seldom. However, addi-
tional calibration DACs must match with the main DAC.
The digital calibration presented here take advantage of
digital mismatch information storage. The method does not
require usage of additional calibration DAC or accurate A/D
converter since mismatch is measured with a simple com-
parator. Calibration is also suitable for high clock rates and
low supply voltages.
2. DAC ARCHITECTURE
The architecture of the core DAC is shown in Fig. 1. Cur-
rent sources are constructed of unit current sources, which
are separated into two arrays. In the MSB array there are 67
equal current sources, which are switched by 7 thermometer
decoded MSBs. Four additional MSB sources provide re-
dundancy exploited by the calibration. 10 LSB current
sources are binary weighted. Additionally there are three
calibration sources providing currents corresponding to 1/2
LSB, 1/4 LSB and 1/8 LSB that are placed into the LSB
array.
The current-source arrays need different bias currents,
which are generated in the current scaler. For testing pur-
poses the bias current ratio can be adjusted by 11 external
control bits, which is used for controlling the systematic
mismatch between the current source arrays. Output cur-
rents drive external 50-Ω load resistors directly.
Clock signals are created in the clock generator, which
basically consists of a clock buffer and an adder type clock
divider. Differential external clock signal is converted to
single ended in the clock buffer. The divider is needed be-
,6&$6
 O u t + O u t -
O u t p u t C u r r e n t U n c a l i b r a t e d C a l i b r a t e d

M i s m a t c h b e t w e e n

a M S B s o u r c e a n d
6 7
T h e r m o m e t e r 6 7 C u r r e n t t h e L S B a r r a y
1 3 C u r r e n t s w i t c h e s
d e c o d e r s w i t c h e s

C o m p a r a t o r
6 7
3 O f f s e t
1 0
1 3 c a l i b r a t i o n
M S B s o u r c e s L S B s o u r c e s
s o u r c e s

2 0

1 6
D i g i t a l I n p u t
C u r r e n t
i n p u t C o n t r o l
s c a l e r

I n p u t C o d e
1 1

S c a l e
C a l i b r a t i o n
I B I A S
c o n t r o l
u n i t
Fig. 2. Calibration principle.
C l o c k
C l o c k +
g e n e r a t o r

C l o c k -
means that the more accurate the MSB array is, the less
c
C

o
l o

n t r
c k

o l
1 2

redundancy is required. Contrary to the MSB array, cur-

rent sources in the LSB array must achieve adequate match-
Fig. 1. DAC block diagram. ing intrinsically. However, even highly linear LSB array is
small comparing to the MSB array.
Calibration is carried out by measuring mismatch off-
cause calibration unit clock frequency must be lower than sets depicted in Fig. 2. Once an offset is calculated it is
the 400-MHz full speed clock. 12-bit clock control enables summed with the preceding offsets giving a cumulative off-
trimming of the division ratio. set. Cumulative offsets are stored into memory registers. In
normal operation there are four possible cumulative offset
3. CALIBRATION values for an input code, since the cumulative offset can be
as large as 4 times the MSB code value (210 ). If the in-
Usually the worst static linearity errors in current-steering put code gives a location in a forbidden section, the corres-
DACs originate from mismatched current source arrays. The ponding cumulative offset is added to the code performing
bias current ratio adjustment can remove any systematic mis- skipping over discontinuation.
match, but it is ineffective against random DNL errors. The
objective of the calibration is to correct the residual random 3.2. Calibration process
mismatch caused by the MSB array.
At start-up situation the calibration unit in Fig. 1 is given
control over DAC current switches via input control. The
3.1. Calibration method
core of the calibration unit is a state machine, which ex-
The output current of each 67 MSB sources are trimmed ecutes consecutive calibration steps. Comparator, described
with the bias current adjustment to be systematically less later on, is controlled by the calibration unit also. It is cap-
than the maximum output current of the LSB array. It is able of sampling and thus able to compare two different
necessary for the calibration algorithm to work correctly. DAC output voltages. By using three calibration sources
The resulting output transfer function has negative steps at the offsets can be measured with accuracy of 1/8 LSB.
every point a new MSB current source is connected to the The procedure for measuring the offsets is depicted in
output. This is illustrated in Fig. 2, which contain part of Fig. 3. CAL-value refers to the output current of a MSB
uncalibrated and calibrated DAC transfer function. source, which is under calibration. The CAL-value is com-
The concept of the calibration has similarities with the pared to a REF-value (reference), which is swept down in
method published in [4]. The fundamental difference in four LSBs steps as shown by arrows in Fig. 3. Down-sweep
this approach is that the discontinuations are skipped over continues until the comparator toggles. Then sweep direc-
instead of using a calibration DAC. Skipping is analogous tion is changed and the step size is reduced to 1/8 LSB.
to consider the mismatch related pieces of the uncalibrated The offset is calculated at the point the comparator toggles
transfer function as forbidden and disuse them. The draw- again. The calibration proceeds with the rest of the MSB
back is reduced full input range, which should be extended sources until all the 67 offsets are measured.
accordingly. The four additional MSB sources are used for By using a sampling comparator the offsets can be found
that purpose. Full 16-bit input range is achieved if the sum without a high-resolution A/D converter that are slow in
of all the mismatches is less than the redundancy which general. However, for mitigating the effect of noise an av-

,
 O u t p u t C u r r e n t Res1 Res2 Res3 Sample Res4

In+ Comp Out-

Vref
F i r s t R E F -
In- Comp Out+
v a l u e

Res1 Res2 Res3 Sample Res4

Res1
Res2
4 L S B Res3
Sample
Res4
Comp
C A L - v a l u e

M e a s u r e d
CAL-value REF-value
at input at input
o f f s e t

Fig. 4. Comparator structure.

I n p u t C o d e

the measurement to the cumulative offsets. However, that

C A L - v a l u e
should be tolerable if only a few largest LSB current sources
are to be calibrated.

3.4. Comparator
1 / 8 L S B

The comparator and its control waveforms are sketched in

Fig. 4. The structure is an offset insensitive switched-capacitor
circuit consisting of several operational amplifiers, switches
Fig. 3. Offset measurement procedure. and capacitors. High resolution is achieved by cascading
four amplifiers.
Comparison begins in reset mode. CAL-value is sampled
erage over sufficient number of comparisons must be taken by opening the reset switches of the first three stages. Once
at each REF-value resulting in increased calibration time. the CAL-value is sampled, the DAC is switched to a REF-
For experimental reasons the number of comparisons can value and a differential voltage is stored by opening sampling
be chosen arbitrarily between one and two million. switches. Then the fourth reset switches are opened. Com-
parison is accomplished by connecting the last coupling ca-
3.3. Accuracy considerations pacitors to a reference voltage Vref. The Vref voltage level
is half of the supply voltage.
The LSB array dominates the post-calibration non-linearity. The comparator is fully insensitive to the amplifier off-
Hence, special attention must be paid to dimensioning of set but some error originate from switch charge injections.
the LSB current sources. Sufficient intrinsic linearity is Most of the charge injections are canceled as they are stored
achieved by distributing all of the unit current sources in a with the amplifier offsets to the capacitors of the next stages.
common-centroid layout. The matching of the LSB sources However, some residual error is caused by mismatched charge
can be further improved by following methods. injections of the fourth stage reset switches. The final error
The transistor area of the LSB sources can be increased is the error voltage at the input of the fourth amplifier di-
because the overall silicon area is relatively small, as a result vided by the gains of the three preceding stages [6].
of reduced area consumption of the MSB sources. That is If the fourth stage charge injections are mismatched, the
due to the fact that poorer matching, thanks to the proposed comparator still have some offset due to finite gains of the
calibration, can be allowed for the MSB current sources. first three stages. This limits the accuracy since it accumu-
The matching accuracy of the LSB current sources can lates with every cumulative offset thus giving rise to non-
also be enhanced by extending the same calibration method linearity.
for few largest LSB currents. However, the LSB sources to Because of the possibility of charge injection mismatch
be calibrated are required to have also the systematic offset despite of careful layout design, the calibration period starts
for ensuring the functionality of the calibration algorithm. with a measurement of the comparator offset. The man-
In addition, the required amount of memory is doubled per ner of the measurement is shown in Fig. 5. First a con-
each bit added to the calibration range. stant reference point on the DAC transfer function is chosen.
The memory requirement can be alleviated by measur- The corresponding output value, added with 1/8 LSB, is
ing the offsets of the LSB sources at one code value only. sampled to the comparator. After that the DAC is switched
That results in accumulation of the quantization error of to the first comparison point, which must be larger than

,
 O u t p u t C u r r e n t
INL uncalibrated INL calibrated
0.8
5
4 0.6
3 0.4

INL [LSB]

INL [LSB]
2
0.2
1
R e f e r e n c e 1 / 8 L S B
0 0
v a l u e Ŧ1
Ŧ0.2
Ŧ2
Ŧ3 Ŧ0.4
C o m p a r a t o r
Ŧ4 Ŧ0.6
t o g g l e v a l u e
Ŧ5
Ŧ0.8
16k 32k 48k 16k 32k 48k
Input code Input code
I n p u t C o d e
C o m p a r a t o r DNL uncalibrated DNL calibrated
o f f s e t
1.5
0.5
1
Fig. 5. Comparator offset calibration.

DNL [LSB]

DNL [LSB]
0.25
0.5

0 0

Ŧ0.5
Ŧ0.25
the reference point. Both the reference point and the first Ŧ1
Ŧ0.5
comparison point are selected externally via a control vec- Ŧ1.5
16k 32k 48k 16k 32k 48k
tor. The comparison result should indicate that the refer- Input code Input code
ence point is lower so the procedure continues by sweeping
the comparison point down in 1/4 LSB steps until the com- Fig. 6. Simulated DNL and INL min/max envelopes with
parator toggles. The comparator offset is calculated at this 13-bit LSB array linearity.
toggle point. Correct toggle point is guaranteed because the
1/8 LSB calibration source is connected with the reference
value only. The measured comparator offset is subtracted clear improvement in static linearity and that the residual
from each cumulative offset resulting in adequate cancella- non-linearity originates from the LSB array. The possibilit-
tion. ies of linearizing the LSB array by extending the calibration
range are discussed. By using the presented calibration, a
DAC with 12-bit intrinsic static linearity, can be improved
4. SIMULATIONS so that 16-bit linearity is achieved.
The effect of the calibration on static linearity was simulated
with MATLAB. 1000 DACs were generated with two dif- 6. REFERENCES
ferent LSB array matching profiles. Matching of the MSB
current sources corresponded to the requirements of a 12-bit [1] G. A. M. Van der Plas, et al., “A 14-bit Intrinsic Accur-
DAC. acy Q2 Random Walk CMOS DAC”, IEEE Journal of
If the matching of the LSB current sources corresponded Solid-State Circuits, pp. 1708-1718, Dec. 1999.
to the linearity requirements of a 13-bit DAC, the calibration [2] D. Mercer, “A 16-b D/A Converter with Increased
improved the DNL yield from 0% to 99.7% and the INL Spurious Free Dynamic Range”, IEEE Journal of Solid-
yield from 0% to 89.2%. If 14-bit matching was defined State Circuits, pp. 1180-1185, Oct. 1994.
for the LSB sources, the improvement of the DNL and INL
yields were from 0% to 100% and from 0% to 97.8%, re- [3] D. W. Groeneveld, H. J. Schouwenaars, H. A. H. Ter-
spectively. meer, and C. A. A. Bastiaansen, “A Self-Calibration
Envelope curves for the minimum and maximum DNL Technique for Monolithic High-Resolution D/A Con-
and INL values of the 13-bit LSB matching are presented in verters”, IEEE Journal of Solid-State Circuits, pp.
Fig. 6. Worst case DNL is calibrated from 1.5 LSB down to 1517-1522, Dec. 1989.
0.7 LSB. INL is improved from 5.5 LSB to 0.75 LSB. [4] Y. Manoli, “A Self-Calibration Method for Fast High-
Resolution A/D and D/A Converters”, IEEE Journal of
5. CONCLUSIONS Solid-State Circuits, pp. 603-608, Jun. 1989.

A digital start-up calibration for current-steering DACs has [5] Y. Cong, R. L. Geiger, “A 1.5V 14b 100MS/s Self-
been proposed. The calibration method does not require Calibrated DAC”, Solid-State Circuits Conference, Di-
additional calibration DAC or A/D converter, but uses a gest of Technical Papers, pp. 128-129, Feb. 2003.
simple comparator for mismatch measurement. The idea [6] E. A. Vittoz, “ The Design of High-Performance Ana-
of skipping over transfer function discontinuations and the log Circuits on Digital CMOS Chips”, IEEE Journal of
use of four redundant MSB sources to achieve full 16-bit Solid-State Circuits, pp. 657-665, Jun. 1985.
input range has been demonstrated. The simulations show

,
 A STATISTICAL METHODOLOGY FOR THE DESIGN OF HIGH-PERFORMANCE
CURRENT STEERING DAC’S

Paolo Crippa, Massimo Coizti, Claudio Turclaetti

Dipartimento di Elettronica e Automatica, University of Ancona

Via Brecce Bianche, 60131 Ancona, ITALY
E-mail: pcrippa@eealab.unian.it

ABSTRACT
Random device variations are a key factor limiting the perfor-
mances of high-resolution CMOS current steering D/A convert-
ers. In this paper a novel design methodology based on statistical
modeling of MOS drain current has been developed. This tech-
nique requires firstly an estimation of mean value and autocorre-
lation function of a single stochastic process, which all the pro-
cessldevice variations are lumped in. Then a behavioral model of
D/A converters has been developed. Finally the statistical simu-
lation of static performances (DNL and INL) has been carried out
for different DAC architectures.
1. INTRODUCTION
Designing high-performance DAC’s requires a deep understanding
of the relationship between performance and source of technolog-
ical errors, especially for high-resolution DAC’s to reach a higher
effective number of bits. Earlier works have presented several ap-
proaches facing this problem [l, 21.
Recently new architectures using segmentation have been sug-
gested which benefits the advantages of both the binary- and the
thermometer-coded architecture [3]. However one of the main
lacks in designing high-performance DAC’s is the statistical mod-
eling of the error sources, which results not adequate to predict
statistical effects on performance. In particular assuming uncor-
related error sources, as done in previous works, not only gives
unreliable results but also results scarcely useful in reduction mis-
match effect through a suitable layout design. Instead a reduction
Y)
Figure 1: Error source modeling parameter mismatch.
On the basis of such considerations the following simple
model of the random term will be assumed
11 = I& (IT.,L ) y (x,y) (1)
where the term I: accounts for the device operating region (being
/3 a fitting parameter), g (111 L ) takes into account the dependence
on dimensions and y(z:y ) summarizes all the sources of error de-
pending on the device position in the die. Therefore y(z,y) can be
considered as a spatial stocliastic process. while 11 is a stochastic
process, assumed to be with zero mean, not only dependent on the
coordinates ( 2 ;y) but also on bias and device sizes.
Referring to a circuit with N devices placed at different posi-
tions in the die, Ai sources of error act in the circuit. The statistical
properties of such a system can be summarized by means of the
autocorrelation function R,,,,resulting in
R,,, ( . % . I . ?/r,
~ ) E ( 7 1 ( r ( Y!
j ~ ,j = . 171 (r.1 Y I ) } i

of performance sensitivity to mismatch error can be obtained by = ~ { ( , ~ ~ ( ~ : ‘ , ~ ~ ) - I r ~ ) ( ? ~ ~ ((3.) ~ . , ~ ? / , ~ ) - ~ r ~

exploiting the statistical behavior of error sources and in particular
their dependence on position in the die, so as to choose a suitable
layout minimizing the mismatch effect.
2. MISMATCH MODELING
We assume that mismatch effect could be modeled as an error
source 17 coupled in parallel with the nominal current I D .as shown
in Fig. I, so that the total drain current i o is given by
= c,,,, ( : l : , , ? / > ; : r , , . y j ) .
Eq. (3)means that the covariance function C,,, ,” of i n is the same
as the autocorrelation function of ’1. As the non-random temis can
be taken out from the expected value we have
C,,,,= A . R?;. A = C , , , , (4)
where C , ,’ is the covariance matrix of drain currents whose
generic i,j-element is

io = I D + 71. (1)
The non-random term I D represents the usual dc drain current, and
while the term 71 gives raise to some random fluctuations (around
I D )depending on the device position in the wafer, the region of
operation of the device and its dimensions T I ‘ and L .
This work was pnrtially supported by CNR - Prog. Final. MADESS I1 Eq. (4) is of central importance since it relates the covariance of

V-311
0-7803-6685-9/01/$10.000200l IEEE
 Shared
Gate 6 2

Figure 2: Schematic and layout of transistors' array with selection

circuitry. Figure 3: Covariance matrix C , , , , obtained from a set of
arrays build with devices having an aspect ratio of II-/L =
2/10 ,um/pm and biased with 12;s 1 = 0.6 1 and 1b s = 3.0 1-.
~

the current to the covariance of the error source, making possible

to derive a model for C,,,,once a mathematical model for R,, has
been assumed. An usual choice for R?-,is the Gaussian function,
namely for a stationary process

where ( I , , IC.,.. and IC,, are fitting parameters and T , ~= :r, - x;,,,
T,,= U , - {I, are distances between a pair of devices along :r:- and
y-axis respectively. As a consequence C,,,,predicts a dependence
on ( . I . : y). other thin on voltages and dimensions.

3. MODEL ESTIMATION FROM EXPERIMENTAL DATA

To estimate C,,,,a test pattern with different sized transistors ar-

ranged in A..I m a y s with A', rows and N , columns of identical
transistors has been designed. By assuming io (3:: g). or that is the
same ? ( x .y). is a wide-sense stationary process, thus the mean Figure 4: The autocorrelation function R,, obtained by fitting
value of the drain current w , ~(n:,;y)
, = I D = c o r i ~ tcan
. be esti- measured data reported in Fig. 3.
mated from measurements through the following relationship

the above methodology to a set of device arrays with aspect ra-

where ~ is the drain current of the device placed at //-position
of t -th 'array. Additionally. from measurement we can estimate the
covariance matrix of drain currents whose generic /j-th element is
given by:
tio of 11-/L = 2/10 p i i / p i n and biased with 1 ;;SI = 0.6 1
and ID.? = 3.0 I - . The current variance cr;D corresponding to
C ' l D ; D ( O . 0) is also reported in Fig. 3. A Gaussian function as
in (7) has been assumed for R,, where c y 1 , IC.r, and Ayl/are esti-
mated from measurements. The procedure for fitting the autocor-
relation function model to measured data has been implemented
in MATLAB by exploiting algorithms based on least square min-
imization of errors. For data reported in Fig. 3 the following pa-
rameter values have been obtained: 0-, = 1.2 ' 10-". K,z =
0.0187 p - ' and K!, = 0.1689 p n - ' while the resulting auto-
correlation function R,, ( T , ~T ~is)reported in Fig. 4.
~

In order to have a suitable amount of data for estimation, nine as-

pect ratios have been chosen for both PMOS and NMOS transis-
tors: II-/L = 2/10. 5/1.4. 2/1, l/O.i', 0.i/O.5, 0.5/0.35. 1/1.
O . T / l . 0.3/1 / / i i i / p ~ i i .Thus 18 arrays (one for each geometry)
of 8 x 8 cascode transistor pairs have been designed in a single
die. Finally 39 replicas of the die have been implemented on an
8-inches wafer manufactured with 0.35 p m CMOS technology.
Figure 2. shows the schematic of a single m a y with row and
column decoders added for selecting one transistor at a time. Fig-
ure 3 shows the covariance matrix C , , , , obtained by applying
4. STATISTICAL SIMULATION OF DAC'S
PERFORMANCES
Statistical simulation at system level is essential as a first stage
in statistical design of high-performance DAC's in order to com-
pare different architectures. It requires, as schematically shown in
Fig. 5. the following steps:
i ) Establish the vector of performances c p , that is the perfor-.

V-3 12
 - -
lo
DAC
ARCHITECTURE
OUT
PERFORMANCE
B
+
Figure 5 : Simulation at system level.
I .vdd
Figure 6: (a) Binary weighted DAC, (b) Thermometer coded DAC.
mances which characterize the behavior of the system, i.e. Differ-
ential Non-Linearity (DNL), Integral Non-Linearity (INL), ...
ii) Define for a given architecture a relationship relating the
DAC output OUT to the vector of all current sources io and a
mathematical model relating the performances cp to the output.
At the end of this process, assuming a linear relationship be-
tween L+Y and io (achieved through linearization in case of non-
linearity), it is straightforward to derive the covariance of the per-
formances as a function of the covariance of the currents, resulting
in
c;, = s ' c,,,, sT
' (10)
where S is a matrix depending on the DAC architecture.
4.1. Non-dynamical performances
To derive an input-output relationship relating DAC output to the
vector error sources q ,we define OUT as the vector whose com-
ponents are the 2" output levels and which will be assumed as the
output of the DAC. Referring to the architecture shown in Fig. 6(a)
for a binary weighted DAC, that in Fig. 6(b) for a thermometer
coded DAC and to a mixed mode DAC which uses both the ar-
chitectures, a relationship relating the output OUT to the current
vector i~ can be derived. Since all the architectures considered
are linear networks, the dependence of output on source currents
will be linear as well. Therefore, it results
OUT = T iD
being T a matrix dependent on the specific architecture whose ex-
plicit relationships have been derived for the three architectures
mentioned before.
In order to obtain non-dynamical performances DNL and INL,
it is useful to derive the vector _10[TT whose components are
the random variables associated with the ideal output levels. By
combining eqs. ( 1 ) and ( 1 1 ) it results
1 0 1'T = T ' q
08-
06.
03
02.
Figure 7: Normalized covariance matrix C , , of error sources.
It can be shown that DNL and INL are related to the vector 77
through the following matrix equations
where
being Dnl and In1 matrices independent of the architecture.
Eqs. (13) and (14) establish a linear dependence between the
performances DNL, INL and the random sources 77. Thus it is
straightforward to derive the covariance matrices of DNL and INL
C D V DLN L = J D N L . C,,, . J T n n r ~ , (17)
C I .L ~I h ' L = J l h L . c,,,. JTA~L. (18)
These equations, whose form is the same as eq. (IO), are the re-
quired relationships for statistical simulation of DAC architectures.
5. APPLICATION EXAMPLES
On the basis of the behavioral DAC models previously derived the
statistical simulation of the performance can be carried out.
Before proceeding with such a task it is worth to note that in
general every current source Z D in a DAC is implemented with a
set of sub-sources I'D (of LSB value or less) whose total current ex-
actly fits the 7,9 value. In such a way the large number of freedom
degrees can be used to reduce statistical technological variations.
Thus as the covariance matrix C,,,,refers to the errors q of the cur-
rents i n , a new matrix C , , J ,taking
~ , into account the errors q' of
sub-currents );2 has to be defined. Because every current Z D is a
sum of one or more &,, the vector q is achieved from q' through
a linear transformation L, that is
(11) q = L 77' (19)
so that it results
G1',
= L C,f,,f LT
' '
In the simulation examples we assume all the error sources y are
correlated with the autocorrelation function given by eq. (7). The
random samples have been generated by a suitable software pro-
gram according to the distribution chosen. The covariance matrix
behavior derived in such way for a weal; correlation between error
(12) sources is reported in Fig. 7.
V-3 13
 To describe the current sources arrangement we use a matrix
notation in which the term Bx (Tx) represents a sub-source related
to the x-th binary (thermometric) source. With such a notation, re-
femng to a 6-bit purely binary DAC, the current sources arrange-
ment shown in the box of Fig. 8 has been chosen. In this case
the results achieved are not satisfactory as clearly appears from
Figs. &(a)and 8(b) reporting the diagonal terms of the covariance
matrices C D N L D , V L and C I , V L
I , W L respectively (normalized to
the variance of LSB), that is the variance of the performances as
function of the input code. As you can see both DNL and INL have 35
a maximum variance corresponding to the half-code transition. 30
Better results have been obtained with a layout solution sug- 25
gested in [I], which takes into consideration mismatch effect. The 0
,
20
arrangement chosen shown in the box of Fig. 9 is such that all
15
the six binary sources have been split into arrays of not contigu-
10
ous unitary sources. As you can see in Fig. 9(a) the maximum in
the variance at half-code disappears, as well as the values of the 5
(b)
variance at the other transitions decrease. Moreover the maximum 0
10 20 30 40 50 60
values result even less than the ones in the case of uncorrelated er- Input Code
ror sources, meaning that correlation between random sources can
be suitably exploited. Also INL improves with such a layout as it Figure 8: Diagonal terms of the covariance matrices
clearly appears from Fig. 9(b). (a) C O\ L D\ L and (b) C , \ L 1 L for a 6-bit DAC (current
Let us now consider a thermometer DAC. In this case the vari- sources are ‘arranged as shown in the box).
ance of DNL ( ~ 6is simply oiSB
. ~ ~ for every transition. With re-
_ _ _ . _ ~
gard to INL it is worth noting that in order to reduce its variance a
B 1 8 6 85 86 8 3 86 B5 86
suitable sequence of current source selection, named “hierarchical 86 8 3 8 6 05 8 6 0 4 8 6 8 5
symmetrical switching” [ 2 ] , has been adopted. The thermometer 16 85 86 81 86 B5 86 82 86

current sources have been arranged as shown in the box of Fig. 10

making possible to obtain the results shown in Fig. IO. 2 10
BS 65 BS 81 8 6 85 BS 81
81 86 8 5 8 6 8 4 86 8 5 W
86 64 86 B5 86 8 3 86 85 I
6. CONCLUSIONS

A statistical method to design high-performance CMOS current-

steering DAC’s has been presented. The methodology allows the
designers to explore DAC architectures and study the technology-
dependent effects of circuit layout on the system performances
without using CPU-time expensive Monte Carlo simulations. This
technique takes into account the mismatches of current sources de-
vices by using a simple statistical MOS model based on stochas-
tic processes theory. For the model characterization a test pat-
tern with different sized arrays of identical transistors has been
designed. Behavior level DAC model for two main static perfor-
mances, namely DNL and INL, has been derived and used in the Input Code
simulation tool. As application examples, simulations of three dif-
ferent DAC topologies have been performed. Figure 9: Diagonal terms of the covariance matrices
(a) CO\ L D \ L and (b) C , \ L \ L for a 6-bit DAC (current
7. REFERENCES sources are arranged as shown in the box).

[I] C. A. A. Bastiaansen, D. W. J. Groeneveld, H. J. Schouwe-

naars, and H. A. H. Termer, “A IO-b 40 MHz 0.8-pm CMOS
current-output DIA converter.” IEEE J. Solid-Stare Circuits,
vol. 26, n. 7, pp. 917-921, July 1991.
[ 2 ] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazava, TSP T3T T61 Tn T25 T51 T41 T Y I
“A IO-b 70-MSIs CMOS D/A converter,” IEEE J. Solid-State T I 0 T U 759 T27 l31 163 TIP Tu)

Circuits, vol. 26, n. 4, pp. 637-642, April 1991.

[3] G. A. M. Van der Plas, J. Vandenbussche. W. Sansen, M. S. J. 20 30 40 50
Steyaert, and G. G. E. Gielen “ A 14-bit intrinsic accuracy Q’ h u t Code

random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol.

34.11. 12, pp. 1708-1718, Dec. 1999. Figure 10: Diagonal terms of the covariance matrix C I \ L I \-L for
a 6-bit DAC (current sources are arranged as shown in the box).

V-3 14
 IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE
A Study Of Error Sources In Current Steering Digital-to-Analog Converters
Douglas Mercer
Analog Devices Inc.
Wilmington, MA, USA
(doug.mercer@analog.com)
Abstract
This paper will discuss a number of error sources which
potentially limit the distortion and S N R performance of
modem current steering Digital-to-Analog Converter designs.
Static matching errors as well as timing and non-linear output
impedance errors will be presented along with possible design
solutions.
Introduction
Fine line CMOS technologies have become the process of
choice for high sample rate switched current digital to analog
converter design [1 - 41. Switching speeds of sub-micron gate
length MOS transistors has allowed sample rates of many
hundreds of MHz. Unlike switched capacitor circuits used in
many ADCs which require so called mixed-signal process
variants with high quality poly-poly or metal-metal capacitors,
switched current DACs can make use of the standard CMOS
processes. The designs have marched down the process
generations from 0 . 8 to
~ 0 . 1 8 ~and beyond. There are certain
common features of these designs which have become givens.
Universally, DACs with resolutions from 8 bits to 16 bits are
split into two or more segments. The most significant bit
(MSB) segment is always made from unit weighted elements
and is thermometer coded. The number of bits in the MSB
segment can vary from as few as four to as many as 7 bits, with
5 and 6 being the slightly more common choice. The rest of
the bits may be binary coded but are often further segmented
into a thermometer coded intermediate significant bit (ISB)
section and a least significant (LSB) binary coded section. A
notable exception to the use of thermometer coding is
proposed by Deveugele in [181. Here competitive performance
is achieved using unit elements but combined and switched in
binary fashion.
It also seems that PMOS currents and switches are used more
often then NMOS currents. Using PMOS devices on a
standard twin well process on P-type wafers provides the
opportunity to isolate the back gates of the devices and bias
them at some potential other than a power supply or ground.
With PMOS there is the convenience of having the output load
referenced to ground as well. Newer triple well processes have
become available in deep sub-micron which provide the ability
to isolate the NMOS devices but poorer l/f noise performance
has limited the appeal of going with NMOS currents.
Power or supply current in a CMOS switch current DAC can
be divided into three categories. The first comes from the
digital logic and clock section and often directly scales with
the sample frequency and the data pattern. CMOS has the
advantage that the design will benefit from advances in process
and supply voltage scaling. The second and third supply
current categories are analog in nature. The full scale output
current can be a big part of the current in the analog supply
and can range from as little as 1 mA or less and up 20 mA. The
rest of the analog supply current is overhead and comes from
the reference and bias circuits for cascodes and output
switches. Sometimes this overhead current can be made to at
least partially scale with the full scale output. Sometimes
0-7803-8495-4/04/$20.0002004 IEEE.
I - ,
designs make use of mixed voltage process options to allow
the analog sections to be powered from higher supply voltages
and provide larger voltage swings on the output.
Static Errors and Calibration
Device matching in CMOS processes has been studied and is
well documented starting with the often cited work by Pelgrom
[SI. By taking advantage of statistical averaging, layout
techniques and random switching order, accuracy of up to 14
bits has been reported by Vandenbussche [6].To achieve even
higher accuracy or to increase yields with less layout area
trimming or calibration techniques are often used as in
Schofield [4] and Groeneveld [7], There are two basic
approaches to implementing self-calibration, foreground and
background. A converter which is foreground calibrated must
be taken off line and not used while being calibrated because
as each current source is measured it is removed from the
output. In background calibration an additional current source
is used to replace each current source as it is calibrated. This
allows the DAC to be in use while being continuously
calibrated. However, the operation of removing and replacing
current sources from the output could cause extra disturbances.
There are also two basic approaches to storing the correction
factors for the individual current sources. One technique as
proposed in [7], is shown in figure 1. Here a correction voltage
is stored on the gate capacitance of a MOS transistor M1. A
dynamic technique such as this needs to be constantly
refreshed and lends itself to background calibration. There is
also a minimum clock rate reauirement and the calibration will
be lost if the clock is turned o k during power saving modes.
CW
Figure 1 Calibration (a) Normal Operation (b)
There are certain systematic sources of error in this technique.
The operating conditions of trim device M1 and the devices in
the main current source Im vary between the calibration and
operation modes. The Vds of the devices is set equal to the Vgs
of M1 while in calibration. However, while in normal
operation, the Vds is set by whatever circuitry is connected to
the terminal OUT. This could be a cascode device or the
output switches of the DAC. Because of the finite output
impedance of these devices the current that results in the
operating mode will be different than that which flowed in the
calibration configuration. Each cell is slightly different and the
amount of adjustment needed, i.e. the gate voltage of M1, will
be different. The change in current between calibration and
9-5-1 185
 operation modes will depend on the level of the adjustment. ploted in fig. 3(b) for a 7-bit segment case. The magnitude of
This will limit the accuracy of the calibrated result. In order to the resulting INL curve, fig. 3(c), is a function of the number
maximize the headroom in designing current sources the
devices are often biased such that the vds is marginally larger
than vdsat of the device. In this configuration the Vds of M1
and Im must be equal to the Vgs of M1 when in calibration.
Static storage of a digital correction value as used in [4] does
not need to be refreshed and would lend itself to foreground
calibration. In this approach, shown in figure 2, the current to
be calibrated is measured against a master reference current
and the difference adjusted as close to zero as possible through
the successive approximation register (SAR) logic and a C A L
DAC which injects a small correction current in parallel with
the main current source.
.......................
a a
a a
a td *
IL Figure 3 (b)Output ( 4 JNL
When the single-ended harmonic distortion analysis done by
Van den Bosch in [8] is extended for differential third order
distortion, a single cascode causes the output impedance to
limit third order intermodulation distortion at low a frequency
as seen for the lower curve in figure 4. This limit can be
increased with a second cascode as in seen in the upper curve.

I ...........

1#
Figure 2 Static digital storage correction. eo
The switches which redirect the current either to the output
node or the calibration hardware act as the cascode devices 60
and thus fix the drain voltage of the main current source device 4cI
to be the same, within the matching of the Vgs of the two
cascode switches, in both cases. This can result in a much 20
more accurate calibration. The additional circuitry used for the
calibration is not clocked during normal operation and does
not use power or inject noise into the main signal path. Figure 4 Single vs double cascode
While it is true that output impedance requirements are greatly
reduced for fully differential output configurations, as pointed
out by Luschas in [9], it is important to design the output
switches and their gate voltages so as to keep the output
switches in saturation. This maximizes the attenuation of the
output swing 'seen at the common source nodes of the
differential switches. The small signal attenuation of the
switches is given by the ratio of the device gp to gds. Typical
values of this ratio are in the range of 20.
T
Figure 3(a) Code dependent output impedance
Finite Output Impedance
*e
Vbias
mJ
I lmsb

An INL. mechanism that results from the use of a thermometer

coded architectures is code dependent output impedance,
figure 3(a). As the number of unit elements is switched to the
output, the resistance RSW of that element's current source cs 2 cs
appears in parallel with the load resistor RI.. As the number of
,-
vcs
elements turned on increases the effective output impedance of
the DAC in total decreases. The varying impedance in parallel
with the load resistor results in a non-linear output voltage ...
across the load. This gain compression effect in each output is Figure 5 Differential current switch

186 9-5-2
 Early work in BiCMOS by Mercer in [16] pointed out that
high-speed operation requires a small and linear source node
capacitance for the switches.. A switch unit element will see an
attenuated output signal on the switch common source node,
and any non-linear back gate capacitance, depicted as C1 in
figure 5 , on this node will produce distortion. Tying the switch
and cascode transistors’back gates to the supply reduces non-
linear capacitances, but for a large array, the total non-linear
capacitance can be significant. The input of a unity-gain level-
shifting amplifier can be connected to the switch common
source node and used to drive the back gate of the switches
and cascode [4]. The non-linear back gate capacitances now
see the signal on both plates, thereby bootstrapping the well
capacitances and leaving small linear parasitic capacitances.
The amplifier’s dc level shift should set high to minimize the
switch’s non-linear capacitance.
Switch Gate Drive
It is very necessary to optimize the waveform, i.e. the crossing
point of the gate drive signals of the current source switch pair
as shown in figure 5 . The circuit that drives the differential
switches Ml,M2 needs to ensure that the current is always
flowing at a constant value. If the voltage at node Cs is
allowed to move then some of the current will flow in the
parasitic capacitance, C 1, shown in the figure. The best way to
insure that the current flow is constant is to have the gate
signals cross at a point below the nominal DC voltage of the
. common node Cs equal to the Vgs of one of the switch devices
( M1,M2 ) when 1/2 of the current is flowing through the
switch. This minimizes the excursion of the voltage at Cs
during a transition and hopefully the disturbance is symmetric
around the nominal DC value as indicated by the center
waveforms in the figure. An important point is that it is not
necessary to bring the gates of the switch devices any higher
than the voltage on the Cs node when turning off the device
(Vgs = 0). This reduces any feed through of the gate drive
signals to the outputs or the common source node Cs.
(c)
Figure 6 Common Source Waveforms
Another source of dynamic error relates back to the fact that a
small attenuated amount of the output signal leaks through the
gds of the differential switch onto node Cs. The amplitude of
the signal seen at node Cs is typically about 1/20 that seen at
outputs IA and IB or 50 mV for a 1V swing at the output. Each
9-5-3
switch element turns on at a different point in the transfer
function and as a result will have a different wave shape on
node Cs. In figure 6(a) the complementary outputs IA and IB
are shown. Referring to figure 5 , node Cs will have the
attenuated version of IA when M1 is on and the attenuated
version of IB when MI is off ( M 2 on ). In figure 6@) we see
what the signal on Cs will look like when a switch element is
near the lower end of the transfer function. Similarly,for figure
6(c) we see the signal on Cs when a switch element is near the
top of the transfer function.
In figure 5 , note that the point at which M1 and M2 switch is
determined by the crossing point of gate drive signals G1, G2
with respect to the value of node Cs. If the relative value of Cs
is modulated by the output swing and where in the transfer
function the switch element is, the actual time point when the
switches change will also be a function of the output swing and
their position in the transfer function. This will result in a
signal dependent jitter seen in the output. As indicated in
figure 6@) M1 switches from on to off when Cs is at its low
point and M1 switches from off to on when Cs is near the high
point. For the case shown in figure 6(c) just the opposite
happens. The amount of jitter depends on the magnitude of the
signal on Cs and the rise/fall time of the gate drive signals.
time, nSeconds
Figure 7 Switching delay vs output swing
An example case is shown in figure 7, where the normalized
zero crossing point of the differential output voltage at IA,IB
is shown for three cases. The horizontal axis is 5 pSec per
division and the vertical axis spans about 1 mV. The three
curves are for cases where the difference between IA and IB
when the switch flips is -333 mV, 0 V and +333 mV. For these
three cases the node Cs has shifted its nominal value by a total
of 32 mV or approximately 1/20 of the output. We see a shift
in time of 4 pSec, which results fiom a differentialslew rate on
the gate drive signals Gl,G2 of 125 pSecN. This could be a
significant source of error when generating high frequency
outputs.
Similarities between DAC and Flash ADC
The thermometer coded segments of a switched current DAC
are very much analogous to the full parallel flash ADC. The
complexity and hardware of both doubles for each bit of
resolution. In the ADC, the distribution of the analog input
signal to the comparators with matched delays is much the
187
 same as the collection and combining of the individual unit
current outputs of the DAC. Also, as in the Flash ADC where
the delays in the clock distribution to the individual
comparators must be tightly matched, the clock distribution
network driving the final stage of re-timing latches in the DAC
is equally important.
Delay = A
jClOCk
Input
Figure 8 Distribution by Propagation Matching
One possible approach to this is propagation delay matching
[4]illustrated in figure 8. Here if we assume that each cell has
the same delay A and the delay along the clock distribution
line from cell 1 to cell n is 61 and the delay along the output
line is 62 then the sample timing is preserved if61 = S2.
$1
Clock DAC
-
Input
-
Output
-
Delay A whether the content ( state ) of the latch is changing or not.
Figure 9 Distribution by Constant Wavefront Matching
Binary tree distribution structures are often used to match
these delays as well as done by Schafferer in [15]. This results
in a constant wavefront as illustrated in figure 9. The clock
distribution tree is arranged to have equal lengths ffom the
driver to each cell. Likewise the output collection tree is
arranged with equal length ffom each cell to the output pad(s).
The clock tree delay does not need to match the output tree
delay.
The physical placement of the unit cells in the layout is an
important consideration and geometric shuffling of the
placement is often used to breakup any linear gradients in the
cell delay A ( figure 8,9 ) that might be present.
188
Digital data pattern dependent noise
Gonzales in [lo] observed that noise generated by the data
passing through the digital logic portions, specifically the
thermometer decode section, of a DAC can cause spurious
tones and distortion in the analog output. Gong [ 1 11 teaches us
that it is possible to concentrate this noise at the clock
frequency Fs or Fs/2. This is accomplished by including a
shadow or mirror data path with a one to one correspondence
to the main data path. This shadow data path is driven by a
data pattern is such a way that for each node in the main data
path that does not change value at a give clock transition the
correspondingnode in the shadow path does. Likewise, when a
node in the main path does change the corresponding shadow
node does not change. This makes the sum total of all nodes
changing at each clock transition constant and independent of
the data pattern.
An example of this technique in an over-sampled switched
current audio DAC is proposed by Rueger in [17]. In this
design a dummy data shift register creates constant local
digital edge activity on the supply, ground and substrate.
NMOS switch devices, driven by full rail swings, are used to
switch the cascoded PMOS current sources. The use of the
dummy data to drive dummy switch devices balances the
switching activity injected into the output stage thus
minimizing the demodulation of out-of-band noise into the
base band.
A similar notion referred to as modified mismatch shaping
(MMS) is proposed by Shui in [12]. The idea is to set the
number of elements or cells switching per clock period to a
constant. This tums the errors caused by non-ideal element
dynamics into a dc offset and energy at Fsl2. Shui assumed an
oversampling converter, where the maximum output
bandwidth is reduced. The choice of what fraction of the total
number elements to set the constant to is problematic and the
optimum is a function of the nature of the signals being
converted, however. In any case, the constant can never be set
to more than 1/2 the number of elements. This limits either the
maximum amplitude or the maximum output frequency to only
1/2 of what it would have been otherwise. Therefore, we
conclude that, for a Nyquist rate converter, to make use of this
constant element switching concept we would need twice as
many elements.
Data Dependent clock loading
A rather important special case of data pattern dependent
timing error comes from the varying load seen by the final
clock driver which drives the last re-timing latch of the DAC.
The basic issue is that all latches to some extent present a load
to the circuit, which drives the clock input, that depends on
Given the finite strength of the driving circuit, the rise time of
the clock waveform will be a function of the number of the
multiplicity of latches connected to this common clock driver
which are changing their state at a given time. This results in a
shift in time of the output samples which is a function of the
rate of change on the waveform and thus gives rise to odd
order distortions mainly third order.
An example of this effect is shown in figure 10. The time when
the rising edge of the clock signal crosses mid supply (1.25 V)
is plotted for the case of a single latch when the input data is
not changing and when the input data is changing. This
simulation shows a 2 pSec difference. This effect is magnified
when a large number of latches are driven by the same
9-5-4
common clock driver and is proportional to the number of differential outputs. Switch M1 is switched off for 1/2 of the
latches which change their state. In the case of thermometer clock period while the DAC current switches (IDAC) change
coded data the number of data bits changing is proportional to and then back on after the currents have settled. Resistor R1
the rate of change of the output waveform. provides a load while M 1 is off. As well, there is switch M2 to
1.8 short the output to ground, through resistor R2, when the other
I I I I I I I switch is off thus the return-to-zero operation. This effectively
reduces the timing skew between the various DAC switches.
There is however a loss of 1/2 of the signal amplitude, 6&,
due to the return-to-zero output.

I I I I I I I
-20 -15 -10 -5 0 5 10 15 20
time, pSeconcla
Figure 10 Data dependent clock delay Figure 12 Return to Zero Concept, output waveform
We can get a workable solution by taking the shadow or mirror
Return to zero switching can reduce the distortion from digital
data paths concept of [ l l ] and combining it with what we
data noise induced timing errors, but for very high sample
concluded from [121 and realize that by doubling the number
rates if the output does not completely settle in each half of the
of latches by simply adding the second as a mirror path for cycle then the history effect or inter-symbol interference is not
each original latch and driving the mirror latch in such a way eliminated and can result in signal dependent distortions. It is
as to cause it to change state only when the main data latch important to note that this scheme is not totally free of signal
does not. One way this mirror data can be generated is shown

,
dependent timing errors. The turn on and turn off points for
in figure 11. By combining the main data signal with a clock
M1 and M 2 will depend on the signal levels seen at the node
signal at Fs/2, or 1/2 the main clock rate, with an exclusive OR
OUT. It is difficult to tell if the reported SFDR results for this
gate the mirror data signal is created such that it changes only
method are really any better than those reported in [4]because
when the main data does not. By doubling the number of
both seem to be limited to about -75 dBc for output
latches we have doubled the load on the clock driver but it is
fkquencies above 25 MHz, which seems the measurement
now independent of the incoming data pattern.
limit of most spectrum analyzers

LFp
I

Quad Switching I Constant Data Activity

DATA Dynamic element matching or distortion spreading techniques
are popular methods of improving spurious free dynamic range
by smearing the distortion into a noise like component in the
output of the DAC. Random spreading produces a more white
noise like result. Other approaches can shape the noise
characteristicto place it out of the band of interest, if there is
some amount of oversampling in the system. While DEM will
increase the amount of data activity it is not constant for each

4
Fclock

"\ %Driver
k:
clock cycle. When constant switching techniques are used the
distortion or noise is concentrated as a tone at the sampling
frequency.

Ordinary differential current switching results in some data-

Figure 11 Data pattern independent clock loading
Return-to-Zero Switching
Another way to re-time the data samples at the output of the
DAC is to use a return-to-zero output stage as proposed by
Bugeja in [13]. In this case a set of additional switches have
been added in the output path between the current switches and
the external output load as shown in figure 12, for one of the
dependent distortions arising from the jump or glitch on the
common source node of the switch pair. This ordinary switch
does not toggle every clock transition, and as a result the
switching event is dependent on the data pattern, introducing
distortion in the band of interest. Another approach to the data
pattern dependent dynamic errors pointed out in [121, is a quad
differential current switch proposed by Park in [14] for an
oversampling DAC and again by Schafferer in [15] for a multi-
bit Nyquist DAC.

189
 By using four switches instead of the normal two, we are in
effect interleaving two return to zero switches. The
configuration of the quad switch is shown in figure 13. There
are four switch devices M1, M2, M3 and M 4 which share a
single common source connection Cs. The unit element current
Im is supplied to node Cs as in the ordinary differential switch.
Only one of the four switches is on at any given time as
indicated by the switching waveforms of figure 14.
,I lmsb
Figure 13 Quad Switch
G J I ISCAS 1999 Digest of Technical Papers, pages 11452-455
U -8OdBc IMD to 300MHz and < -160dBm/Hz noise power specaal
G2
. .
u
G3
t L I converters” IEEE Joumal of Solid-state Cicuits,Volume: 24 , Issue: 6 ,
G4
I
I \ U
I Dec. 1989 Pages:1517 - 1522
‘“B
IA
Figure 14 Quad Switch Waveforms
The gate of each switching transistor is driven by a signal
shown in Fig. 14, three of the four gates will be high and one
low for a given clock cycle. Each clock cycle the gate that is
low will transition high and another gate will transition low. At
the bottom of the figure the outputs IA and IB indicate where
the current Imsb is being directed. The output at IA and IB is
logically the same as with ordinary differential switching.
There will be switching glitches as indicated even if the
current does not change outputs. Switching in this manner
eliminates the nonlinearity due to uneven pulse duration, as in
RZ switching, because every pulse has the same width. There
are at least two and only two signal transitions, one rising and
one falling, per clock transition. Switching noise is now moved
to the sample clock frequency by the constant toggling of both
sides of the switch. It also important to note that the
disturbance seen on the common source node Cs is constant
and independent of the input data pattern.
190
Quad switching like this incorporates some of the good points
of both RZ switching and ordinary differential switching, is
suitable for high sample rates, and reduces transition-
dependent noise. A drawback of quad switching is an increase
in complexity, four gate signals need to be generated and the
increased dynamic power consumption due to the fact that one
pair of the four switches each cycle.
Conclusions
Seven major contributors to errors and distortion in modem
switched current Digital-to-Analog converters have been
discussed. Static device matching can be addressed either
though statistical averaging or calibration. One or more
cascodes can be included, along with insuring that the output
switches remain in saturation, to reduce the effect of output
impedance variation. The importance of gate drive signals was
explored. Much like the flash ADC, clock distribution is a key
factor. Digital data pattern generated noise needs to be
addressed and the effect on clock jitter can be a major source
of distortion. Return-to-zero switching can be employed to re-
time the output sampling time. The use of a quad switch and
constant data activity switching techniques can shift spurious
outputs to the sampling frequency.
References
[l] Mercer D., Singer L.; “12-b 125 MSPS CMOS D/A Designed For Spectral
Performance”; ISLPED 1996 Digest of Technical Papers, Pages 243-246
[2] Lin C-H., Bult K.; “A lob 250MSample/s CMOS DAC in I d ”;
ISSCC 1998 Digest of Technical Papers, Pages 214-215
[3] Tesch B., Pratt P. Bacrania K, Sanchez M.; “A 14-b, 125 MSPS Digital to
Analog Converter and Bandgap Voltage Reference in 0.5um CMOS”;
[4] Schofield, W., Mercer, D., St Onge, L.; “A 16b 400MS/s DAC with <
density”; ISSCC Digest of Technical Papers , 9 Feb. 2003 Pages:126-127
[SI Pelgrom, M.J.M.; D u i i i j e r , A.C.J.; Welbers, A.P.G.; ”Matching
properties of MOS transistors” IEEE JSSC .Volume: 24 , Issue: 5 , Oct.
1989 Pages1433 - 143
[6] Vandenbussche, J. et al.”A 14 b 150 Msample/s update rate 42 random
walk CMOS DAC”, ISSCC 1999 Digest of Technical Papers, 15-17 Feb.
1999 Page(s): 146-14
[7] Groeneveld D.W.J., Schouwenaan H.J., Tenneer H.A.H., Bastiaansen
C.A.A.; “A self-calibration technique for monolithic high-resolution D/A
[8] A.Van den Bosch, et al., “SFDR Bandwidth Limitations for High Speed
High Resolution Current Steering CMOS D/A Converters,” Proc. ICECS,
pp. 1193-1196,1999.
[9] Luscbas S., Lee H.-S.; “Output impedance requirements for DACs”
Proceedings of the 2003 ISCAS, Volume: 1 ,25-28 May 2003 Pages:I-861
- 1-864 vol. 1
[IO] Gonzalez, J. L.; Alarcon, E,; “Clock-jitter Induced Distortion In High
Speed CMOS Switched-current Segmented Digital-to-analog Converters”
ISCAS 2001 Digest of Technical papers, May 2001, Pages 1-512-515
[l I] %g; ” Digital signal processor with reduced pattern dependent noise’’,
United States Patent no. 5,719,572 issued 17 Feb. 1999
[12] Shui T., Schreier, R., Hudson, F.; “Mismatch shaping for a current-mode
multibit delta-sigma DAC” Solid-state Circuits, IEEE Journal of ,Volume:
34, Issue: 3 ,March 1999 Pages:331 - 33
[13] Bugeja, A.R., Song, B.-S., Rakers, P.L.; Gillig, S.F.; “A 144, 100-MSis
CMOS DAC designed for spectral performance” Solid-state Circuits, IEEE
Joumal of ,Volume: 3 4 , Issue: 1 2 , Dec. 1999 Pages:1719 - 1732
[I41 Park, S.; Kim, G.; Park, S.C.; Kim, W.; “A digital-to-analog converter
based on differential-quad switching” Solid-state Circuits, IEEE Journal of
, Volume: 3 7 , Issue: 1 0 , Oct. 2002 Pages:1335 - 1338
[15] Schafferer, B.; Adams, R.; “A 14b 1.4 GS/s 3V CMOS DAC for Multi-
Carrier Applications;”ISSCC Digest of Technical Papers, Feb. 2004
[16] Mercer D.; “A 16b D/A Converter with Increased Spurious Free
Dynamic Range,” IEEE JSCC, vol. 29, no. 10, pp. 1 180-1185, Oct. 1994.
[I71 Rueger, T.;“A llOdB Ternary PWM Current-Mode Audio DAC with
Monolithic 2Vrms Driver”, ISSCC Digest of Technical Papers, Feb. 2004
[18] Deveugele, J.; “A 10-b 250MS/s Binary-Weighted Current-Steering
DAC”, ISSCC Digest of Technical Papers, Feb. 2004
9-5-6
IDDQ TESTING OF A CMOS 10-BIT CHARGE SCALING
DIGITAL - TO - ANALOG CONVERTER

A Thesis

Submitted to the Graduate Faculty of the

Louisiana State University and
Agricultural and Mechanical College
in partial fulfillment of the
requirements for the degree of
Master of Science in Electrical Engineering

in

The Department of Electrical and Computer Engineering

by
Srinivas Rao Aluri
Bachelor of Engineering, Osmania University, Hyderabad, India, 2000
December 2003
Acknowledgements

I would like to dedicate my work to my parents, Mr. and Mrs. A.Sreedhar Rao

and my brother Seshu, for their constant prayers and encouragement throughout my life.

I am very grateful to my advisor Dr. A. Srivastava for his guidance, patience and

understanding throughout this work. His suggestions, discussions and constant

encouragement have helped me to get a deep insight in the field of VLSI design.

I would like to thank Dr. P. K. Ajmera and Dr. Martin Feldman for being a part of

my committee.

I am very thankful to Electrical Engineering Department, for supporting me

financially during my stay at LSU.

I would like to thank my friend Miss. Chandra Srinivasan for her constant love

and support for me through out my life.

I take this opportunity to thank my friends Anand, Uday, Vijay and Harish for

their help and encouragement at times I needed them. I would also like to thank all my

friends here who made my stay at LSU an enjoyable and a memorable one.

Last of all I thank GOD for keeping me in good health and spirits throughout

my stay at LSU.

ii
Table of Contents
Acknowledgements...........................................................................................................ii

List of Tables ...................................................................................................................v

List of Figures ..................................................................................................................vi

Abstract ............................................................................................................................x

Chapter 1: Introduction ...................................................................................................1

1.1 Description of IDDQ ......................................................................3
1.2 Reliability Benefits Derived from IDDQ........................................5
1.3 Literature Review.........................................................................5
1.4 Chapter Organization ...................................................................9

Chapter 2: The Digital-to-Analog Converter (DAC) Design .........................................10

2.1 Performance Specifications of Digital-to-Analog Converter ......12
2.2 Digital-to-Analog Converter Architectures .................................19
2.3 Digital-to-Analog Converter Operation.......................................24
2.3.1 Capacitor Array Design .......................................27
2.3.2 Operational Amplifier Design .............................30
2.3.3 A Two Stage CMOS Opamp Topology...............33
2.3.4 Current Mirrors....................................................33
2.3.5 Active Resistor.....................................................37
2.3.6 Unity Follower.....................................................45
2.3.7 Sample-and-hold circuit.......................................47
2.3.8 The Transmission Gate Switch............................50
2.3.9 The Storage Capacitor .........................................51
2.4 10-bit Digital-to-Analog Converter .............................................52

Chapter 3: Built-in Current Sensor Design .....................................................................61

3.1 Current Testing in CMOS Integrated Circuits Using BICS.........61
3.2 IDDQ Hardware..............................................................................62
3.2.1 External IDDQ Testing..........................................64
3.2.2 Internal IDDQ Testing ...........................................66
3.3 Physical Faults in CMOS Integrated Circuits..............................67
3.3.1 Open Faults .........................................................67
3.3.2 Bridging Faults....................................................70
3.3.3 Gate-Oxide Short Defects ...................................73
3.4 Definition and Description of IDDQ of a Faulty Circuit................73
3.4.1 Description of IDDQ of a Faulty Inverter ............75
3.5 Design Considerations of BICS ...................................................77
3.5.1 Previously Proposed Schemes ...........................77
3.5.2 The Design of the BICS.....................................78
3.6 The Implementation of BICS.......................................................80

iii
 3.6.1 BICS in Normal Mode ......................................80
3.6.2 BICS in Test Mode ...........................................82
3.6.3 Detailed Analysis of BICS ...............................83
3.7 Layout, Simulation and Timing Diagrams for BICS ...................84
3.7.1 Current Mirror Circuit.......................................84
3.7.2 Current Differential Amplifier..........................84
3.7.3 BICS..................................................................87
3.8 Fault Detection, Simulation and Testing .....................................87
3.8.1 Fault-Injection Transistor...................................89

Chapter 4: Theoretical and Experimental Results ...........................................................97

4.1 Simulation Results .......................................................................97

Chapter 5: Conclusion and Scope of Future Work .........................................................121

Bibliography: ..................................................................................................................123

Appendix A: SPICE LEVEL 3 MOS Model Parameters for Standard

n-well CMOS Technology ........................................................................127

Appendix B: Chip Testability ..........................................................................................129

Vita...................................................................................................................................136

iv
List of Tables
4.1 Theoretical and measured IDDQ for different fault types........................................119

4.2 Comparison of built-in-current ..............................................................................120

v
List of Figures

1.1 Block diagram of IDDQ testing .............................................................................4

1.2 Example of how IDDQ detects physical defects ....................................................6

2.1 Block diagram of a digital-to-analog converter ...................................................11

2.2 Basic Architecture of a DAC without the S/H circuit..........................................13

2.3 DNL Characteristics of a 10-bit charge scaling DAC [19]..................................14

2.4 INL characteristics of a 10-bit charge scaling DAC [19] ....................................16

2.5 Offset in a DAC ...................................................................................................17

2.6 Gain error in a DAC.............................................................................................18

2.7 A simple resistor string DAC...............................................................................20

2.8 Current steering based DAC architecture ............................................................22

2.9a Charge scaling DAC Architecture .......................................................................23

2.9b Equivalent circuit with MSB =1, and all other bits set to zero ............................23

2.10 Schematic block diagram of a 10-bit charge scaling DAC..................................25

2.11 Integrated Capacitance network, multiplexer switches and amplifier part

of the circuit of Fig. 2.10 .....................................................................................26

2.12 Layout of a unit capacitance made of poly1 and poly2 used in the design .........28

2.13 Layout of the capacitor array using unit capacitor configuration ........................29

2.14 Layout showing the use of dummy capacitors to match the capacitors
present at the corner of the capacitor array..........................................................31

2.15 Block diagram for an integrated opamp...............................................................32

2.16 A CMOS operational amplifier............................................................................34

2.17 PMOS current mirror design................................................................................36

2.18 NMOS current mirror design ...............................................................................36

vi
2.19 Layout of an operational amplifier design of Fig. 2.16 .......................................40

2.20 Post-layout transfer characteristics of the circuit of Fig. 2.16 .............................41

2.21 Input and Output response of the amplifier circuit of Fig. 2.16 ..........................42

2.22a Frequency response characteristics of the circuit of Fig. 2.16 .............................43

2.22b Phase response characteristic of the circuit of Fig. 2.16......................................44

2.23 The non-inverting OPAMP configuration ...........................................................46

2.24 The CMOS operational amplifier as a unity gain amplifier (follower) ...............48

2.25 Schematic diagram of a sample-and-hold amplifier ............................................49

2.26 Sample and Hold CMOS circuit ..........................................................................54

2.27 Layout of a CMOS sample-and-hold circuit (S/H) circuit...................................55

2.28 Sample-and-hold circuit response........................................................................56

2.29 Schematic block diagram showing opamp, TG-switch, storage capacitor

and unity gain buffer ............................................................................................57

2.30 Sample and hold response of circuit of Fig. 2.26 obtained from post
layout SPICE simulations ....................................................................................58

2.31 Layout of a 10-bit charge-scaling DAC...............................................................59

2.32 DAC output response for all (0000000000 – 1111111111) combinations

of the input digital word.......................................................................................60

3.1 Faulty (IDEF) and fault-free (IREF) IDDQ current ....................................................63

3.2a Off-chip IDDQ current measurement using an automatic test equipment..............65

3.2b Off-chip IDDQ current measurement .....................................................................65

3.3 Block diagram of IDDQ testing..............................................................................68

3.4 Open circuit defect ...............................................................................................69

3.5 Drain-source and inner-gate bridging faults in an inverter chain ........................71

3.6 Bridging defect.....................................................................................................72

vii
3.7a Gate-oxide-short (GOS) in a MOSFET ...............................................................74

3.7b Equivalent circuit model. RS is the effective resistance of the short. B models
the rectifying behavior of new current path introduced by the defect .................74

3.8 Bridging fault causing IDDQRB drop and a path to the ground .............................76

3.9 CMOS built-in current sensor circuit...................................................................79

3.10 Built-in current sensor with CUT ........................................................................81

3.11 n-MOS current mirror circuit...............................................................................85

3.12 Schematic of a current differential amplifier .......................................................86

3.13 Layout of a built-in current sensor circuit............................................................88

3.14a Fault-injection transistor (FIT).............................................................................91

3.14b Fault-injection transistor between drain and source nodes of a CMOS

inverter .................................................................................................................91
3.15 Layout of a 10-bit DAC with BICS showing the defects induced in
the CUT using fault-injection transistors..............................................................92
3.16 CMOS operational amplifier circuit with defect 1 introduced using a FIT..........93
3.17 CMOS unity gain buffer circuit for S/H with defect 2 introduced using a FIT....94

3.18 CMOS MUX circuit with defect 3 introduced using a FIT ..................................95

3.19 CMOS MUX circuit with defect 4 introduced using a FIT ..................................96

4.1 CMOS chip layout of a 10-bit charge scaling DAC with four
fault injection transistors distributed across the chip............................................98

4.2 MOS chip layout of a 10-bit charge scaling DAC including BICS within a
padframe of 2.25mm × 2.25mm size ....................................................................99

4.3 Microchip photograph of 10-bit charge scaling DAC and BICS for
IDDQ testing...........................................................................................................101

4.4 Simulated and measured characteristics of a 10-bit charge scaling DAC ...........102

4.5 Measured DNL characteristics of a 10-bit charge scaling DAC...........................103

4.6 Measured INL characteristics of a 10-bit Charge Scaling DAC...........................104

viii
4.7 Voltage gain response of op-amp with fault introduced .......................................105
4.8 Transfer function of op-amp with fault (VE1) induced..........................................106
4.9 Gain versus frequency response of the CMOS opamp circuit with
fault introduced .....................................................................................................107
4.10 Simulated output response of the multiplexer circuit of Fig 3.18
without defect........................................................................................................108
4.11 Simulated output response of the multiplexer circuit of Fig. 3.18
with fault activated................................................................................................109
4.12 Simulated BICS output of the circuit of Fig 3.16 when Error-signal-1
for defect-1 is activated.........................................................................................110
4.13 Simulated BICS output of the circuit of Fig 3.17 when Error-signal-2
for defect-2 is activated ........................................................................................112
4.14 Simulated BICS output of the circuit of Fig. 3.18 when Error-signal-3
for defect-3 is activated.........................................................................................113
4.15 Simulated BICS output of the circuit of Fig.3.19 when Error-signal-4
for defect-4 is activated.........................................................................................114
4.16 CMOS circuit diagram of 10-bit charge scaling DAC with four
fault injection transistors distributed across different parts of the circuit.............115

4.17 Simulated BICS output with defects induced using fault injection transistors.....116

4.18 HP 1660CS logic analyzer test results on a fabricated CMOS 10-bit charge
scaling DAC showing the performance of BICS in normal and test modes.........118

5.1 Block diagram of a sigma-delta ADC...................................................................122

B.1 Pin configuration of 10-bit DAC with BICS.........................................................134

B.2 Microchip photograph of 10-bit charge scaling DAC and BICS

for IDDQ testing .....................................................................................................135

ix
Abstract

This work presents an effective built-in current sensor (BICS), which has a very

small impact on the performance of the circuit under test (CUT). The proposed BICS

works in two-modes the normal mode and the test mode. In the normal mode the BICS is

isolated from the CUT due to which there is no performance degradation of the CUT. In

the testing mode, our BICS detects the abnormal current caused by permanent

manufacturing defects. Further more our BICS can also distinguish the type of defect

induced (Gate-source short, source-drain short and drain-gate short). Our BICS requires

neither an external voltage source nor current source. Hence the BICS requires less area

and is more efficient than the conventional current sensors. The circuit under test is a 10-

bit digital to analog converter using charge-scaling architecture.

x
Chapter 1

Introduction

Conventional logic testing applied in digital circuits can detect faults, which can

cause logic errors [1]. It, however, cannot detect several physical defects such as the gate-

oxide shorts, floating gates and the bridging faults. These physical defects do not cause

any logical error at the time of testing but can manifest into a fault at an early stage of the

circuit life. Thus, circuits should also be tested for physical defects apart from logic

errors. Though methods exist for testing digital circuits but testing of analog circuits is

still a problem. Mixed signal circuits are even more difficult to test. A general and

efficient solution for testing mixed-signal integrated circuits is still not available.

Functional test approach applied to test the functionality of analog and mixed-

signal integrated circuits is based on empirical development of a test set [2, 3]. This

approach needs a reasonably large number of sample circuits for collecting the test data.

The approach also does not have any inherent test metric to measure the achievement of a

test goal. Design for testability (DFT) is another widely used method [4]. Oscillation test

strategy is based on the DFT technique [4, 5], which gives good fault coverage and does

not require any test vectors. In this method, the complex analog circuit is partitioned into

functional building blocks such as an amplifier, comparator, Schmitt trigger, filter,

voltage reference, oscillator, phase-lock loop (PLL), etc., or a combination of these

blocks. During the test mode, each building block is converted into a circuit that

oscillates. The oscillation frequency, fOSC of each building block can be expressed as a

function of its components or performances. The oscillation test method allows removing

the analog test vector generator and output evaluators, and consequently reduces the test

1
complexity, area overhead, and test cost. However, the method suffers from performance

degradation in complex integrated circuits since it is not usually possible to divide the

circuit into the fundamental blocks. Built in self-test (BIST) method is based on

measuring the output data and calculating the performance of the system using an on-chip

circuitry [6,7]. This method reduces testing complexity of mixed-signal integrated

circuits by incorporating all or some of the testing circuitry on the silicon. An important

component of a mixed-signal BIST is a precision analog signal generator required for on-

chip stimulation. While the area overhead is kept to a minimum, these generators should

be capable of synthesizing high-precision single-and multitone signals with controllable

frequency and amplitude. This method also suffers from performance degradation and

does not cover physical defects.

The steady state or quiescent current (IDDQ) testing of CMOS integrated circuits is

known to be very efficient for improving test quality [8, 9]. The test methodology based

on the observation of the quiescent current on power supply lines allows a good coverage

of physical defects such as gate-oxide shorts, floating gates and bridging faults. These

defects are neither well modeled by the classical fault models, nor detectable by

conventional logic tests. In addition, IDDQ testing can be used as a reliability predictor due

to its ability to detect defects that do not yet involve faulty circuit behavior, but could be

transformed into functional failures at an early stage of circuit life. Thus, IDDQ testing

became a powerful complement to the conventional logic testing. In analog circuits, the

quiescent current, termed as IPS may be in the order of µA’s or mA’s [10]. Under the

fault conditions, the normal values of IPS may be increased, decreased or generally

2
distorted. Thus, fault detection can be accomplished by monitoring the IPS current

fluctuations using a current sensing circuit.

In this thesis, a simple built-in current sensor (BICS) is presented, which provides

a digital output for supply current monitoring and testing in mixed-signal circuits. The

proposed BICS is based on current differential amplifier architecture providing a digital

output proportional to the IDDQ (IPS) current of the circuit under test. BICS is inserted in

series with the power supply or the ground of the CUT to detect abnormal IDDQ current in

the integrated circuit [5] as shown in Fig. 1. The new BICS requires less area and has less

performance degradation than reported earlier [11-18]. Furthermore, BICS requires

neither an external voltage reference nor a current reference since the reference is

generated on chip. It only requires two extra control pins, which control the mode of

operation of the BICS and one output pin. The proposed BICS has been designed to test a

10-bit charge scaling digital-to-analog converter (DAC) [19].

1.1 Description of IDDQ

IDDQ’s definition is the current that flows in the CMOS circuit under quiescent (steady

state) operating condition. Any current above the quiescent current would indicate the

presence of physical defects in the circuit. Figure. 2 shows how an IDDQ test can identify

physical defects. Q4 has a defect that causes a resistive path between its gate and source.

When VIN is logic ‘1’ level, the gate and the source of Q4 are held at ground by Q2, which

prevents the flow of any IDD current [20]. When VIN switches to a logic ‘0’ level, Q4’s

gate is pulled high by Q1. This allows the current to flow from VDD through the defective

path to ground.

3
 VDD

PMOS
BLO C K

IN P UT S

O UT P UT

NMOS
BLO C K

P AS S /F AIL

BIC S

Figure 1.1: Block diagram of IDDQ testing.

4
1.2 Reliability Benefits Derived from IDDQ

IDDQ testing has been shown to identify gate oxide shorts (GOS). Many of these gate

oxide shorts do not initially cause a functional failure but over the time they can

deteriorate until functionality is affected. To quantify this effect, Ford Microelectronics

Inc. (FMI) conducted a life test study on IDDQ failures for ASIC’s, recording leakage

current instability [20]. It was theorized that any instability could be used as a leading

indicator for predicting component reliability. After 48 hours of life testing, the ASIC

components passed all burn-in, hot and cold functional testing, and parametric testing but

failed for IDDQ. The circuit under test (ASIC components) had IDDQ values ranging from 0

µA to greater than 100 µA [20]. This experiment was repeated and verified on similar

devices. Failing IDDQ does not necessarily result in non-functional behavior. However,

data is available, which confirms a significant number of IDDQ failures will result in

reliability problem [20]. Life test studies conducted at FMI have shown a statistically

significant number of IDDQ failures have become inoperative over time [20]. This life test

experiment studied the effect of IDDQ values versus product reliability.

1.3 Literature Review

In the following section a brief review of the selected works on IDDQ testing are

described which are used to compare with the present work

• Maly and Patyra’s design [13]: The main idea is to make use of a differential

amplifier with a reference voltage at the non-inverting node and the current-

related voltage at the inverting node. Two clocks φ1 and φ2 are used to control

when to sample the data. The importance of minimizing the impact of BICS on

the performance of the CUT is taken into consideration. Hence a lateral NPN BJT

5
 VD D VD D

ID D

Q1 Q3

Vin Vo u t

Q2 Q4

D efec t

Figure 1.2: Example of how IDDQ detects physical defects.

6
• is used to supply a large current with an allowable drop [13,18]. Due to the

exponential characteristic of the BJT, this design [13] also enhances the IDDQ

detectability even when the abnormal current is little more than steady state

current. However, the requirement of external voltage reference, double clocks,

and lateral NPN BJT make this design difficult to implement.

• Favalli et al. design [14]: In this design, each gate requires two extra transistors

and the whole circuit requires other transistor (see Fig. 3 of [14]). All these

transistors are used to convert analog faults to stuck-at faults. A selection line is

used to switch between normal mode and test mode. The design is easy to

implement since it uses only digital circuits. However, the area overhead is quite

high since each gate requires two additional transistors.

• Miura and Kinoshita’s design [15]: The design consists of a V-I translator, a level

translator and a integrator circuit. The V-I translator transforms the current of a

given CUT to a corresponding voltage. The level translator transforms the output

voltage of the V-I translator to an appropriate logic value. The integrator circuit

produces a faulty signal when the faulty logic generated by the level translator

lasts for certain time intervals. This BICS itself can be tested by applying an

external current source to the special ground pin NGND (Fig.1 of [15]).

• Shen et al. design [16]: The design is similar to the comparator circuitry (the

differential amplifier) of Ref.15 and consists of a differential amplifier

(comparator) circuit and an output circuit. A clock generator is used to generate a

two-phase clock CLK1 and CLK2 so that the transient current can be bypassed. A

diode is used to limit the voltage drop on the sensing device. The comparator

7
 circuit compares the externally generated IREF with IDDQ from the CUT. Through

proper sampling in the steady state, a PASS/FAIL flag is then detected from the

output circuit. This scheme may still degrade the circuit since the cut-off voltage

0.6V of the diode may be too high when compared to the low level output voltage

VOL = 0.5V. The design also requires external current reference and a two-phase

clock generator.

• Verhelst’s design: By employing the “virtual short” property of an OP-AMP the

voltage drop on BICS is further reduced. The current supplied by the CUT passes

through the current sensing transistor Ts. This current is compared with the

reference current. Since the transistor, Ts operates in the linear region, less current

can be provided for a given device dimension. Thus, even if the voltage stability

is increased, the current supply capability is limited. An external current reference

is also needed. [See U.S. patent 5057774, Oct. 15, 1991 by S.C. Verhelsts, E.

Seevinck and K. Baker, “ Apparatus for measuring the quiescent current of an

integrated monolithic digital circuits” referred in J.J. Tang, K.J. Lee and B.D. Liu,

“ A practical current Sensing Technique for IDDQ Testing,” IEEE Trans. on Very

large Scale Integration (VLSI) Systems, vol.3, No.2, June 1995, pp.302-310].

Methods have been developed to test integrated circuits based on dynamic supply

current (IDD) measurement [21], on-line power dissipation measurement and IDDQ testing

[22] and on-chip transient current measurements [23-26]. Current sensors have been

proposed for analogue applications [22]. In [22], the sensor design is based on a series

voltage regulator, in which a series transistor is connected between the supply and the

8
(CUT). One drawback is the area required to realize this serial transistor since it has to

sink all the current to the CUT.

1.4 Chapter Organization

In the following chapters, the methodology, circuit design and technology

considerations, transient simulations, post layout measurements and experimental results

are discussed.

Chapter 2 explains the basic structure and operation of a 10-bit charge scaling digital to

analog converter (DAC).

Chapter 3 explains concept of IDDQ testing, design and implementation of a built-in

current sensor. The mechanism of fault simulation and fault detection in a 10-bit charge

scaling using the BICS is explained.

Chapter 4 describes the simulation result and design considerations of each module of

10-bit charge scaling DAC. Simulations results of each module of the DAC are included.

It also describes the simulation results for each module of the built-in current sensor.

Finally, a description of the abnormal current behavior and fault detection in the DAC is

explained and simulation results are included. Experimental results of the fabricated

device are presented, compared with simulations. Results are also compared with the

published work.

Chapter 5 provides a summary of the work presented and scope for future work.

The MOS model parameters used for design is presented in Appendix A. The

entire chip testing procedure is presented in Appendix B.

9
Chapter 2

The Digital –to- Analog Converter (DAC) Design

The ability to convert digital signals to analog and vice versa is very important in

signal processing. The digital-to-analog conversion is a process in which digital words

are applied to the input of the DAC to create from a reference voltage an analog output

signal that represents the respective digital word. In this conversion process, an N-bit

digital word is mapped into a single analog voltage. Typically, the output of the DAC is a

voltage that is some fraction of a reference voltage, such that [27-29].

VOUT = F VREF (2.1)

Where VOUT is the analog voltage output. VREF is the reference voltage. F is the fraction

defined by the input word, D, that is N bits wide. The number of input combinations

represented by the input word D is related to the number of bits in the word by

Number of input combinations = 2N (2.2)

The maximum analog output voltage for any DAC is limited by the value of some

reference voltage VREF. If the input is an N-bit word, then the value of the fraction, F, can

be determined by,

D
F= (2.3)
2N

Figure. 2.1 shows a conceptual block diagram of a DAC converter. The inputs are a

digital word of N-bits (b1, b2, b3… bN) and a reference voltage, VREF. The voltage output,

VOUT, can be expressed as

VOUT = KVREFD (2.4)

10
 VREF
MSB

DN-1
DN-2
Vout
Input word, D
(N bits wide)

DN-3 Digital-to-analog
Converter
(DAC)
D1
D0

LSB

Figure 2.1: Block Diagram of a digital-to-analog converter

11
Where K is a scaling factor and the digital word D is given by

b1 b2 b3 bN
D= 1
+ 2 + 3 + ……+ N (2.5)
2 2 2 2

N is the total number of bits of the digital word, and bi is the ith coefficient and is either 0

or 1. Thus, the output of a DAC can be expressed by combining Eqs. 2.4 and 2.5 to get

b1 b2 b3 bN
VOUT = K VREF ( 1
+ 2 + 3 + ……+ N ) (2.6)
2 2 2 2

The basic architecture of a DAC without a sample and hold circuit at the output is

shown in Fig. 2.2. The various blocks are a voltage reference, which can be supplied

externally, binary switches, a scaling network, and an output amplifier. The voltage

reference, binary switches, and scaling network convert the digital word as either a

voltage or current signal, and the output amplifier converts this signal to a voltage signal

that can be sampled without affecting the value of conversion.

2.1 Performance Specifications of Digital-to-Analog Converter

The following are some of the important static and dynamic performance

parameters used to characterize a DAC [27-29].

• Differential Nonlinearity (DNL)

The DNL gives a measure of how well a DAC can generate uniform analog LSB

multiples at its output. It is defined as follows

DNLn = (actual increment height of transition, n) – (ideal increment height).

Where ‘n’ is the number corresponding to the digital input transition. DNL is illustrated

in Fig. 2.3.

12
 Vref KVrefD Vout = KDVref
Voltage Scaling Output
Reference Network Amplifier

Binary
Switches

b1 b2 b3 bN

Figure 2.2: Basic Architecture of a DAC without the S/H circuit.

13
 0.8

0.6

0.4

0.2
LSB's

0
0 200 400 600 800 1000
-0.2

-0.4

-0.6

-0.8
Digital Input Code

Figure. 2.3: DNL Characteristics of a 10-bit charge scaling DAC [19].

• Integral Nonlinearity (INL)

Another important static characteristic of a DAC is called integral nonlinearity

(INL). It is defined as the difference between the data converter output values and a

14
reference straight line drawn through the first and last output values as shown in Fig. 2.4.

INL defines the linearity of the overall transfer curve and can be described as follows.

INLn = (output value for the input code, n) – (output value of the reference line at the

point).

• Offset

Offset of the DAC is defined as the amount of shift in the transfer characteristics when

the digital input code D = 0. This shift is similar to the offset voltage for an operational

amplifier. It is shown in Fig. 2.5.

• Gain Error

Gain Error is defined as the difference between the ideal slope and the actual slope of the

transfer characteristics. It is described as follows and shown in Fig. 2.6.

Gain Error = (ideal slope – actual slope)

• Dynamic Range

Dynamic range is defined as the ratio of the largest analog output value (Full Scale (FS))

to the smallest analog output value. The dynamic range in decibels is given by,

DR = 20 log (2N – 1) dB. (2.7)

For our design, which is a 10bit, charge-scaling DAC, the dynamic range is 60.19 dB.

• Resolution

It is described as the smallest change in the analog output with respect to the value of the

reference voltage VREF. The resolution is given by [29]

15
 0.9

0.8

0.7

0.6

0.5
LSB's

0.4

0.3

0.2

0.1

0
0 200 400 600 800 1000
Input Code

Figure.2.4: INL characteristics of a 10-bit charge scaling DAC [19].

16
 Actual

Ideal
Normalized Analog output

Figure 2.5: Offset in a DAC.

17
 Ideal

Normalized Analog output Actual

Figure 2.6: Gain error in a DAC.

VREF 2V
Resolution(N) = Log2 ( ) = Log2( ) = 10 bits. (2.8)
1LSB 1.9mV

2.2 Digital-to-Analog Converter Architectures

A wide variety of of DAC architectures exist, ranging from very simple to complex.

Each of course, hast its own merits. There are primarily three architectures of DAC

namely-

• Resistor String

• Current Steering

• Charge Scaling

18
 • Voltage Division

In this architecture, the analog output voltage is divided uniformly among the

resistor string as shown in Fig. 2.7 [27]. Depending on the input digital word, the

switches shown close or open if the input is a ‘high’ or ‘low’ voltage, respectively. The

analog output is simply the voltage division of the resistors at the selected tap. The value

of the voltage at the tap associated with the ith resistor is given by [27]

(i ).VREF
Vi = N
, for i = 0, 1, 2… 2N-1 (2.9)
2

This architecture typically results in good accuracy, provided that no output current is

required and that the values of the resistors are within the specified error tolerance of the

converter. Another problem with this architecture is the balance between the area and

power dissipation. So this architecture is not suited for high resolution DAC’s.

19
 VREF

R2 N S2 N-1

V2 N-1
R2 N-1 S2 N-2
V2 N-2
S2
VO UT
V2
R2 S1

V1
R1 S0

V0
R0

Figure 2.7: A simple resistor string DAC.

• Current Steering

The current steering based DAC architecture is shown in Fig. 2.8 [27]. This DAC

architecture uses current through out the conversion known as current steering. This type

of DAC requires precision current sources that are summed in various fashions. Since

there are no current sources generating iOUT when all the digital inputs are zero, the MSB,

20
D2N-2, is offset by two index positions instead of one. The binary signal controls whether

or not the current sources are connected to either iout or GND. The output current iout has

the range of

0 ≤ iout ≤ ( 2N – 1). I (2.10)

One advantage of the current steering DAC’s is the high-current drive inherent in the

system. Of course, the precision needed to generate high resolutions is dependent on how

well the current sources can be matched or the degree to which they can be made binary

weighted. Another problem associated with this architecture is the error due to the

switching.

• Charge Scaling

A very popular architecture used in the CMOS technology is the charge scaling

DAC and is shown in Fig. 2.9(a). In this architecture, a parallel array of the binary-

weighted capacitors, 2N C, is connected to the op-amp, where C, is a unit capacitance of

any value. After initially being discharged, the digital signal switches each capacitor to

either VREF or ground (GND) causing the output voltage, VOUT, to be a function of the

voltage division between the capacitors. Since the capacitor array totals 2NC, if the MSB

is ‘high’ and the remaining bits are ‘low’, then a voltage divider occurs between the MSB

capacitor and the rest of the array. The analog voltage, VOUT becomes

21
D2 N--2 D2 N--3 D2 N-4 D1 D0

iO UT

I I I I I

Figure 2.8: Current steering based DAC architecture.

22
 VOUT
2N-1C 2N-2C 4C 2C C C

VREF
DN-1 DN-2 D2 D1 D0

Figure 2.9 (a): Charge scaling DAC Architecture.

2N-1 C

VREF VOUT

2N-1 C

Figure 2.9 (b): Equivalent circuit with MSB =1, and all other bits set to zero.

VREF
VOUT = , (2.11)
2

23
which confirms the fact that the MSB changes the output of a DAC by ½ VREF. Figure

2.9(b) shows the equivalent circuit under this condition. Therefore, the value of VOUT for

any digital word is given by [27]

N −1
VOUT = ∑D
k =0
k 2k-N . VREF where k = 0, 1…N-1. (2.12)

The 10-bit DAC used in our design uses charge scaling DAC. The unit capacitance in the

DAC is 10fF. The reference voltage used is 2V, VSS is –2.5V and VDD is +2.5V.

2.3 Digital-to-Analog Converter Operation

The basic circuit diagram of a 10-bit charge-scaling DAC is shown in the Fig.

2.10. This circuit converts the 10-bit digital input word to a respective analog voltage

depending on the capacitive network. The various blocks associated with the DAC are

operational amplifier, sample-and-hold circuit (S/H), capacitive network and the

multiplexer switches to which the digital word is given. Figure 2.11 shows the integrated

capacitance network, multiplexer switches and amplifier part of the Fig 2.10. Initially the

input digital word is given to a multiplexer circuitry. Depending on the logic value of

each bit of the word, the multiplexer chooses the particular voltage to which the capacitor

is to be charged. If the input bit in the digital word is logic ‘0’ then the multiplexer

chooses the input which is connected to the ‘GND’ and the capacitor is charged to ‘GND’

and if the input bit in the digital word is logic ‘1’ then the capacitor is charged to VREF.

The capacitor at the end of the network is used as a ‘terminating capacitor’. Depending

on the capacitors, which are charged to different voltages based on the input digital

24
 STORAGE UNITY-GAIN
TG SWITCH
CAPACITOR BUFFER
CAPACITOR ARRAY ARCHITECTURE OPAMP

-
A=1
- +
+ Vo
+
CH -
512C 256C 128C 64C 32C 16C 8 C 4C 2C C C

CIRCUITRY TO GENERATE DIGITAL INPUT WORD

Sample and Hold Input

O utput of Multiplexer

25
VREF
Control Signal

Figure 2.10: Schematic block diagram of a 10-bit charge scaling DAC.

Note: VDD = +2V, VSS = -2V, GND = 0V.
 CAPACITOR ARRAY ARCHITECTURE OPERATIONAL AMPLIFIER

VDD

M8 M7
W/ L =45/3
W/ L =90/3
W/ L =90/3
M6

W/ L =90/3 W/ L =90/3
512C 256C 128C 64C 32C 16C 8C 4C 2C C C
CC =30FF
- Vin M1 M2 Vout

26
W/ L =9.6/3 M9 M3 M4
W/ L =90/3
M5
W/ L =45/3
W/ L =45/3

V SS

V REF V REF V REF

Control Signal Control Signal Control Signal

Figure. 2.11: Integrated capacitance network, multiplexer switches and amplifier part of the circuit of Fig. 2.10
The capacitor at the end of the network is used as a ‘terminating capacitor’. Depending

on the capacitors, which are charged to different voltages based on the input digital

words, the effective resultant analog voltage is calculated for the respective digital

combination. This analog voltage is passed through the OPAMP and through the S/H

circuit and appears as analog voltage. Thus, the digital to analog conversion is performed.

The DAC consists of several blocks and their design is explained in following section.

2.3.1 Capacitor Array Design

The capacitor architecture in the DAC is being drawn using two poly layers poly1

and poly2. The unit capacitance used in the capacitor array is 10fF. Figure 2.12 shows the

layout of the unit capacitor used in the design. This design considers unit capacitor

configuration since it is a very successful way of overcoming or reducing the effect of

various errors introduced during fabrication. In the fabrication process of on-chip

capacitors, the capacitance value of a single capacitor can vary with up to 10 to 30

percent from the desired value. Because of this, it is difficult to produce high accuracy

capacitors in a standard CMOS process as well as integrated circuits, which rely on the

accuracy of a single capacitance value. If, instead, capacitance ratios are used, the relative

error is cancelled since it is the ratio of the capacitance that is taken in to consideration

but not the single capacitance value alone. Figure 2.13 shows the layout of the capacitor

array using unit capacitor configuration. The array is surrounded with dummy capacitors

and guarded by the guard ring to cancel out the effect of parasitics.

The capacitors, which are present at the end of the arrays, do not have the

surrounding capacitors to cancel out the relative error. To take care of these capacitors

27
Figure 2.12: Layout of a unit capacitance made of poly1 and poly2 used in the design.

28
Figure 2.13: Layout of the capacitor array using unit capacitor configuration.

29
dummy capacitors are added to the array [31]. Figure 2.14 shows the use of dummy

capacitors in the capacitor array layout. The substrate noise present in the substrate can

be coupled to the capacitor through its parasitic capacitor and any voltage variation

present is also coupled to other components of the chip. To avoid this coupling the

capacitor array is shielded from the substrate with N-well under it and connecting it to a

quiet DC potential [31]. The guard rings are used in the layout around the capacitor array

to prevent from any sort of interference.

2.3.2 Operational Amplifier Design

In the analog world, the most commonly used device is the operational amplifier

(OPAMP). An operational amplifier is an electronic device whose output can be related

to its input in terms of a known mathematical operation. This is usually achieved by using

active or passive elements such as resistors and capacitors in integrators and differentiator

circuits. A typical operational amplifier is characterized by a high open loop gain, high

bandwidth, a very high input impedance, low output impedance and an ability to amplify

differential mode signals to a large extent and at the same time, severely attenuate

common mode signals. The amplifier in the 10-bit DAC (Fig.2.10) is realized by one

such operational amplifier. Figure 2.15 shows the block diagram of an operational

amplifier [30]. An OPAMP normally consists of four main functional blocks. First is the

input differential gain stage that amplifies the voltage difference between the input

terminals, independently of their average or common mode voltage. Most of the critical

parameters of the OPAMP like the input noise, common mode rejection ratio (CMRR)

and common mode input range (CMIR) are decided by this stage. The differential to

single-ended conversion stage follows the differential amplifier and is responsible for

30
 Dummy Capacitor

Figure 2.14: Layout showing the use of dummy capacitors to match the capacitors
present at the corner of the capacitor array.

31
 V+ Second
+ + DC + +
Input + Differential
Differential to Gain V0
Single-Ended Level
V- Amplifier - -
- Conversion Stage

32
Shift

Figure 2.15: Block diagram for an integrated OPAMP.

producing a single output, which can be referenced to ground. As it is necessary to bias

the second gain stage properly, a level-shifting block is introduced after the differential to

single-end conversion stage. Finally, additional gain is obtained in the second gain stage.

A description as well as the design methodology of each of the stages mentioned

above is carried out in the following subsections.

2.3.3 A Two-Stage CMOS OPAMP Topology

The most widely used CMOS operational amplifier is a two-stage configuration

as shown in Fig. 2.16. This circuit configuration provides a good voltage gain, a good

common mode range and good output swing. Before the analysis of the OPAMP is done,

some of the basic principles behind the working of MOS transistors are reviewed. The

input differential amplifier stage is implemented by a differential pair of p-MOS

transistors (M1 & M2) with their sources tied together. The differential pair is biased by

current mirrors, which act as the active load too. Two current mirrors: a p-MOS current

mirror (M7 & M8) and an n-MOS current mirror (M3 & M4) are used instead of just one

in order to increase the common mode rejection ratio (CMRR) of the differential pair.

The p-MOS current mirror serves as a constant current source and the n-MOS mirror,

which sinks current, acts as an active load across which the first stage output is taken,

there by performing a differential to single-ended conversion in the process.

2.3.4 Current Mirrors

Current mirrors are used extensively in MOS analog circuits both as biasing elements and

as active loads to obtain high AC voltage gain [28, 29]. Enhancement-mode transistors

remain in saturation when the gate is tied to the drain, as the drain-to-source voltage

33
 VDD

M8 M7
W/L=45/3
W/L=90/3
W/L=90/3
M6

+ Vin
W/L=90/3 W/L=90/3
- Vin CC =30FF
M1 M2 Vout

M9 M3 M4
W/L=9.6/3 W/L=90/3
M5
W/L=45/3
W/L=45/3

VSS

Figure 2.16: A CMOS operational amplifier.

34
(VDS) is now always going to be greater than the gate-to-source voltage (VGS) due to the

threshold voltage (Vth) drop i.e

VDS > VGS – Vth (2.13)

Based on Eq. (2.13), constant current sources are obtained through current mirrors

designed by passing a reference current through a diode-connected (gate tied to drain)

transistor. Figures 2.17 and 2.18 shows the p-MOS and n-MOS current mirrors design. A

p-MOS mirror serves as a current source while the n-MOS acts as a current sink. The

voltage developed across the diode-connected transistor is applied to the gate and source

of the second transistor, which provides a constant output current. Since both the

transistors have the same gate to source voltage, the currents, which when both transistors

are in the saturation region of operation, are governed by the following equation 2.14

assuming matched transistors. The current ratio IOUT / IREF is determined by the aspect

ratio of the transistors. The reference current that was used in the design is 100µA. The

desired output current is 200µA.

For the p-MOS current mirror, we can write,

IOUT / IREF = (W7 / L7) / (W8 / L8) (2.14)

For (W7/L7) / (W8/L8) = 2,

IOUT = 2 x IREF = 200µA (2.15)

For identical sized transistors, the ratio is unity, which means that the output current

mirrors the input current. Because the physical channel length that is achieved can vary

substantially due to etching variations, the accurate current ratios usually results when

devices of the same channel length are used, and the ratio of currents is set by the channel

width. For the n-MOS current mirror design shown in Fig 2.18,

35
 VDD

M8 M7
(45/3) (90/3)

I0 = 200µA
IREF = 100µA

Figure 2.17: PMOS current mirror design.

IREF = 100µA

M3 M4
45/3 45/3

VSS

Figure 2.18: NMOS current mirror design.

36
 IOUT / IREF = (W4/L4) / (W3/L3) (2.16)

For (W7/L7) / (W8/L8) = 1,

IOUT = IREF = 100µA. (2.17)

2.3.5 Active Resistor

The reference current that is applied to the current mirror is obtained by means of

an active resistor. A resistor can be obtained by simply connecting the gate of a MOSFET

to its drain as shown in Fig 2.17 and 2.18. This connection forces the MOSFET to

operate in saturation in accordance with the equation.

IDS = β (VGS – Vth)2 / 2 (2.18)

Where all the symbols have their usual meanings. Since the gate is connected to the

drain, the current IDS is now controlled directly by VDS and therefore the channel

transconductance becomes the channel conductance. The small signal resistance is given

by

rout ~ rds / ( 1+gm. rds ) ≅ 1 / gm (2.14)

where gm is the transconductance of the MOS transistor. It is defined as the ratio of the

change in drain current to a change in the applied gate and is described by the following

equation.

gm = δIDS / δVGS | VDS, constant (2.19)

or gm = 2 β ID . (2.20)

It is to be noted that the transconductance of a MOS increases as the square root of the

drain current. Therefore, MOS amplifiers need several stages to achieve large gains due

to their low gm values.

37
 The operational amplifier designed in this work is shown in Fig. 2.16. The small

signal gain of the differential amplifier stage is described as follows [27]

A1 = gm1 (ro2 || ro4) =

2 β =
2
(2.21)
(λ 2 + λ 4) ISS (λ 2 + λ 4)(VGS − Vthp )

Where ISS is the differential amplifier bias current and Vthp is the threshold voltage

of the pmos transistors forming the differential pair. The differential amplifier needs to be

biased by a constant current source, which is provided by the 100µA current source. The

same current is supplied to the two stages of the operational amplifier by the p-channel

current mirrors M8, M7, M6 which provide the bias current for the two stages. In the first

stage i.e. the differential amplifier stage not only is the differential amplification

accomplished but also the differential to single ended conversion done. Thus, the output

is taken only from one of the drains of the transistors. The n-channel devices M3 and M4,

which are the load for the p-channel devices, also aid in the single ended conversions.

The second stage provides a level shift for the output of the differential amplifier stage

and it also provides the additional gain. It is once again biased by a current source, which

is also used to maximize the gain of the second stage. To get a high gain with reasonable

high output resistance the minimum channel length used is 3µm and maximum width of

the transistor used is 90µm. Transistor M5 is critical to the frequency response, is biased

at ID5 = 200µA and has (W/L)5=(W/L)max = 30. The input pair is biased at –ID7 = 200µA.

To avoid input offset voltage transistors M3 and M4 are dimensioned according to [28]

(W L) − I D 6 200µA W  1 W 
5
= = = 1 →   =   = 15 (2.22)
2 * (W ) I D7 200µA  L  3, 4 2  L  5
L 3, 4

38
Therefore, the W = 45µm for the transistors M3 and M4. To obtain the bias current of

100µA a MOS resistor is used with appropriate value of width. (which is the MOSFET

simulating resistors). Large W/L ratios for the transistors in the operational amplifier are

obtained by using the following technique. The four transistors are connected in such a

way that the effective W/L ratio is four times the W/L ratio of each transistor. The

technique reduces the required area, in comparison to a device laid out in a

straightforward manner. The benefit of this technique is reduced junction capacitance,

and is well characterized. The simplicity, modularity and predictability of the device

overcome the penalty of associated area.

The physical layout of the amplifier was made using the L-EDIT 8.20 and the

‘spice’ netlist is extracted including parasitic capacitances. The layout of the amplifier is

shown in the Fig.2.19. Figure. 2.20 shows the transfer characteristics obtained from DC

sweep analysis. The output offset voltage is approximately 33µV. Figure 2.21 shows the

transient analysis of operational amplifier. An input voltage of 500µV is applied to the

inverting terminal of the OPAMP at a frequency of 100 kHz. An inverted waveform is

obtained at the output of the OPAMP with peak-to-peak amplitude of 2v, giving a gain of

4000. Figure 2.22 shows the frequency response characteristics. Figure 2.22(a) shows the

amplitude versus frequency behavior. The 3dB bandwidth of the amplifier obtained is

approximately 100 kHz and 3dB gain is 77. Figure 2.22(b) shows the phase versus.

frequency response. The phase noise margin as shown in Fig.2.22 (b) is 200. The

maximum input range is ± 100mV.

39
Figure 2.19: Layout of an operational amplifier design of Fig. 2.16.

40
 Output,V
2.5
2
1.5
1
0.5
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
-0.5 0 0.1 0.2 0.3 0.4 0.5 0.6
-1 Input,V
-1.5
-2
-2.5

DC Offset Voltage = 33 µV

Figure 2.20: Post-layout transfer characteristics of the circuit of Fig. 2.16.

41
 Gain = 4000
2.5
Output
2 Input
1.5
1
0.5
Voltage(V)

0
-0.5 0 100 200 300 400 500

-1
-1.5
-2
-2.5
Time(us)

Figure 2.21: Input and Output response of the amplifier circuit of Fig. 2.16.

42
 90 Gain = 80dB - 3dB = 77dB
80
70
60
Gain (dB)

50
3 dB Band Width
40
= 100 KHz
30
20
10
0
1 10 100 1000 10000 100000 1E+06 1E+07 1E+08

f (Hz)

Figure 2.22(a): Frequency response characteristics of the circuit of Fig. 2.16.

43
 50
45
40
Phase (degrees) 35
30
25
20
15
10 Phase margin = 200
5
0
10 100 1K 10K 100K 1M 10M 1G

frequency (Hz)

90
80
70
60
Gain (dB)

50
40
30
20
10
0
10 100 1K 10K 100K 1M 10M 1G
frequency (Hz)

Fig. 2.22(b): Phase response characteristic of the circuit of Fig. 2.16.

Note: The phase margin is 200.

44
2.3.6 Unity Follower
A unity follower is basically an amplifier with a gain of unity. It is used mainly as

a buffer amplifier in order to increase the current driving capability of the amplifier stage.

An ideal unity follower would exhibit infinite input impedance, zero output impedance,

large bandwidth and unity gain. The gain-bandwidth product of the amplifier is known,

as it’s figure-of-merit, and is a constant for any given amplifier. It is usually determined

for an OPAMP by putting it in the unity follower configuration.

From basic OPAMP theory, we know that the gain of an OPAMP in its non-

inverting configuration as shown in Fig. 2.23 given by

Rf
V0 = (1 + ) Vi (2.23)
R

Rf and R are the feedback and series resistances of the OPAMP and Vi and V0 are the

input and output voltages of the OPAMP. The gain of the OPAMP is determined by the

resistive network alone and is given by,

Rf
Av = (1 + ) (2.24)
R

If Rf is zero, then the gain of the amplifier is unity. The input to be buffered is applied to

the non-inverting terminal of the unity follower, and the output connected to the inverting

terminal of the OPAMP in the feedback configuration. So, as the signal increases in

strength at the non-inverting terminal, the signal at the inverting end increases too thus

forcing the output to follow the input. Only the differential stage of the amplifier

discussed was used to realize the unity follower buffer as shown in Fig 2.24. The drain of

transistor M5 is coupled back to the gate of the input transistor M1. This connection

45
 Rf

- Vo

+
Vi

Vo = (1 + Rf ) Vi
R

Figure.2.23: The non-inverting OPAMP configuration.

46
introduces feedback to the inverting terminal of the OPAMP, thus, putting it in the unity

follower configuration.

2.3.7 Sample-and-hold Circuit

The principal application for sample-and-hold (S/H) amplifier is to maintain a constant

output of the DAC during conversion. The characteristics of the S/H amplifier are crucial

to system accuracy and the reliability of the analog data. As its name indicates, a S/H

amplifier has two modes of operation, programmed by a digital control input. In the

sample mode, the output follows the input, usually with a gain of unity. When the mode

input switches to hold, the output of the S/H amplifier ideally retains the last value it had

when the command to hold was given, and it retains that value until the mode input

switches back to sample. At this time, the output ideally jumps to the input value and

follows the input until the next hold command is given. Figure 2.25 is a block schematic

of a sample-and-hold amplifier. It consists of three major components: a transmission

gate switch (TG-switch), a storage capacitor CH and a unity gain follower. Each of these

elements need to be designed/chosen carefully for good performance. The operation

mechanism is as follows. The TG-switch is operated by the VCONTROL signal and is closed

during the sample interval and open during hold. So, during sample, the circuit is

connected to promote rapid charging of the storage capacitor, CH and during hold, the

capacitor, CH is disconnected from its charging source and ideally retains its charge. The

capacitor is connected to a unity-gain buffer-follower whose output follows the charge

held by the storage capacitor. The unity gain buffer is used at the output to avoid the large

overshoot, which might occur, on the output when the input changes quickly.

47
 VDD

M8 M7
W/L=45/3
W/L=90/3
W/L=90/3
M6

+ Vin

W/L=90/3 W/L=90/3
CC =30FF
- Vin M1 M2 Vout

W/L=9.6/3 M9 M3 M4
W/L=90/3
M5
W/L=45/3
W/L=45/3

VSS

Figure.2.24: The CMOS operational amplifier as a unity gain amplifier (unity follower).

48
 STORAGE UNITY-GAIN
TG SWITCH BUFFER
CAPACITOR

Mp -
SOFT NODE
A= 1
+
+ Vo
+
Mn CH -
VH

VCONTROL -

Figure 2.25: Schematic diagram of a sample-and-hold amplifier.

49
2.3.8 The Transmission Gate Switch

The input switch to the S/H amplifier is controlled by a digital signal generated

from an external control and synchronizing logic to represent the two modes of operation

- the sample and hold. The switch should ideally offer zero resistance to the signal when

it is closed (sample) and infinite resistance when open (hold). Moreover, when closed, it

should exhibit the same properties irrespective of whether the capacitor is charging or

discharging. An ideal switch also takes zero time to turn on or off. A CMOS transmission

gate switch (TG-switch) is constructed by paralleling an n-MOS transistor with a p-MOS

transistor. The transmission gate switch can be made to turn ON or OFF for either

polarity of the mode control signal by connecting a simple inverter between the gates of

the transistors. Since the transmission gate has both an n-type and a p-type devices,

connected in parallel, there is no degradation of the signal whether it is large or small.

The expression for the charging time constant through a CMOS transistor gate can be

expressed as [32]

1
τn = CH [ + Req] (2.26)
βn (VDD − Vtn)

and the discharging time constant as [32]

1
τp = CH [ + Req] (2.27)
βp (VDD − Vtp )

where CH is the hold capacitor. The term Req represents the equivalent resistance of the

transmission gate which remains a constant during charging and discharging. From the

above two equations, if the threshold voltages of the n-MOS and p-MOS transistors are

made equal and the aspect ratios of them are so adjusted such that βn = βp, the time to

charge and discharge through the transmission gate would be equal, thus giving

50
symmetrical response. Since the transition from ON to OFF and vice versa is much faster

now with the use of a transmission gate switch, two important terminologies with

reference to S/H amplifiers are defined. Acquisition Time is the time required by the

output of the S/H to reach its final value, within a specified error band, after the sample

command has been given. Aperture (Delay) Time is the time required for the switch to

open fully after the hold command is given. The held voltage is, in effect delayed by this

interval and the hold command should therefore be advanced by this amount for precise

timing. Needless to say, both these times are reduced significantly by the use of a

transmission gate switch rather than a pass gate.

2.3.9 The Storage Capacitor

The storage capacitor limits the slew rate in the sample mode and determines the

‘droop’ in the hold mode of operation. The slew rate is the rate at which the voltage

across the capacitor can change with respect to time and is entirely a function of the input

signal frequency. The equivalent circuit of the S/H amplifier during sample is that of a

low-pass filter with the series resistance of the filter consisting of the TG-switch

resistance when closed, and the storage capacitor CH . For the voltage of the capacitor to

follow the input signal fairly well, the RC time constant of the filter should be close to the

time period of the input signal. The value of the storage capacitor to be used is therefore a

function of the input signal frequency. The other consideration for the value of the

storage capacitor is the droop rate. ‘Droop’ is the gradual drop in the ‘held’ voltage by

the capacitor with time, during the hold period. Obviously, this introduces errors in the

digital-to-analog conversion process, as the voltage level at any time after the instant it

was sampled would be different from the level at which it was sampled.

51
 The storage capacitor CH was implemented using the Poly1 and Poly2 layers in

standard CMOS process. The parallel plate capacitance used in the design is 12 pF.

Figure 2.26 shows the S/H CMOS circuit. The layout of the sample-and-hold CMOS

circuit of Fig 2.26 is shown in Fig. 2.27. The post-layout SPICE simulations were

performed. Figure 2.28 shows the post-layout simulated sample and hold response of the

circuit of Fig 2.26. The input to the circuit is a 4V p-p sine wave and the control voltage

given to the circuit is 5V p-p pulse. When the pulse is HIGH, the circuit samples the

input and when the pulse is LOW, the circuit holds its previous state. A microvolt signal

was applied to the input of the OPAMP and a control signal Vcontrol was applied to the

sample-and-hold circuit as shown in Fig. 2.29. The amplified signal from the OPAMP

was reproduced by the unity follower with a total offset of about 33µV. Figure 2.30

shows the circuit behavior of the circuit of Fig. 2.29 obtained from post-layout

simulations.

2.4 10-bit Digital to Analog Converter

Figure 2.31 shows the layout of a 10-bit DAC. The 10-bit charge scaling DAC is

tested by giving various combinations of digital input words and the respective analog

output voltage is obtained. The referenve voltage used in the design is 2.0V. The 10-bit

charge scaling DAC has about 1024 digital word combinations and is quantized within

the reference voltage of 2.0V with a step of 1.9mV. This is obtained as follows

Total number of input combinations = 1024 (since it is 210 combinations of input)

The reference voltage used is 2V. The least significant change in the output value is

2
LSB = = 1.9mV. (2.28)
1024

52
Figure. 2.32(a) and (b) show the DAC output characteristics, for all combinations of the

digital input word starting from ‘0000000000’ to all ‘1111111111’s.

53
 STORAGE
TG SWITCH
CAPACITOR UNITY GAIN BUFFER

VDD

M8 M7
W/LN=4.5/1.6
W/L=45/3 W/L=90/3
W/L P =4.5/1.6 W/L=90/3
M6

W/L =4.5/1.6

Mp W/L=90/3 W/L=90/3

54
CC =30FF
+ -V M1 M2 Vout
Input of S/H Mn CH in
W/L =4.5/1.6 M9 M3 M4
VH W/L=9.6/3
W/L=90/3
M5
W/L=45/3
- W/L=45/3
(VCONTROL)

VS S

Figure 2.26: Sample-and-hold CMOS circuit

 VINPUT

VO UT VCO NTRO L

Figure.2.27: Layout of a CMOS sample-and-hold circuit (S/H) circuit.

55
2.0V

0V

-2.0V
V(Input)
4.0V

0V Sample period Hold period

-4.0V
V1(Vcontrol)
4.0V

0V

-4.0V
0s 50us 100us 150us 200us 250us 300us 350us 400us
V(Output)
Time

Figure 2.28: Sample-and-hold circuit response.

Note: Sample and hold period are as shown in figure.

56
 OPERATIONAL AMPLIFIER STORAGE UNITY GAIN BUFFER
TG SWITCH
VDD CAPACITOR VDD

M8 M7 M8 M7
W/L=45/3 W/L=45/3
W/L=90/3 W/L=90/3
W/L=90/3
M6 W/L=90/3
M6
+ Vin

W/L=90/3 W/L=90/3 Mp
- Vin CC =30FF W/L=90/3 W/L=90/3
M1 M2 CC =30FF
+ - Vin M1 M2 Vout
M9 M3 M4 Mn CH
W/L=9.6/3 W/L=90/3
M5 VH W/L=9.6/3 M9 M3 M4

57
W/L=45/3 W/L=90/3
W/L=45/3 M5
W/L=45/3
- W/L=45/3
VSS (VCONTROL)

VSS

Figure 2.29: Schematic block diagram showing op-amp, TG-switch, storage capacitor and unity gain buffer.
 2.0V

0V

-2.0V
I/P of OPAMP
2.0V

0V

-2.0V
O/P of OPAMP
4.0V

0V Sample period Hold period

-4.0V
V1(Vcontrol)
4.0V

0V

-4.0V
0s 50us 100us 150us 200us 250us 300us 350us 400us
V(Output)
Time

Figure 2.30: Sample-and-hold response of the circuit of Fig. 2.26 obtained from post-
layout SPICE simulations.
Note. Input signal peak-to-peak voltage is 4V.

58
Multiplexer

Op-amp Capacitor - Array

Storage capacitor (CH)

Unity gain buffer

TG - Switch

Figure 2.31: Layout of a 10-bit charge-scaling DAC.

59
 2

1.5

0.5

0
0 1000 2000 3000 4000 5000 6000
Time(us)

(a)

DAC output characteristics

Analog Output Voltage

2.5
2
1.5
1
0.5
0
0 256 512 768 1024
Digital Input Code

(b)
Figure.2.32 DAC output response for all (0000000000 – 1111111111) combinations of
the input digital word.

60
Chapter 3

Built-in Current Sensor Design

This chapter focuses on IDDQ testing using built-in current sensors (BICS), the

design and implementation of the BICS in a 10-bit charge scaling DAC, the fault

simulation and detection methodology. It also discusses previously proposed schemes for

IDDQ testing and the important physical faults commonly seen in the design of integrated

circuits. Simulations and design considerations for the BICS are also discussed.

3.1 Current Testing in CMOS Integrated Circuits Using BICS

IDDQ testing of CMOS ICs is shown very efficient for improving test quality. The test

methodology based on the observation of quiescent current on power supply lines allows

a good coverage of physical defects such as gate oxide shorts, floating gates and bridging

faults, which are not very well modeled by the classic fault models, or undetectable by

conventional logic tests [1]. In addition, IDDQ testing can be used as a reliability predictor

due to its ability to detect defects that do not yet involve faulty circuit behavior, but could

be transformed into functional failures at an early stage of circuit life. Due to obvious

quality and reliability improvements, this approach became powerful complement to the

conventional logic testing. Quiescent current monitoring is considered as an interesting

and efficient technique for mixed-signal testing, where fault detection of analog parts

requires the precise measure of the IDDQ. In analog circuits, the quiescent current, termed

as IPS, may in the order of µAs or even mAs. Under fault conditions, the normal values of

IPS may be increased or decreased or generally distorted. Thus, fault detection can be

accomplished by monitoring the IPS current fluctuations. Figure 3.1 shows the fault free

IDDQ current in the quiescent state, which is about 1mA and shooting to 3mA when fault

61
is injected in the CUT [19]. Elevated IDDQ does not necessarily result in nonfunctional

behavior. However, data are available confirming that IDDQ failures will result in

reliability problems [33]. Considerable impact can be made towards achieving higher

quality by incorporating IDDQ testing along with conventional logic testing.

Built-in current sensors (BICS) have speed and resolution enhancements over

off-chip current sensors, mainly because the large transient currents in the output drivers

are by-passed and less parasitic are encountered. On chip current testing is both time-

efficient and sensitive. Moreover, on-chip current tests can also be used as an on-line

testing tool, and is important when components are to be used in high reliability systems.

For high speed and high sensitivity, unaffected by large pad currents, a fast built-in

current testing circuit is desired [34]. In the present work, a simple design of a built-in

current sensor is presented to detect bridging faults in a 10-bit charge scaling DAC. A

novel method has been introduced for the fault injection to simulate physical defects

present in a chip.

3.2 IDDQ Hardware

IDDQ measurements require analog circuitry that can ideally measure current

below 1 µA in the range 10 KHz- 33 MHz [35]. Different methodologies exist for IDDQ

testing. IDDQ testing can be classified in two groups, 1) external IDDQ testing and 2)

internal IDDQ testing. External IDDQ testing monitors power supply current through the

power pins of the integrated circuit package while internal IDDQ testing monitors power

supply current built-in current sensors [36].

62
+ 2.5v
VERROR - SIGNAL

-2.5v

1mA
IREF

3mA IDEF

IDDQ
1mA
10US 20US 30US 40US 50US 60US 70US 80US
Time

Figure 3.1: Faulty (IDEF) and fault-free (IREF) IDDQ current.

Note: IREF is same as IDDQ. IDEF is the current in presence of faults. VERROR is the
signal output.

63
3.2.1 External IDDQ Testing

The simplest form of hardware for testing is the automatic testing equipment

(ATE) precision measurement unit. It can be connected to the CUT’s power pin and used

to measure IDDQ. This strategy is acceptable if the number of measurements is less than

20; otherwise test time becomes expensive [1]. Figure 3.2 shows off-chip instrumentation

schematic. Figure 3.2 (a) illustrates an approach for an off-chip IDDQ instrumentation

[33]. The tester is connected in series with the VDD line of the CUT. CDD is the total

capacitance at the VDD node and includes that due to the IC itself and any capacitance

added by the tester and instrumentation circuit. The tester measures dVo/dt during the

quiescent time and can estimate IDDQ if CDD is known using [1].

IDDQ = CDD dVO/dt (3.1)

Figure 3.2 (b) shows another schematic for off-chip IDDQ current measurement [35]. An

off-chip sensor monitoring the power supply current is a simple implementation of IDDQ

testing and widely used in production testing. The transistor Q1 is ON only during

transient when the CUT is drawing large currents. To filter the high impedance noise at

high frequencies, a small capacitor C1 in the range of 2-2.5nF is added in between the

sense circuit and the CUT [37]. Once transients are settled, the Q1 is OFF and capacitor

C1 supplies the static current to the CUT. IDDQ is measured by the voltage drop across the

transistor Q1.

Off-chip current measurement technique has the ability to detect vast majority of

manufacturing defects, including those that are not detected by the traditional stuck-at

fault testing [34]. However, off-chip measurement techniques have speed and sensitivity

64
 V0
TESTER

VDD IDD

1pF
CUT
CDD

.
Figure 3.2 (a): Off-chip IDDQ current measurement using an automatic test equipment.

n-MOS

Sense Circuit

To power
CUT Q1 supply
C1
C1

To
sample &
hold

Figure 3.2(b): Off-chip IDDQ current measurement.

65
limitations [38]. Low-current resolution is critical in detecting defects such as floating

gates, which do not cause large abnormal currents. Off-chip measurements may not

detect this small current due to its sensitivity limitations. Several other factors can

degrade off-chip IDDQ instrumentation. 1) All testers have current probes, which offer

significant capacitive loading at the power supply, causing a large voltage drop across it,

and lack in DC accuracy [1,20]. 2) The test board exists in a noisy electrical environment

and long leads are used and electromagnetic fields are high [35]. Current measurement is

slow and susceptible to static noise in the power supply bus. Considerable noise is

therefore introduced into the measurement. 3) Above all, the major portion of the IDDQ

current in CMOS VLSI chips is generated at the output pad circuits, and abnormal IDDQ

current is overshadowed by the output currents [36]. Owing to these limitations with off-

chip current measurements, the built-in current sensor is a preferred approach in many

applications. It can be integrated in to the CMOS design to test for physical faults in the

circuit.

3.2.2 Internal IDDQ Testing

The effectiveness of IDDQ testing can be enhanced if built-in current sensors are

applied on chip to monitor defect –related abnormal currents in the power supply buses

[34]. This testing technique applies on-chip current sensors that detect abnormal power

bus currents and overcomes the limitations of the off-chip IDDQ current measurements.

Essentially, this technique adds a BIC sensor in series with VDD or GND lines of the

circuit under test. A series of input stimuli is applied to the device under test while

monitoring the current of the power supply (VDD) or ground (GND) terminals in the

quiescent state conditions after the inputs have changed and prior to the next input change

66
[35]. Figure 3.3 shows the block diagram of the IDDQ testing with BICS. The many

advantages of BICS over the off-chip current testing or the ATE, include: reduction of

test equipment cost, increase of testing rate, improvement of the detectability and high

current sensing resolution [38].

Typically, sub-threshold current in the transistors, which are ‘off’ in a CMOS

static circuit should be negligibly small. However, in some cases, due to charge presence

in a gate oxide or latch-up, the sub-threshold current may be large enough to become an

essential component of IDDQ . The BICS can be designed to detect this current also.

3.3 Physical Faults in CMOS Integrated Circuits

In CMOS technology, the most commonly observed physical failures are bridges,

opens, stuck-at-faults and gate oxide shorts (GOS). These defects create indeterminate

logic levels at the defect site [1]. Very large-scale integrated circuits processing defects

cause shorts or break in one or more of the different conductive levels of the device [36].

We briefly discuss these physical defects that cause an increase in the quiescent current.

3.3.1 Open Faults

Figure 3.4 shows a 2-input NAND open circuit defect. Logic gate inputs that are

unconnected or floating inputs are usually in high impedance or floating node-state and

cause elevated IDDQ [34]. In Fig. 3.4, node VN is in the floating node-state. For an open

defect, a floating gate may assume a voltage because of parasitic capacitances and cause

the transistor to be partially conducting [37]. Hence, a single floating gate may not cause

a logical malfunction. It may cause only additional circuit delay and abnormal bus current

[34]. In Fig. 3.4, when the node voltage (VN), reaches a steady state value, then the output

voltage correspondingly exhibits a logically stuck behavior and this output value can be

67
 PMOS
BLOCK

INPUTS

OUTPUT

NMOS
CUT BLOCK

PASS/FAIL

BICS

Figure 3.3: Block diagram of IDDQ testing.

68
 VDD

VA
Q1 Q2

V0

Q3

VN

Q4

Figure 3.4: Open circuit defect.

69
weak or strong logic voltage. Open faults, however, may cause only a small rise in IDDQ

current, which the off-chip current sensor may not detect because of its low-resolution

[1]. It can be detected using BIC sensors. An open source or open drain terminal in a

transistor may also cause additional power-bus current for certain input states. In this

scope of work, we deal with bridging faults.

3.3.2 Bridging Faults

The short circuit faults in very large-scale integrated circuits are popularly termed

as bridging faults. When IDDQ measurements are used, a bridge is detected if the two nets,

which compromise it, have opposite logic values in the fault-free circuit [37] and are

connected by a bridge due to the introduction of the fault in the circuit. Bridging faults

can appear either at the logical output of a gate or at the transistor nodes internal to a

gate. Inter-gate bridges between the outputs of independent logic gates can also occur.

Bridging fault could be between the following nodes 1) drain and source, 2) drain and

gate, 3) source and gate, and 4) bulk and gate. Examples of bridging fault are shown in

Figs. 3.5 and 3.6, respectively. Figure 3.5 shows example of possible drain to source

bridging faults in an inverter chain in the form of low resistance bridges (R1, R2 and R4).

Resistance bridge, R3 is an example of inter-gate bridge. Figure 3.6 shows examples of

gate to source and gate to drain bridges in an NAND gate circuit.

Bridging faults can be modeled between adjacent metal lines in a 10-bit

charge scaling DAC at different conducting levels. We have introduced faults in the 10-

bit charge scaling DAC by using “fault-injection transistors” instead of hard metal shorts

invented in our group [19]. The introduction of a fault via the “fault-injection”

70
 VDD

R3 R4

R1
V1 Vo

R2

VS S
Path from VDD to ground

Figure 3.5: Drain-source and inner-gate bridging faults in an inverter chain.

71
 VDD

V0
VA

Bridge 1: Drain-gate

VB

Bridge 2 : Gate-source

Figure 3.6: Bridging defect.

72
transistor enables the 10-bit DAC to function fault-free under the normal conditions. The

faults considered include source-drain bridge, drain-gate bridge and source-gate bridge.

Bridging defect cannot be modeled by the stuck-at model approach, since a bridge often

does not behave as a permanent stuck node to a logic value [37]. IDDQ testing using BICS

is an effective method of detecting bridging shorts.

3.3.3 Gate-Oxide Short Defects

Gate-oxide short (GOS) defects occur frequently in CMOS technology. The

principle physical reasons for GOS are the breakdown of the gate oxide and the

manufacturing spot defects in lithography and processes on the active area and

polysilicon masks [38]. Figure 3.7 illustrates the circuit level gate oxide short defect

model [37]. These defects can be seen as short-circuits between the gate electrode and the

conducting channel of the device through SiO2 . GOS short causes an undesirable current

injection in to the channel [36, 38]. This current injection forces a substantial increase in

the quiescent current. The diode-resistor combination could be used to model the

rectifying behavior of the new current path introduced by the defect [38].

These defects are unlikely to produce logical errors, but cause important deviation

of parametric specification especially important in low power equipment [39].

3.4 Definition and Description of IDDQ of a Faulty Circuit

IDDQ’s definition is the level of power supply current in a CMOS circuit when all

the nodes are in a quiescent state. Static CMOS circuits use very little power and at stand-

by or quiescent state, it draws practically negligible leakage current [35]. In steady state,

there should not be a current path between VDD and GND path. Ideally, in a static CMOS

circuit, quiescent current should be zero except for associated p-n junction leakage

73
 Gate
Source Drain

n+ n+

p - Si

(a)

S D

Rs

(b)

Figure 3.7(a): Gate-oxide-short (GOS) in a MOSFET.

Figure 3.7(b). Equivalent circuit model. RS is the effective resistance of the short. B
models the rectifying behavior of new current path introduced by the defect.

74
currents. Any abnormal elevation of current should indicate presence of defects. To

assure low stand-by power consumption, many CMOS integrated circuit manufacturers

include IDDQ testing with other traditional DC parametric tests [36].

3.4.1 Description of IDDQ of a Faulty Inverter

Figure 3.8 shows how an IDDQ test can identify defects. The current in static

CMOS is not constant during transient [40]. When an output transition occurs, a peak of

IDDQ current is observed. This peak is due to charging and discharging of the load

capacitance at the output circuit and corresponds to the short circuit. When the transition

is completed, the circuit is in the quiescent state. IDDQ is very sensitive to physical faults

in the circuit. In mixed-signal CMOS circuits such as data converters. IDDQ is around

1mA, which increases in presence of defects.

Let us evaluate current testing in CMOS circuits in the presence of bridging

faults. Two nodes connected by a bridge must be driven to opposite logic levels under

fault-free conditions for bridging fault to occur. In Fig.3.8, a typical bridge is one

between the node VO and VDD. To detect this defect, input pattern must drive the node

VO1 to the logic low value (‘0’), as this node is assumed to be bridged with the power rail.

Thus, a path from power to ground appears allowing the existence of an abnormal high

IDDQ current. IDDQ value is directly dependent on the resistance offered by the conducting

path and hence on the size of the transistors in the conducting path. The presence of the

physical fault causing the high abnormal current can be effectively detected by IDDQ

testing using BICS. A set of realistic bridges have been modeled between adjacent

metal lines in a 10-bit charge scaling DAC at three different (conducting levels), to

75
 VDD

(IDDQ RB ), V

RB

V1 V01 V02

Path from VDD to ground VSS

Figure 3.8: Bridging fault causing IDDQRB drop and a path to the ground.

76
examine the effect on the value of IDDQ and detect the presence of the fault using the

BICS.

3.5 The Design Considerations of BICS

A simple design of a BIC sensor built into the 10-bit charge scaling DAC is

presented using the current mode design. It determines whether the circuit quiescent

current is below or above a threshold level. Previously proposed schemes and the

characteristics required for a good BICS are discussed briefly in this section.

3.5.1 Previously Proposed Schemes

Different BICS schemes have been proposed for detection of the abnormal IDDQ

current and the physical faults commonly observed. While most BICS designs

concentrate on mere detection of the fault, some can detect the location of the fault as

well [41]. The entire design is divided into n sub blocks (SB) where n equals the number

of outputs. The divided SB’s are checked individually through their corresponding output

and a faulty area is easily detected by observing the outputs. The performance impact of a

BICS on a circuit under test (CUT) is the key issue to be considered when designing

BICS. Insertion of the BIC sensor between CUT and GND involves series voltages, and

these voltages could degrade the performance of the CUT [40,11]. A large number of

earlier BICS are based on voltage amplifiers such as differential amplifiers or sense

amplifiers. The stability of the BICS is limited in this case since the quiescent point (Q-

point) of an amplifier may not be stable and can vary with the change of dc supply

voltage, VDD. The detection time and hardware overhead is increased due to the extra

hardware required to stabilize the Q-point.

77
 To overcome problems of slow detecting time, resolution, instability of the BICS

and large impact on the CUT performance, the current-mode circuit design approach has

been adopted using a single power supply. In this work, simple design of a BICS

employing current mirrors and current differential amplifier has been proposed. It has

minimum area over head in the chip and no impact on over all performance.

Characteristics required for a good BIC sensor are [39]:

1. Detection of abnormal static and dynamic characteristics of the CUT.

2. Minimal disturbance of the static and dynamic characteristics of the CUT.

3. The design should be simple and compact to minimize the additional area

necessary to build it.

4. The IDDQ test should have good resolution and speed.

3.5.2 The Design of the BICS

Figure 3.9 shows the CMOS circuit diagram of the built-in current sensor. It

consists of a current differential amplifier (M2, M3), two current mirror pairs (M1, M2 and

M3, M4) and an inverter. The n-MOS current mirror (M1, M2) is used to mirror the current

from the constant current source which is used as the reference current IREF for the BICS.

The current mirror (M3, M4) is used to mirror the difference current (IDEF-IREF) to the

current inverter, which acts as a current comparator. The differential pair (M2, M3)

calculates the difference current between the reference current IREF and the defective

current IDEF from the CUT. The W/L size of the n-MOS current mirrors (M1, M2) is set to

27/1.6 and (M3, M4) is set to 72/1.6. Therefore ID3 = IDEF-IREF. The constant reference

current is set to approximately the same value as the quiescent state current when the

78
 VDD

VDD

18/1.6 VDD
M5 CUT
6/1.6
M6 VDD
VSS
I DEF
I REF EXT VSS 150/1.6
IDEF - IREF OUTPUT
I REF
27/1.6 ( PASS/ FAIL )
27/1.6
60/1.6 25/1.6
M2 M3
M0 M1 M4
72/1.6
72/1.6
VENABLE VSS

VSS

Figure 3.9: CMOS built-in current sensor circuit.

79
CUT is fault free. In the present design, the reference current, IREF is set to 1mA. The

output inverter buffer has an aspect ratio ((W/L)P / (W/L)N) of 6/1 to counter capacitive

parasitics at the output node and detect the presence of the physical fault through the

PASS/FAIL flag at the output.

The proposed scheme operates in two modes: the normal mode and the test mode.

The mode of operation is controlled by ‘VENABLE’ signal applied to the gate of transistor

M0. The W/L size of the M0 is 60/1.6. This enables the 10-bit charge scaling DAC, which

is the CUT to operate as fault-free in the normal mode of operation. Further explanation

on the design is provided in section 3.6.

3.6 The Implementation of BICS

Figure 3.10 explains the basic structure of the BIC sensor connected between

CUT and GND in IDDQ testing. The BICS is inserted in series with GND or VSS line of

the circuit under test. The proposed BICS works in two modes: the normal mode and the

test mode. The mode of operation is decided by the VENABLE signal. In the normal mode

(VENABLE = ‘1’), the BICS is isolated from the CUT. In the test mode (VENABLE = ‘0’), the

quiescent current from the CUT is diverted in to the BICS and compared with reference

current to detect the presence of the fault.

3.6.1 BICS in Normal Mode

During the normal operation, the signal ‘VENABLE’ is at logic ‘1’ and all the IDD

current flows to ground through M0 (control transistor). When switching occurs, M0 is

turned on. Therefore, the n-MOS current mirrors have no effect on dynamic current. It

follows that the BICS’s output is not affected by the dynamic current. Thus, in the normal

mode, the BICS is totally isolated from the 10-bit DAC (CUT). Since in normal mode the

80
 VDD

PMOS CUT
BLOCK
VIN
Output

NMOS
BLOCK
VDD

18/1.6 VDD
M5

M 6 6/1.6
VSS
IDEF
IREF EXT OUTPUT
VSS
IDEF - IREF PASS/FAIL
IREF
27/1.6
72/1.6 150/25
60/1.6
27/1.6 M 2 M3
M0 M1 M4
72/1.6
VENABLE

VSS

Figure.3.10: CMOS built-in current sensor with CUT.

81
current coming from the CUT is same as the reference current the difference current IDEF

– IREF becomes negligible and the output of the BICS is at logic ‘0’. In the normal mode,

it cannot detect the presence of any physical fault in the CUT.

Since the BICS is inserted in series with GND line of the CUT, it causes a voltage

drop and large capacitance between the CUT and the substrate. These effects cause

performance degradation and ground level shift. To reduce these extra undesirable

effects, an extra pin EXT is added to the proposed BICS. Pin EXT is connected to the

drain of transistor M0. In the test mode, it is left floating. In the normal mode, EXT gets

connected to logic ‘0’. In the normal mode, since the EXT pin is grounded by passing the

BICS, the disturbance of the ground level shift during normal operation of the circuit

never happens. Therefore, there is no impact on the performance of the DAC, while the

BICS is in normal mode.

3.6.2 BICS in Test Mode

During the test mode, the ‘VENABLE’ signal is at logic ‘0’. The IDDQ current from

the CUT is diverted by the BICS and the n-MOS current mirror pair replicates the

reference current to the current differential amplifier which assigned a value nearly same

as the fault-free current. This mirrored reference current is compared with defective

current IDEF current coming from the CUT. The output of the current comparator, which

is in the form of PASS/FAIL, will detect the presence of the fault.

The difference current is converted to a voltage by mirroring it and getting the

drop of VDS across the transistor M4. In the test mode, the difference current is large

which turns-ON M4 heavily and forces its output node pulled-down to logic ‘0’ and is

detected as PASS/FAIL output ‘1’, indicating presence of defects in CUT. In the testing

82
mode, EXT pin is floating. The ‘VENABLE’ signal is connected to GND and M0 is off. The

timing diagram and detailed analysis of BICS are explained in the following sections.

3.6.3 Detailed Analysis of the BICS

The current differential amplifier and the current mirror are most important parts

of the proposed BICS. Performance of the current mirror greatly affects the BICS’s

ability to detect abnormal current due to physical defects. The current mirror has a

property that, in a constant current stage, the reference current in one branch of the circuit

is mirrored in the other branch [22]. The current differential amplifier on the other hand

receives reference current IREF one input, and the defective current IDEF from CUT as the

other input. The differential amplifier calculates the difference between the two currents.

The other n-MOS current mirror mirrors the difference current calculated by the current

differential amplifier to the inverter (M4, M6) which acts as comparator (Fig.3.10). The

output of the current comparator is used as the PASS/FAIL flag. If the IDDQ is greater

than the reference current, we presume there are defects within the functional circuit. If

the IDEF is less than the IREF, we assume that the functional circuit is free from physical

defects that induce abnormal IDDQ current. Functionally, in inverter, ID = IREF – IDEF. If

IDEF > IREF, then the PASS/FAIL output shows a logic ‘1’. Conversely if IDEF < IREF, a

logic ‘0’ will appear at the PASS/FAIL output. Input impedance of the inverter is very

large [23]. Because of the high input impedance of the current comparator and the

utilization of the current mirror along with current differential amplifier, even a very

small difference between IDEF and IREF can be distinguished. That means the BICS can

achieve a high resolution. Several SPICE simulations were performed to determine the

functionality and performance of the BICS design.

83
3.7 Layout, Simulation and Timing Diagrams for BICS

3.7.1 Current Mirror Circuit

The simplest form of constant current source consists of current mirrors

constructed by passing a reference current through a diode-connected (gate tied to drain)

transistor as shown in Fig. 3.11. The voltage developed across the diode-connected

transistor provides the constant current output. The current ratio IOUT / IREF is determined

by the aspect ratio of the transistors in the current mirror circuit design. Both n-MOS

transistors have the same W/L ratio of 27/1.6. The output current of the current mirror

circuit mirrors the input current to it. Therefore,

IOUT / IREF = 1 (22)

In our design,

IOUT = IREF =1mA.

3.7.2 Current Differential Amplifier

The current differential amplifier used in our design is the most important part of

the BICS. The current differential amplifier calculates the difference between the

reference current IREF and defective current IDEF. Figure 3.12 shows the circuit diagram of

differential amplifier. The currents IREF (i1) and IDEF (i2) are the input currents of the

amplifier. The difference current (IDEF – IREF or i2 – i1) is calculated and mirrored to

output of the current differential amplifier. The BICS design comprises of two n-MOS.

current mirrors and a current differential amplifier. One n-MOS current mirror provides

the reference current as one input to the differential amplifier and the other input current

comes from the CUT. The other n-MOS current mirror replicates the difference current to

84
 IREF
IOUT

M1 M2

Figure 3.11: n-MOS current mirror circuit.

85
 VDD

i2
i1 i1 i2 - i1 i2 - i1

M1
M2 M3 i2 - i1
27/1.6 M4
27/1.6
72/1.6

72/1.6

VSS

Figure 3.12: Schematic of a current differential amplifier.

86
the output inverter which acts as a current comparator. The proper design of the current

mirrors is most crucial for working of the BICS. The input impedance of the current

differential amplifier is simply the small-signal resistance of a diode connected

MOSFET, and is given by

Rin = 1/ gm. (23)

The current differential amplifier finds applications in both low-power and high-speed

circuit design.

3.7.3 BICS

Figure 3.9 shows the circuit diagram of the BICS. It comprises of two current

differential amplifiers and a current comparator. It operates in two modes: 1) normal

mode and 2) test mode. The test signal is applied to an n-MOS transistor, M0 (W/L =

60/1.6), which decides the mode of operation. When the test signal is ‘0’, the BICS is in

the test mode. When the test signal is at logic ‘1’, the BICS is isolated from the CUT and

its output is at logic ‘0’. The output inverter buffer has an aspect ratio ((W/L)P/(W/L)N) of

6/1. Figure 3.13 shows the layout of the BICS of the circuit shown in the Fig. 3.9.

3.8 Fault Detection, Simulation and Testing

The primary reason for a fault is a defect in the integrated circuit. A manufacturing defect

causes unacceptable discrepancy between its expected performance at circuit design and

actual IC performance after physical realization [34]. A defect may be any spot of

missing or extra material that may occur in any integrated circuit layer.

Two nodes are connected if there is at least one path of conducting transistors

87
 IREF IDEF

VSS

BICS
O/P
VENABLE
VDD
EXT

Figure 3.13: Layout of a built-in current sensor circuit.

88
between them. If the two nodes are at opposite potentials under fault-free conditions, a

conducting path between them will increase the IDDQ current due to fault in the circuit.

After transient switching, each node in a digital circuit is one of the following four states

1. VDD state: This state occurs when the node is connected to VDD.

2. GND state: This state occurs when the node is connected to GND.

3. Z state: The high-impedance state occurs when the node is neither VDD nor GND

connected.

4. X state: This state occurs when the node is both VDD-connected and GND-connected

[34].

The ‘X’ state should never occur in fault-free CMOS integrated circuits. Many

defects cause an X state to occur in CMOS integrated circuits. Thus, we can view testing

as a way to detect the X state, which causes detectable abnormal steady state current.

Bridging faults have been induced in the DAC at various conducting levels using a fault-

injection transistor (FIT), discussed further ahead, which cause abnormal elevation of the

steady state current.

3.8.1 Fault-Injection Transistor

In this work, four bridging faults have been placed in the 10-bit DAC design using fault-

injection n-MOS transistors. Activating the fault-injection transistor activates the fault.

The use of a fault-injection transistor for the fault simulation prevents permanent damage

to the 10-bit DAC by introduction of a physical metal short. This enables the operation of

the DAC without any performance degradation in the normal mode. Figure 3.14 (a)

shows the fault-injection transistor. To create an internal bridging fault, the fault-injection

transistor is connected to opposite potentials. When the gate of fault-injection transistor

89
ME) is connected to VDD, a low resistance path is created between its drain and source

nodes and a path from VDD to GND is formed. In the Fig. 3.14(b), an internal bridging

fault is created in the CMOS inverter between the drain and source nodes using the fault-

injection transistor. Logic ‘0’ is applied at the input of the inverter. Therefore, the output

of the inverter is at logic ‘1’ or VDD. When the logic ‘1’ is applied to the gate (VE) of the

n-MOS fault-injection transistor (ME), it turns on. This causes a low resistance path

between the output of the inverter and the VSS. This gives rise to an excessive IDDQ

current as a path from VDD to GND is created, which can be detected by the BICS.

Figure 3.15 shows the layout of a 10-bit charge scaling DAC with BICS. The area

of the DAC alone is 692 × 502 µm2. The entire area of the CUT along with BICS is 692 ×

516 µm2. Therefore the BICS occupies only 242 × 40 µm2 of the entire chip area. Four

defects have been introduced using fault-injection transistors. The n-MOS fault-injection

transistor (ME) is designed for W/L equal to 4.5/1.6. The fault-injection transistors are

activated externally using ERROR signals VE1, VE2, VE3 and VE4, respectively. Error

signal VE1 is applied to the gate of the fault-injection transistor in defect 1, which forms a

short between the source and drain in the operational amplifier circuit shown in Fig. 3.16.

Error signal VE2 is applied to the gate of the fault-injection transistor in defect 2, which

forms a short between the drain and gate in the unity gain buffer circuit shown in Fig.

3.17 for S/H. Error signal VE3 is applied to the gate of the fault-injection transistor in

defect 3, which forms a short between the gate and the source in the multiplexer circuit

shown in Fig. 3.18. Error signal VE4 is applied to the gate of the fault-injection transistor

in defect 4, which forms a short between the gate and the substrate in the multiplexer

circuit shown in Fig. 3.19.

90
 VE
G

ME
D S
(4.5/1.6)

Figure 3.14 (a): Fault-injection transistor (FIT).

VDD

VI V0
D

(4.5/1.6)
ME VE
G

VSS FIT

Figure. 3.14 (b) Fault-injection transistor between drain and source nodes of a CMOS
inverter.

91
 Defect 4
Defect 3

Defect 1

Defect 2

Figure 3.15: Layout of a 10-bit DAC with BICS showing the defects induced in the CUT
using fault-injection transistors.

92
 VDD

M8 M7
W/L=45/3 W/L=90/3
W/L=90/3
M6

+ Vin
W/L=90/3 W/L=90/3
- Vin CC =30FF
M1 M2 Vout
W/L=4.5/1.6 W/L=9.6/3
M9 M3 M4
VE1 W/L=90/3
M5
W/L=45/3
W/L=45/3

VSS

Fault-Injection Transistor (S-D)

Figure.3.16: CMOS operational amplifier circuit with defect 1 introduced using a FIT.

93
 VDD
M8 M7
W/L=45/3 W/L=90/3
W/L=90/3
M6

+ Vin

W/L=90/3 W/L=90/3
CC =30FF
M1 M2 VOUT
VE2

M9 M3 M4
W/L=9.6/3 W/L=4.5/1.6 W/L=90/3
M5
W/L=45/3
W/L=45/3

VSS
Fault-Injection Transistor (S-D)

Figure 3.17: CMOS unity gain buffer circuit for S/H with defect 2 introduced
using a FIT.

94
 Output of Multiplexer

VE3

VREF
Control Signal

Fault Injection Transistor (G-S)

Figure 3.18: CMOS MUX circuit with defect 3 introduced using a FIT.

95
 Output of Multiplexer

W/L= 4.5/1.6

VE4

VREF

Control Signal

Fault Injection Transistor (S-Sub)

Figure 3.19: CMOS MUX circuit with defect 4 introduced using a FIT.

96
Chapter 4

Theoretical and Experimental Results

This Chapter discusses theoretical results obtained from post-layout PSPICE

(MicroSim Pspice A/D Simulator, V.8) simulations on IDDQ testing of a 10-bit charge

scaling DAC. SPICE level 3 MOS model parameters were used in simulation [42], which

are summarized in Appendix A. The chip was designed using L-EDIT, V.8.03 in standard

1.5µm n-well CMOS technology. The chip occupies an area of 692 µm × 516 µm and

includes 240 µm × 40 µm area of BICS. DAC design was put in 2.25 mm × 2.25mm

size, 40-pin pad frame for fabrication and testing. In the following sections, theoretical

results (simulated from PSPICE) and experimentally measured values will be presented

and discussed. HP 1660CS logic analyzer was used for testing the packaged device

described in Appendix B.

4.1 Simulation Results

Figure 4.1 shows the layout of a 10-bit charge scaling digital-to-analog converter

with four fault injection transistors distributed across the chip. FIT-1 is injected in the

operational amplifier part of the chip. FIT-2 is injected in S/H circuit of the chip. FIT-3

and FIT-4 are injected in the multiplexer parts of the chip. Figure 4.2 shows the chip

layout of 10-bit charge scaling DAC including BICS within a pad frame of 2.25 mm ×

2.25 mm size. . The area of the DAC alone is 692 × 502 µm2. The entire area of the CUT

along with BICS is 692 × 516 µm2. Therefore the BICS occupies only 242 × 40 µm2 of

the entire chip area. Figure 4.3 shows the microchip photograph of 10-bit charge scaling

97
 Defect 4 (FIT-4)
Defect 3 (FIT-3)

Defect 1 (FIT-1)

Defect 2 (FIT-2)

Figure 4.1: CMOS chip layout of a 10-bit charge scaling DAC with four fault injection
transistors distributed across the chip.

98
Figure 4.2: CMOS chip layout of a 10-bit charge scaling DAC including
BICS within a padframe of 2.25mm × 2.25mm size.

99
DAC and BICS for IDDQ testing. Figure 4.4 shows the simulated and measured

characteristics of the 10-bit charge scaling DAC when the faults are not activated. The

equivalent analog output voltage is shown for all the 1024 input combinations. Figure 4.5

shows the measured DNL characteristics of the 10-bit charge scaling DAC when the

faults are not activated. DNL is within ± 0.6 LSB. Figure 4.6 shows the measured INL

characteristics of the 10-bit charge scaling DAC when the faults are not activated. INL is

less than 1 LSB.

Figure 4.7 shows the simulated output of the opamp when the fault (VE1)

is activated (Fig 3.16). When the opamp is given a sine wave of 1mV p-p, the output

obtained is a sine wave of 105mV p-p with a gain of 105. Offset voltage is increased to

1.9V from 33µV without faults. Figure 4.8 shows the transfer function with the fault

activated with significant non-linearity introduced in the narrow transition region. Figure

4.9 shows the gain versus frequency response of opamp with fault activated. The

amplifier 3dB gain with the fault activated is 38dB as compared to 77dB when the fault is

deactivated. The bandwidth is increased to 3 MHz from 100 KHz without fault (Fig

2.16).

Figure 4.10 shows the simulated output response of the multiplexer circuit when

FIT-3 is deactivated (Fig. 3.18). When the VCONTROL goes HIGH the multiplexer chooses

the VREF and when VCONTROL goes LOW, the multiplexer chooses GND input. The output

waveform obtained is a pulse of 2.5V p-p. Figure 4.11 shows the simulated output

response of the multiplexer circuit when FIT-3 is activated (Fig 3.18). The output

waveform obtained is 1.7V p-p. Figure 4.12 shows the simulated BICS output when the

100
Figure 4.3: Microchip photograph of 10-bit charge scaling DAC and BICS for IDDQ
testing.

101
 DAC output characteristics Simulated
Experimental

2.5
Analog Output

2
Voltage

1.5
1
0.5
0
0 256 512 768 1024
Digital Input Code

Figure 4.4: simulated and measured characteristics of a 10-bit charge scaling DAC.
Note: Faults are not activated.

102
 0.8

0.6

0.4

0.2
LSB's

0
0 200 400 600 800 1000
-0.2

-0.4

-0.6

-0.8
Digital Input Code

Figure 4.5: Measured DNL characteristics of a 10-bit charge scaling DAC.

Note: Faults are not activated.

103
 0.9

0.8

0.7

0.6

0.5
LSB's

0.4

0.3

0.2

0.1

0
0 200 400 600 800 1000
Input Code

Figure.4.6: Measured INL characteristics of a 10-bit Charge Scaling DAC.

Note: Faults are not activated.

104
 2.5 Gain = 105 Input
Output
2

1.5
Voltage (V)

1 Offset = 1.9V

0.5

0
0 100 200 300 400 500
-0.5

-1
Time (us)

Figure: 4.7 Voltage gain response of op-amp with fault introduced.

Note: Input is applied at the non-inverting input.

105
 3

Output
2.5
2
1.5
1
0.5
0
-0.015 -0.01 -0.005 -0.5 0 0.005 0.01 0.015

-1 Input

-1.5
-2
-2.5

Figure 4.8: Transfer function of op-amp with fault (VE1) induced.

106
 Gain = 41dB
3dB Gain = 41dB - 3dB = 38dB

45
40
35
30
Gain (dB)

25
20 3dB Band width = 3MHz
15
10
5
0
1 10 100 1000 10000 10000 1E+06 1E+07 1E+08 1E+09
Frequency0(Hz)

Figure 4.9: Gain versus frequency response of the CMOS opamp circuit with fault
introduced.

107
VREF
2.0V

GND 0V

t
2.5V

VCONTROL

-2.5V
t
Error-Signal
0V

t
2.5V
MUX
Output

-2.5V
t
0s 5us 10us 15us 20us 25us 30us 35us 40us 45us 50us

Time

Figure 4.10: Simulated output response of the multiplexer circuit of Fig 3.18
without defect.

108
 VREF 2.0V

GND 0V

2.5V

VCONTROL

-2.5V
0V
Error-Signal
2.5v

2.0V

MUX
Output
0.3V

0s 5us 10us 15us 20us 25us 30us 35us 40us 45us 50us

Time

Figure 4.11: Simulated output response of the multiplexer circuit of Fig. 3.18 with fault
activated.

109
+2.5V

0V
-2.5V

VENABLE

+2.5V

0V

-2.5V

Error-Signal (VE1)

+2.5V
0V
-2.5V

0s 5us 10us 15us 20us 25us 30us 35us 40us 45us 50us
BICS Output
Time

Figure 4.12: Simulated BICS output of the circuit of Fig. 3.16 when Error-signal-1 for
defect-1 is activated.

110
FIT-1 is activated. FIT-1 is a defect injected between the source and drain of the

operational amplifier circuit (Fig.3.16) of the chip (Fig 4.2). In Fig. 4.12, when the

VENABLE signal is ‘high’, the BICS is by-passed and the defect is not detected. When the

VENABLE signal is ‘low’, the BICS is enabled and if the Error-signal is ‘high’, the BICS

detects the faults and the output of the BICS is ‘high’. Figure 4.13 shows the simulated

BICS output when the FIT-2 is activated (Fig.3.17). FIT-2 is a defect injected between

the gate and drain of the unity gain buffer in the S/H circuit (Fig. 3.17) of the chip (Fig.

4.2). In Fig. 4.13, when the VENABLE signal is ‘high’ the BICS is by-passed and the defect

is not detected. When the VENABLE signal is ‘low’ the BICS is enabled and if the Error-

signal is ‘high’ the BICS detects the faults and the output of the BICS is ‘high’. Figure

4.14 shows the simulated BICS output when the FIT-3 is activated. FIT-3 is a defect

injected between the gate and source of the multiplexer circuit of Fig. 3.18 of the chip

(Fig. 4.2). In Fig. 4.14 when the VENABLE signal is ‘high’, the BICS is by-passed and the

defect is not detected. When the VENABLE signal is ‘low’, the BICS is enabled and if the

Error-signal is ‘high’, the BICS detects the faults and the output of the BICS is ‘high’.

Figure 4.15 shows the simulated BICS output when the FIT-4 is activated. FIT-4 is a gate

oxide short injected between the gate and substrate of the multiplexer circuit of Fig 3.19

of the chip (Fig 4.2). When the VENABLE signal is ‘high’, the BICS is by-passed and the

defect is not detected. When the VENABLE signal is ‘low’, the BICS is enabled and if the

Error-signal is ‘high’ the BICS detects the faults and the output of the BICS is ‘high’.

Figure. 4.16 shows the CMOS circuit diagram of a 10-bit charge scaling

DAC with four fault injection transistors. Figure 4.17 shows the simulated output of the

111
 4.0V

0V

-4.0V
VENABLE
4.0V

0V

-4.0V
Error-signal (VE2 )
4.0V

0V

-4.0V
0s 5us 10us 15us 20us 25us 30us 35us 40us 45us 50us
BICS Output
Time

Figure 4.13: Simulated BICS output of the circuit of Fig. 3.17 when Error-signal-2 for
defect-2 is activated.

112
 4.0V

0V

-4.0V
VENABLE
4.0V

0V

- 4.0V
Error-Signal (VE3 )
4.0V

0V

-4.0V
0s 5us 10us 15us 20us 25us 30us 35us 40us 45us 50us
BICS Output
Time

Figure 4.14: Simulated BICS output of the circuit of Fig. 3.18 when Error-signal-3 for
defect-3 is activated.

113
 4.0V

0V

-4.0V
VENABLE
4.0V

0V

-4.0V
Error-Signal (VE4 )
4.0V

0V

-4.0V
0s 5us 10us 15us 20us 25us 30us 35us 40us 45us 50us
BICS Output
Time

Figure 4.15: Simulated BICS output of the circuit of Fig.3.19 when Error-signal-4 for
defect-4 is activated.

114
 STO RAGE UNITY-GAIN
TG SWITCH BUFFER
CAPACITO R

CAPACITOR ARRAY ARCHITECTURE OPAMP

+

A=1
- +
-
Vo
+
CH -
512C 256C 128C 64C 32C 16C 8C 4C 2C C C

CIRCUITRY TO GENERATE DIGITAL INPUT WO RD

Sample and Hold Input

VDD VDD
M8 M7 M8 M7
Output of Multiplexer W/L=45/3
W/L=90/3 W/L=45/3
W/L=90/3 W/L=90/3
M6 W/L=90/3
M6
+ Vin
+ Vin
W/L=90/3 W/L=90/3
- Vin
CC =30FF W/L=90/3 W/L=90/3
M1 M2 Vout CC =30FF
W/L=4.5/1.6 W/L=9.6/3 M1 M2
- Vin Vout
M9 M3 M4 VE
VE W/L=90/3
M5 M9 M3 M4
W/L=45/3 W/L=9.6/3 W/L=4.5/1.6 W/L=90/3
VREF W/L=45/3 M5
W/L=45/3
Control Signal VSS W/L=45/3

VSS
Fault-Injection Transistor (S-D)

Fault-Injection Transistor (G-D)

Output of Multiplexer
Output of Multiplexer
W/L=4.5/1.6

VE
VE

VREF
Control Signal
VREF
Fault Injection Transistor ( G-S) Control Signal

Fault Injection Transistor ( Sub-S)

Figure 4.16: CMOS circuit diagram of 10-bit charge scaling DAC with four fault
injection transistors distributed across different parts of the circuit.

115
 2.5V

-2.5V
t
VENABLE

2.5V

-2.5V
t
ERROR-SIGNAL-1

2.5V

-2.5V
t
ERROR-SIGNAL-2

2.5V

-2.5V
t
ERROR-SIGNAL-3

2.5V

-2.5V
t
ERROR-SIGNAL-4
2.5V

-2.5V
t
10US 20US 30US 40US 50US 60US 70US 80US 90US 100US
BICS OUTPUT
Time

Figure 4.17: Simulated BICS output with defects induced using fault injection
transistors.

116
BICS when four FIT’s are activated. In Fig. 4.17, when the VENABLE is ‘high’ the BICS is

disabled and when it is low the BICS is enabled. When the BICS is enabled and if there is

any Error-Signal going ‘high’ the BICS detects the fault. Table-1 shows the faulty IDDQ

values obtained for the different kinds of faults are injected in the chip. Figure 4.18

shows the wave forms obtained form the logic Analyzer. The error signal is kept ‘high’

and the BICS is tested for its operation in the normal mode and test mode. When the

VENABLE is ‘low’, the BICS is in the test mode and if the error signal is ‘high’,

PASS/FAIL gives logic ‘1’ and thus, it detects the fault induced. When the VENABLE is

‘low’, the BICS is in the normal mode, PASS/FAIL gives logic ‘0’ thus, no fault is

detected.

Table 4.1 summarizes calculated (simulated) and measured IDDQ values

corresponding to four different faults distributed across the chip. The reference current, is

IREF is 1mA. Table 4.1 shows that in the presence of faults IDDQ reaches to 3mA. The

calculated and measured IDDQ values are in close agreement. Table 4.2 summarizes a

comparative study of design of previously reported BICS with the present BICS design.

Our BICS design uses only seven transistors and an inverter buffer. The BICS requires

neither an external voltage source nor a current source. Further more, the BICS does not

require clocks.

117
Figure 4.18: HP 1660CS logic analyzer test results on a fabricated CMOS 10-bit charge
scaling DAC showing the performance of BICS in normal and test modes.

118
Table 4.1 Theoretical and measured IDDQ for different fault types
Note: The reference current, IREF =1mA

Defect Faulty IDDQ Faulty IDDQ

(Sim) mA (Meas) mA
Source-Drain short 3.00 mA 2.8 mA
Gate-Drain short 2.8 mA 2.7 mA
Gate-Source short 2.7 mA 2.6 mA
Gate-oxide short 2.5 mA 2.2 mA

119
 Table 4.2: Comparison of built-in-current sensors

# Device Clock Signal Mode Select Control Output

Pin Pin
Maly’s TR: 10 Single Clock Y 5 1
Design[13] Inv: 2
Nand: 1
Miura’s TR: 16 Not Used Not 3 1
Design[15] R: 1 Reported
C: 1
Shen’ TR: 13 Two Phase N 3 2
Design[16] Diode: 1 Clock
Tang’s TR: 24 Single Clock N 3 1
Design[38] R: 1
Favalli’s TR: Not Used Y 1 1
Design[14] 2*gates+1
Nigh’s TR: 13 Two Phase Y 3 1
Design[17] Inv: 1 Clock

Proposed TR: 7 Not Used Y 2 1

Design Inv: 1

Note: Mode Select: Normal Mode / Test Mode, Control Pins: VENABLE and EXT.

120
Chapter 5

Conclusion and Scope of Future Work

A 10-bit DAC using charge-scaling architecture is designed in standard 1.5 µm n-

well CMOS technology. The DAC is tested with all 1024 digital input word

combinations. The unit step is about 1.9mV. DAC operates with ±2.5V supply voltages.

The reference voltage used is 2V for a ‘HIGH’ and ground (0V) for a ‘LOW’. The 10-bit

DAC is used as a circuit under test (CUT). The CUT is tested with a novel built-in

current sensor (BICS), which has a very negligible impact on the performance of the

circuit under test.

The present BICS works in two-modes: normal mode and the test mode. In the

normal mode, BICS is isolated from the CUT due to which there is no performance

degradation of the circuit under test. In the testing mode, BICS detects the abnormal

current caused by permanent manufacturing defects. The BICS requires neither an

external voltage source nor a current source. The present BICS is designed with only

seven transistors and an inverter buffer. The present BICS design which is based on

current comparison, combined with the novel fault-injection technique, can be used for

IDDQ testing of other type of data converters of the type shown in Fig. 5.1 and is

suggested for future work. The built-in current sensor of the present work requires less

area and is more efficient than the conventional current sensors. It is shown that with the

use of a novel fault injection technique, combined with a built-in current sensor design,

has significantly improved the testing of mixed signal integrated circuits

121
 O vers am p ling C lo c k

1-Bit D igital O utp ut

A nalo g F irs t O rd er M o d ulato r D ec im ato r 8-Bit

Inp ut D igital O utp ut

(a)

A nalo g Inp ut 1-Bit D igital O utp ut

Integrato r 1-Bit A D C

1-Bit D A C

(b)

Figure 5.1: Block diagram of a sigma-delta ADC

122
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[42] www.mosis.edu.

126
Appendix A

SPICE LEVEL 3 MOS MODEL Parameters for standard n-

well CMOS Technology [42]

(A) Model Parameters for n-MOS transistors.

. MODEL NMOS NMOS LEVEL=3 PHI=0.700000 TOX=3.0700E-08 XJ=0.200000U

+TPG=1 VTO=0.687 DELTA=0.0000E+00 LD=1.0250E-07 KP=7.5564E-05
+UO=671.8 THETA=9.0430E-02 RSH=2.5430E+01 GAMMA=0.7822
+NSUB=2.3320E+16 NFS=5.9080E+11 VMAX=2.0730E+05 ETA=1.1260E-01
+KAPPA=3.1050E-01 CGDO=1.7294E-10 CGSO=1.7294E-10
+CGBO=5.1118E-10 CJ=2.8188E-04 MJ=5.2633E-01 CJSW=1.4770E-10
+MJSW=1.00000E-01 PB=9.9000E-01

(B) Model Parameters for p-MOS transistors.

. MODEL PMOS PMOS LEVEL=3 PHI=0.700000 TOX=3.0700E-08 XJ=0.200000U

+TPG=-1 VTO=-0.7574 DELTA=2.9770E+00 LD=1.0540E-08 KP=2.1562E-05
+UO=191.7 THETA=1.2020E-01 RSH=3.5220E+00 GAMMA=0.4099
+NSUB=6.4040E+15 NFS=5.9090E+11 VMAX=1.6200E+05 ETA=1.4820E-01
+KAPPA=1.0000E+01 CGDO=5.0000E-11 CGSO=5.0000E-11
+CGBO=4.2580E-10 CJ=2.9596E-04 MJ=4.2988E-01 CJSW=1.8679E-10
+MJSW=1.5252E-01 PB=7.3574E-01

127
Mosis Fabricated Chip Model Parameters (T1AZ)

(A) Model Parameters for n-MOS transistors.

. MODEL CMOSN NMOS LEVEL=3 TOX=3.07E-8 NSUB=2.75325E15

+GAMMA= 0.7620845 PHI=0.7 VTO=0.6298903 DELTA=0.8569392
+UO=702.9336344 ETA=9.99916E-4 THETA=0.0734963 KP=7.195017E-5
+VMAX=2.766785E5 KAPPA=0.5 RSH=0.0474566 NFS=6.567094E11 TPG=1
+XJ=3E-7 LD=4.271014E-12 WD=7.34313E-7 CGDO=1.75E-10
+CGSO=1.75E-10 CGBO=1E-10 CJ=2.944613E-4 PB=0.9048351 MJ=0.5
+CJSW=1.236957E-10 MJSW =0.05

(B) Model Parameters for p-MOS transistors.

. MODEL CMOSP PMOS LEVEL=3 TOX=3.07E-8 NSUB=1E17 GAMMA=0.4940829

+PHI=0.7 VTO=-0.8615406 DELTA=0.5236605 UO=250 ETA=7.55184E-3
+THETA=0.1344949 KP=2.438731E-5 VMAX=9.345228E5 KAPPA=200
+RSH=36.5040447 NFS=5.518964E11 TPG=-1 XJ=2E-7 LD=9.684773E-12
+WD=1E-6 CGDO=2.09E-10 CGSO=2.09E-10 CGBO=1E-10 CJ=2.965467E-4
+PB=0.744678 MJ=0.4276703 CJSW=1.619193E-10 MJSW=0.1055522

128
Appendix B

Chip Testability

Figure B.1 shows the 10-bit DAC with BICS in 2.25 mm × 2.25 mm padframe.

Figure B.2 shows the Microchip photograph of 10-bit DAC with BICS. The design

includes individual sub-modules for testing the device.

B.1 Inverter Module and Testing.

PIN No. Description

13 Input

14 Output

DC test was performed on the independent inverter module to test if the chip did

not have fabrication problems. Logic ‘0’ is applied at the input pin #13 and output (logic

‘1’) is observed on pin #14. A logic ‘1’ is applied at the input pin #13 and output (logic

‘0’) is observed on pin #14.

B.2 Opamp Module and Testing

PIN No. Description

8 Positive OPAMP

6 OPAMP Output

9 Negative OPAMP

The opamp is tested by giving a sine wave with 4V p-p to the positive input pin

#8 and the output is observed at the output pin #6. The negative input pin is grounded.

129
B.3 Sample and hold Circuit and Testability

PIN No. Description

1 S/H Output

2 Control voltage

4 S/H Input

The sample and hold circuit is tested by giving 4V p-p sine wave. The control

voltage of the sampling capacitor is a pulse of ±2.5V. When the pulse is HIGH, the input

is sampled and when the pulse is LOW, the circuit is in the hold mode. The output is

observed at pin #1.

B.4 10-bit DAC with BICS and Testability

Table B.1gives the pin numbers and their description to test 10-bit DAC

Pin No. Description of PIN

1 S/H Output

2 Control Voltage

3 VSS

4 S/H Input

5 VDD (corner pad)

6 OPAMP Output

7 VDD

8 Positive Input (OPAMP)

130
9 Negative Input (OPAMP)

10 VSS

11 Input Bit (D10)

12 Input Bit (D9)

13 Input (Test Inverter)

14 Output (Test Inverter)

15 VDD (Corner Pad)

16 Input Bit (D8)

17 Input Bit (D7)

18 Input Bit (D6)

19 Input Bit (D5)

20 Input Bit (D4)

21 Input Bit (D3)

22 Input Bit (D2)

23 Input Bit (D1)

24 Error-Signal-2

25 VSS (Corner Pad)

26 Error-Signal-1

27 VCONTROL

28 VENABLE

29 Error-Signal-3

30 VDD

31 BICS Output

131
 32 EXT

33 Error-Signal-4

34 BICS output for Test module

35 VSS (Corner Pad)

36 DAC output

37 VSS

38 VGND

39 VREF

40 VDD

B.5 10-bit DAC Testing in Normal Mode

1. Supply voltages of ±2.5V is given to the power supply pin numbers of the chip

(VDD = +2.5V and VSS = -2.5V).

2. The VENABLE pin (#28) is given a ‘high’ voltage (+2.5V), which makes the BICS

to function in the normal mode.

3. The EXT pin (#32) is connected to the VSS (-2.5V) when the BICS is in the

normal mode. (VENABLE = ‘1’ = +2.5V)

4. The fault-injection transistors must be de-activated by giving a ‘low’ voltage (-

2.5V) to the error-signals VE1, VE2, VE3 and VE4.

5. The DAC is tested with giving various combinations of inputs to the digital input

pins 11,12,16-23. (MSB – LSB).

6. The output of the DAC is observed at pin #36 on the oscilloscope.

132
B.6 IDDQ Testing of the 10-bit DAC in Test Mode

1. The VENABLE is given a LOW voltage (-2.5V) to make BICS operate in the test

mode.

2. The fault-injection n-MOS transistors are activated by connecting the error-

signals VE1, VE2, VE3 and VE4 to a HIGH voltage (+2.5V)

3. The reference current generated on-chip is about 1mA.

4. When the error signals are activated, faults are injected into the chip and the

faulty current shoots up to 3mA.

5. The PASS/FAIL output is observed. The output of the BICS shows a HIGH value

(PASS/FAIL = ‘1’ = +2.5V) when the faults are injected into the chip and when

the BICS is in test mode. When the BICS is in the normal mode the output is

LOW (PASS/FAIL = ‘0’ = -2.5V).

B.7 Testing of 10-bit DAC using Logic Analyzer HP 1660CS

1. The VENABLE is given a pulse input. When the pulse input is ‘high’ the BICS is in

the normal mode and when the pulse input is low the BICS is in the test mode.

2. The Error Signal is given a high voltage (+2.5V).

3. The PASS/FAIL output is observed. The output of the BICS shows a HIGH

value (PASS/FAIL = ‘1’ = +2.5V) when the VENABLE is low and the Error Signal

is high. The output of the BICS shows a low value (PASS/FAIL = ‘0’ = -2.5V)

when the VENABLE is high and the Error Signal is ‘high’ since the BICS is

disabled.

133
Figure: B.1 10-bit DAC with BICS in the 2.25 mm × 2.25 mm padframe.

134
Figure B.2: Microchip photograph of 10-bit charge scaling DAC and BICS for IDDQ
testing.

135
Vita

Srinivas Rao Aluri was born on June 20, 1978, in Hyderabad, India. He received his

Bachelor of Engineering in Electronics and Communication Engineering degree from

Osmania University, Hyderabad, India, in April, 2000. He was enrolled in the

Department of Electrical and Computer Engineering at Louisiana State University, Baton

Rouge, Louisiana, to attend graduate school. He is presently working for Micron

Technology Inc., Allen, Texas. His research interests include IDDQ Testing of Mixed

signal Integrated Circuits and Memory design.

136
 ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

AN ACCURATE STATISTICAL YIELD MODEL FOR

CMOS CURRENT-STEERING D/A CONVERTERS
A. Van den Bosch, M . Steynert and W. Sansen
K.U. Leuven,
Department of Electrical Engineering, ESAT-MICAS,
Kard. Mercierlaan 94, B-3001 Heverlee, BELGIUM
e-mail : anne.vandenbosch@esat.kuleuven.ac.be

ABSTRACT 2. INL-YIELD ESTIMATION IN

To obtain a high resolution CMOS current-steering digital-
to-analog converter, the matching behavior of the current
source transistors is one of the key issues in the design. At
this moment, these matching properties are taken into
account by the use of time consuming and CPU intensive
Monte Carlo simulations. In this paper a formula is derived
that allows to accurately describe the impact of the
mismatch on the INL (integral non-linearity) yield of
current-steering D/A converters without any loss of design
time.
1. INTRODUCTION
The evolution in the field of wireless communications and
the mixed signal area pushes the designer to put an
increasing amount of effort in the integration of digital and
analog systems on one chip. Consequently, the interface
between these systems is becoming one of the most
challenging blocks to design in the telecommunication
devices of today. The demand for high performance
digital-to-analog converters - with applications in the area
of e.g. video, HDTV and GSM - has strongly increased.
Nowadays CMOS current-steering D/A converters are
frequently used for such applications since these circuits
can be implemented using a small silicon area (in
comparison with resistor ladder based implementations)
and can be easily integrated in fully digital CMOS
technologies implying a considerable cost reduction.
However, a current-steering D/A converter falls into the
category of circuits which are made using a large number
of identical building blocks (current sources) and therefore
its most important specifications are dependent on the
matching behavior of these blocks. It is important to be
able to determine the number of functional current-steering
D/A converters as a function of the matching properties of
the current sources.
In section 2, the yield estimations found in open literature
are evaluated and their pro’s and contra’s are discussed. In
the following section a new yield model will be presented
that in a minimum of time gives the wanted result. Finally
a conclusion will be formulated in section 4.
LITERATURE
2.1 Introduction
Due to the mismatch of the current source transistors, the
INL (integral non-linearity) specification of different D/A
converters made in the same process technology will vary
randomly. It is therefore important to be able to predict this
specification within certain boundaries. For this purpose,
the concept of the D/A converter’s INL-yield has been
introduced. This yield figure is defined as the percentage
of functional D/A converters with an INL specification
smaller than half an LSB (least significant bit).
In this section analytical expressions for the D/A
converter’s INL-yield found in open literature will be
discussed and evaluated. All of the models including the
new one start from the assumption that the unit current
source errors have a gaussian nature.
2.2 Lakshimikumar approach
A first suggestion to analytically determine the yield of a
D/A converter as a function of the matching parameters of
the current source transistors has been made in [ 11 :
-1
INL - yield = n erf Jz
i=2
(-)Q i
Qi
N = the number of bits,
-
z i = the mean normalized output at code i
0I0 = unit current relative standard deviation
However, this formula is based on the assumption that
there exists no correlation between the outputs of the
current-steering D/A converter. The INL-yield can then be
obtained by multiplying the probabilities that each output
has an error smaller than half an LSB (eq.1). To
demonstrate that this assumption is not correct the
following example is given. The outputs corresponding

0-7803-5482-6/99/$10.0002000 IEEE

IV- 105
with the digital input word 01100 and 01101 are strongly
correlated since they are both implemented using the same
current sources. The formula given in eq.1 gives us a rather
pessimistic view on the INL-yield (fig.1) leading to an
oversizing of the current source transistors [2] (eq.2) and
hence of the total chip area.
In [3] an adjustment of the formula in eq.1 has been
presented. Here the MSB (most significant bit) transition is
viewed as the most critical one since in a binary
implementation this transition has the largest probability of
generating an output error. Furthermore, the D/A
converter's outputs before and after the MSB transition are
not correlated and the yield can then be described as :
2" -I
ZNL-yield =
i=2"-'-1
erf (a)
Jz
(3)
Qi
N = the number of bits,
-
zi = the mean normalized output at code i
= unit current relative standard deviation
I
However, the yield estimation given in eq.3 is too
optimistic (fig.1) since the influence of only two outputs is
taken into account while the errors generated by the other
outputs are being ignored.
Comparing the two approaches one can conclude the
following : designing a chip using eq.1 can lead to a large
but nearly fault-free D/A converter while eq.3 gives you a
compact but low yield circuit. The correct yield estimation
is situated somewhere in between these two results.
2.3 Monte Carlo approach
To obtain an accurate estimation of the I N L j i e l d , the
Monte Carlo simulation [4,5] has been up till now
considered to be the only good altemative.
The following procedure can be used. Each of the (2N-1)
current sources has a random value that has been derived
from a gaussian distribution with mean value and a
standard deviation o(1). For every digital code the output
current of the D/A converter is calculated and compared to
the ideal value. If the difference is larger than half an LSB
- even for only one digital code - the D/A converter is
regarded as not functional and is therefore rejected. For
every o(1) this procedure is repeated a Iarge number of
times (> 100) to obtain reliable results. The INL-yield is
then given by the ratio of the number of functional D/A
IV- 106
converters (INL<1/2 LSB) to the total number of try-outs.
In this way the relation between the unit current standard
deviation and the INL-yield is determined (fig.1).
However, to obtain the results depicted in fig.1 a large
amount of CPU time is necessary. Running a Monte Carlo
simulation for a high resolution D/A converter takes
several hours and that is a major drawback for this
approach.
, !
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
sigma(lyl
Fig. 1 : Monte Carlo simulations(0)of the INL-yield
compared to the results of the formulas in eq.l(+) and
eq.3(.) for a 10 bit DIA converter
3. NEW INL-YIELD FORMULA
3.1 Introduction
In this section, a formula will be presented that describes
the INL-yield of the D/A converter as accurately as the
Monte Carlo simulations but without any loss of design
time. The idea will be elaborated for an arbitrary number
of bits N. For the simplicity of notation the following
symbols are defined :
Definition 1 : X(j) is the sum of j non correlated unity
current sources
Definition 2 : Yfj) is the difference between Xu) and the
sum of the ideal current sources
Every current source has a normal distribution with a mean
value I,, and a standard deviation o(1).This implies that
both Xu) and Yu) also have a normal distribution with the
following properties (eq.4) :
3.2 Theory
The exact possibility that an INL error will occur is based
on the fact that each current source can generate an error
and hence is given by the following sum of probabilities
(eq.5) :
P(INL-error) = can be deduced from eq.9. At this point, the INL yield is
no longer described as a sum of probabilities (eq.5) but as
P((Y(1)l Z 0.5 & IY (2)(< 0.5 &
I -I
...& Y ( 2 N 1) < 0.5) +
the possibility that a sample from a normal distribution is
P(IY(2)I 2 0.5 & ...& Y ( 2 N -1) < 0.5) + ...+ (5)
I I smaller than half an LSB. This requirement can be written
as :
P ( k ( 2 N -l)l> 0.5)

However, this equation is not transparent and therefore not

-1 I ZLSB -Co (10)
suitable for practical use.
INL - yield
= 0.5 +
The basic idea behind the new theory is based on the 2
assumption that if at any point IY(i)l reaches half an LSB,
there exists a 50% chance that the error increases and 50% with P ( Y ( ~ ~the
) ) probability density function (fig.2).
chance that it decreases again since a normal distribution Eq.10 directly gives the following result :
with mean value zero is used. Extending this line of 1
C *B ( Y ( 2 N))I-LSB
thought one can say that if an INL error occurs - when 2
passing through all the possible codes generated by the with:
2N-1digital input words - there is a 50% chance that this
C = inv -norm(-,,,)(0.5 + INL - yield
> 0.5).
error still exists for the fictive code 2N((Y(2N)J )
2

Fig.2 : the shaded area determines the probability

P(Y(2N))< 112 LSB

This idea can be expressed as :

P(3j E [1..(2N - 111 :IY ( j ) l > 0.5)
I NI
P(Y(2 ) > O S ) =
2
(6)
At this point the INL-yield of the D/A converter can be
integrated in the calculation since there exists an obvious
relation between the yield and the possibility of an INL C = inv -norm(-,,,)(0.75 + INL-4yield 1
error to occur :
Eq.11 can be rewritten as a relationship between the unit
INL-yield = 1 - P ( 3 j ~[1..(2N - l ) ] : ~ Y ( j ) ~ > O S ) (7) current relative standard deviation and the INL-yield of
the D/A converter (incorporated in coefficient C) :
Combining eq.6 and eq.7 :
1 - INL - yield
2
From eq.8 the possibility that no INL error occurs at code Fig.3 shows the Im-yield of the D/A converter in
2Ncan be easily derived and equals : function of the coefficient C.
INL- yield In fig.4 the INL-yield of a 10 bit D/A converter calculated
(9) using the new formula (eq.12) and simulated using the
2
Monte Carlo approach are depicted. From this figure it can
Since Y(2N) has a normal distribution with a standard be concluded that the formula is in good agreement with
deviation P o ( I ) (eq.4), the relation existing between the Monte Carlo simulations.
the IN-yield of the current-steering D/A converter and To gain more insight in eq.12, the unit current standard
the matching properties of the current source transistors deviaticn is plotted in logarithmic scale versus the

IV-107
 100
Fig.4 : Comparison between the Monte Carlo simulations
(*) and the formula (line) for a IO bit D/A converter
resolution of the D/A converter (fig.5). As can be seen
from fig.5 these are straight lines since
Furthermore, one can easily conclude from this figure that
for the design of a high accuracy current-steering CMOS
D/A converter the matching parameters play a significant
role. A small deviation of the required sigma(I)/I can lead
to a severe yield degradation.
01
0.01
______ _ -
0.001 4
I------ I
6 8 10 12 14
number of bits
Fig.5 : The unit current relative standard deviation in
function of the resolution of the D/A converter for a 30
yield of 99.7% (+), a yield of 50% ( 0 )and of 10% (m)
The time to create a figure like fig.5 using Monte Carlo
simulations in MATLAB is given in table 1. In this table
the results for the INL-yield from 100% to 10% for a
current-steering D/A converter with different resolutions
can be found. For all the simulations twenty values for the
relative unit current standard deviation were taken. This
can be understood as follows. In a first coarse
approximation a simulation using 10 values for sigma(I)/I -
that span a wide range- is run. From the obtained result the
interval for the sigma(I)/I that obtain a high INL-yield can
be specified. In this interval another 10 points are
IV-108
simulated. In almost all cases this procedure gives accurate
results.
Constructing fig.5 using the new formula takes only a few
minutes. The time to write the short program For
MATLAB is so to speak the most time consuming. It is
also worth noting that the time necessary to calculate .the
yield is independent of the resolution of the D/A converter
while the time consumption of the Monte Carlo
simulations “explodes” with an increasing D/A converte:r’s
accuracy.
14 bit
Table1: comparison between the time consumption of the
Monte Carlo simulations and the new formula
4. CONCLUSION
Since high resolution current-steering D/A converters are
strongly dependent on the matching characteristics of the
technology in which they are processed, it is important to
know the number of functional chips in a set of fabricated
devices. It is proven in this paper that time consuming
Monte Carlo simulations are no longer necessary to obtain
results for the Im-yield with a good accuracy. A new
formula has been presented that directly gives you the
INI-yield of a current-steering D/A converter in function
of the transistor mismatch parameters of the current
sources without any loss of design time.
5. REFERENCES
[ I ] K. Lakshimikumar and al., “Characterization and Modeling
of Mismatch in MOS Transistors for Precision Analog
Design”, IEEE Journal of Solid State Circuits, v01.21, Dec
1986, pp. 1057-1066
[2] M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching
Properties of MOS Transistors”, IEEE Journal of Solid
State Circuits, vol. SC-24, Oct. 1989, pp. 1433-1439
[3] K. Lakshimikumar and al., “Reply to ‘A Comment on :
Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design”, IEEE Journtzl of
Solid State Circuits, vo1.23,Feb. 1988, pp. 296
[4] C. Conroy, W. Lane and M. Moran, “A Commenf. on
‘Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design,’” IEEE Journd of
Solid State Circuits, ~01.23,Feb. 1988, pp. 294-296
[5] J. Bastos and al., ‘‘ A 12 bit Intrinsic Accuracy High Speed
CMOS DAC,” IEEE Journal of Solid Slate Circuits, vo1.33,
No.12, Dec. 1998,pp. 1959-1969
 Characterization of a CMOS Current-Steering DAC using State-Space Models
K. Ola Andersson and J. Jacob Wikner
Dept. of E.E., Linkoping University
SE-581 83 Linkoping, Sweden
MERC, Ericsson Microelectronics AB
Box 1885, SE-581 17 Linkoping, Sweden
-
Abstract Performance limitations on current-steeringdig-
ital-to-analog converters (DACs) are due to 6nite output
impedances, nonideal switches, parasitic capacitances, match-
ing, etc. In this work we present a dynamic state-space model
of a 14-bit current-steeringDAC which includes dynamic non-
idealities. Simulation results are presented and compared to
measurement results. The model can be used for fast perform-
ance estimation of DIA converters.
I. INTRODUCTION
For high speed and high resolution communication appli-
cations the current-steering digital-to-analog converter
P A C ) is suitable [ 11. In this work we focus on the dynamic
properties of the current-steering converter. With increasing
signal frequency, dynamic errors, e.g., nonlinear settling
errors and glitches, tend to determine the performance of the
DAC. We need good behavioral-level models of the
dynamic properties in order to understand the DAC design
criteria.
In Sec. I1 we introduce the different nonideal components
used in a current-steering DAC. These components are put
together to a circuit level model of the whole DAC, as pre-
sented in Sec. 111.
In Sec. IV we present a mathematical analysis of the cir-
cuit-level model. The differential equations of the system
are given on a state-space form, yielding short simulation
times. The model helps us understand what can be done to
minimize the influence of dynamic errors. The model is
Spice-like, but used in Matlab it has an improved modularity
and flexibility.
In Sec. V we discuss the application of the model on a
14-bit current-steering DAC. Single-tone and multi-tone
properties are discussed.
n. NONIDEAL CURRENT-STEERING
DAC CIRCUITELEMENTS
In this work we focus on the influence of unwanted resis-
tive and capacitive parts (parasitics). The parasitics in the
current sources have one of the most crucial impacts on per-
formance. Matching is not considered but can easily be
introduced in simulations of the model presented by simply
changing the numerical values of currents and parasitics.
A. The Current Source
The ideal current source (Fig. l(a)) should have an infi-
nite output impedance. A cascoded PMOS implementation
of a current source is shown in Fig. l@). The cascode tran-
h c . 43rd IEEEmdwest Symp. on Clrcuits and System, Lanslng MI, Aug 8-11,2000
0-7803-6475-9/00/$10.~~~~ 2oM)
source transistor
-Id
cascade transistor
t
@)
lout
Fig. 1. (a) Ideal, (b) PMOS, and (c) simplified model of MOS current
source.
sistor increases the output impedance [2], but still the source
will have a finite output impedance (Fig. l(c)). The output
impedance contains a capacitive part [11, which will degrade
the performance at higher signal frequencies.
B. Theswitch
Using differential signal paths is an effective way of
rejecting noise and distortion, e.g., substrate noise or chan-
nel charge injection, if the two paths are symmetrically
designed [2]. Therefore, differential current switches are
commonly used and they are implemented with two or more
MOS transistors in parallel (Fig. 2(a)). In this work the
switch is represented by the MOS switch-on resistance(Fig.
2@)). There also exist parasitic capacitances in the switch,
but these are lumped into the parasitics of the current source
and output wire.
C. The Output Wire
The output wires of the DAC should have zero imped-
ance to reduce the voltage drops. In reality, the wires contain
resistive as well as capacitive and inductive parts. For high
accuracy, a transmission line model or an RC-ladder should
be used for the wire [3]. However, we want to achieve short
simulation times, i.e., a small number of circuit nodes.
Therefore, we trade accuracy for a lower complexity model.
As a simple approximation, we use a resistor and capacitor
in parallel, i.e., a simple RC-ladder, as shown in Fig. 3. The
impedance includes the internal wire impedance as well as
the off-chip load.
III. CIRCUIT-LEVEL
MODELING
In this section we briefly present the ideal current-steer-
ing DAC, followed by a presentation of the nonideal DAC
constructed with the components described in Sec. 11.
668
 Fig. 2. (a) Ideal and (b) nonideal differential switch.

Fig. 3. Model of the output wire.

hh
A. The Ideal Current-SteeringDAC
An ideal differential current-steering DAC is shown in Fig.
4(a) where all current sources have infinite output impedance.
The switch and wire impedances are zero and the load imped-
ance is purely resistive.
B. The Nonideal Current-SteeringDAC
The ideal components are substituted with the nonideal
4L
..........
._......__

%@ +
Fig. 4. The (a) ideal and (b) nonideal current-steering DAC.

components presented in Sec. II forming the circuit of Fig.

4@). This is the architecture we examine in our work. T
('1 = [vl(t) *.. v K ( f ) v,(f)l
Iv. STATE-SPACE MODELOF ONE CHANNEL
We form the state vector X
To illustrate the model we formulate the differential equa-
tions describing one of the DAC outputs. We look at the tran- X ( t ) = V ( t )- V ( 0 ) (4)
sient behavior between two consecutive switching instants.
The switching instants occur at multiples of T s and for sim- where V ( 0 ) is the initial value of V just before the switching
plicity we start at t = 0 . occurs. We rewrite the equations and get
Assume that we during a certain period have K current V(t) = X ( t ) = A . X ( t ) + B . u(t) (5)
sources connected to the output as illustrated in Fig. 5 , i.e., the
current sources I . where j = 1, ...,K . The following equa- where the elements of the (K + 1) x (K + 1) matrix A tare
I
tions hold for this system

aj, = -(&.+;)$, for j = I, ..., K

J

Combining the equations yields aj ., K + 1 -

- - 1 for j = 1, ..., K
Rs, jcj

a K + 1, i
-
- R ~1j ,c for j = 1, ..., K

and
a 1,. J. = 0 for all other i, j
We want to write the equations on vector form and we
introduce the voltage vector, V ,defined as and the vector B is given by

669
 (4 PSD plot for a single-lone input,fsample = 2 MHz
0

-20.
I
E
g -40-

e -60-
-
0
I.......+....... I .g -80-
a
m
a-100-

@oR
l

-
5
Fig. 5. One output channel during a switching period.

@) PSD pld for a single-tone input,fsample = 10 MHz

B = A . V ( O - ) +[ y c , ... IK/cK dT (7)

0-

-20
The input signal, u(t) ,is a unit step. Since the final values of
the nodal voltages, V i ( T ) ,will become initial values in the
next switching period, all those are needed as output signals
from the state-space system. We also need the output voltage, I I
VJ?),and it is convenient to define the output, Y , as
Y(t) = V ( t ) = X(t) + v(o-)
. u(t) (8)
Equation (5) together with (8) is a standard state-space formu-
lation of the differential equations describing the system [4].
-8""
0.1 0.2 0.3 0.4 0.5
Normalized Frequency
At a first stage, the issue for the simulator is to determine the
output values at multiples of T. Fig. 6. Single-tone spectra for the DAC model using sampling frequencies
of (a) 2 MHz and (b) 10 MHz.

v. SIMULATION RFSJLTS
TABLE I
SMULATION VALUES FOR SOURCES AND PARASIllCS.
The results from Sec. IV enables us to do simulations in a
numerical computation environment, e.g., Matlab, which has Component LSB value MSB value
been chosen for this work. The advantages of using mathe-
matical over circuit-level simulators are for example the sim- Source output resistance 150 GQ 18.3 MSZ
plicity of creating different input signals to the system and the
powerful signal processing tools. Source output capacitance
Quantitative values on parasitics and other nonidealities Source output current 1.22 p A 1OmA
have been estimated through layout extractions and process I I

parameters of a 0 . 3 5 ~CMOS process. The values have been
used to simulate the behavior of a 14-bit current-steering
DAC. In Table I we show the circuit values used in the simula-
tions. Simulations are compared to measurements of a 14-bit
converter with approximately the same properties as given in
Table I.
A. Simulated Signal Spectra
We have carried out single-tone simulations of the 14-bit
DAC at different frequencies. In Fig. 6(a) a half-scale single-
tone spectrum of the differential output signal is shown, where
the sampling frequency is f, = 2 MHz . Fig. 6(b) shows the
situation for f = 10 MHz . In both cases the ratio between
the signal and sampling frequencies is prime and
f signal'f s 1'9
In the 2 MHz case we basically find no difference between
Switch on-resistance I 50051 I 16 51
I Loadcapacitance I 120 pF ~ - -1
I Wire resistance I 100 SL I
the nonideal and an ideal spectrum. No visible spurious tones
are appearing, only the quantization noise is present. How-
ever, when the frequencies are increased by a factor of 5, we
clearly see how the dynamic nonidealities introduce distortion
of odd order. In the separate channels there also exist harmon-
ics of even order that are cancelled in the shown differential
output spectrum. These even order terms become visible in
the differential spectrum aswell, if there is a slight mismatch
between the two channels, e.g., a difference between the load
resistances. In a real implementation we would expect to have
spurious tones even at relatively low frequencies, due to cur-
rent source mismatch and other nonidealities not included in
the modeling.

670
B. Single-Tone Linearity
One important single-tone linearity measure is the spuri-
ous-free dynamic range (SFDR), which is defined as the
power-ratio between the signal and the largest spurious tone.
In Fig. 7 we show simulated and measured values of SFDR
as a function of signal frequency. The sampling frequency is
fs = 10 MHz . Simulated and measured results show a close
agreement. However, for increased sampling frequencies the
model show worse performance than measurements, e.g., at
f, = 40MHz the simulated SFDR is approximately 10 dE3
worse than the measured. This implies that a somewhat more
complex model is needed to closer resemble reality at high
clock frequencies. The rough model of the wire probably
accounts for a significant part of the discrepancies between
measurements and simulations, and how the wire should be
modeled for enough accuracy without to much increase of
complexity requires further investigation. The output imped-
ances and switch resistances has been modeled as linear com-
ponents, although they are nonlinear. This is another source of
model errors.
C. Multi-Tone Linearity
In several communication applications a multi-tone input
signal is commonly used, e.g., discrete multi-tone (DMT). In
these cases, the multi-tone power ratio (MTPR) is an impor-
tant linearity measure. The MTPR is determined using M
tones with equal amplitudes, a , and equally spaced in the fre-
quency domain. One of the tones is left out, and MTPR is
defined as the ratio between the power of the used tones, i.e.,
a 2 / 2 , and the power of the distortion term appearing at the
leftout frequency position. This is illustrated in Fig. 8, where
M = 33 and a = 2 ” - ’ / ( 2 M ) to avoid signal clipping.
Besides the in-band distortion determining the MTPR, we
can also see that the nonlinearities introduce a significant
amount of distortion outside of the signal band.
Multi-tone properties are more complex than single-tone
properties. MTPR is strongly dependent on the peak-to-aver-
age ratio (PAR) of the signal, i.e., a higher PAR yields a lower
MTPR [SI.In the simulation presented in Fig. 8 there is a ran-
dom phase in each tone for reduced PAR.
SFDR vs Signal Frequency,10 MHz sampling frequency
80,
PSD plc4 for a multi-tone input, fsample = 10 MHz
-1 40;
0.1 0.2 0.3 0.4 ( 5
NormalizedFrequency
Fig. 8. Multi-tone spectrum for the DAC model using
a sampling frequency of 10 MHz.
VI. CONCLUSIONS
A simple state-space model of a CMOS current-steering
DAC has been presented, and used to characterize the single-
tone performance of a 14-bit DAC. Comparisons between
measurements and simulations verify the model to relatively
high accuracy, and the model explains some important limita-
tions on DAC performance. The concept of mismatch can eas-
ily be introduced in the model by simply changing the
numerical values of currents, impedances etc.
In some applications a higher accuracy behavioral-level
model can be desired. This can be done by introducing, e.g.,
nonlinear parasitics and transmission line model of wires.
However, a major advantage of the model is low simulation
times with relatively high accuracy. A refinement of the model
as discussed above will probably increase simulation times
significantly, perhaps to a level where a circuit-level simula-
tor, e.g., Spice or Spectre, inight be preferred.
ACKNOWLEDGMENTS
The authors would like to thank MSc. Niklas U. Anders-
son, Ericsson Microelectronics, for valuable discussions and
all help with DAC measurements.
I

\
REFERENCES
75 -
M. Gustavsson, J.J. Wikner, and N. Tan, CMOS datu converfers for
- communications, Kluwer Academic Publishers, Boston, U S A , 2000,
e
370
ISBN 0-7923-7780-X
-----
E
“65-
simulated ‘,
D.A.’Johnsand K. Martin, Analog integrated circuit design, John Wiley
and Sons, New York, U.S.A., 1997, ISBN 0-471-14448-7
Z.F. Jin, J.J. hurin, and Y. Savaria, “A new approach to analyze inter-

6o
55‘
1o5
t 1on
I
10’
connect delays in RC wire models,” in Proc. of the 1999 IEEE Int’l
Symp. on Circuits and Systems (ISCAS’99), vol. 6, pp. 246-249,
Orlando, FL,USA, May 30 - June 2,1999
Signal Frequency [Hz] T. Glad and L. Ljung, Reglerteori - jervuriabla och olinjara metoder,
Fig. 7. Simulated and measured SFDR as a function of the signal Studentlitteratur, Lund, Sweden, 1997, ISBN 91-44-00472-9
frequency. The sampling frequency is 10 MHz. AN971 8, Application Note, Intersil Corporation, April, 1997

671
Clock Jitter Compensation for Current Steering DACs
Andreas Wiesbauer, Dietmar Luis Hernandez Daniel Gruber
Straussnigg, Richard Gaggl,
Martin Clara Universidad Carlos III Telematics / Network Engineering
Madrid, Spain Carinthia Tech Institute, CTI
Infineon Technolgies Austria AG luis.hernandezguc3m.es Klagenfurt, Austria
Villach, Austria daniel.grubergedu.fh-kaernten.ac.at

Abstract-Clock jitter is an important source of error in high- digital means. Simulation results and the simulation setup are
speed current-steering D/A converters. A technique to discussed in section IV, revealing the required hardware
compensate these errors is introduced. Simulations show a complexity to significantly reduce clock jitter sensitivity for
significant reduction to clock jitter sensitivity for the example a 30MHz analog bandwidth, 12bit resolution SD DAC. We
of a Sigma Delta DAC with an analog bandwidth (ABW) of 30 consider random timing errors as the dominant timing error
MHz clocked at 360 MHz. throughout this paper, even though the method can handle
nonrandom jitter as well.
I. INTRODUCTION -------------------------------------
' ~~DAC
analogue signal
is well
It known, that continuous-time sigma-delta (CT digital analogue signal (+ errorej) corrected)
SD) ADCs suffer from sensitivity to clock timing errors signal DAC
caused dominantly by injection of these errors into the sigma
delta loop via the current steering DAC in the outermost ------------- -es---------
estimated
estimated
digntal
error esimal
~ 'esfimated
eo
feedback branch [1]. A model and an analytical description Clk
of the jitter error effect were described in [2]. The jitter esfimated
sensitivity is inherent to any current steering DAC either r---- errorsignal
used inside a CT SD ADC or as a stand-alone DAC. i
' j i er
ero
error

To reduce the clock jitter sensitivity..several methods are ~~~~~~~~~~~~measuring

... .. ' 0 estimation
ci * digital
known in the literature. The highest sensitivity is given if the correction
DAC has a low resolution [1], e.g. single-bit SD DAC. Jitter error modeling
analogue
correction
Therefore the sensitivity can be reduced by using multi-bit
DACs, at the cost of an increase in circuit complexity.
Another way to circumvent the problem is to use switched
capacitor (SC) DACs instead of current steering DACs.
However, SC-DACs don't allow as high update rates or II. JITTER ERROR ESTIMATION
cause higher power drain compared to switched current It was shown in [2] how the error introduced by jitter can
DACs. Furthermore, there are pulse-shaping techniquese, a tee
reoe whc tage to reuc clc jitrsniiiyb be modeled. Based on this model, a jitter-error estimation
reortedzich thcurrent pulse shape
optimizing the cuff ent pulse shape [3].
[3].*DACs,
hardware developed
theisdiscrete time next. For non return to zero coded
error sequence ej[n] induced by jitter
In this paper we introduce a method which in principle can be described by
allows removing errors caused by clock jitter. A block
diagram of the configuration is shown in Fig. 1. Essentially,
the error caused by the clock jitter is estimated and thereafter
subtracted in the analog or digital domain from the erroneous
ej [n] = (y[n]-y[n -l ]) - ATDACLn T
(1)
signal. If the estimated jitter error signal matches well with
the generated error signal a perfect compensation is obtained. where y[n] represents the digital signal and ATDAC[n] the
In section lI.the
jitter eror estimation is described in, time error in each clock-cycle and T the ideal clock period.
Therefore an error-estimation can be performed by
detail and a possible circuit implementation is presented. multiplying the time-error sequence with the first derivative
detail and aosibecicutimla.
Section III ws efent ementation of thejt of the digital signal, as depicted in Fig. 3.
error compensation where the error subtraction iS done by

0-7803-9390-2/06/$20.00 ©)2006 IEEE 5375 ISCAS 2006

A. Clock Jitter Measurement Accuracy requirements for the measurement circuit,
In order to get a representation of ATDAC[n] an analog such as gain error, offset error and noise, will be discussed in
circuit has to be developed. The approach suggested in this the simulation section and implementation-cost issues will be
shown...............
aril is current
artcl*isshwnin Fig. 2. A single-bit steering DAC summarized
and in theaconclusions.
I-DAC have However,
resolution of one bit both
only the
andSC-DAC
a fixed
(I-DAC) delivers a charge proportional to the clock period to
an integrator. At the same time, via a SC DAC, a fixed input set to '1', allowing simple circuit design.
amount of charge is subtracted. When properly dimensioned,
the charge stored in the integration capacitor is proportional III. JITTER ERROR COMPENSATION
to the time error in each clock-cycle. After a full clock cycle
the integrator is read out via an ADC and reset by closing the Fig. 4 shows the block diagram of a typical setup of a SD
switch across the integrating capacitor. For proper timing DAC, consisting of a DAC and a noise-shaper extended with
and readout it might be necessary to implement two such the before discussed implementation of the jitter error
circuits and operate them in ping-pong mode. Because, as compensation method. To allow an efficient DAC design the
will be shown in subsequent sections, the required accuracy well known digital noise-shaper concept [4] is used to reduce
of the measurement circuit is small compared to the accuracy the digital wordlength of the noise-shaper input X(z) (m-bit)
of the main converter, the area and power overhead incurred to the DAC input Y(z)( n-bit ).
by using this compensation method will be very limited.
As indicated before the clock jitter induces a jitter error at
the output of the DAC, which can be compensated by the
injection of an estimated digital jitter error E.(z) in the
SC L DA
measured
|feedback loop of the noise-shaper.
I bit, input--I . clock jitter digital noise-shaper
(analogue)
1- DAC ~~~~~~~~~~~~~~~~~~~X(z)
hbit)( bt
m

1 bit, inputi |LSBdigital analogue

Figure2. clock jitter measurement

_
RW

measured
clock jitter measured jitter error
(analogue) clock jitter measuring estimation
ADC(digital)
(digital) estimatedII
~~~~~~~~~~~~~~~~circuit
10 X jitter error
Figure 4. Noise-shaper DAC withjitter compensation
differentiated It follows from the linear model of a noise-shaper that an
digital signal error EJ(z) subtracted from the signal in the feedback loop of
digital T W
signal the noise-shaper will contribute to the output Y(z) of the
noise-shaper in the form
Y(Z) = X (Z)+ Eq (Z)(1 - R(Z)) - Ej (Z)R (Z) ' (2)
where R(z) is the transfer function of the loop filter in the
Figure3. Clockjittererrorestimation feedback branch as depicted in Fig. 4 and Eq(z) is the
quantization error. If properly dimensioned, (11-R(z)l)
<< 1
B. Jitter Error Estimation in the band of interest resulting in
Jitter error estimation is based on (1) and requires Y(z) X(z) - Ej (z) for f < (fample 1(20SR)) (3)
,

multiplying the measured clock time-error with the

difference of two consecutive samples (YSTEP). For single-bit
DACs YSTEP can have only three values (+1,-i,0). Therefore
the required hardware is negligible. Multi-bit DACs in
general require more hardware for the implementation.
However, if the DAC is of oversampling type, YSTEP is most
often limited to the range [±2,±1,O,-1,-2], again allowing a
cost efficient implementation of the multiplier.
at the output of the noise-shaper. This means that the
architecture in Fig. 4 provides a signal to the DAC which is
predistorted by the estimated jitter error E.(z). In case Ej(z) is
equal to the real jitter error at the output of the DAC, the
Jitter error is canceled perfectly.

5376
 IV. MODELLING AND SIMULATION RESULTS Additionally to the measured values the theoretical SNR
values achievable with the given long-term clock jitter were
The clock jitter sensitivity of a DAC with a noise-shaper calculated using the formula derived in [6]
for the wordlength reduction from 12bit to 6bit was K
evaluated. A clock of 360MHz for the DAC and an SNR=-20 logl 2zf ig " I|. (4)
oversampling ratio of 6 are assumed (30MHz bandwidth). y2fJ
The noise-shaper was designed for a peak Signal-to-Noise
Ratio (SNR) of 72dB. 80
Fig. 5 shows the PSD ofthe output signal ofthe modeled I III I I I
DAC including the jitter error and compensated with the 70 7QT
estimated jitter error. Furthermore the PSD of the modeled H \\
clock source, which resembles a typical PLL-type on-chip 60 - FT - .
-
rT- -1 T1 rFITr-
T F \-IrI T T -TI-T -I-

clock synthesizer [5], can be seen on the top right side. _ -_ _ -_ i < L- 1 -_-
504
0 __ _I_I liii I liii IQI liii I

~~~
~~~l II~>II

24011 signa -o
compensat on

-120
'
, 4
theoretical SNRfor givenGl1t 1 1 1 1 1 11 i1
i

-YF ,1 3 fi l t iM 30 1-iH~
II ~ -I-t -i -i -ig+ i_IIII i_ _4 __ _IIIII
+-- -i t=- =
I11
4 I11 I11
-4 ;~~=~~-=
'£j -812 -1 -^4410 -9Cit S
c20-ompina
9I~~~~Jrnl w/n w/ cmpesain
--------- -------------
-m ~~~~~~~~~~~f1010
-2MAOmignlwith 2orMpendtlinaoihno pnsto 0 e1i=0 10l0.X

W | iK i 6 1 M Xi [ " t . | ~~~~~~~~~Figure 6. SNR vs. clock jitter

-140>
Worcie of ban
o.; 0-0W ntflterst It
B. Quantized measured jitter
0 2 4 6 8 10 12 14 16 The second set of simulations includes a more realistic
lequency [Hz] X1 measurement of the clock jitter values. These were sampled
and quantized, simulating an analogue-digital conversion of
Figure 5. Spectrum ofFthe signal with jitter error and the jittered clock the clock jitter values.
(upper right corner)
pensation
corr
To show the impact on the performance of the w.
proposed
correction method several simulation scenarios were 70r-7alisi--c- K ----- V
investigated. As a size for the jitter intensity the long term me o co j- vals T S
rms-jitter (ola) was used. To measure the performance ofqthe 65 simlain a analogue-digital of
proposed jitter error compensation method the SNR vs. clock - - - -- -- - -
60t0 -F-Aes.- - + i \ <K- K
jitter is evaluated. corner)
- 1 4 1-G1 1 1 111 I
A. Idea/measurement and compensation z 50 - - -I -I-~-~~6
-~ -I - - A- - - 4 - +A- - - ---
For the first set of simulations ideal measured clock jitter I I 1111 I I II IIlll i
lXlI
values for each sample instance were assumed. The result of 45 -h--I_I- e-l - 4
these simuationsl aoncompensationFig.o6
tneseslmulatlonscanseseenmrlg.O. 40 \al jtralgeo.
wloo cl o |
400 clock jittersamplingresolution:2bic -
.. . . . ,. .|
,~~~~~~~~~~~clock
>| jitter sampling resolution: 3 bit i i i i i
At low jitter values quantization noise limits the SNR. 35 - clock jitter sampling resolution: 4 bit 4 L -_ _--
-
With increasing clock jitter, starting at 2ps, the SNR of the-r signal with ideal compensationI I I
uncorrected signal decreases linearly with the logarithm of 10-11 -10
the long-term clock jitter. The signal with compensation 10 t[si 10
shows much better performance up to high clock jitter
intensity. The decrease of the SNR at a long-term clock jitter Figure 7. SNR vs. clock jitter for different ADC resolution
intensity of about l00ps results from limitation of the
compensation values the values in the feedback loop may The modeled jitter error is no longer exact and introduces
not exceed reasonable size. The compensation does no additional quantizationnoiseinthe feedbackloop. Therefore
longer cancel the error fully but does still decrease it. the performance of the compensation deteriorates with
decreasing resolution of the ADC converting the clock jitter
values. Fig. 7 shows the SNR vs. clock jitter for different

5377
C. Influence of measurement errors

1) Gain error

Em
70

65 - - - --T-T

60

55
- -
----

-
I
I

I
l111
I-
.\ ~ ~ ~ ~ ~ ~ I I1 II\ I \
ADC resolution. The ADC had full scale at 5 times the
standard deviation of the cycle-cycle clock jitter values
which covers over 99°0 of the possible clock jitter values.

The final set of simulations was performed to show the

robustness of the jitter error compensation against
measurement errors in the clock jitter measuring circuit,
mainly gain and offset errors. Both result in lower
performance of the compensation method as they degrade
the jitter error estimation.

As can be seen in Fig. 8, the method is robust towards

gain errors. With a 1dB gain-error, clock jitter sensitivity
reduction by one order of magnitude is maintained. Gain-
accuracy of 1 dB can be achieved with conventional low cost
circuitry.

1111111
IIlulL
III

1111
1
I1-

Iit--
I
I

X1111I

lI
I___

-0
1 11 1 1Il
l11l l

I ~~~~~~~II I1I1I1I
--t
-
g
IN
4-11-
- Ii I II- I

-t
1
l l l l l l l l l

t
_ \_

x
I
--4\_-
_T 7
IC
compensation. The resolution of the jitter measurement is 8
bits lower than the converter resolution. Compared to the
main DAC the measurement DACs and integrator noise and
accuracy specifications are relaxed by a factor of 256,
leading to an almost negligible cost adder.

m C

l
EE

Zl I0-
75
704
65
60 -

35

..=
I
-1-
-

- - -

111
I

- - -i-

1-

---1-1-5IIiIK- I _
I_ ___
1

--
45 - --_ - -___I-
I
I I II-1114
- -I-I-I-I HI

-
I 1111111
--

I
-1-I
I I
__ I _ II Al--
-
I I
1-1-1

--1 - _-- - 4- - - - -¼_

signal w/o compensation
-G signal with ideal compensation

10
40
7

1-1-lX1-4
H--

offset error 10% ADCfull scale I I l

--
I I I

offset error20% ADCfull scale 1-1-I! L _

fullls
c al
offset error 50% ADCfullscale
-A I I

10
4 I
I I ii

[s]
-HI I

Figure 9. SNR vs. clock jitter for different offset errors

A-I-

-1-I 4-4

I4
-

liL

3
I
I

4X41

_I I I

I I I III
4-4 4~~~~~~~~~
4

1JA\I-1-0

1 1
W-
---]

4-I--- --]

-lo
-I_]

11WWWW
I
X

rr I I I1I111 V. CONCLUSIONS
z 50 - -- 1 11111
1 I 11It-+
+Ht --t
A method for compensating clock jitter errors was
- - + + -

41 I41
b I14
45 ---I--I--I-HI-HI-----H--t-H4-4I
45
I
--I

4I-
-4 A

presented. Sensitivity reduction of one order of magnitude

40
signal w/o compensation
signal with ideal compensation - K 4 4 1 K14 _
I IIIII
_--
\ M
was shown in the example of a 12bit 3OMHz analog
bandwith current steering DAC. Application of this method
-
x- gainerror of 1dB 1 1
35 gain error of 2dB - L 4 2 1 Ll l - X allows realizing high resolution data converters without the
gain error of 3dB l
I I I 1111 I ~need for clock sources exhibiting high spectral purity.
10~1 1o~0
Glt [s] REFERENCES
Figure 8.SNR vs.Figure
clock jitterSNR
[s] for different vs.cockjttersfodiffrentain[1]
. Cherry, J.A.; Snelgrove, W.M.; "Continuous-Time Delta-Sigma
gainerrorsModulators for High-Speed A/D Conversion", Kluwer Academic
Publishers, Boston, MA, 1999
2) Offset error [2] L. Hernandez, A. Wiesbauer, S. Paton, A. Di Giandomenico,
An offset error occurs if the jitter measuring circuit adds "Modelling and Optimization of Low Pass Continuous-Time Sigma-
a constant value to the measured clock jitter values. Due to Delta Modulator for Cock Jitter Noise Reduction ," Proceedings of
the estimation this error reduces the signal amplitude slightly 2004 IEEE ISCAS, May 23 - 26, pp. 1072-1075, May 2004
but shows little to no effect on the compensation if it is [3] M. Ortmanns, Y. MAnoli, F. Gerfers, "A Continuous-TIme Sigma-
within reasonable bounds. An offset error does only affect Delta Modulator with Reduced Jitter Sensitivity," Proc. of 28th
the performance of the compensation if it leads to saturation ESSCIRC, pp. 287-290, Sept. 2002.
of the error estimation circuit but this requires rather big [4] Candy, James;
Converters Temes, Gabor:
Theory,Design, and "Oversampling Delta-Sigma
Simulation". New Data
York: IEEE
offset values. The impact of an offset error on the Press,1992.
compensation performance can be seen in Fig. 9. With [5] A. Hajimiri and T. H. Lee, "The Desing of Low Noise Oscillators",
increasing offset errors the SNR curve drops sharply at lower Norwell, MA: Kluwer, 1999
intensity of the clock jitter. [6] N. Da Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer,
,,Numerical modeling of PLL jitter and the impact of its nonwhite
3) Noise spectrum on the SNR of sampled signals", in Proc. Southwest Symp.
Noise in the jitter measurement circuit will contribute Mixed-Signal Design 2001, Austin, TX
directly to the output signal. According to the simulations in
section IV- B, additional noise equivalent to 4bit
quantization noise will have little effect on the jitter

5378
 CLOCK-JITTER INDUCED DISTORTION IN HIGH SPEED CMOS
SWITCHED-CURRENT SEGMENTED DIGITAL-TO-ANALOG CONVERTERS
Jose' Luis Gonzdez and Edtrard Alarcdn
Department of Electronic Engineering, Universitat Politecnica de Catalunya,
Gran Capita s/n, Modul C4 Campus Nord UPC, 08034 Barcelona, Spain
Phone: +34 93 401 67 48, Fax: +34 93 401 67 56, E-mail: jlgonzalez@eel.upc.es
ABSTRACT
The design of high-speed CMOS current-steering (sometimes called
switched-current) segmented DAC converters requires an optimal
segmentation to balance area and performance requirements. In this
paper a new design criteria is introduced based on the effects of the
clock-jitter in the DAC spectral performance measured through the
SFDR. The study of the clock-jitter produced both by a random
process. independent of the input sequence. and by the dUdt noise
originated in the binary to thermometer decoder is presented. In this
later case the clock-jitter is not independent from the input sequence
and is related with the number of input bits assigned to the
thermometer code segment. Simulation results providing design
guidelines for selecting the proper segmentation are also given.
1. INTRODUCTION
Modern broad-band communication integrated circuits require as a
fundamental part of the system high-speed and high-resolution digital
to analog converters (DAC) [l]. Wide bit-count DACs working at
sampling clock fiequencies in the range of the hundred of MHz will
be required. The goal of this work is the evaluation of a 16 bit high-
speed current-steering DAC with thermometerhinary code
segmentation against clock-jitter produced by random noise and
switching noise (dl/dt noise). The DAC performance is analyzed
through the spurious-free dynamic range (SFDR) measurement. The
output waveform distortion of a DAC comes &om two sources. First.
the amplitude of the output current corresponding to a certain input
word may be slightly different from the expected value due to the
DAC output current sources MOS transistors mismatching [2].
Second. the output samples should be converted at futed times
determined by the input clock signal. However, a phase noise
superimposed with the clock signal produces slight time
displacements in the output samples. If the time displacements vary
from sample to sample. the output signal is distorted. The
thermometer code segmentation is used to reduce the distortion both
due to random mismatching by limiting the size of the largest output
current source and by avoiding input-dependent glitch energy [3].
Thermometer code also assures monotonicity. New switching
schemes for current-steeringsegmented DAC to rednce even more the
gradient based mismatching induced distortion have been recently
reported [4][5][6]. In this paper we will focus on the distortion
produced by the clock-jitter. Several authors have used as a criterion
to find the optimum DAC segmentation a trade-off between the
distortion due to mismatch and the area of the digital binary to
thennometer decoder [5]. The originality of this work is the
introduction of a third parameter in the optimization loop: the
distortion due to the sampling clock-jitter. The clock-jitter can be
related with the DAC segmentation because it can be originated by
the switching noise generated by the simultaneous switching of many
bits at the digital binary to thermometer decoder input. The larger the
1-5 12
0-7803-6685-9/01/$10.0002001 JEEE
thermometer section is the higher the maximum number of
simultaneous switching bits would be and hence. a larger clock-jitter
should be produced, because the noise induced in the internal power
supply lines dynamically affect the delay of the clock driver. In
section 2 the relation between the DAC architecture. the switching
noise amplitude and the clock-jitter is addressed. Section 3 presents
the high-level model of thel6-bit DAC converter and the simulation
procedure used for detennining the SFDR. Section 4 shows the SFDR
results obtained for different DAC segmentationschemes and various
clock-jitter amplitudes. Finally. section 5 summarisesthe main results
of the work.
2. INPUT DEPENDENT CLOCK-JITTER
PRODUCED BY DI/DT NOISE
Figwe 1 shows a block diagram of a 16-bit current-steering
segmented DAC. The n lowest bits of the input are the binary code
segment of the converter and they control directly the switches of the
N LSB binary weighted output cnrrent sources. The 171 highest bits are
the thennometer code segment. They are decoded to drive the
switching of 2"' output current sources. all of them of the same unary
weight. The size of the decoder increases exponentiallywith n7.
w u r data[li 01
clock
1n !I
I LhI;;;y II p
l ;,;!L, I
gir':'::,:"
Fig. 1. Segmented current-steering DAC.
2.1 dUdt noise generated by the decoder. When multiple bits of the
thennometer code segment (TCS bits) of the input signal switch
simultaneously. the decoder will generate dUdt noise (or switching
noise) at the internal power supply nodes. The amount of dI/dt noise
roughly depends on the effective power and ground pins package
inductance. the on-chip built-in decoupling capacitanceand the digital
current pulse shape. The later is determined by the logic signal rise
times. the saturation current of the gates output transistors and the
number of simultaneously switching gates [7]. In this way. there is a
relation between the TCS bits simultaneously switching and the
amount of switching noise that is generated. The maximum noise will
be produced when all the TCS bits make a simultaneous transition.
This. a larger 111 (the number of input bits assigned to the TCS)
increases the maximiun dUdt noise that is generated by the decoder in
the worst case. For the sake of simplicity it will be assiuned in this
work that the amplitude of the dUdt noise spike increases linearly
with the number of simultaneously changing bits. Tliis is justified by
the fact that the circuits with highest fan-out are the inverters that
complement the input bits and distribute them to several decoder
gates. For example. in the vicinity of the crossover point of a
sinusoidal input, one sample should be 01 11111111111111 and the
next should be 1000000000000000.If the thermometer code segment
has a length in = 8 bits, there will be a total of 8 simultaneous
switching large fan-out inverters at the input of the decoder.
Meanwhile, at the decoder output only one of the 256 bits will tum
on.
2.2 Clock jitter produced by the dUdt noise. The exact time at
which the analog output signal switches is fixed by the clock signal
edges. The clock driver generates the internal clock signal from an
external clock. The digital input codes are supplied to the
synchronized with the external clock. The input bits changes generate
Wdt noise at the internal power supply nodes, as explained before.
That noise is either coupled directly to the clock driver if it shares the
same digital power supply or it is coupled through the substrate if it
does not. The dVdt and/or substrate noise affects the delay of the
output driver. generating clock-jitter [SI. Figure 2 shows the
simulated delay change of a clock driver due to Wdt noise generated
by the decoder when multiple bits of the input code simultaneously
change. The simulation w a s performed using HSPICE with a 0.5pm
technology transistor models [9] and a typical clock driver circuitry.
not shown here for confidentiality reasons. The on-chip decoupling
capacitance and damping resistance are S pF and 1 R. respectively.
and the power supply package pins inductance is varied from 3 nH to
10 nH. The triangular current pulse used to model the decoder activity
is 500 ps wide and its amplitude is varied from 5 mA to 100 mA. The
input data is changed 3 ns before the clock rising edge. Even if the
current pulse due to the input data change is not simultaneous with
the external clock edge (as is the case here). the damped oscillation
generated by the dUdt noise pulse in the package-chip RLC resonant
circuit [lo] affects the internal clock edge delay. Different noise
levels from sample to sample produce different delay changes in the
clock driver and this is the cause of the internal clock-jitter. This
effect is much more pronounced than that due to thermal noise. as
shown in [SI.
h the following analysis it will be used a linear expression relating
the clock-jitter amplitude and the number of input bits simultaneously
switching based on the explanations of subsection 2.1 and the results
of figure 2. Only the changes in the TCS bits are relevant. In this way.
an increase in the size of the thermometer segment I I I will raise the
maximum clock-jitterand produce a lower SFDR. as s h o w below.
w as the slope of the linear relation between the number of bits changing
m from sample to sample and the delay added to tlie clock signal (i.e. an
Fig. 2. Clock signal delay changes caused by dVdt noise.
3. SIMULATION SET-UP
The model of the 16-bit DAC used for the simulations is based in the
work of [ll]. This model is implemented in the SABER simulator
[12]. An ideal ADC that samples an analog sinusoidal voltage source
generates the digital sample values. This ADC is implemented using a
C routine that obtains the samples by applying a successive
approximation algorithm to an analog input source (see figwe 3).
The ADC block provides the digital input word and the clock signal
to the DAC model. mhich performs the digital-to-analog coilversion.
This model contains a simple struchral description of the DAC itself
1-5 13
implemented using a binary array of switched current sources. In our
analysis all the non-idealities that may be included in the DAC model.
such as current source finite output resistance, different switching
times. parasitic elements and mismatching. are hmed off. since we
are interested only in the clock-jitter effects. In this case the binary
output structure can be used for both binary and thermometer
segments. The DAC incorporates a first order reconstruction output
filter with a cut-off frequency equal to half the sampling frequency.
The sampling frequency isfs = 105 MHz (sampling period T, = 9.52
us). The converter is sized to provide a differential output with a 2 V
maximum amplitude across a 50 R load resistor. The exact sizes of
the perfectly scaled output current sources are not relevant for the
results of the analysis because they are considered ideal current
sources without mismatching.
Fig. 3.DAC siinulation set-up
The clock-jitter is introduced in the ADC block that generates the
clock signal for the DAC by adding a variable delay to an external
clock signal (see figure 3). This delay can be of two different types.
One type causes a random clock-jitter. The other type causes input-
dependent clock-jitter and it is calculated from the number of TCS
bits changing from sample to sample using the model presented in
section 2. The number of TCS bits that change is multiplied by the
jitter amplitude. that is a parameter of the simulation.
In the case of the random jitter a uniformly distributed random
number is generated for every sample and the sample's clock delay is
calculated from that number. The amplihlde of the distribution of that
random number is also a parameter of the simulation.
In order to determine the effects of clock-jitter in the output signal
distortion and the relation ~ t theh DAC segmentation struchwe. a set
of simulations are performed. The parameters of the simulations are:
input frequency v,,). type of clock-jitter (random or input-dependent).
number of TCS bits ( n i that ranges form 0 to 16) and clock-jitter
amplitude. In the case of the random clock-jitter. the amplitude is
defmed as the 50% value of the positive uniform random distribution.
In the case of the input-dependent clock-jitter the amplihrde is defmed
amplitude of 0.5 ps/bit will produce a change in the clock signal delay
of 2.0 ps if 4 of the 111 input bits of the thermometer segment switch
simultaneously).
Three different input frequencies are selected (1.08 MHz. 5.13 MHz
and 10.9 MHz). Transient simulations are perfoimed containing SO
cycles of the input sinusoidal signal. Then the FFT of the analog
outpnt signal is obtained taking 131072 samples and usiug a H&g
window to obtain the frequency spectnun of the output signals and to
measure the SFDR.
4. RESULTS
4.1. Uniformly distributed random clock-jitter: When the clock-
jitter comes from a uniform random process (i.e. thermal noise or any
other source of switching noise coupled to the clock driver but not
correlated with the input code stream) the observable effect in the
output s i b a l spectnun is an increase in the noise floor. The results
are s h o w iu figure 4. where tlie noise floor obtained due to
quantization errors is also included as a lower boiiiid.
An increase of a factor of 10 in the jitter amplitude produces a 20 dB
increase in the noise floor. There is also depeudeuce with the input
frequencykampling frequency ratio. For lower ratios. the noise floor
is lower than for higher ratios.
Uniformelydistributedrandom clock jitter 16 bit DAC
f (AUsvAtchingt !s)
-40 1 P 80 I--to.5ps
a
70 -
U)
60-

- m
40 10 15 20

#bits in Thermometer code ( m )

tin = 5.13 MHz
0 2 4 6 8
Input frequency(MHz)
10 12

17- ’lo
100 Clock-jitter
amplitude

Fig. 4. Effects of random clock-jilter on the DAC perfonuance. P 80

Analytically, considering as the ideally sampled sinusoidal signal:
S ( l ) = Asirz(2&t) (1)
and assuming the random jitter to be described by a Gaussian
distribution of N(O.O;,,,~,) , the non-uniformly sampled jitter-distorted J
40 o 10 I 15 1
20
signal with uncertain sampling instants &can be properly modeled
-[13][14]- by a uniformly sampled signal with an amplitude error As. #bits in Thermometer code ( m )
though the mean of the slew rate, yielding an approximated noise fin = 10.9 MHz
power given by 110 7
Clock-jitter
amplitude
(AUsvAtchingb
The previous expression holds provided that the following coudition
P 80 -0.5~~
is fulfilled:
2 T L l ~ j l , , <<
w 1 (3)
Thus. fmally. the noise power due to the DAC jitter corresponds to:
(4) I
The 20 dB/dec dependence on b0th-L aiid jitter accurately models the 0 5 10 15 20
shulatiou results. When condition ( 3 ) does uot hold. the jitter- #bits in Thermometer code ( m )
induced equivalent noise tends to saturate as a functiou of6,. as can
be seen in figure 4. Fig. 5. Effects of input-dependent clock-jitter on the DAC
performance.
4.2. Input code dependent clock-jitter: hi this case. the clock-jitter
depends on the number of bits changing iu two consecutive input Iu the followiug. an insight on the saturation on the SFDR versus 111
codes. Only the changes of the TCS bits are accouuted for. The length curves is given. For small 111 values only the most significant bits are
of the thermometer code segment 111 is varied from 0 to 16 of a total of respousible of the clock-jitter. These bits change less frequently than
16 input bits. The SFDR results are shown in figure 5. the less significant bits. for an ordered sequence. A sinusoidal input
The SFDR depends on the segmentatiou until a certain III. and then produces an ordered sequence slowly changing in the mini” and
saturates. h the flat part of the curves the behavior of the SFDR is maximum of the waveform and rapidly changing in the crossover
equivalent to the case of random clock-jitter (there is a 20dB part. As 111 increases the less significant bits are included in the input
reduction of the SFDR for each 10x iucrease iu the jitter amplitude of the decoder. To assure that the sequence of all the 2N codes for a
and the same dependence with the input frequeucy/sampling given number of input bits (N) appear at the input of the DAC it must
frequency ratio. For 111 small (few TSC bits) the SFDR degrades be verified that in the worst case two samples of the sinus correspond
rapidly with increasing 111. to two consecutive quantization levels. This occurs at the crossover
The saturatiou in the SFDR versus ti? curves can be explained by part of the wavefonn where the slope is the highest possible. As just
looking at the samples binary value distribution for sinusoidal signals the 111 most significaut bits are connected to the decoder input. there is
showi in figure 6. The fi-we shows an histogram of the number of a limit ratio between the sampling frequency and the input frequency.
switching bits from cousecutive input codes corresponding to or equivalently. there is a limit 191 value that verifies that all the
different TCS lengths and for two iuput frequencies. As s h o w in the possible input codes are used:
figure. the average number of bits increases proportioually to the
leugth of the thermometer segment up to 111 = 8. For larger segments
[$)<- 1
2 ‘’I IT
the ceuter of the distribution does not change appreciably and it is ~I

around 6 to 7 simultaneous switching bits for the highest input
frequency and around 5 to 6 for the lowest freqneucy. This means that
the saturation point (the m value where the corner iu the SFDR ciirves
appears) depends on the input frequency.
For higher 111 some iuput codes are randomly skipped from the
ordered sequence (if there is no relatiou between the input and the
sampling frequency) and the number of TCS bits that change from
sample to sample behave as a random process.

1-5 14
 with the same effects on DAC performance show previously. There
fin= 10.9 MHr fin=1.03MHr
is a linear dependence with jitter amplitude (a 10x factor in jitter
amplihide reduces 20dB the SFDR) and with input frequency
(approximately 3dB of SFDR are lost for every 2x increase in the
input frequency).
The results obtained in this work reveal the importance of limiting the
1000 clock-jitter in high-speed DACs to values below 0.1% of the sampling
50 500 period by avoiding large Wdt or substrate noise that causes clock-
4m0 2 4 6 8 10 12 14 16 3ooo0 2 4 6 8 10 12 14 16 jitter and distorts the output signal. The influence of ni (the number of
350 thermometer code segment bits) is only important for small
300 segmentation ratios (nr 5 4). For larger segmentation ratios. SFDR
250 shows no dependence on nz. Several techniques can be used to reduce
200
150 1000
the dvdt or substrate noise. but they are out of the scope of this paper.
100
500
Interested readers are referred to the bibliography [7]. The
50
0 dependence with the segmentation ratio that has been found in the
4oo0 2 4 6 8 10 12 14 16 3ooo0 2 4 6 8 10 12 14 16 case of input-dependent clock-jitter is proposed as an additional
design criteria that can be used to find the optimal segmentation for
250 2000 high-speed current-steering DACs.
Acknowledgements. Work supported by CICYT Project No. TIC-469.
and by Fulbright fellowship FU 1998-0038446010.The authors would
like to thank David Anderson and Paul Hu, from Motorola, Phoenix (AZ)
and Prof Olgierd A. Palusinski form University of Arizona. Tucson (AZ)
for providing the simulation models of the driver and Guido Stehr and Tao
Wu for helping with the DAC SABER modeling.
7 250

1000
1500 k REFERENCES

3ooo0 2 4 6 8 10 12 14 16 [l] H. Samueli, “Broadband Communications ICs: Enabling high-bandwidth

2500 connectivity in the home and office”. in Proc. IEEE 1999 ISSCC, Feb.
m = 14 bits
1999,pp. 26-30.

?LL&.l
2000
%1
.,
0 500
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Number of swltching bits inside the thermometer code segment
Fig. 6 Nstograin of the number of swtchmg bits causlng clock-jitter
m the l6-blt DAC for two different mput frequencies and for vanous
thennoineter code segnent lengths
5. CONCLUSIONS
hi this paper the effect of clock-jitter in the performance of high-
speed segmented cuurent-steering DACs has been s h o w . The clock-
jitter affects the performance either by increasing the noise floor and
thus reducing the number of significant bits or by reducing the SFDR.
When a randoin process independent from the input sequence
originates the clock-jitter. the noise floor increases linearly with the
jitter amplitude. There is also a dependence with the input frequency:
for a fixed sampling frequency. higher input frequencies are more
affected by clock jitter than lower frequencies.
The clock-jitter is also produced by the switching noise generated in
the binary to thermometer decoder. The noise generated by the
decoder modifies the delay of the clock driver. The decoder switching
uoise depends on the input sequence. This. the dVdt originated clock-
jitter depends on the input sequence and on the decoder size. Larger
segmentation ratios produce larger switching noise because the
decoder comprises more bits. ln this case. dependence between the
SFDR and the thermometer segment size has been found. An increase
in the thermometer code segment bit count ( i n ) reduces the SFDR up
to a certain ni value. For higher i n values. SFDR reduction saturates
and does not depend on in. Thus the input dependent clock-jitter for
large segmentation ratios can be considered as random clock-jitter
[2] Marcel J.M. Pelgrom, Aad C. J. Duinmaijer, and Anton P.G. Welbers,
“Matching Properties of MOS Transistors”. IEEE J. Solid-Store Circriifs,
Vol. 24, NO.5, Oct. 1989,pp. 1433-1440.
[3] David A. Johns, Ken Martin. Analog Integoied Circriit Design. John
Wiley& Sons. Inc. New York, 1997.
141 Geet A. M. Van der Plas, Jan Vandendbussche,Willy Sansen, Michel S. J.
Steyaert, and Geroges G.E. Gielen, “A 14-bit Intrinsic Accuracy Q’
Random Walk CMOS DAC, IEEE J. Solid-Side Circtiit.y, Vol. 34, No.
12,Dec. 1999,pp. 1708-1717.
[ 5 ] Chi-Hung Lin and Klaas Bult, “A 10-b, 500-Msaples/sCMOS DAC in 0.6
“2..
, IEEE J. Solid-Strite Circiiits, Vol. 33, No. 12, Dec. 1998, pp. 1948-
1958.
161 Yonghua Cong, and Randall L. Geiger, “Switching Sequence
Optimization for Gradient Error Compensationin Thermometer-Decoded
DAC Arrays“, IEEE Tr. on Circriits rind .y\srenn-II, Vol. 47. No. 7, July
2000. pp. 585-595.
[7] Xavier Aragones, Jose Luis Gondez. and Antonio Rubio,. Ano!isis ond
Soliitions for Siiitching Noise Coripling in Mixed-Signril ICs. Kluwer
Academic Publishers.Boston, 1999.
[SI F r d Herzel, and Behzad Razavi, “A Study of Oscillator Jitter Due to
Supply and Substrate Noise”, IEEE Tr. on Circriits rind Sistenrs-ll, Vol.
46, No. 1, Jan. 1999,pp. 56-62.
[9] MOTOROLA 0.5pm proprietalyprocess.
[IOIPatrik Larsson, “Resonance and Damping in CMOS Circuits with On-
Chip Decoupling Capacitance”. IEEE Tr.on Circriits rind Ststenid, Nol.
45, No. 8, Aug. 1998,pp. 849-858.
[11]Guido Stehr. Behcwiorircil Modelling of o High-precision, High-speed
Digitcil-to-rincinlog Converter, Master’s Thesis. Universitat Karlsruhe
(TH). Germany, 1999.
[12]Sober Sinriilrrror Ver 5.0, Analogy Inc.. Beavrton, OR (USA)
[13] Selim Saad Awad, ‘Analysis of Accumulated Timing-Jitter in the Time
Domain’, IEEE Tr. on Instrrinientritionrnid Memrirenrent, Vol. 47, No. 1,
Feb. 1998,pp. 69-73.
[14]Ham0 Kobayashi, Masanao Moriniura, Kensuke Kobayashi. and
Yoshitaka Onaya, ‘Aperture Jitter Effects in Wideband Sampling
Systems’,Proc. of IMTC‘99 Conference, 1999. pp. 880-885

1-515
 Combining DACs for Improved Performance
K. Ola Andersson1,2, Niklas U. Andersson1,2, Mark Vesterbacka1, and J. Jacob Wikner3
1Dept. of E.E., Linköping University, 581 83 Linköping, Sweden, fax +4613139282
2LiDC, Ericsson Microelectronics AB, Box 1554, 581 15 Linköping, Sweden
3SDC, Ericsson Microelectronics, Westmead Dr., Swindon, SN5 7UN, UK, fax +441793490151
E-mail: {olaa, niklasa, markv}@isy.liu.se, jacob.j.wikner@mic.ericsson.se
Summary For higher signal and updating frequencies dynamic er-
This work is an overview of recently proposed methods rors tend to be the limiting factor on the linearity. One
on combining DACs in order to improve performance. source of dynamic nonlinearity is the nonzero output ca-
Some further development of these techniques are also pacitance of the current sources, causing signal depend-
presented. The techniques aim at reducing glitches and ent settling errors, which in turn yields an overall
sensitivity towards limited output impedance in current nonlinear behavior. This phenomenon was modeled with
sources. Matlab in [5]. The equivalent circuit representation of
that Matlab model is shown in Fig. 1(b). It includes the
Keywords: D/A conversion, glitches, nonlinearities
output capacitance and resistance of the current sources,
1. Introduction switch resistance, wire resistance and capacitance. In
Today’s telecommunication applications require high- Sec. 4 we give an example on how to use two sub DACs
speed and high-resolution data converters. In, e.g., digital to reduce the distortion due to limited output impedance
subscriber line (DSL) applications the requirements on by introducing redundancy which allows the common-
the digital-to-analog converter (DAC) is in the order of mode signal to be varied.
12-14 bits of resolution and several MHz of signal band-
2. General multi-DAC concept
width. These requirements are not always easily fulfilled,
Assume that we have an N -bit DAC consisting of a set of
and in this work we give an overview of some recently
M parallel sub DACs, with their outputs summed to pro-
proposed techniques utilizing several sub DACs com-
duce the total output. The number of weights in the sub
bined into one DAC for improved performance.
DACs are chosen so that the overall N -bit resolution can
The current-steering approach (see Fig. 1(a)) is often
used in high-speed applications, since the architecture en-
ables fast operation. The performance is however often I0 Ij IN-1
limited by linearity problems. Mismatch between the
transistors in the current sources causes errors in the bit b0 bj bN-1
weights and limits the static linearity of the DAC. To
solve this problem calibration or randomization tech-
I+ I-
niques, so called dynamic element matching (DEM, see A+ A-
e.g. [1]), are often suggested. In some applications distor-
tion is more crucial than the noise, especially in oversam- RL RL
pled systems where much of the noise typically can be (a)
filtered out. DEM techniques utilize redundant codes and
randomization to transform distortion into noise with the
benefit of linearizing the device but introducing more
switching activity and hence noise. There are schemes to
minimize the glitching activity and still maintain a rea-
sonable amount of randomization [2, 3]. It is also known
that the glitching activity is reduced by using special
codes, such as segmentation of the MSBs or other ar-
rangements. In this work we overview different ways to
combine a pair of converters to reduce the glitches to a
relatively low (digital) hardware cost. In Sec. 3 we high- (b)
light an example where the converters are linearly coded
[4] yielding low glitch errors. Figure 1: (a) Ideal and (b) model of current-steering
DAC including parasitic resistances and capacitances.
be met. The input to each sub DAC is denoted X m . We
let the outputs of the sub converters, A m+ and A m– , be dif-
ferential, where A m– = A mmax – A m+ . A mmax is the maxi-
mum amplitude that can be represented by the given sub
DAC. The sum of inputs equals the overall input and the
sum of the outputs equals the wanted output.
In e.g. [1] investigations are presented on how the influ-
ence of analog errors can be spectrally shaped and atten-
uated in the signal band. The investigations use the
concept of DAC banks and then digital encoding circuits
to redistribute the signal to the different DACs. As men-
tioned, the drawback with these methods is the increased
switching activity and in e.g. [2] and [3] we find methods
to reduce the glitching and still maintain randomization at
a reasonable low hardware cost.
3. Combined DACs with small relative
glitch error and DEM
In this section we present a DAC architecture that can be
used to improve the glitch performance of high-speed and
high resolution D/A converters. The basic architecture
was previously presented in [4]. In this work we also
show how a simple form of DEM can be incorporated in
the structure.
3.1 Linear-coded DAC architecture
A linear-coded DAC is obtained by weighting the cur-
rents in Fig. 1(a) according to I j = ( j + 1 )I 0 , j = 0, 1,…,
n–1 [4]. An interesting property of the linear-coded DAC
is that the glitch magnitudes are small for transitions in-
volving low values, and become increasingly larger for
transitions involving higher values. The distribution of
glitches is rather different from, e.g., a segmented con-
verter, which has a constant envelope of glitch magni-
tudes for all values. The property of nonuniform glitch
distribution can be utilized to design a DAC with low
glitch magnitudes around the DC level, i.e. a DAC with a
small relative error with respect to glitches. This is ob-
tained by connecting two linear-coded DACs in parallel
according to Fig. 2, where one DAC converts negative
values, and the other positive values. Note that the 4:1
multiplexers are used to illustrate the principle. In an im-
plementation they can be simplified to one layer of AND
gates.
To explain the function of the combined DAC architec-
ture we set the control input P(n) to zero. The magnitude
of the input will be linear encoded. If we have a positive
input, then the sign of the input is used to connect the lin-
ear-coded word to DAC 2 via the 4:1 multiplexer. Mean-
while, DAC 1 outputs the highest value that can be
represented. Assuming a binary-weighted number repre-
sentation, this corresponds to inverting all bits of a zero
as illustrated in Fig. 2. On the other hand, if the input is
Linear 0
DAC 1 A+
X(n) |X|
encoder
0
0 Ij=(j+1)I0 A
0
–
X<0
0 0
DAC 2 A+
0 0 Ij=(j+1)I0 A
–
I– I+
P(n) RL RL
Figure 2: Proposed linear-coded DAC architecture
with small relative glitch error and DEM.
negative, the linear-coded word is inverted and connected
to DAC 1, i.e. the inversion causes an increase in magni-
tudes to a corresponding decrease in the output. DAC 2
outputs zero.
The control input P(n) has been designed to change role
of DAC 1 and DAC 2 with respect to the sign of the data.
Hence, a simple form of DEM can be incorporated in the
structure by connecting this input to a pseudo-random bi-
nary sequence (PRBS) generator that alternates the use of
the DACs randomly. Note that this improvement requires
little additional hardware. The overhead is a layer of
XOR gates compared with the solution presented in [4],
plus the PRBS generator.
3.2 Simulation
To characterize the amount of glitching in the DAC we
use a first-order model that considers the glitch magni-
tude G(X(n–1), X(n)) to be proportional to the sum of
weights involved in a transition from value X(n–1) to
X(n). In Fig. 3 the glitch magnitude is plotted for two 14-
bit DACs, where a conventional segmented DAC with
seven thermometer-coded most-significant bits is simu-
lated in (a), and the new DAC-architecture is simulated in
(b). A ramp with a slope of one has been used as input to
both DACs. If larger transitions are investigated, e.g., by
increasing the slope, the trend is that the glitch error is in-
creased, but the distribution is similar. The plot indicates
that we can expect about the same worst-case glitch mag-
nitudes for both DACs, but a much improved behavior
around the DC level for the combined linear-coded DAC
architecture.
4. Combined DACs for immunity towards
limited output impedance
In this section we present another redundant DAC archi-
tecture that can be utilized to limit the impact of finite
output impedance in the current sources. This architec-
ture was previously presented in [6], together with a few
examples on how utilize the redundancy. In this work we
also present a further developed method of utilizing the
redundancy.
 300 r(n) is a control signal and X max is the maximum value
of X , which occurs when b i = 1 for all i . If X is binary
250
coded, then X max – X is achieved by inverting all indi-
vidual bits of X , motivating the inverter symbol in Fig. 4.
200
The A – terminals of each DAC is connected to a silent
DC voltage V dump . With ideal DACs, the control signal
(X-1,X)

r(n) is added to both output currents (multiplied with the

150
gain of the DACs). For the differential current,
seg
G

I diff = I 1 – I 2 , the same operation as is achieved as be-

100
fore. This architecture is redundant in that there are sev-
eral ways of representing the differential signal with
50
different common-mode signals, since r(n) is added to
the common-mode input signal ( X 1(n) + X 2(n) ) ⁄ 2 . One
0
-8000 -6000 -4000 -2000 0 2000 4000 6000 8000 factor that limits the possibly useful control signals is the
X
common-mode rejection of the following circuitry.
300
In an implementation, the two DACs have to be mutually
well-matched, preferably manufactured on the same die,
250
sharing same master bias, etc. It is also important to avoid
clock skew between the two DACs, and therefore it is de-
200
sirable that they share the same clock net. Obvious pen-
alties, compared to conventional DACs are increased
G (X-1,X)

150
area requirements and power consumption
lin

100 A+
X1(n)
DAC1
50 A-
X(n) r(n)
0 Vdump
-8000 -6000 -4000 -2000 0 2000 4000 6000 8000
X
A+
X2(n) I2 I1
Figure 3: Glitching in 14-bit DACs with (a) DAC2
conventional 7-bit segmented architecture and (b) the A- RL RL
proposed linear-coded architecture.
4.1 Architecture overview
The single-ended output currents for the ideal current- Figure 4: Proposed redundant differential DAC
steering DAC in Fig. 1(a) are given by architecture.

I+ = Iu ⋅ ∑ b i ⋅ w i and I – = I u ⋅ ∑
N–1 N–1
b i ⋅ w i , (1) 4.2 Simulations
i=0 i=0 One choice of r(n) discussed in [6] is a random dither
and the differential output current by signal with a given amplitude. This choice of r(n) yields
N–1 N–1 a form of DEM. Another choice that was mentioned in
I diff = I + – I – = 2 ⋅ I u ⋅ ∑ bi ⋅ wi – I u ⋅ ∑ wi (2) [6], is to choose r(n) as the smallest constant signal
avoiding overflow of X 1 and X 2 . In this way the parasit-
i=0 i=0
ic load at the output nodes is lowered. This approach is
where I u is the unit current, b i is bit i of the input code
only applicable to a limited class of signals, i.e., the ones
X , b i is the inverse of b i , and w i is the weight of bit i .
that do not utilize the possible input range, and need to es-
The proposed redundant architecture is shown in Fig. 4, timate the maximum value of all future samples of the in-
composed of two parallel, nominally identical, current- put signal. In this work we modify this approach and
steering DACs (DAC1 and DAC2). The input signal to instead choose r(n) as the smallest integer fulfilling the
DACi is denoted X i(n) , where boundary conditions
X 1(n) = X (n) + r(n) and (3) r(n) ≥ – min(X (n), X max – X (n)) = r min(n) and (5)
X 2(n) = X max – X (n) + r(n) . (4) r(n) – r(n – 1) ≤ ∆r max (6)
Boundary condition (5) ensures that overflow is avoided, 3−tone PSD for conventional DAC
and ∆r max is chosen such that the common mode varia- (a) 0
tions can be sufficiently rejected in following circuitry (in
the previous approach, ∆r max = 0 ). The boundary con- −20
ditions should hold for all n , so we need to keep track of
a few future samples of X , otherwise we risk choosing −40

PSD [dB/Hz]
r(n) too small to fulfil both (5) and (6) for some future
sample. However, since we need to keep track of less −60
samples than before, this approach is more suitable for an
actual implementation. −80

In Fig. 5(a) and (b) we show simulated 3-tone PSD plots

−100
for a single DAC and for the proposed redundant DAC
with r(n) chosen as above respectively. The simulation
−120
model is a 14-bit binary weighted version of the one pre- 0 1 2 3 4 5
Frequency [Hz] 6
x 10
sented in [5] (see Fig. 1(b)), parameter values are given
in Table 1, and ∆r max = 20 . The peak-to-peak value for 3−tone PSD for redundant architecture
this particular input signal is approximately 10600, and (b) 0
the spectra have been normalized with respect to the peak
power. The largest distortion term is reduced from –72 −20
dB to –82 dB.
−40
PSD [dB/Hz]

Parameter Value
−60
Output resistance (unit current source) 1 GΩ
Output capacitance (unit current source) −80
5 fF
Switch resistance (all switches) 100 Ω −100

Load and wire resistance 100 Ω

−120
0 1 2 3 4 5
Load capacitance 200 pF Frequency [Hz] 6
x 10

Table 1: Simulation parameters and their values.

5. Conclusions
We have presented ideas on how to combine multiple
DACs in order to improve the performance in terms of
glitches and decreased sensitivity towards limited output
impedance.
References
[1] I. Galton, “Spectral shaping of circuit errors in digit-
al-to-analog converters,” IEEE Trans. on Circuits
and Systems II, vol. 44, no. 10, Oct. 1997, pp. 808-17
[2] M. Rudberg, M. Vesterbacka, N. Andersson, and
J.J. Wikner, "Glitch minimization and dynamic ele-
ment matching in D/A converters," IEEE Proc. The
7th Int. Conf. on Electronics, Circuits, and Systems,
ICECS’00, vol. 2, Beirut, Lebanon, Dec. 17-20,
2000, pp. 899-902.
[3] C. Lyden and A. Keady, “Tree structure for mis-
match noise-shaping multibit DAC,” IEE Electronics
Letters, vol. 33, no. 17, Aug 14, 1997, p. 1431-2
Figure 5: Simulated 3-tone PSD plot for (a) a single
(conventional) DAC and (b) the proposed redundant
architecture.
[4] M. Vesterbacka, "Linear-coded D/A converters with
small relative error due to glitches," Proc. IEEE 2001
Midwest Symp. on Circuits and Systems, MWS-
CAS’01, vol. 1, Fairborn, Ohio, Aug. 14-17, 2001,
pp. 280-3
[5] K.O. Andersson and J.J. Wikner, "Characterization
of a CMOS current-steering DAC using state-space
models," Proc. IEEE 2000 Midwest Symp. on Cir-
cuits and Systems, MWSCAS’00, Lansing, Michigan,
USA, Aug. 8-11, 2000
[6] K.O. Andersson, N.U. Andersson, M. Vesterbacka
and J.J. Wikner, "A differential DAC architecture
with variable common-mode level," accepted to
IEEE International Symposium on Circuits and Sys-
tems, ISCAS’02, Scottsdale, Arizona, USA, May 26-
29, 2002
ESSCIRC 2002

Current Mode Deglitcher for Current-Steering DACs

Jussi Pirkkalaniemi, Mikko Waltari,

Marko Kosunen, Lauri Sumanen,
Kari Halonen
Helsinki University of Technology
jussi.pirkkalaniemi@hut.fi

Abstract Current Bias 5 Digital Trimming

Biasing
A current mode track-and-hold circuit designed for IB,LSB IB,MSB
1 : 256
deglitching a 14-bit current steering DAC is presented.
The deglitcher is based on a developed highly linear cur- LSB MSB
rent memory. The prototype circuit is designed using a 8 Binary Weighted 2 Binary Weighted
+

0.35-m BiCMOS (SiGe) technology. According to mea- Current Sources 15 Nonweighted

Current Sources
Digital
surements, a -66.8-dBc THD is achieved with a 9.1-MHz Input
14
1 8 1 17
4 to 15 15
input signal and 30-MHz clock frequency. Two-tone test encoder 25
Latches Current Switches
gives intermodulation levels below 68 dBFS at 40-MS/s 10
sampling rate. The power dissipation is 360 mW from a DAC Clk
IDAC+ IDAC-

3-V power supply. 1 Clk+ Clock

Clk- Buffer
DG Clocks Deglitcher

1. Introduction IOUT+ IOUT-

Current Output

Traditionally the applications of high-speed DACs
have been in video and computer graphics applications,
but recently the migration to wideband wired and wire-
less telecommunication standards and the evolution of ra-
dio transmitter architectures toward the software-defined
radio have created a need for high-speed, high-resolution
telecommunication DACs.
In the past the research and development of DACs
have been heavily concentrated on improving the static
(DNL, INL) and, to some extent, the time domain specifi-
cations (settling time, glitch area), almost totally neglect-
ing spectral purity and other frequency domain character-
istics that are essential in telecommunication devices.
Practically all high-speed DACs are based on the cur-
rent steering architecture, one of the main reasons for
this popularity being its capability of driving resistive
loads without buffering. A 14-bit static linearity has
been achieved by using trimming, self-calibration [3],
and even intrinsically [1]. A typical problem in these
DACs is the rapid increase in harmonic distortion when
the signal frequency is increased. This is mainly due to
the glitches occurring at the code changes. The glitches
are results of incoherent timing of the current switches,
non-optimal shape of the switch control waveforms, and
coupling of the digital signals to the analog output.
Attempts to reduce glitches include the use of latches
to synchronize the switch controls, circuits to generate
1 This work was supported by Nokia Networks and the Finnish Na-
tional Technology Agency (TEKES).
Figure 1. Block diagram of the DAC.
optimal control waveforms for the switches, and the use
of return-to-zero-type output to suppress the output dur-
ing the code changes. The return-to-zero technique uti-
lized in [2] yields a clear improvement in high-frequency
SFDR compared to earlier reported DACs, but still has
some limitations, such as the difficulty of providing large
amplitudes to a low-resistance load, the complicated cir-
cuitry needed to handle signal dependent parasitics, and
sensitivity to clock jitter, which is not relaxed, unlike in
conventional DACs, when signal frequency is decreased.
To alleviate the first two of these problems the same
authors have proposed the track/attenuate technique [3],
which is basically a switch put in parallel with the load to
short the output during the DAC switching.
To avoid the jitter problem and signal attenuation it is
possible to use a track-and-hold circuit as a deglitcher;
the DAC is cascaded with a T/H circuit which tracks the
DAC output when it is in steady state and holds a sampled
voltage during DAC settling. Although the deglitcher
does a good job of removing code-dependent glitches it
typically cannot achieve as high a speed as a current-
steering DAC and, furthermore, the voltage output pro-
vided by the T/H needs to be buffered in order to drive
resistive loads.
The deglitcher presented here is based on current
mode circuitry. The output is provided in the form of

479
 a current which eliminates the need for a buffer. A high Digital input IOUT+

speed is achieved by employing parallelism. The circuit Vb1

DAC clk Current
Vc3
M1 Steering
does not rely on matching, which makes it very robust DAC M3

and eliminates the need for calibration. IDAC- IDAC+

Vc1 M2

2. Architecture
Clk-
Clk+ Clk+
The core DAC, shown in Figure 1, is based on seg-
mented architecture. The current sources are divided I3 I4
into two unit current source arrays, with 8 LSBs in one Clk1 Current
memory
Clk2 Current
memory

and 6 MSBs in the other. In the LSB array the current 3 4

sources are binary-weighted and constructed of parallel

Figure 2. The deglitcher.
unit sources distributed around the matrix to compensate
for linear and center-symmetric process variations. In Clk+
the MSB matrix the two least significant bits are binary- Clk-
DAC clk
weighted and the remaining four are formed with 15 un- Clk1
Clk2
weighted sources constructed of four unit sources laid
I3
out in common centroid geometry. To reduce cumula- I4
tive mismatch errors, the consecutive unweighted sources
are selected in such a manner that if one source is con- Figure 3. Clock signals.

structed of transistors on the periphery of the matrix, the

next one will have its transistors closer to the center, and
vice versa.
The current bias for the LSB and MSB arrays is gen-
erated in a bias array from a single external reference cur-
rent. The bias array is a current mirror that generates two
currents, the LSB bias being 1/64 and the MSB bias 4
times the reference. The current ratio can be manually
trimmed with an external 5-bit control signal.
The current switches are controlled with a 10-bit bi-
nary code and a 16-level thermometer code, which are
synchronized with a latch stage before the switches.
The DAC output is connected to the deglitcher, which
requires a 1.75-V voltage headroom; thus, the DAC has
to fit within 1.25 V when a 3.0-V supply voltage is used.
This has an effect on the sizing of the current sources and
the DAC switches; the current sources are biased to a 1.2-
V gate-source voltage to minimize the effect of threshold
voltage variation in the available voltage headroom.
The clock signal is brought into the chip in differen-
tial form to improve the noise rejection on the board and
package level.
the DAC output current. At the end of the phase the feed-
back loop is opened and the current gets sampled in the
memory. In the hold phase the current memory acts as a
current source, whose value is the one stored in the mem-
ory. In this phase the circuit is connected to the external
load. Since the current value is set by feedback and kept
unchanged when the circuit is connected to the load, no
accurate matching is required between the current mem-
ories.
The clock waveforms for the circuit are shown in Fig-
ure 3. The DAC is clocked at the full rate, while the
deglitcher uses a set of half-rate clocks. The current
switches are controlled with the complementary signals
Clk+ and Clk-, which have a 50% duty cycle. Signals
Clk1 and Clk2 are non-overlapping clocks for the current
memories. Two currents I3 and I4 are also shown to clar-
ify the operation.
A more detailed implementation of the deglitcher
is shown in Figure 4. There, the current switches are im-
plemented with bipolar transistors and a cascode transis-
tor is inserted between the current switch and the circuit

3. Deglitcher Digital input IOUT+

DAC clk Current

The principle of the deglitcher is shown in Figure 2. It Vb1 M1 Steering Vc3
M3
consists of four single-ended current mode sample-and- DAC
IDAC- IDAC+
hold circuits and four switch pairs that operate in time- Vc1 M2
interleaved fashion. During one clock cycle the DAC dif-
ferential output current is sampled into two current mem-
Clk-
ories and the other two supply to the output the current Clk+ Clk+
which has been sampled in the previous clock cycle. This
way the DAC is never directly connected to the output I3 I4
Clk1 Clk2
and the sampling phase is extended to cover nearly the Current Current
Memory Memory
whole clock cycle, maximizing the speed. 3 4

In the sampling phase the current memory is enclosed

in a feedback loop that forces its current to be equal to Figure 4. Implementation of the deglitcher.

480
output. In addition, a cascode current source is added in
parallel with the DAC to bias the current memory. The
base currents of the switch transistors—as long as the
transistors in the switch pair are matched—are not a prob-
lem, since the switches are enclosed in the feedback loop
when the current is sampled.
3.1. Current Memory
Typically, the current memories are based on a MOS
transistor whose gate capacitance is used as an internal
storage element, while the memory input and output are
both the drain current.
As regards high resolution applications, the most se-
vere limitation of this circuit is the harmonic distortion
originating from the sampling switch charge injection.
The nonlinear relationship between the gate voltage and
the drain current results in a situation where even a con-
stant charge injection produces harmonic distortion in the
output current. Moreover, the switch operates against
the gate voltage (V G ), which makes the charge injec-
tion signal-dependent. Ways of reducing the effect of
the charge injection range from the use of differential cir-
cuitry and dummy switches to the very accurate S 2 I tech-
nique [4].
In this design the approach taken to achieve 14-bit
resolution is two-fold. First, the linearity of the current
memory is maximized to make the circuit less sensitive to
the constant charge injection, and second, the signal de-
pendency of the charge injection is significantly reduced.
Furthermore, when the current memory is linear, even an
error linearly dependent on the signal can be tolerated,
since it only affects the signal amplitude.
The current memory is shown in Figure 5. The gate-
source voltage of the sampling switch (MS) is made vir-
tually constant by using bootstrapping. Neglecting the
bulk effect, this makes the channel charge, as well as
the injection resulting from its release, constant. The ac-
tual switch realization is based on the circuit presented
in [5]. Bootstrapping is also a reliable way to increase
the gate voltage above the supply voltage without vio-
lating the technology reliability specifications [6]. The
maximum gate overdrive yields a low on-resistance with
a small switch transistor, minimizing the nonlinear para-
sitic capacitances, which are effectively in parallel with
the memory capacitor.
Besides the channel charge, there is also charge re-
distribution in the gate overlap capacitance C Gol . Since,
when entering the off-phase, the switch gate is pulled to
a constant voltage, the resultant signal-dependent error
charge is CGol
VG . When the capacitances are constant
(which is mostly true) and the current memory linear the
error results in only a small change in signal amplitude.
If necessary, this error could be avoided by switching the
gate to a voltage that is the V G properly buffered and
level-shifted.
The high linearity of the current memory is based on
the fact that the transistor M1 (Figure 5) is biased in the
triode, not the saturation, region. There, the drain current
is given by
 
Cox W VDS
2
ID = (VGS VT ) VDS : (1)
L 2
Now, if the drain-source voltage is kept constant, the cir-
cuit is perfectly linear. To make the voltage on the drain
as constant as possible M1 is cascoded with the bipolar
transistor Q1, which has an inherently large gm, which
is further boosted by using regulation. To achieve a high
linearity it is necessary to bias the transistor M1 deep in
the linear region. The cascode current source, consisting
of M2 and M3, is for biasing M1.
The sampling speed of the deglitcher is determined
by the time constants associated with the feedback loop.
When the loop is broken at the gate of M1 (leaving the
capacitor C1 on the output side) there is only one high
impedance node (the DAC output), which justifies the
use of the single pole approximation, giving the follow-
ing gain-bandwidth product:
gm1
GBW = ; (2)
C1 + CDAC
where gm1 is the transconductance of M1 and C DAC the
DAC output capacitance. Since the transconductance (to-
gether with the full-scale output current) determines the
voltage swing on the memory capacitor and the capacitor
value the sensitivity to charge injection and noise, there
is a tradeoff between speed and accuracy. The sampling
switch on-resistance and the other nodes in the loop pro-
duce non-dominant poles that affect the phase margin.
3.2. Limitations
A potential problem in all circuits using time inter-
leaved parallelism is mismatch between the parallel cir-
cuits. Such mismatch can produce an offset component
at half the clock frequency and a spectral image of the
signal around it. Similar image can be generated by a
clock skew in the half-rate clocks. Therefore any devia-
tion in the timing of the current switches should be min-
imized. The current memory-based deglitcher, however,
does not rely on matching as long as charge injections of
bootstrapped sampling switches and base currents of the
current switch pairs match. To reduce the skew error the
half-rate clocks for the current switch control circuit are
generated by dividing the full-rate clock with a carefully
matched synchronous divide-by-two circuit constructed
with a fully differential D-flipflop. For prototyping pur-
poses a manual rise time control circuit was included in
the signal path for fine-tuning the duty cycle.
4. Experimental Results
The circuit was designed using a 0.35-m BiCMOS
(SiGe) technology and the chip (Figure 6) occupies a to-
tal 5.7 mm2 of silicon area. The majority of the area is
consumed by the DAC current sources, the deglitcher be-
ing only a small block on the lower right corner of the
481
 IMEM POWER SPECTRUM @ 30 MS/s
10
Vref + M2 f
sig
0
A1 Q1
Clk − M3 −10
n1
−20

SIGNAL POWER [dBc]

Fb_in −30
M1 biased in
MS triode region
bootstrapping −40
circuitry C1
fclk/2
−50

−60
Figure 5. BiCMOS current memory cell. 2fsig

−70

−80

−90
0 2 4 6 8 10 12 14 16
Frequency [MHz]

Figure 7. Spectrum with a full-scale input signal.

POWER SPECTRUM @ 40 MS/s

0
f1 f2

−10

−20
Figure 6. A microphotograph of the chip.
SIGNAL POWER [dBFS]

−30

−40
chip. Attention was paid to the power distribution issues fclk/2
and symmetry because any deviation in the ground volt- −50

age level between the deglitcher and its biasing circuitry

−60
results in misbiasing of the deglitcher. A spectrum mea- f −f
2 1
2f +f
2 1
2f +f
1 2 f +f
f +f 1 2
sured from differential output with a 9.1-MHz input sig- −70 1 2

nal and 30-MHz clock frequency is shown in Figure 7. −80

The second harmonic, aliased to 11.8 MHz, lies 66.8 dB
below the signal level. Mismatch between current mem- −90
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
ories operating at the opposite clock phases produce a Frequency [MHz]
50-dBc offset component at half the clock frequency.
Figure 8 shows measured two-tone test with input sig- Figure 8. Two-tone test with -6 dBFS input signals.

nals at frequencies 11.5 MHz and 12.5 MHz, clock fre-

quency being 40 MHz. Intermodulation products are be-
low 68 dBFS. The power consumption, which is domi-
nated by the deglitcher, is 350 mW measured from a 3.0-
V supply with 40-MHz clock frequency and a 12-MHz
input signal.
5. Conclusions
The idea of using a current mode track-and-hold cir-
cuit as a deglitcher after a current-steering DAC has
been proposed and demonstrated with a prototype circuit.
The time-interleaved deglitcher uses the current copying
principle, which minimizes its sensitivity to component
matching. The current memorys good linearity is based
on a bootstrapped sampling switch and a transconductor
constructed of a triode region MOSFET cascoded with a
regulated bipolar transistor. Measurement results show
that good dynamic performance is achieved with high in-
put signal frequencies at relatively high sampling rates.
The design presented demonstrates that a current mode
track-and-hold circuit, which does not need any output
buffering, can be used for removing glitches from the out-
put of a high-speed current-steering DAC.
[1] G. A. M. Van der Plas, et al., “A 14-bit Intrinsic Accuracy
2
Q
Random Walk CMOS DAC,” IEEE JSSC, pp. 1708–
1718, Dec. 1999.
[2] A. R. Bugeja, B-S. Song, P. L. Rakers, S. F. Gillig, “A
14-b, 100-MS/s CMOS DAC Designed for Spectral Perfor-
mance,” IEEE JSSC, pp. 1719–1732, Dec. 1999.
[3] A. R. Bugeja, B-S. Song, “A Self-Trimming 14-b 100-MS/s
CMOS DAC,” IEEE JSSC, pp. 1841–1852, Dec. 2000.
[4] J. B. Hughes, K. W. Moulding, “S2 I: A Switched-Current
Technique for High Performance,” IEE Electronics Letters,
no. 16, pp. 1400–1401, Aug 1993.
[5] M. Dessouky, A. Kaiser, “Input switch configuration for
rail-to-rail operation of switched opamp circuits,” IEE
Electronics Letters, no. 1, pp. 8–10, Jan 1999.
[6] A. M. Abo, P. R. Gray, “A 1.5V, 10-bit, 14.3MS/s CMOS
Pipeline Analog-to-Digital Converter,” IEEE JSSC, pp.
599–606, May 1999.

482
 DESIGN AND IMPLEMENTATION OF VIDEO DAC IN
0.13pm CMOS TECHNOLOGY
Cristiun Ionuqcu Dun Burdid
'Department of Applied Electronics and Intelligent Systems 2Department of Telecommunications
e-mail address: cionascuQetc.tuiasi.ro dburdia@etc.tuiasi.ro
Faculty of Electronics & Telecommunications
"Gh. Asachi" Technical University o f l a s i

ABSTRACT are high glitch energy even with very carefully design of switches
and large DNL (differential nonlinearity) error [Z].The second
This paper presents the design and implementation of video supposes a conversion of digital inputs into a special code named
digital-to-analog converter (DAC) in CMOS 0.13pm technology thermometer, where the number of the outputs is equal to the
on 8 bits resolution, 500 MS/s, with good performances, smaller decimal value of the input signal. The advantages of this
area low glitch energy, which makes it suitable for RAMDAC structure are good DNL and small dynamic switching errors. The
(Random Memory Access Digital to Analog Converter) mathematical description of current sources behavior for these
application. The proposed current steering DAC is a fully two StNCtUreS is:
thermometer architecture which assumes a smaller area for a
single DAC unit with a new deglitching circuit architecture u ( N )= K * L S B ( I ) (Binary-weighted)
added to improve the dynamic performances. In this way the I
interface between the digital part, which operates at low power
supply 1.2V. and the analog part operating at 3.3V supply is
made possible. AI) = 0
I
LSB (2) (Unary current sources)

1. INTRODUCTION In ( I ) and (2) it is assumed a normal distribution for unit current

The demand of circuits that operate at higher clock frequencies
is continuously increasing. especially in signal proccssing
domain. The evolution of DAC's follows the evolution of cmos
technology. however the frequency is increased in nano-cmos
technologies but there are more severe limitations in
performances, depending on the application.
RAMDAC circuit contains triple digital-to-analog converters,
according to the three fundamental colors used in color television
and three input registers [ 6 ] . This kind of circuits is used to
convert the digital signal derived from color palette table (usually
sources with standard deviation O(1)
In this work a good trade-off between performances, resolution
and area concepts are described. The proposed circuit is based on
the well-known current steering architecture [I]; structured on
two matrix current cells with a relatively new deglitching circuit
and a modified current cell schematic. The block schematic is
presented in figl.
4b DAC LSB CELL
rFp+--+ i 2
chlhh

a RAM circuit) in analog signal for VGA display. The most 8Digibl
important block is the DAC which has to operate at pixel clock Inputs
frequency with minimum distortions, to provide high current
scale and precise voltage full scale level compatible with
standards such RS-170, RS-343 [ 6 ] and standard load
terminations (75 Ohm). Its speed determines the rtsolution level
and corresponding refresh rate. Faster RAMDAC speeds. allow
more pixels per second to be placed on the screen. This result in
two important benefits: higher resolution allows the viewer to see
better and a faster refresh rate reduces flicker and eyestrain.
Most of conventional high-speed digital to analog converters
employ current steering architectures for their speed and
linearity. However, the current steering DAC's show static and 4b DAC MSB CELL
dynamic performance limitations due to process variation,
current mismatch, and glitch energy.
There are two well-known current steering architectures: binary-
weighted and unary decoded. In the first, every input signal
drives directly a switch that leads the current source hinary-
weighted to the output load. The drawbacks of this architecture Fig1 The block schematic ofRAMDAC (a single DAC.unit)

0-7803-7979-9/03/$17.00 02003 IEEE 381

 This structure has a great advantage: the smaller area occupied
by the circuit as compared to the similar converters with full
thermometer decoder architecture. For example, while a 8 bits
resolutions requires 256 current cells, in the 'proposed DAC
structure only 15+15 current cells are needed, which is obviously
a smaller area. The main drawback with this structure is the
dificulty to match those two DAC's 4b (MSB cell and LSB cell)
that are connected in parallel. Another important drawback is the
glitch energy that occurs at code transition 00001111 into
00010000, even with equal delays of entire digital structure. The
proposed deglitching circuit with careful design and layout for
switches and current cells salves these tu'o drawbacks.
The 'input registers, row decoder, column decoder and the
selection circuit were designed using low voltage transistors,
1.2V normal models. The thermometer decoder, practically, is
made,of row. column decoders and the matrix switching decoder
- deglitch circuit the worst case glitch occurs from transitions code
(selection circuit). Unlike [I], more buffers should he added in
row and column decoder to equalize time delays between MSB
and LSB matrix and inherently delays between gates for these
decoders. Achieving equal delays is very important in all the
digital parts but especially in selection circuit [I]. Anyway in
layout this task is a more dimcult one, but the deglitching circuit
proposed will increase the dynamic performances (section 2).
2. DEGLITCHING CIRCUIT
The schematic of this circuit is shown in fig2. A RAMDAC
circuit requires the load termination 75 ohm, as generally all
video circuits, because of impedance matching with coaxial cable
used in video-frequency. It could he also possible to add a
special output buffer for impedance matching, which will drive
the load with desired level of output voltage. However this
configuration has the important drawback of limited slew rate
which. of course, degrades the performance of the circuit before
it. namely the DAC.
Fig2.7he schematic of deglitching circuit
The deglitching circuit will provide special signals for switches,
which in this case are PMOS transistors (section 3); the required
levels of the outputs are 0 and 3.3V. These high levels are
required by thc "cry high full-scale current p I 7 m A ) on load
382
termination I5 ohms and this implieslfouf,, = I,R,, cca
1.2V. That is why, using 1.2V transistor models for analog side
is impossible. The solution is in this case to use 3.3V transistor
models with voltage levels for switches greater than 2V (to have
enough overdrive voltage for switches). One of the important
roles is to make the interface between 0-1.2V voltage levels for
digital side with 0-3.3V voltage levels, with a lower crossing
point (fig3).
The glitch energy appears at code transitions (usually at inajor
code transitions). In thermometer architecture these glitches are
with minimum energy, but improper switches sizes, improper
driver signals for switches, could he major sources of errors.
Glitches limit the performances of DAC, and these are revealed
in SFDR (spurious free dynamic range), SNDR (signal to noise
and distortion ratio), with lower values. With the proposed
15 to 16 with 6.2 pV*sec.
The reason to achieve a lower crossing paint is to never turn-off
completely both of transistor switches, because the current
sources may come out of saturation, and it can take a long time
for the current to settle again to the correct value. The output
waveforms are planed in fig3 (out and ouln). The lowering of the
crossing point can he implemented by making one of the rising or
falling edge slower, but this results in asymmetrically outputs of
DAC. The effect is increased amplitude of spectral line for the
second harmonic frequency, and to provision of an offset error in
differential output voltage. Another way is to delay one of the
transitions. In this circuit a combination of both methods with a
minimum offset error was used.
The circuit is in fact a latch with buffers (M6-13. 3 . 3 ~
transistors) that comcts the rising and falling edges to make
possible signals with minimum rise and fall time. In this way the
settle time is decreased. The transistors MI, M14, M5, h44 are
3 . 3 ~transistors and MI, M14, MO, M3 are driven by the signal
with 0-1.2V levels. and MO, M3 composes an inverter 1.2V
supply. The ratio between pmos sizes and nmos size:; will
achieve different rise and fall times with low crossing point as in
kig3.
.:-"," I.On,,_lRm-
.:-,
I
I d
Fig.) The waveforms for deglitching circuit
 Another iechnique to increase the dynamic performances of
this DAC srchitecture is to make rising and falling edges of
driving signals, especially for MSB switches, as equal as
possible, by taking into account the larger capacitance that h p to
be driven by the outputs signals of the deglitching circuit for
MSB switches in ccmparison with LSB switches (I_MSB=16
1-LSB). AS it is shown in fig4 the signals out and outn have a
lower crossing point with almost equal rising and falling edges,
more delay being added between them as compared to the signals
out-latch and outn-latch.
I
.i Jn
.:ul
r
Fig.4 Output waveforms plotted according to fig.?
Fig.5 Current cell schematic
2. PROPOSED CURRENT CELL
Video standards imply doubly load termination 75 Ohms,
large full scale output current, higher clock frequency and low
3 83
DNL, INL (integral nonlinearity) errors. To get maximum
performances under these conditions, a schematic for the current
cell is shown in fig.5. All transistors used in this cell (except
deglitching circuit) are 3.3V transistors, M2 and M3 represents
the switches, MO and M I the unary current source.
Many trade-offs have to be accomplished when designing
this block, for example the switches have to be large to lower the
effect of their own parasitical resistance, but on the other hand,
this will increase glitches amplitude, due to the .
clockfeedthrough (parasitical coupling through Cgs of MO and
MI for both edges of driving signals). The solution is to
minimize the sizes of switches and to increase the output
impedance for the current sources. In this work, for the current
sources a single cascode stage was preferred. There f e many
converters with a single transistor as the current source, using the
switch in saturation region to increase the overall output
impedance, especially for small full-scale currents.
In this design, a minimum possible size of the switches with
maximum possible impedance for current sources in case of a
large LSB current value (max 65.5 PA) was obtained.
Another important problem is matching of the unary current
sources. Using 131, the investigations show that the area of the
objects matching can characterize the variance of the stochastic
relative matching errors. As it was shown in most of the articles
related to matching behavior of CMOS transistors, the larger
transistors have a better performances in matching parameters.
So, to achieve a good matching, a special layout techniques was
developed (double common centroid): This was also
accomplished using the connection of several current sources in
parallel. Sizing of current sources is difficult because of limited
headroom (by the necessity of large full-scale currents). This
limits the maximum size transistors and the limited output
impedance of current sources that has to be achieved gives
minimum limit. In fig.6 the transient simulations results for
IOOMhr update frequency with RC extracts is presented. The
glitch energy is about 6.5pV'sec.
~ 0 m Q s m n m ~ c o ~ w I o I p .
n"rInADml0lol
. __"- m
-s -- I 1.- (I T I
-.
--
 3. LAYOUT CONSIDERATIONS I

In this paper a high performance full custom layout was

achieved, with special design of switches; using common
centroidstructure. This technique provides an equal dispersion of
threshold voltage and equal C , for both transistors. The layout
of switches is isolated from both MSR current sources array and
LSR array. Full layout view is for a single DAC unit shown in
tig7. The matching of the current sources is extremely important
and this will be accomplished using special layout techniques to
compensate symmetrical and graded errors caused by the
temperature, process, and electrical gradients with special
switchibg techniques as in [4]; [SI, and [2] (double common
centroid). These techniques require a complicated routing layout.
Another complicated issue is that three DAC's must be on the Fig.8 SFDR over the Nyquist window -4YdRc, signal
same chip and these have to be matched with minimum area and tone=20Mhz, Fclock=500 MSis
power consumption. A maximum INL error around 0.8 LSR is
considered as acceptable, but with very good DAC t o DAC Tablel. Performance Summary (for a single DAC unit cell)
matching.
The realized DAC shows a good SFDR (tig8) behavior (for Resolution I 8 bits
video frequency bandwidth) for 8 bits resolution with post-layout Supply Voltage I I .2V (digital supply),
simulations of parasitical RC distributed extract using Spectre 3.3V (analog supply)
simulator bsim3v3 models, technology is 0.13vm n-well four Maximum Update Rate 500 Mhz
metal /single poly. Time Settling 2.511s
SFDR (Foul=ZOMhz -4YdBc
4. CONCLUSION Fclock=SMMhz) I
A high performance video-dac has been presented, based on SFDR (Fout=lMhz -61.2dRc
fully thermometer current steering architecture with 8 hits Fclock=500Mhz)
resolution, low glitch energy, at high full scale currenL with Glitch energy I 6.2 pV*sec
extremely smaller area consumption per DAC unit (0.14 mm'). Process 1 0.13pm n-well Sour
The presented current sources architecture is more complex than
binary ,weighted current DAC with minimum size of transistors Area consumption per DAC 0.14 mm2(360,,m 390 v,n)
with complicated switching sequence that implies a difficult task unit
to develop lull custom layout. However the performances
obtained. under the condition of given application. justifq. all the
efforts done. Future develoomcnts of entire RAMDAC chio

Fig .7 Layout view of a single unit DAC

384
Mismatch Modeling and Design of CMOS Current-
Steering Digital-to-Analog Converters
Ola Andersson
Reg no: LiTH-ISY-EX-3026
November 3, 1999
Mismatch Modeling and Design of CMOS Current-
Steering Digital-to-Analog Converters
Thesis for Degree of Master of Science
Department of Electrical Engineering
Division of Electronics Systems
Ola Andersson
Reg no: LiTH-ISY-EX-3026
November 3, 1999

DAC

Supervisor: J. Jacob Wikner

Examiner: Mark Vesterbacka
 Datum
Avdelning, Institution Date
Division, department
Department of Electrical Engineering
Electronics Systems 1999-11-03

Språk Rapporttyp ISBN

Language Report: category
Svenska/Swedish Licentiatavhandling ISRN
x Engelska/English x Examensarbete
C-uppsats Serietitel och serienummer ISSN
D-uppsats Title of series, numbering
Övrig rapport

LiTH-ISY-EX- 3026
URL för elektronisk version

Titel Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog

Title
Converters

Författare Ola Andersson

Author

Sammanfattning
Abstract

The requirements on today’s telecommunications equipment are very hard. Most of the signal processing
is done in the digital domain, but the information has to be transferred with analog signals, and therefore
analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are crucial building blocks.
In this report we concentrate on the matching properties of current-steering DACs. Because transistor-
level simulations are time demanding, we need to approach the problems on a higher level of abstraction.
A mathematical model of so called linearly graded mismatch has been developed and analyzed for a par-
ticular DAC structure.
A DAC structure that will reduce the influence of linearly graded mismatch has been developed, and two
sets of DAC chips with different types of current switches has been implemented. Some design issues for
mixed mode applications in general, and especially DACs, are also discussed.

Kraven på dagens telekommunikationsutrustning är väldigt höga. Största delen av signalbehandlingen

sker digitalt, men överföringen av information måste ske med analoga signaler, och därför är A/D-om-
vandlare och D/A-omvandlare viktiga byggblock.
I den här rapporten koncentrerar vi oss på matchningsegenskaperna hos strömstyrda D/A-omvandlare.
Eftersom simulering på transistornivå är tidskrävande måste vi angripa problemen på en högre abstrak-
tionsnivå. En matematisk modell av så kallat linjärt varierande matchningsfel har utvecklats och analyser-
ats för en speciell D/A-omvandlarstruktur.
En D/A-omvandlar struktur som minskar inverkan av linjärt varierande matchningsfel har konstruerats,
och två uppsättningar D/A-omvandlarchip har implementerats. Vissa konstruktionsfrågor rörande mixed-
mode-tillämpningar i allmänhet, och D/A-omvandlare i synnerhet, tas även upp.

Nyckelord
95-11-01/lli

Keywords
DAC, matching, mixed mode design, current source, CMOS, analog design
 Abstract
The requirements on today’s telecommunications equipment are very hard. Most of the
signal processing is done in the digital domain, but the information has to be transferred
with analog signals, and therefore analog-to-digital converters (ADCs) and digital-to-ana-
log converters (DACs) are crucial building blocks.
In this report we concentrate on the matching properties of current-steering DACs. Be-
cause transistor-level simulations are time demanding, we need to approach the problems
on a higher level of abstraction. A mathematical model of so called linearly graded mis-
match has been developed and analyzed for a particular DAC structure.
A DAC structure that will reduce the influence of linearly graded mismatch has been de-
veloped, and two sets of DAC chips with different types of current switches has been im-
plemented. Some design issues for mixed mode applications in general, and especially
DACs, are also discussed.
 Acknowledgments
I would like to thank my supervisor Tekn.Lic. J. Jacob Wikner for his invaluable help in
introducing me to the world of data conversion, teaching me how to use all the IT-tools and
giving me useful remarks on my work.
My deepest gratitude to Ericsson Components AB and Ph.D. Gunnar Björklund for giving
me the opportunity to do this work.
Special thanks to my office colleagues Niklas Andersson and Pierre Dahlheim Lander,
without you two the spirit of the office would not have been on the same high level. I also
thank Elmo for never complaining.
Finally I thank my fiancé, Helena, for always supporting me.
 Table of Contents

1 Introduction................................................................................... 1
1.1 Background........................................................................... 1
1.2 Brief Overview of the Work ................................................... 2
1.2.1 Background Research ................................................................. 2
1.2.2 High-Level Approach ................................................................... 2
1.2.3 Implementation ............................................................................ 2

2 Introduction to DACs .................................................................... 3

2.1 Introduction ........................................................................... 3
2.2 Behavioral-Level Description ................................................ 3
2.2.1 Static Properties .......................................................................... 3
2.2.2 Dynamic Properties ..................................................................... 5
2.2.3 Frequency Domain Properties ..................................................... 6
2.3 The Ideal DAC ...................................................................... 7
2.3.1 Definition of the Ideal DAC .......................................................... 7
2.3.2 Behavioral-Level Description ....................................................... 8
2.3.3 Performance of the Ideal DAC..................................................... 8
2.4 Current -Steering DAC Structure .......................................... 8

3 Modeling of the Influence of Linearly Graded Mismatch ........... 11

3.1 Introduction ........................................................................... 11
3.2 The CMOS Process.............................................................. 11
3.2.1 Relations for NMOS Transistors .................................................. 12
3.2.2 Relations for PMOS Transistors .................................................. 13
3.2.3 Small-Signal Equivalents ............................................................. 13
3.3 Parameter Modeling ............................................................. 14
3.4 Mismatch Applied on DACs .................................................. 15
3.5 Linearly Graded Mismatch.................................................... 15

i
3.5.1 Mismatch Modeling...................................................................... 15
3.5.2 DC Properties Arising from Linearly Graded Mismatch ............... 17
3.5.3 SFDR due to Linearly Graded Mismatch ..................................... 18
3.5.4 SNDR due to Linearly Graded Mismatch..................................... 21
3.5.5 Simulated Signal Spectras........................................................... 24
3.6 Conclusions .......................................................................... 24

4 Implementation of Current-Steering DACs ................................ 27

4.1 Introduction ........................................................................... 27
4.2 The Implemented Structure .................................................. 27
4.2.1 Segmentation............................................................................... 27
4.2.2 The Choice of Current Sources ................................................... 28
4.3 DAC Building Blocks............................................................. 29
4.3.1 The Current Source ..................................................................... 29
4.3.2 Biasing ......................................................................................... 30
4.3.3 The Switch ................................................................................... 30
4.3.4 Binary-to-Thermometer Encoder ................................................. 31
4.3.5 Switching Signal Generator ......................................................... 33
4.4 Layout considerations........................................................... 33
4.4.1 The Overall Structure................................................................... 33
4.4.2 The Unit Source........................................................................... 34
4.4.3 Clock Signal Distribution.............................................................. 34
4.5 The Final Chip ...................................................................... 35

Appendices
A Using MatLab for Behavioral-Level Simulations ........................ 39
A.1 Introduction ........................................................................... 39
A.2 Brief MatLab Overview ......................................................... 39
A.3 Creating DAC Models using MatLab .................................... 39
A.4 Creating Input and Output Signals for the DAC.................... 39

ii
A.5 Analyzing Signals in the Frequency Domain ........................ 40
A.6 M-file Listings........................................................................ 40
A.6.1 createDAC.m ............................................................................... 40
A.6.2 corr_choice.m .............................................................................. 41
A.6.3 INLest.m ...................................................................................... 41
A.6.4 DNLest.m..................................................................................... 42

B Integrated Circuit Design with Cadence..................................... 45

B.1 Introduction ........................................................................... 45
B.2 A Brief Overview of the Design Process............................... 45
B.3 Schematic Editor................................................................... 46
B.4 Analog Artist Simulations...................................................... 46
B.5 Layout Editor......................................................................... 47

C Contribution to the NORCHIP Conference, Nov 1999 ................ 49

iii
iv
 Abbreviations
Notation Description

Cov ( X , Y ) Covariance between X and Y

2 Variance of X
Var ( X ) = σ (X )
ADC Analog-to-digital converter
ADSL Assymmetric digital subscriber line
CFT Clock feedthrough
DAC Digital-to-analog converter
DNL Differential non-linearity
DSL Digital subscriber line
FFT Fast Fourier transform
HDSL High data rate digital subscriber line
INL Integral non-linearity
LSB Least significant bit
MSB Most significant bit
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
VDSL Very high data rate digital subscriber line

v
 Chapter
1

Introduction

Digital-to-analog converters (DACs) are very important building blocks in telecommunica-

tions equipment. A large problem for DACs, and analog designs in general, is component
mismatch. Two components, e.g., transistors or capacitors, that ideally are supposed to be
identical, suffer from dissimilarities due to process variations.
This report is a presentation of a graduation work carried out at the department of Elec-
trical Engineering, Linköping University, Sweden in cooperation with the Microelectron-
ics Research Center (MERC), Ericsson Components AB, Kista, Sweden. This work can be
divided into three main parts:
1. Perform a literature study on how component mismatch can be modelled
2. Make a behavioral-level model of a DAC and investigate how the mismatch
affects the performance of the DAC
3. Use the knowledge achieved to implement a DAC on silicon where the
mismatch influence is decreased.

1.1 BACKGROUND
With the number of Internet users growing at a very high rate, the need for better and fast-
er telecommunications equipment is increasing. Digital subscriber line (DSL) is one tech-
nology for bringing high bandwidth information over ordinary copper telephone lines [1].
The reason for wanting to use copper lines is that this infrastructure already exist. xDSL
refers to different variations of DSL, such as HDSL (high bit-rate DSL), ADSL (asymmet-
ric DSL) and VDSL (very high data rate DSL).
Most of the signal processing is performed digitally because this is more accurate than if
analog circuitry were to be used. However, digital data has to be transferred on a long dis-
tance line using only analog signals, and therefore DACs and analog-to-digital converters
(ADCs) are crucial building blocks, or even the bottle-necks in some applications.
There is good knowledge in how to make high-speed/low-resolution converters or low-
speed/high-resolution converters. However, what is needed today for telecom applications
is both high-speed/high-resolution converters.

1
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

1.2 BRIEF OVERVIEW OF THE WORK

In this section we present how the work has been carried out, and also briefly how the re-
port is divided.

1.2.1 Background Research

Studies of papers treating the subject of mismatch in CMOS processes in general, and
DACs in particular, show that the parameter mismatch for CMOS current sources often
shows an approximately linear geometrical dependence. We denote this type of mismatch
linearly graded mismatch. In chapter 2 we introduce DACs on a behavioral level, and a
particular type of DAC, the current-steering DAC, is presented.

1.2.2 High-Level Approach

Because circuit-level simulations require a large amount of time, the problem has to be ap-
proached on a higher level of abstraction. A mathematical model of the DAC was developed
based on the knowledge from literature treating the subject. The performance of the DAC
was analytically examined using this model, and results were achieved in terms of DNL,
INL, SFDR and SNDR. This part of the work is presented in chapter 3.
To verify the analytical results, the DAC model was also implemented in MatLab. The re-
sults from the MatLab simulations are presented together with the analytical results in
chapter 3.
The simulation results show a very good agreement with the analytical expressions devel-
oped for describing the DAC performance due to linearly graded mismatch.
The text describing the actual MatLab simulations has been placed in appendix A, this is
to emphasize the simulation results rather than the simulations themselves.
The theoretical part of the work also resulted in a paper accepted for publication at the
NORCHIP conference in Oslo, Norway, November 1999. This paper is included in appen-
dix C.

1.2.3 Implementation
Two sets of DAC-chips were implemented. In chapter 4 some issues concerning the chip
design are discussed, and special care is taken to the knowledge achieved about mismatch
in the theoretical part of the work. Discussions about design methodologies and the Ca-
dence design tools used to implement the DACs have been placed in appendix B.

2
 Chapter
2

Introduction to DACs

2.1 INTRODUCTION
The requirements on today’s telecommunication circuits are in the order of 25MHz band-
width and 14-bit resolution, or even more [1]. To meet these requirements, the design of
analog and mixed-signal circuits becomes very hard. One of the bottle-necks is the inter-
face between the digital signal processing circuits and the analog amplifiers and filters
sending and receiving the signal. The interface consists of the digital-to-analog converter
(DAC) and the analog-to-digital converter (ADC). In this report we concentrate on the
matching properties and design issues of current-steering DACs most often used in tele-
communications applications. In this chapter we will introduce the reader to the concept
of DACs.

2.2 BEHAVIORAL-LEVEL DESCRIPTION

In this section we describe the behavioral-level properties of DACs to be used in this re-
port. A DAC performs a mapping of a digital signal onto an analog one. The ideal DAC is
described in section 2.3. However, in reality DACs suffer from non-idealities, and we there-
fore need some measures to describe those non-idealities. We will define static, dynamic
and frequency domain properties of the DAC.

2.2.1 Static Properties

In Fig. 2-1 below the real and the wanted output of a DAC is plotted as a function of the
input code. We denote the wanted output for a digital input is X by A wanted ( X ) , and the
corresponding real output A real ( X ) . A real( X ) denotes the settled value of the non-ideal
DAC output, compare section 2.2.2. We define the deviation from the wanted value
d ( X ) = A real ( X ) – A wanted ( X ) , and we can now introduce the following performance mea-
sures:
1. Differential Non-Linearity, DNL
DNL ( X ) = d ( X ) – d ( X – 1 ) (2-1)
2. Integral Non-Linearity, INL
INL ( X ) = ∑Y ≤ X DNL ( Y ) (2-2)

3
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

The DNL value describes the deviation from an ideal step in the transition between the
codes X – 1 and X , and INL describes the overall deviation from the wanted output.

Ideal (solid) and non−ideal (dashed) output of a DAC

7

Output value 5

4 A real ( 3 )
A wanted ( 3 )
3

1
d0
0
0 1 2 3 4 5 6 7
Input code X

Fig. 2-1: Illustration of real and wanted output of a DAC

Deviations from the wanted transfer characteristics of the DAC can be divided into two
main groups, offset errors and gain errors. The offset error may be defined as the deviation
from the wanted minimum output, marked d 0 in Fig. 2-1. Two types of gain errors, linear
and non-linear, are illustrated in Fig. 2-2 below.
Because linear gain errors and offset errors do not affect the performance of the DAC, INL
and DNL are often calculated with respect to a best-fit straight line,
A best-fit ( X ) = kX + A offset . k and A offset are calculated using the least square method and

Illustration of linear and non−linear gain error

2000

1800

1600

1400
linear gain error
Output value

1200

1000

800

600 non-linear gain error

400

200 wanted output

0
0 200 400 600 800 1000 1200 1400 1600
Input code

Fig. 2-2: Illustration of linear and non-linear gain error

the real outputs of the DAC, further discussed in [2]. Better values of INL and DNL than
in Eq.(2-1) and Eq.(2-2) are now given by:

4
 Chapter 2 - "Introduction to DACs"

DNL ( X ) = A real ( X ) – A real ( X – 1 ) – k (2-3)

INL ( X ) = A real ( X ) – A best-fit ( X ) (2-4)
Eq.(2-3) and Eq.(2-4) are the definitions of DNL and INL that will be used in this report.
Those properties are often given in the unit [LSB] ( k = 1 [LSB]), which we also will use in
this report.

2.2.2 Dynamic Properties

When switching the input code from one value to another, it takes a certain amount of time
before the output reaches it’s final value, and thus the static properties are not enough to
describe the performance of the DAC. Fig. 2-3 below shows the qualitative behavior of the
output when switching the input code, there is also a plot of an ideal step included for easy
comparison

1.2

0.8
output

0.6 ts

0.4

0.2

0
0 5 10 15 20
time

tr

Fig. 2-3: Ideal step (dashed) and real step response (solid)

We can define the following measurements to describe the dynamic properties

1. Rise time, t r
The time it takes for the output to go from 5% to 95% of it’s final value
2. Settling time, t s
The time it takes for the output to settle within 5% of it’s final value

The percentages given in the above definitions are often used, but they are not a standard,
so the reader should not be surprised if other values are given in the literature.
When we have relatively small code transitions, the output can be well approximated with
a linear system, and we have so called linear settling. However, for larger code transitions
the output driving capability is a limiting factor. We define the slew rate as

5
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

3. Slew rate, SR

SR = max dY (2-5)
dt
where Y is the output value.

The dynamic properties are strongly dependent on which codes are involved in the transi-
tion, and are therefore difficult to model. In this work we limit ourselves to model the in-
fluence of the static errors.

2.2.3 Frequency Domain Properties

Most of the characterization of the DAC is done in the frequency-domain [3]. It is impor-
tant that the wanted signal can be separated from the noise and distortion that also ap-
pears on the output of a DAC. The DAC can be characterized by the amount of power in
the signal compared to the amount of power in the noise and the distortion. The measures
defined below, are examples of such characterizations, which will also be used later in this
report.
1. Signal-to-Noise Ratio, SNR
P signal
SNR = ---------------
- (2-6)
P noise
2. Signal-to-Noise-and-Distortion Ratio, SNDR
P signal
SNDR = -------------------------------------------
- (2-7)
P noise + P distortion
3. Spurious-Free Dynamic Range, SFDR
P signal
SFDR = ---------------
- (2-8)
P ld
In the equations above P signal is the signal power, P noise is the noise power, P distortion is
the the distortion power, and P ld the power of the largest distortion term. An example of
a signal spectrum is shown in Fig. 2-4 to illustrate those concepts.
Deeper discussions on DAC performance characterization can be found in e.g. [2] or [4].

6
 Chapter 2 - "Introduction to DACs"

harmonic distortion terms

signal −20
SFDR
−40

Signal Power [dB]

−60

−80

−100

−120

−140

0 0.1 0.2 0.3 0.4 0.5

Normalized frequency

Fig. 2-4: Example of a signal spectrum.

2.3 THE IDEAL DAC

We need to define what we mean with the word "ideal" when describing DACs. This is done
in the sections below, where the performance of the ideal DAC also is discussed.

2.3.1 Definition of the Ideal DAC

If a band limited signal is sampled with a sampling frequency, f s , that is larger than two
times the bandwidth of the signal, the signal can be ideally reconstructed using sinc pulses
according to [5]

X rec ( t ) = ∑n X ( n )sinc( f s t – n) (2-9)

where X rec(t) is the value of the reconstructed signal at the time t , X ( n ) is the value of the
sampled signal at sampling instant n , and we sum over all values of n .
The sinc function is defined as

sin ( πx )
sinc(x) = ------------------- (2-10)
πx
Since the reconstruction of Eq.(2-9) is not possible to implement, the sinc-function has to
be replaced by a function that does not have an infinite extension in time. Most often the
sinc is replaced by a square pulse, as shown in Fig. 2-5 where the sinc also is plotted. When
we refer to the ideal DAC in this report, we mean a DAC where the sinc has been replaced
by a square pulse, i.e., sample-and-hold elements are used at the output. This causes the
signal spectrum to be sinc weighted.
This definition of the ideal DAC does not really correspond to right meaning of the word
ideal, since the reconstruction of the signal is indeed not ideal. It is instead a description
of what we want to achieve when designing DACs.

7
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

time

Fig. 2-5: The sinc function (dashed) plotted together with the square pulse (solid) used instead.

2.3.2 Behavioral-Level Description

For an ideal DAC, as defined in section 2.3.1 the output is only dependent on the value of
the digital signal at the sampling instant. The N -bit digital word
X = { b N – 1, b N – 2, …, b 1, b 0 } is mapped onto the analog value
N–1

∑ bk 2
k
A ( X ) = A ref ⋅ (2-11)
k=0
A ref in Eq.(2-11) is a reference value, often an electrical voltage, current or charge.

2.3.3 Performance of the Ideal DAC

Since the output of the ideal DAC exactly follows the wanted staircase of Fig. 2-1, the ideal
DAC will have:

INL ideal = 0 (2-12)

and

DNL ideal = 0 (2-13)

for all input codes.
Since the output of the ideal DAC only adopts discrete levels, we will have so called quan-
tization noise. According to [2] the ideal N -bit DAC has a SNR value of

SNR = 6.02N + 1.76 dB (2-14)

when applying a full scale sinusoid on the input. For an ideal DAC the SFDR is also limited
by quantization noise, which is also dependent on the sampling rate.

2.4 CURRENT -STEERING DAC STRUCTURE

There are many types of DAC realizations [2, 6]. The current-steering DAC, as sketched
in Fig. 2-6a), is suitable for high-speed and high-resolution applications [7]. The basic
structure needs no feedback loops and no operational amplifier and hence the bandwidth
is large. The power efficiency is almost 100% since all current is directed to the output,

8
 Chapter 2 - "Introduction to DACs"

a)
b)
I0=Iunit I1=2Iunit IN-1=2N-1Iunit
∆k
Ik

b0 b1 bN-1 bk

Iout Iout,k

Fig. 2-6: a) Current-steering DAC and b) unit current source with matching error ∆k.

where it is terminated over a resistive load (typically 50 Ohms). The N -bit DAC in Fig. 2-
6a) is constructed by using N binary-weighted current sources, I k . Each current source I k
utilizes 2 k parallel unit current sources, I unit . The bits b i choose which current sources to
connect to the output. b 0 is the least significant bit (LSB) and b N – 1 is the most significant
bit (MSB), hence the total output current for an ideal DAC is given by (compare with Eq.(2-
11))

I out(n) = [ b N – 1(n) ⋅ 2 N – 1 + … + b 1(n) ⋅ 2 + b 0(n) ] ⋅ I unit = X (n) ⋅ I unit (2-15)

where X (n) is the binary input code X (n) = { b N – 1(n), …, b 0(n) } at the sampling instant
n.
In reality it is impossible to create unit sources that produce exactly the same current
I unit . The current sources will be unmatched, and therefore Eq.(2-15) do not hold, i.e., the
DAC is non-ideal. Instead we model the binary weighted current source of bit k as a nom-
inal current source, I k , in parallel with a error source, ∆ k , as illustrated in Fig. 2-6b). The
output of the non-ideal DAC will now become
N–1
I out ( n ) = ∑ bk ( n )I out, k (2-16)
k=0
where
k
I out, k = I k + ∆ k = I unit 2 + ∆ k (2-17)
In the next chapter the matching errors, ∆ k , are further discussed, and a study of a special
case of matching errors, linearly graded mismatch, is presented.

9
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

10
 Chapter
3

Modeling of the Influence of Linearly

Graded Mismatch

3.1 INTRODUCTION
Analog designs are often dependent on certain relations between devices used in the de-
sign. Examples of such relations can be that two transistors should be identical or that
there should be a certain relationship between their sizes. When fabricating the design,
those relations will not be fulfilled due to imperfections in the fabrication process, causing
so called matching errors. In this chapter we will describe the matching errors and how
they affect the performance of the current-steering DAC.

3.2 THE CMOS PROCESS

The most commonly used process in today’s integrated circuits is the complementary metal
oxide semiconductor (CMOS) process [2]. The two types of transistors available in a stan-
dard CMOS process are the NMOS and the PMOS. The corresponding circuit symbols are
given in Fig. 3-1. A simplified view of the CMOS transistor is shown in Fig. 3-2.

a) drain (D) b) S

gate (G)
bulk (B) G B
(substrate)

source (S) D

Fig. 3-1: Circuit symbol of a) NMOS transistor and b) PMOS transistor.

11
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

gate of poly silicon

drain
insulator of silicon
dioxide
source drain gate L
L
substrate b) W
a) source

Fig. 3-2: a) Side view and b) top view of a CMOS transistor.

For an NMOS device the substrate is of p-type, whereas the source and the drain are heavi-
ly n-doped. For a PMOS device the substrate is of n-type, whereas the source and the drain
are heavily p-doped. A deeper discussion on the physics behind the metal oxide semicon-
ductor field effect transistor (MOSFET) can be found in e.g. [8], in this report we only
present the approximate relations between currents and voltages in a MOSFET.

3.2.1 Relations for NMOS Transistors

The MOSFET has three different regions of operation; cut-off region, linear region, and
saturation region. What region is used is dependent on the different voltages of the tran-
sistor. For the NMOS transistor the following relations hold approximately [2].

1. Cut-off region ( v GS ≤ v T , n )
iD ≈ 0 (3-1)
2. Linear region ( v GS > v T , n ) and ( v DS ≤ v GS – v T , n )
µ 0, n C ox W
i D ≈ ------------------- ----- ( 2 ( v GS – v T , n ) – v DS )v DS ( 1 + λv DS ) (3-2)
2 L
3. Saturation region ( v GS > v T , n ) and ( v DS > v GS – v T , n )
µ 0, n C ox W 2
i D ≈ ------------------- ----- ( v GS – v T , n ) ( 1 + λv DS ) (3-3)
2 L
The threshold voltage, v T , n , can be determined using

v T , n = V T 0, n + γ ( 2 Φ F, n – v SB – 2 Φ F, n ) (3-4)
The mobility µ 0, n , the oxide capacitance C ox , V T 0, n , γ and Φ F, n are constants for the
specific process. The subscript n indicates that the constant is specific for an NMOS de-
vice. The channel length modulation factor λ is dependent on the transistor size, but is
often set to zero when less accuracy is needed. The width, W , and the channel length, L ,
of the transistor are indicated in Fig. 3-2. The drain current, i D , and the different voltages
are defined in Fig. 3-3a).

12
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

v SG
iD v DS v SB
v BS v SD
v GS iD

a) b)

Fig. 3-3: Definitions of voltages and drain current in a) an NMOS transistor and b) a PMOS
transistor.

Even though the linear relation between i D and v GS that is present in the linear region is
not present in the saturated region, transistors in analog designs are most often operated
in the saturated region. This is because the current is (almost) only dependent on one volt-
age, v GS , and therefore more easily controlled than then the current for a transistor in the
linear region. An exception to this is when the transistor is used as an analog switch, and
then operated in the linear or cut-off region.

3.2.2 Relations for PMOS Transistors

The corresponding relations for the PMOS transistor are listed below.

1. cut-off region ( v SG ≤ v T , p )
iD ≈ 0 (3-5)
2. linear region ( v SG > v T , p ) and ( v SD ≤ v SG – v T , p )
µ 0, p C ox W
i D ≈ -------------------- ----- ( 2 ( v SG – v T , p ) – v SD )v SD ( 1 + λv SD ) (3-6)
2 L
3. saturation region ( v SG > v T , n ) and ( v SD > v SG – v T , p )
µ 0, p C ox W 2
i D ≈ -------------------- ----- ( v SG – v T , p ) ( 1 + λv SD ) (3-7)
2 L
The threshold voltage for the PMOS transistor, v T , p , is determined by

v T , p = V T 0, p + γ ( 2 Φ F, p – v SB – 2 Φ F, p ) (3-8)
The different process parameters are similar to those for the NMOS transistor. Here the
subscript p indicates that the constant is specific for the PMOS device. The drain current,
i D , and the different voltages are defined in Fig. 3-3b)
3.2.3 Small-Signal Equivalents
When analyzing the small-signal response of CMOS circuits, linearized models, small-sig-
nal equivalents, of the MOSFET are used. A simple small-signal equivalent of an NMOS
is shown in Fig. 3-4 below.
The small-signal parameters in Fig. 3-4 are defined as

13
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

G + D

v gs 1
g m v gs r ds = -------
g ds
-
S

Fig. 3-4: Simplified small signal equivalent of an NMOS transistor.

∂i D
gm = (3-9)
∂ v GS
Q

∂i D
g ds = (3-10)
∂ v DS
Q
The subscript Q denotes that the partial derivatives are evaluated in the quiescent (DC
operation) point.
In the saturated region, Eq.(3-9) and Eq.(3-10) become

W W
g m ≈ µ 0, n C ox ----- ( v GS – v T , n ) = 2µ 0, n C ox ----- i D (3-11)
L L
and

µ 0, n C ox W 2
g ds = λ ------------------- ----- ( v GS – v T , n ) ≈ λi D (3-12)
2 L

3.3 PARAMETER MODELING

Generally a MOSFET-parameter, P , can be modeled as a sum of one fixed and one ran-
domly varying term; P = P 0 + ∆P . The random part, ∆P , which causes mismatch to the
circuit, arises from many different random processes during the fabrication. As seen in [9]
those error sources can be divided into two main groups
1. Short distance variations that can be modeled as spatial white noise (the correlation distance
is typically much shorter than the transistor length)
2. Long distance variations arising from a circular parameter distribution on the wafer due to
fabrication processes such as substrate fabrication and oxide growth.

A further analysis, given in [9], gives the following result for the variance of the parameter
mismatch:
2
2 A 2 2
σ ( ∆P ) = -------P- + S p D x (3-13)
WL
In the above equation W and L are the transistor width and length, D x is the distance
between the compared transistors, and A P and S P are constants (for the particular wafer)
describing the short- and long-distance variations of parameter P respectively. From
Eq.(3-13) we can see that for good matching properties we should place the transistors as
close together as possible, and keep the product WL as large as possible.

14
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

3.4 MISMATCH APPLIED ON DACS

In DACs implemented with binary-weighted current sources it is very important that the
current sources are closely matched in order to achieve high performance (e.g. linearity,
SFDR, and SNDR). The impact of uncorrelated matching properties can be reduced by the
use of unit current sources. If a binary-weighted current source is constructed using K
unit current sources in parallel the relative accuracy is improved with a factor K [10], if
the mismatch is uncorrelated.
When implementing a current-steering DAC the unit sources are placed in an array as il-
lustrated in Fig. 3-5. A deeper discussion of the implementation is found in chapter 4.
The long distance variations due to parameter gradients give rise to deterministic match-
ing properties. However since we do not know where on the wafer the particular chip is
produced, the gradient can have any direction unknown to us. This problem has been ap-
proached in a few different ways, e.g. randomization techniques [11] and special layout
styles. Fig. 3-5a) shows the principle of a layout style used to reduce the impact of param-
eter gradients [10]. The current sources that are part of a particular bit are distributed

unit current source

unit current source, part of MSB
unit current source, part of MSB-1

a) b)

Fig. 3-5: a) Layout reducing gradient matching errors and b) straight forward layout

uniformly over the array of current sources. Even though every unit source has errors as
described previously, this type of layout tends to cancelate those errors slightly. Fig. 3-5b)
shows a more straight forward type of layout. Since the unit sources for each bit are placed
very close to each other their errors are very much correlated and the total error for a par-
ticular bit can be quite large. However, this kind of layout has some advantages concern-
ing, e.g., wire routing.

3.5 LINEARLY GRADED MISMATCH

The mismatch of CMOS transistors has shown to have a certain geometrical dependence
which we choose to call linearly graded mismatch. This type of mismatch and it’s influence
on the DAC type of Fig. 3-5b) is discussed in the following sections.

3.5.1 Mismatch Modeling

M N–M
The unit sources are arranged in an array with 2 sources in the x-direction and 2
sources in the y-direction, indexed as in Fig. 3-6a). Although this is not a particularly good
design strategy, we now can form the binary weighted current sources as shown in the ex-
ample of a 6-bit DAC in Fig. 3-6b), where M = 3 .

15
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

a) b)
i(1,1)
i(-1,1)
I5

I4
i(-2M-1,-2N-M-1)
i(1,-1) I3
y dummy
I2 I1 I0
x source

Fig. 3-6: a) Array of unit current sources with defined directions and positions.
b) Assignment of unit sources to specific bits for a 6-bit DAC.

We model the unit current sources in the same way as the binary weighted sources, hence
a nominal current source in parallel with an error source (compare with Eq.(2-17))

i ( a, b ) = I unit + δ ( a, b ) (3-14)
Using the notation above we have:

 I = 2k ⋅ I
 k unit
 (3-15)
 ∆k =

∑ δ ( a, b )
( a, b ):i ( a, b ) ∈ I k

Investigations of CMOS current sources [12] show that the deterministic part of the mis-
match often show a linear distribution over the chip, i.e. the geometrical dependence of the
current sources can be well approximated with it’s first order Taylor expansion.
Neglecting the short distance variations and assuming that the matching errors are lin-
early distributed over the chip area (current source array) we can express the error sources
as

δ ( a, b ) = k x ⋅  a – --- sgn ( a ) + k y ⋅  b – --- sgn ( b )

1 1
(3-16)
 2   2 
(equation of a plane) where k x and k y are constants describing the linearly graded match-
ing properties of the unit source array. The terms ( 1 ⁄ 2 ) sgn ( a ) and ( 1 ⁄ 2 ) sgn ( b ) compen-
sates for the fact that there are no unit sources with index a = 0 or b = 0 . We will use
the unit [ LSB ] for all currents ( 1 [ LSB ] = I unit ) , and thus k x and k y will have the unit
[ LSB ⁄ unit source ] . Combining Eq.(3-15) and Eq.(3-16) we achieve an expression for ∆ k

 M – 1 – 2 k + 1 + 2 k – 1 ) – ( k ⋅ ( 2 N – M – 1 – 2 – 1 ) ) ) ⋅ 2 k, 0 ≤ k ≤ M – 1
(kx ⋅ (2 y
∆k = 
 – k y ⋅ ( 2 N – M – 1 – 2 k – M + 1 + 2 k – M – 1 ) ⋅ 2 k, M≤k≤N–1

(3-17)
From Eq.(3-17) we can see that the gradient in the x-direction, as could be expected, only
k
affects the M LSBs. Due to the 2 factor in Eq.(3-17) the largest errors will occur for the
MSBs, provided that k x is not very large compared to k y , which probably is a valid as-
sumption.

16
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

3.5.2 DC Properties Arising from Linearly Graded Mismatch

In this section we will qualitatively describe the DC properties of the DAC using the defi-
nitions of DNL and INL in Eq.(2-3) and Eq.(2-4). Since we are mostly interested in the fre-
quency domain properties, we will not perform a deeper analytical examination of the DC
properties, but be rather satisfied with simulations showing the qualitative behavior.
The simulated DNL and INL for an 8-bit DAC is shown in Fig. 3-7. There is an error gra-
dient only in the y-direction (compare Fig. 3-6a), with value k y = 0.001 [ LSB ⁄ unit source ]
and the width of the unit current source array is given by M = 4 . In Fig. 3-7a) we clearly
see that DNL is largest when turning on the MSB. The same holds for the simulation re-
sult in Fig. 3-7b). The INL is largest for X around 2 N – 1 , since the mismatch error in this
region is the largest (about ± ∆ N – 1 ).

a) DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0 b) INL for an 8−bit DAC with M=4, ky=0.001 and kx=0
1 0.5

0.9 0.4

0.8 0.3

0.7 0.2

0.6 0.1
DNL

INL

0.5 0

0.4 −0.1

0.3 −0.2

0.2 −0.3

0.1 −0.4

0 −0.5
50 100 150 200 250 0 50 100 150 200 250
Input word Input word

Fig. 3-7: Typical a) DNL and b) INL plot for an 8-bit DAC with linearly
graded matching errors only in the y-direction.

a) DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001 b) INL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001
1 0.5

0.9 0.4

0.8 0.3

0.7 0.2

0.6 0.1
DNL

0.5
INL

0
0.4
−0.1
0.3
−0.2
0.2
−0.3
0.1
−0.4
0
−0.5
50 100 150 200 250 0 50 100 150 200 250
Input word Input word

Fig. 3-8: Typical a) DNL and b) INL plot for an 8-bit DAC with linearly
graded matching errors in both the x and y direction.

In Fig. 3-8 we show the simulated DNL and INL when introducing a gradient error in the
x-direction as well. The gradients are given by k x = k y = 0.001 [ LSB ⁄ unit source ] . As ex-
pected these plots are very similar to those in Fig. 3-7. Even though we can see that the M
LSBs no longer are mutually matched, the most prominent errors are still those from

17
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

MSB, MSB-1 etc.

3.5.3 SFDR due to Linearly Graded Mismatch

Most of the characterization of the high-speed DAC is done in the frequency-domain [3].
Since the distortion of a converter is dependent on input DC and amplitude level, the in-
formation on DNL and INL is insufficient. We have to find models for the frequency-do-
main properties as well. When applying a full-scale sinusoid at the input of the DAC, the
output current at the sampling instant, I out(n) , can be written as

f0
I out(n) ≈ 2 N – 1 ⋅ sin  2π ⋅ ----- ⋅ n + e ( n ) + I DC (3-18)
 fs 
where f 0 is the signal frequency, f s is the sample or update frequency, I DC is the signal’s
DC level, n is the sequence index, and e ( n ) is the error signal due to the linearly graded
mismatch. From Eq.(2-16) we have that the error signal can be written as
N–1
e(n) = ∑ bk(n) ⋅ ∆k (3-19)
k=0
It can be shown that
N–2

∑ ∆k ≈ –∆ N – 1 (3-20)
k=0
Using Eq.(3-20) we can calculate the mismatch error for four different inputs

 0, X = [ 0, 0, …, 0, 0 ] or [ 1, 1, …, 1, 1 ]
 –∆
e =  N – 1, X = [ 0, 1, …, 1, 1 ] (3-21)

 ∆ N – 1, X = [ 1, 0, …, 0, 0 ]

Using this information we approximate the error signal with a piece-wise linear signal,
ẽ(n) , as shown in Fig. 3-9. Making a Fourier series expansion on the approximated error
signal gives us
2

1.5 input signal

1 ∆N – 1
0.5

−0.5 ẽ(n)

−1 –∆ N – 1

−1.5

−2
0 1 2 3 4 5 6

Fig. 3-9: Input signal (dashed) and approximative error signal (solid) plotted in different scales.

18
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

∞  0, k even
 f  
ẽ ( n ) = ∑ A k sin 2πk -----n where A k = 
0
(3-22)
∆ N – 1 ------  1 – ------ , k odd
 fs  4 2
k=1  πk  πk 

Besides A 1 , the largest coefficient A k is given by the 3rd harmonic, A 3 . Also, since we
have applied a full-scale sinusoid at the input, the signal amplitude is approximately
N–1
A signal ≈ 2 (3-23)
Combining Eq.(3-22) and Eq.(3-23) gives us the spurious-free dynamic range (SFDR) as
2
A signal ⁄ 2 2 2 2( N – 1)
SFDR ≈ ----------------------  9π  2
- = ----------------------- ⋅ ------------------
- (3-24)
2  4 ( 3π – 2 ) 2
A3 ⁄ 2 ∆N – 1
Using Eq.(3-17) for ∆ N – 1 in Eq.(3-24) we get

2 2  N – 1 M + 1 2 2 2 2M
 9π  2 2
SFDR = ----------------------- ⋅  ---------------------------
–2  9π  2
⋅ k y = --------------- ⋅ --------
–2
- ⋅ ky
 4 ( 3π – 2 )  2 ( N – 1 ) 
(3-25)
 3π – 2 2N
2 2
Rewriting Eq.(3-25) in dB yields

SFDR ≈ 21.6 + 6 ( M – N ) – 20 log k y dB (3-26)

Having achieved an analytical expression for SFDR, it would be nice if we somehow could
verify this with simulations. Fig. 3-10 and Fig. 3-11 show simulated values of SFDR as a
function of N and M respectively

SFDR as a function of N for different values of M, ky=0.0001 [LSB/(unit source)]

100

90

80
M=12
SFDR [dB]

70

60

50

40
M=6
30
12 13 14 15 16 17
Number of bits

Fig. 3-10: SFDR as a function of N for different values of M when ky=0.0001 and kx=0.

19
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

SFDR as a function of M for different values of N, ky=0.0001 [LSB/(unit source)]

100
N=12
90

80

SFDR [dB]
70

N=17
60

50

40

30
6 7 8 9 10 11 12
Number of bits in one row of the array

Fig. 3-11: SFDR as a function of M for different values of N when ky=0.0001 and kx=0.

From those two simulations we can get the following “empiric” expression for SFDR:

SFDR ≈ K + 6M – 6N dB (3-27)
This means that we have a verification of Eq.(3-26) as far as to the dependence of N and
M . K is a function of k y not yet determined.
In Fig. 3-12 the calculated value of SFDR is plotted as a function of k y together with sim-
SFDR as a function ky, kx=0
150

100
SFDR [dB]

65.5

50 65

64.5

64
−4
10

0 −8 −7 −6 −5 −4 −3 −2
10 10 10 10 10 10 10
Gradient in the y−direction [LSB/(unit source)]

Fig. 3-12: Calculated (solid) and simulated (dashed) values of SFDR as a function of ky for a
14-bit DAC with M=8.
ulated values for a 14-bit DAC with an array width of M = 8 . We see a close agreement
between calculated and simulated values for larger gradients, for smaller gradients the
simulated values are limited by the quantization noise, which is dependent on the FFT
length used in the simulations.

20
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

3.5.4 SNDR due to Linearly Graded Mismatch

In order to calculate the signal-to-noise-and-distortion ratio (SNDR) we need to find the
power of the error signal. We will do this in two different ways, starting with the most ac-
curate statistical approach. Using Eq.(3-19) and defining e k(n) = b k(n) ⋅ ∆ k , we get

N–1
 
Var ( e(n) ) =  ∑ Var ( e k(n) ) +  ∑ Cov ( e i(n), e k(n) ) (3-28)
k = 0   ( i, k ):i ≠ k 

When applying a full-scale sinusoid, the dominating covariance term, appearing twice in
the sum above, is
2
∆N – 1
Cov ( e N – 1(n), e N – 2(n) ) = – -------------
- (3-29)
48
The error signals, e k ( n ) , have the following probability functions:

1
 --- x = 0 or ∆ k
P ( ek ( n ) = x ) =  2 (3-30)
0 otherwise

Since we have the probability functions we can calculate the variance for each error signal,
yielding

2 2 2
1 ∆ ∆  ∆
Var ( e k ( n ) ) = --- ⋅  -----2k- + -----2k- = -----k- (3-31)
2 2 2  4

Since we want to use this equation to find SNDR as a function of N , M , k x and k y , we

need to write the ∆ k :s as functions of those parameters. We find the expressions for the
∆ k :s in Eq.(3-17). However when we start manipulating those we find out that the param-
eter k x gives us severe problems finding a neat expression for the variance of the error sig-
nal. Assuming k x to be negligible we set it to zero in order to simplify our calculations,
which is something we can justify with the simulation results in section 3.5.2. Using Eq.(3-
17) we achieve:

 ( 2 N – M – 1 – 2 k – M + 1 + 2 k – M – 1 )2 M + 1 k
-2 M ≤ k ≤ N – 1
 ----------------------------------------------------------------------------------------------
2( N – 1)
∆k  2
-------------- =  (3-32)
∆N – 1  k ( 2 N – M – 1 – 2 –1 )
 – 2 ---------------------------------------
2( N – 1)
- 0≤k≤M–1
 2
Some algebraic manipulations on the above expressions give us:

 k–N k–N k–N

(4 16 – 8 96 + 16 144 ) M ≤ k ≤ N – 1
∆k  2
 ------------- 
- =   2 N – 2 M k (3-33)
 ∆ N – 1 0≤k≤M–1
 16  -------------------4
  2 2N 

We have the formula for a geometric sum

21
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

N–1 N–M
M – Na –1 1
∑
k–N N–M
a = a ------------------------ ≈ { if a >>1 } ≈ ------------ (3-34)
a–1 a–1
k=M
This gives us the expression
N–1
∆ k  2 16 96 144
 -------------
∑
128
- ≈ ------ – ------ + --------- = --------- (3-35)
 ∆ N – 1 3 7 15 105
k=M
In a similar way for the LSBs we get
2
M–1
∆k  2
 -------------  2 N – 2 M  4 M – 1  1  24
M
16 M – N
∑  ∆ N – 1- = 16  -------------------
2N
  ---------------- ≈ 16  -----N- ------- = ------ 4
 4–1 3 3
(3-36)
k=0 2 2
Using these relations we arrive at
N–1 N–1
∆k  2
 -------------
M–N
- ≈ ∆ N – 1  ------------------------------------
1 2 32 + 4 140
∑ ∑
2
Var ( e k(n) ) = --- ∆ N – 1 (3-37)
4  ∆ N – 1  105 
k=0 k=0
Now we can rewrite Eq.(3-28) as
M–N
32 + 140 ⋅ 4
Var ( e(n) ) ≈ ∆ N – 1 ⋅  ----------------------------------------- – ------
2 1
(3-38)
 105 24
We are now ready to express the power of the noise and distortion, P ND , as
2
A
P ND = Var ( e(n) ) + P q – -----1- (3-39)
2
In Eq.(3-39) we have included P q , the power of the quantization noise, and also subtracted
the power of the error signal that appears at the signal frequency f 0 (compare with Eq.(3-
22)). It is known that P q = 1 ⁄ 12 , and from Eq.(3-22) the value of A 1 follows. We can thus
write Eq.(3-39) as

 32 + 140 ⋅ 4 M – N 1 2 2 8
P ND = ------ + ∆ N – 1 ⋅  ----------------------------------------- – ------ –  1 – --- ⋅ ----2-
1 2
(3-40)
12  105 24  π π 

Using Eq.(3-17) and Eq.(3-23) we now get

2
A sig ⁄ 2 2
2N – 3
SNDR = ---------------- = -----------------------------------------------------------------------------------------------------------------------------------------------
P ND 4( N – 1) 
2 2 8 
M–N
1 2 2 32 + 140 ⋅ 4 1 
------ + k y ⋅ ------------------- - ⋅  ----------------------------------------
- – -----
- – 1 – --- ⋅ -----
12 2
2( M + 1)
 105 24  π π 2
(3-41)
In Fig. 3-13 SNDR is plotted in the same way as SFDR was in Fig. 3-12. As we can see from
this figure there is a close agreement between the theoretical expression and the simulated
values. The dependence of N and M has been verified in the same way as for SFDR.
For small gradients the SNDR is determined by the signal-to-quantization noise ratio
(SQNR)

SQNR ≈ 6 ⋅ 14 + 1.76 ≈ 86 dB (3-42)

22
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

SNDR as a function of ky, kx=0

90

80

70

60

SNDR [dB]
50 61

60.95
40
60.9

30 60.85

60.8
20 10
−4

10

0 −7 −6 −5 −4 −3 −2
10 10 10 10 10 10
Gradient in the y−direction [LSB/(unit source)]

Fig. 3-13: Calculated (solid) and simulated (dashed) values of SNDR as a function of ky for a
14-bit DAC with M=8.

We also see that at larger gradients when M – N ≥ 3 , Eq.(3-41) may be approximated by

SNDR ≈ 17 + 6 ( M – N ) – 20 log k y dB (3-43)

An alternative method is to use the same approximation of the error signal as was the case
for the SFDR calculation. To find an approximate value of the power of the error signal we
use
T
1 2
P e ≈ P ẽ = --- ∫ ẽ ( t ) dt (3-44)
T
0
where T is the period of the error signal. With knowledge of the error signal approximation
we can rewrite Eq.(3-44) as
T ⁄4 1 2
4 4 ∆N – 1
∫ ∫
2 2 2
P e ≈ --- ẽ ( t ) dt = … = ∆ N – 1 --- t d t = -------------- (3-45)
T 4 3
0 0
We can now express the power of the noise and distortion as
2
∆ N – 1 1 A1 4( N – 1)
2
2 8
22
P ND ≈ -------------- + ------ – ------ = k y -------------------
-  1--- –  1 – --2- ----
- + ------
1
(3-46)
3 12 2 2 ( M + 1 )  3  π π  2  12
2
Using this value of P ND , SNDR can be approximated with
2N – 3
2
SNDR ≈ ------------------------------------------------------------------------------------------
- (3-47)
2 4N – 2M – 6  1  2 2 8  1
ky ⋅ 2 --- – 1 – --- ----2- + ------
3  π π  12
or, approximating SNDR for larger gradients

SNDR ≈ 15.5 + 6 ( M – N ) – 20 log k y dB (3-48)

23
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

In Fig. 3-14 the SNDR approximation of Eq.(3-47) is plotted together with simulated val-
ues, as in Fig. 3-13. As we can see from the simulations, Eq.(3-41) gives us a much better
approximation of the SNDR than Eq.(3-47) did, on the other hand the latter was much eas-
ier achieved and gives acceptably good results.

SNDR as a function of ky, kx=0

90

80

70

60
SNDR [dB]

50

61
40
60.5
30
60
20
59.5

10 −4
10

0 −7 −6 −5 −4 −3 −2
10 10 10 10 10 10
Gradient in the y−direction [LSB/(unit source)]

Fig. 3-14: Approximated (solid) and simulated (dashed) values of SNDR as a function of ky for
a 14-bit DAC with M=8.

3.5.5 Simulated Signal Spectra

The influence of linearly graded mismatch on the performance of the current-steering DAC
has been established in the previous sections. For completeness we also show typical sig-
nal spectra arising from linearly graded mismatch. Fig. 3-15 shows the output signal spec-
tra for the same input signal, but with different values of k y , k x is zero in all three.One
can clearly see how the gradient in the y-direction give rise to harmonic distortion terms
of odd order, which is typical for this kind of non-linearities.
Fig. 3-16 shows basically the same thing as Fig. 3-15, but here we have added a gradient
in the x-direction. As expected from the discussion previously, k x appears as extra noise in
the signal spectrum.

3.6 CONCLUSIONS
In this chapter we have discussed mismatch of CMOS current sources and presented a
study of a special case of matching errors, linearly graded mismatch. The study was car-
ried out for one particular way of choosing current sources from an array in a CMOS DAC,
a technique known not to be good in suppressing linearly graded matching errors. Howev-
er, the work presented can be seen as a proposed approach to the concept of linearly graded
matching errors that can be applied on other layout styles. It is desirable to keep the layout
as simple as possible in order to keep the amount of time needed to design the DAC as low
as possible. Given expected process parameter variations from the vendor one can, on a
high abstraction level, find how complex layout style is needed to reach the wanted perfor-
mance, e.g. the layout style of Fig. 3-5a) will ideally reduce the influence of linearly graded
mismatch completely, but it is much more complex to design than the layout style of Fig.
3-5b). If the latter is sufficient for the wanted application, it is preferred that it is used in-
stead.

24
 Chapter 3 - "Modeling of the Influence of Linearly Graded Mismatch"

Singel−tone output from 14−bit DAC, M=8, kx=0, ky=0

Signal Power [dB] 0

−50

−100

−150

−200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Singel−tone output from 14−bit DAC, M=8, kx=0, ky=0.0001
0
Signal Power [dB]

−50

−100

−150

−200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Singel−tone output from 14−bit DAC, M=8, kx=0, ky=0.001
0
Signal Power [dB]

−50

−100

−150

−200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized frequency
Fig. 3-15: Signal spectra for different values of ky, when kx=0.
Singel−tone output from 14−bit DAC, M=8, kx=0.001, ky=0
0
Signal Power [dB]

−50

−100

−150

−200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Singel−tone output from 14−bit DAC, M=8, kx=0.001, ky=0.0001
0
Signal Power [dB]

−50

−100

−150

−200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Singel−tone output from 14−bit DAC, M=8, kx=0.001, ky=0.001
0
Signal Power [dB]

−50

−100

−150

−200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized frequency
Fig. 3-16: Signal spectra for different values of ky, when kx=0.001.

25
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

To get a more realistic model of the DAC one needs to introduce more non-idealities than
just the linearly graded mismatch, e.g. short distance variations, wire resistance, finite
output impedance of current sources and circuit noise. Modeling of the mentioned non-ide-
alities are discussed in [4]. A suggestion for future work is to combine those properties into
a DAC model to help DAC designers optimize their design on a high level of abstraction.

26
 Chapter
4

Implementation of Current-Steering
DACs

4.1 INTRODUCTION
In the previous chapters the current-steering DAC has been described in a relatively ab-
stract way concerning mismatch and geometrical structure, but we have not described how
the DAC is really implemented. In this chapter we describe in more detail the implemen-
tation of two 14-bit DACs with two different types of current switches, and where the cur-
rent sources are placed to decrease the influence of linearly graded mismatch as described
in chapter 3.
The DACs were implemented in a 0.35µm standard digital CMOS process with three met-
al layers and two poly layers. The DACs were designed to operate at sampling frequencies
up to 88MHz , using a supply voltage of 3.3 V .

4.2 THE IMPLEMENTED STRUCTURE

In this section we present the circuit structure of the design and the way of choosing unit
sources from the array.

4.2.1 Segmentation
So far we have considered DAC structures where each bit is represented by a binary-
weighted current source which is turned on and off when the bit is 1 and 0 respectively. A
disadvantage with this structure is a phenomenon called glitches, unwanted current peaks
on the output. Glitches occur when some current sources are switched on while others are
switched off. The worst case is the transition between 011…11 and 100…00 . During this
transition we might for a moment have the incorrect input 111…11 (or some other incor-
rect input) due to non-perfect timing of the switching signals.
To avoid glitches we can use segmentation, a transformation of the binary coded input code
to thermometer code. This transformation is illustrated for a 3-bit binary input in Table 4-
1 below. We can see that during a code transition using thermometer code it will never oc-
cur that some sources are switched on while others are switched off, which means that we
will have less glitches.
With an N -bit binary word we will have a corresponding thermometer coded word of
2 N – 1 bits. When we have N = 14 , it is not suitable to have full segmentation, because
the thermometer coded word would then have 2 14 – 1 = 16383 bits. However, to avoid
large glitches we can use segmentation on some of the MSBs. In this implementation we

27
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

binary thermometer
b2b1b0 s7s6s5s4s3s2s1

000 0000000
001 0000001
010 0000011
011 0000111
100 0001111
101 0011111
110 0111111
111 1111111
Table 4-1: Example of segmentation

have chosen the 5 MSBs for segmentation.

4.2.2 The Choice of Current Sources

The way of choosing unit sources from the array described in chapter 3 has shown to be
bad in suppressing linearly graded mismatch and should be seen as an example of how
those errors could affect the performance of DACs rather than how a DAC should be im-
plemented. In the literature (e.g. [10]) layout styles have been proposed that would cancel
the linearly graded matching errors, however those are not very often easy to implement,
and will have disadvantages in terms of wire resistance, wire routing etc. In this DAC im-
plementation we have chosen to use a more simple, but yet effective way of choosing the
unit sources in order to suppress graded errors.
We know from chapter 3 that the unit sources giving current closest to the ideal value I unit
are those closest to the middle of the array, and the bits most often switched are the LSBs.
Therefore we choose to place the sources corresponding to the LSBs in the middle of the
array as shown in Fig. 4-1 a) below. The unit sources are chosen as far to the left as possible

s31
s30

I8
I7 s2
I6 s1
I5
I4 non-segmented LSBs
I3 s1
I2 s2
I1
I0

s30
s31

256 unit sources

a) b)

Fig. 4-1: Assignment of unit sources a) for the 9 LSBs and b) for the 5 segmented MSBs.

28
 Chapter 4 - "Implementation of Current-Steering DACs"

in each row, where also the switches are placed, in order to keep the wire resistance as low
as possible. The unused unit sources (white space in Fig. 4-1) are used for biasing the other
unit sources, as described in section 4.3.2. In order to decrease the influence of linearly
graded mismatch it is preferred that the sources are chosen in the middle of each row, but
then the wire resistance will increase, and a trade off between those two properties has to
be made.
The sources for the thermometer coded bits are chosen in a way developed for reducing the
influence of linearly graded mismatch, as shown in Fig. 4-1b). Each of those sources use
two rows of unit sources, one from the upper half and one from the lower half of the array
equally spaced from the center in order to cancellate the gradient in the y-direction. The
gradient in the x-direction is already taken care of by the fact that we use an integer num-
ber of rows. With exactly linearly graded mismatch this arrangement would totally erase
the mismatch for those bits. However, the mismatch is probably not exactly linearly grad-
ed, and therefore we choose the thermometer bits most often turned off (s31, s30, ...) to con-
trol the sources furthest away from the center of the array, since those are the sources that
most likely have the largest mismatch.

4.3 DAC BUILDING BLOCKS

In this section the design of a few important building blocks are discussed. The analog
parts are described at transistor level, but the digital parts are only described at a logic
level since we want to emphazise on the analog issues of the DAC design.

4.3.1 The Current Source

The currents from the unit sources are switched to a load resistance of 50 Ω . With a max-
imum output swing of 1 V and 14 bits this means that the unit current will be

1
I unit = ---------------------------
14
≈ 1.22 µA (4-1)
50 ( 2 – 1 )
In order to achieve high resolution of the DAC, the output resistance of the current sources
must be very large.. The total output resistance is a function of the input X which can be
written as

r out
R out = --------
- (4-2)
X
where r out is the output resistance of one unit source. Eq.(4-2) is motivated by the fact that
we have connected X unit sources in parallel.
In Fig. 4-2 the implementation of two types of current sources are shown. The single tran-
sistor current source in Fig. 4-2a) is the simplest possible current source, but the output
resistance of this current source, r out = 1 ⁄ g ds, 1 , is not large enough to reach high resolu-
tion. In Fig. 4-2b) we have included a cascode transistor M2 which increases the output
resistance to

g m, 2 1
r out = ------------ ------------ (4-3)
g ds, 2 g ds, 1
3
The increase of the output resistance is about a factor 10 . In order to further increase the
output resistance one could introduce even more cascode transistors, but then we will have
a larger voltage drop over the current source, which would decrease the possible output
swing of the DAC. For this implementation we choose the single cascode current source of
Fig. 4-2b), and reached an output resistance of r out ≈ 150 GΩ for a unit source.

29
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

vbias M1
vbias M1

M2
vcascode
iout

iout
a) b)

Fig. 4-2: a) Single transistor current source and b) single cascode current source.

4.3.2 Biasing
To bias the single cascode current source we use some of the unit sources in the array not
connected to any of the switches to form a wide-swing current mirror [2], as shown in Fig.
4-3. 1024 unit sources are used for the bias circuitry, and the current i ref is therefore
i ref = 1024 ⋅ 1.22µA ≈ 1.25mA . The cascode voltage, v cascode , is chosen to give as large
output swing as possible, keeping all transistors in the saturated region. Both i ref and
v cascode are produced off-chip.

vcascode
unit source

iref

1024 unit sources

for biasing

Fig. 4-3: Biasing the unit sources with a wide-swing current mirror.

4.3.3 The Switch

It is known that differential structures have many advantages [2], e.g. decreasing distor-
tion etc., and therefore the DAC is made differential. The current sources are switched be-
tween the terminals I + and I - as shown in Fig. 4-4. The simplest type of differential switch
is constructed using two MOS transistors as shown in Fig. 4-5a), however this type of
switch suffers from a phenomenon called clock feedthrough (CFT) [2]. When the switch is
turned off the channel charge has to be removed, half of the charge will then go to the out-

30
 Chapter 4 - "Implementation of Current-Steering DACs"

Q Q
I+ I-

Fig. 4-4: Differential switching of current sources.

put giving rise to an unwanted current peak. To reduce CFT we can use the so called dum-
my switch of Fig. 4-5b), the dummy transistor works as a capacitor storing the channel
charge while the switching transistor is turned off, and returning it when the switching
transistor is turned back on again. In order to store the right amount of charge, the dummy
transistor has the same length, L , as the switching transistor, but only half the width, W .
The switching signals Q and Q are further described in section 4.3.5. In this implemen-
tation we have designed two chips, one using the simple switch and another using the
dummy switch, in order to find which one works best.

switching
switching transistors
transistors

Q Q
Q Q
Q Q
I+ I-
I+ dummy I-
transistors
a)
b)

Fig. 4-5: a) simple differential CMOS switch b) differential CMOS dummy switch.

4.3.4 Binary-to-Thermometer Encoder

The simplest form of binary-to-thermometer encoding is when a 2-bit binary code is trans-
formed into a 3-bit thermometer code, something that we will call 2-3-encoding. One sim-
ple way of carrying out this encoding is shown in Fig. 4-6a). Using this circuitry we can
easily achieve 3-7-encoding as shown in Fig. 4-6b), this method can be further extended to
implement a general encoding as shown in Fig. 4-6c).

31
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

≥1 s1
2-3-encoding
s1
b0 b0
s2 ≥1 s2
b0 b1
≥1 s1 b1 s3

b1 s2 ≥1 s3

& s3 b2 s4
b)
a) s5
&

& s6

& s7

≥1 s1
N-(2N-1)-encoding
b0 b0 s1

bN-1 bN-1 s 2N – 1
≥1 s 2N – 1

bN s 2N
c)
& s 2N + 1

& s 2N + 1 – 1

Fig. 4-6: Implementation of a) 2-3-encoding, b) 3-7-encoding and c) general (N+1)-(2N+1-1)-

encoding.

When the number of bits to encode is large, the depth of this encoding circuitry is also
large. For every additional bit to encode, the depth is increased with one gate, or in an
actual implementation with two gates since an or and an and gate is implemented as a nor
and a nand gate with a following inverter. This means that for a large number of bits we
will have to reduce the clock frequency. To solve this problem we use pipelining, every
stage of the circuitry is followed by a D-flip-flop, and therefore the signal only has to prop-
agate through two gates on every clock cycle. Pipelining introduces a delay in the signal,
so we have to delay the binary coded LSBs to the same extent in order not to have a mal-
function of the DAC.

32
 Chapter 4 - "Implementation of Current-Steering DACs"

4.3.5 Switching Signal Generator

When switching a current source it is important that it is never turned off, or it will take
some time before the current settles at the right value when the current source is turned
back on again. Therefore the switches making up the differential switch as described in
section 4.3.3 should never be open at the same time, and thus we need to ensure that we
have overlapping switch signals as in Fig. 4-7 below.

Q Q

Fig. 4-7: Overlapping switch signals.

Those switching signals could be achieved using the circuitry in Fig. 4-8. The way the nand
gates are connected ensures that the outputs are never low at the same time. In order for
one of them to go low, the other has to be high.

D-flip-flop
bit input set
D ≥1 & Q

clk out
& Q

Fig. 4-8: Circuitry accomplishing overlapping switching signals.

With the set signal high, Q is high and Q is low, and with the set signal low, Q follows
the output of the D-flip-flop.

4.4 LAYOUT CONSIDERATIONS

In this section we discuss chip layout issues for the DAC.

4.4.1 The Overall Structure

Since the DAC is a mixed analog digital structure special care has to be taken in the layout
of the circuits. From an analog viewpoint the digital parts can be seen as a high frequency
transmitter giving rise to noise in the analog circuitry through capacitive coupling on the
chip. To avoid this to as large extent as possible we separate the digital parts from the an-
alog and use guard rings around the analog circuitry to shield it from the digital parts. In
Fig. 4-9 the overall structure is shown. To avoid glitches it is important that the wires from
the switch signal generator to the corresponding switch has the same length for all switch-
es, and that the resistance of those wires is as low as possible to get short switching times,
and therefore we place the switches as close to the switch signal generators as possible.
The clock signal for the digital part is distributed using a tree structure as described in
section 4.4.3.

33
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

analog parts

S
S W
31 bits
E I
thermo-
G T
meter
M C
coded
5 MSBs E H
N
T S
A I
G S UNIT SOURCE
T W
I N
I ARRAY
O A
L T
N C
G H
9 LSBs D E E
9 LSBs
E N S
L E
A R
Y A
T
O
digital parts R
S

guard between analog and

digital parts

Fig. 4-9: The overall structure of the 14-bit current-steering DAC.

4.4.2 The Unit Source

From chapter 3 we know that the design and matching properties of the unit sources are
crucial to the performance of the DAC. According to [13] metal coverage on MOS transis-
tors gives very poor matching properties, and therefore we should avoid routing wires over
the current sources, or, if this is not possible, at least cover all sources in the same way.
Fig. 4-10 shows a layout of a single cascode current source described in section 4.3.1. The
source transistor M1 is made relatively long in order to suppress thermal noise, which is
proportional to the transconductance of M1, g m, 1 , and therefore inversely proportional to
the square root of the length of M1. A long source transistors also means a small g ds, 1 ,
yielding a large output resistance. M2 is designed to have a large gain, g m, 2 ⁄ g ds, 2 , to yield
as large output resistance as possible.
The unit sources are arranged in an array with equally spaced sources. For reasons of
matching it is important that all sources have the same geometrical boundary conditions,
and therefore a frame of dummy (unconnected) sources is placed around the array.

4.4.3 Clock Signal Distribution

The pipelined structure of the digital circuitry means that there is a large capacitive load

34
 Chapter 4 - "Implementation of Current-Steering DACs"

vdd connection
substrate connections to
improve performance
gate of M1

gate of M2

output terminal

Fig. 4-10: Layout of single cascode current source

for the clock to drive. It is also important for the function of the DAC that the clock signals
to the different flip-flops has approximately the same delay. Because of these two reasons
the clock is distributed over the chip area with a tree structure as shown in Fig. 4-11 below.

clock signals out

clock signal in

Fig. 4-11: Example of clock distribution for better buffering and equal clock delays

Each inverter in the last stage will only have a small load to drive. If the wires between
two stages all have the same length, the delay will also be the same for all clock signals
from the output of the last stage.

4.5 THE FINAL CHIP

A plot of the whole DAC is shown in Fig. 4-12. The padframe which connects the circuit to
the outside of the chip is also included in the plot. When the chip is packaged, bonding
wires attached to the pads connects the circuit to external pins of the chip, as sketched in
Fig. 4-13. For this implementation a 28 pin SOIC28 package is used.
The pads used differ depending on what their purpose is. In this chip four different kinds
of pads are used.
1. VDD-pad, used for the upper supply voltage.
2. GND-pad, used for the lower supply voltage or ground.
3. Analog input/output pad.
4. Digital input pad.

Common to all types of pads are the (relatively) large metal plates where the bonding wires
are attached. The first three types basically consist of a wire connected to the appropriate

35
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

place, whereas the digital input pad is terminated with a relatively large buffer, as sche-
matically shown in Fig. 4-14, in order to have well defined signals on the chip and good
driving capability of the pad. The input pad also includes protective diodes and resistance
to ensure that the input voltage of the buffer does not reach too high or too low values, also
shown in Fig. 4-14.
To cope with the large current peaks that might occur, capacitors with reservoirs of charg-
es are connected between VDD and GND where there is chip area available. The digital
part of the circuit is by no means optimized in size. It could be made much smaller, but
since there is a lot of chip area available, some distance is kept between building blocks to
simplify routing. The total size of the chip is approximately 2.7 × 2.7 mm, containing al-
most 45 000 transistors. Some chip data is given in Table 4-2.

analog part

digital part

capacitors

2.7 mm

Fig. 4-12: Plot of the implemented DAC, including the pad frame

bonding wires connecting

the pads to the pins

Fig. 4-13: Connecting the circuit with the outside world

36
 Chapter 4 - "Implementation of Current-Steering DACs"

Buffer of inverters

PAD

protection
circuitry

Fig. 4-14: Sketch of a digital input pad structure.

Property Description
Supply voltage 3.3V
Area ( 1.7mm × 1.2mm ) core, ( 2.7mm × 2.7mm ) with pads
Transistor count ~ 45000

Process 0.35µm CMOS, 3 metal layers, 2 poly layers

Resolution 14 bits
Sample frequency 22MHz, 44MHz, 88MHz
Table 4-2: Chip data for the implemented DACs

The specified signal bandwidth for the DAC is 11 MHz , which implies a sample frequency
of at least 22 MHz . To improve the SNR we can use oversampling [2], i.e., we use a larger
sample frequency than 22 MHz to distribute the quantization noise over a larger frequen-
cy range. The noise power appearing at frequencies above the signal band is then removed
with an analog low-pass filter. When using oversampling we operate the DAC at 44 MHz
or 88 MHz .

37
 "Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters"

38
Appendix A
Using MatLab for Behavioral-Level
Simulations
A.1 INTRODUCTION
Due to the long simulation time, it is almost impossible to carry out transistor-level simu-
lations of DACs in order to characterize the influence of mismatch. Therefore it is neces-
sary to create behavioral-level models for the simulations. In this appendix we present how
such simulations can be carried out using MatLab.

A.2 BRIEF MATLAB OVERVIEW

MatLab is a short-hand notation for Matrix Laboratory and is a technical computing envi-
ronment for high-performance numeric computation and visualization. MatLab integrates
numerical analysis, matrix computation, signal processing and graphics. The basic data
element in MatLab is the matrix, and MatLab is written to easily and quickly carry out
matrix operations.
MatLab also features a family of application-specific solutions called toolboxes. The tool-
boxes contains collections of MatLab functions, called M-files, that extends the MatLab en-
vironment to solve particular classes of problems. Examples of areas where toolboxes are
available are control systems, signal processing, statistics, etc.
It is easy to create your own M-files using an ordinary text editor, such as emacs. The M-
files basically contains a sequence of MatLab commands to be executed.
For further information on MatLab we refer to [14].

A.3 CREATING DAC MODELS USING MATLAB

In the models used, the DAC is represented by a 1 × N -matrix containing the values of the
binary-weighted current sources given on the form [ I N – 1, …, I 0 ] , where I N – 1 is the cur-
rent of the most significant bit and I 0 is the current of the least significant bit. This ma-
trix is constructed from a matrix of unit source values where the mismatch is included. The
values of the chosen unit sources are summed, and the value of the binary weighted cur-
rent source is achieved.
This way of representing the DAC on a high level of abstraction only allows us to model
the influence of static non-idealities. Dynamic non-idealities, such as settling times and
glitches, has to be approached in some other way.

A.4 CREATING INPUT AND OUTPUT SIGNALS FOR THE DAC

The digital input signal is constructed using ideal A/D-conversion on the wanted output
signal, e.g. a sine or a ramp. In MatLab this is done by transforming a row-matrix contain-
ing the values of the wanted output into a matrix of ones and zeros where each row is the
digital representation of the corresponding element in the wanted output matrix, as de-
fined below.

39
 Appendix A - "Using MatLab for Behavioral-Level Simulations"

1 1 1
b N – 1 b N – 2 … b0
2 2 2
1 2 b N – 1 b N – 2 … b0
[a , a , …] ↔ (A-1)
. . . .
. . . .
. . . .

i i
a denotes the (wanted) analog value at sample instant i , and b k is the k :th bit of the cor-
responding digital number, either 0 or 1 . This transformation is done using the M-file
a2d2 [15], referred to in the code listings in section A.6.
The output signal of the DAC can now be achieved using simple matrix multiplication,
which is easily done with MatLab.

1 1 1
b N – 1 b N – 2 … b0
2 2 2
1 2 b N – 1 b N – 2 … b0 T
output signal = [ ã , ã , … ] = × [ I N – 1, …, I 0 ] (A-2)
. . . .
. . . .
. . . .

i i
Note that, even for an ideal DAC, ã and a will differ, at least for some values of i , since
the transformation in Eq.(A-1) means a loss of accuracy.

A.5 ANALYZING SIGNALS IN THE FREQUENCY DOMAIN

A fast fourier transform (FFT) algorithm is included in the signal processing toolbox,
which can be used to transform the output signal to the frequency domain. Because the
signal vectors used are of finite length (and are very short for simulation times reasons),
the elements of the signal vectors have to be multiplied with a window function in order to
yield good signal spectras. In this report all spectras are achieved using Hanning windows.
Functions carrying out this, and estimating SFDR and SNDR were developed by Wikner
[15].

A.6 M-FILE LISTINGS

In this section we present some of the M-files used for the behavioral-level simulations of
DACs with linearly graded matching errors.

A.6.1 createDAC.m
This function is used to produce a matrix containing the values of the different unit sources
from an array with linearly graded matching errors.
function [current_sources] = createDAC(NOB, kx, ky, NOx, curr_nom)
% current_sources = createDAC(NOB, kx, ky, NOx, curr_nom)
%
% createDAC returns an array of unit current sources with the nominal value
% curr_nom and a determinstic graded error.
% NOB is the number of bits to be realized, NOx is the number of
% current sources in the x-direction (no. of columns in the array), kx and
% ky is the mismatch [LSB/(unit source)] in the x and y direction
% respectively.

40
 Appendix A - "Using MatLab for Behavioral-Level Simulations"

% find the needed number of current sources in the y-direction (rows in the
% array)
NOy = ceil(2^NOB/NOx);

% use the gradient in the x-direction

x = 1:NOx;
x = x*kx*curr_nom;
x = x-mean(x);
X = ones(NOy,1);
X = X*x;

% use the gradient in the y direction

y = 1:NOy;
y = y*ky*curr_nom;
y = y-mean(y);
Y = ones(NOx,1);
Y = Y*y;

% combine the influence of the gradients in the x- and y-direction into an

% array of unit sources with linearly graded mismatch
current_sources = (X+Y’+curr_nom);

A.6.2 corr_choice.m
This function picks unit sources from an array given by createDAC.m and sums the values
into binary weighted current sources. The unit sources are chosen in a straight forward
manor described in section 3.5.
function [sources, currents] = corr_choice(NOB, kx, ky, NOx, Ilsb);

% [sources, currents] = corr_choice(NOB, kx, ky, NOx, Ilsb);

%
% creates NOB binary weighted current sources by chosing, in a straight
% forward way, unit sources from an array created with createDAC.
% currents = [Imsb,...,Ilsb], sources is the array returned by createDAC.

currents = zeros(1,NOB);
sources = createDAC(NOB, kx, -ky, NOx, Ilsb);

x=0;
y=1;
for i=NOB:-1:1
for j=1:2^(i-1)
x=x+1;
if x > NOx
x = 1;
y =y+1;
end
currents(NOB+1-i) = currents(NOB+1-i)+sources(y,x);
end
end

A.6.3 INLest.m
This function estimates the INL with respect to a best-fit straight line for each digital in-
put word and also returns a vector of input words for easy visualization with the MatLab
plot function.

41
 Appendix A - "Using MatLab for Behavioral-Level Simulations"

function [INL, inputword]= INLest(current_sources)

% function [INL, inputword]= INLest(current_sources)

%
% Returns the INL and the input word vector for a DAC defined by
% it’s current source vector [Imsb ... Ilsb]. The INL is given in [LSB]
% and the input word vector as [0 1 2 ... 2^N] (this is to make simple to
% plot INL against input word)

% find the number of bits

N=length(current_sources);

% create the input ramp (digital)

t=0:1:2^N-1;
y=a2d2(t,N);

% create the output for a ramp input

out=(y*current_sources’)’;

%find a best-fit straight line to the outputsignal (linear regression)

t_mean=mean(t);
out_mean=mean(out);
x1=t-t_mean;
x2=x1.^2;
Ilsb=sum(x1.*out)/sum(x2);
ideal_out=Ilsb*x1+out_mean;

%calculate the INL

INL=(out-ideal_out)/Ilsb;

%Make the input word vector

inputword=t;

A.6.4 DNLest.m
This function estimates the DNL with respect to a best-fit straight line for each digital in-
put word and also returns a vector of input words for easy visualization with the MatLab
plot function.
function [DNL, inputword]= DNLest(current_sources)

% function [DNL, inputword]= DNLest(current_sources)

%
% Returns the INL and the input word vector for a DAC defined by
% it’s current source vector [Imsb ... Ilsb]. The DNL is given in [LSB]
% and the input word vector as [0 1 2 ... 2^N] (this is to make simple to
% plot DNL against input word)

% find the number of bits

N=length(current_sources);

% create the input ramp (digital)

t=0:1:2^N-1;
y=a2d2(t,N);

% create the output for a ramp input

out=(y*current_sources’)’;

42
 Appendix A - "Using MatLab for Behavioral-Level Simulations"

% find a best-fit straight line to the outputsignal (linear regression)

t_mean=mean(t);
out_mean=mean(out);
x1=t-t_mean;
x2=x1.^2;
Ilsb=sum(x1.*out)/sum(x2);

% calculate the DNL

DNL=((out(2:length(out))-out(1:length(out)-1))-Ilsb)./Ilsb;

% Make the input word vector

inputword=t(2:length(t));

43
 Appendix A - "Using MatLab for Behavioral-Level Simulations"

44
Appendix B
Integrated Circuit Design with
Cadence
B.1 INTRODUCTION
In this appendix we describe the different steps of integrated circuit (IC) design. The tools
used are products of Cadence Design Systems Inc., which are assumed to be the most com-
mon tools when designing analog or mixed mode applications [16]. The design method de-
scribed is so called full-custom design, i.e. all transistors and wires are placed manually,
but there are also, at least for digital designs, a few high level design methods, using for
example VHDL, which might be preferred when larger designs are to be implemented.
Since IC is a large field, this appendix only serves as a brief presentation of the subject.
For a more extensive presentation we refer to literature treating the subject, i.e. [17] or
[18].

B.2 A BRIEF OVERVIEW OF THE DESIGN PROCESS

A flow chart of the design process when designing circuits with Cadence tools is shown in
Fig. B-1. This flow chart is, with minor modifications, valid for any kind of tools for full

Schematic
Simulations

Layout LVS
DRC

Extraction

Fig. B-1: Design flow chart.

custom VLSI design. As seen from Fig. B-1 there are three main design steps
1. Design of the circuit on a schematic level.
2. Circuit layout.
3. Netlist extraction from the circuit layout.

When designing on schematic level the design is iterated until simulations show that the
circuit works satisfactory.

45
 Appendix B - "Integrated Circuit Design with Cadence"

When the schematic is completed, a layout of the circuit has to be made, i.e., transistors,
wires etc. have to be placed on the silicon surface. Design rule checks (DRCs) are carried
out on the layout to ensure that it is possible to manufacture the layout.
A netlist is extracted from the layout. This netlist is compared with the schematic netlist
during a layout-versus-schematic check (LVS). If the netlists match, the layout is finished,
otherwise the layout has to be corrected.
The tools used to carry out the steps described in this section will be briefly presented in
the following sections.

B.3 SCHEMATIC EDITOR

As mentioned before, the first step in designing a circuit is usually to create a schematic.
A schematic view of a CMOS inverter from the Cadence Composer schematic editor is
shown in Fig. B-2a). In order for the circuit to be used as a subcell in a larger circuit, a
symbolic view has to be created. A symbolic view of the CMOS inverter is shown in Fig. B-
2b).

a) b)

Fig. B-2: a) Schematic and b) symbolic view of an inverter.

B.4 ANALOG ARTIST SIMULATIONS

The simulator in Cadence is called Analog Artist. It is easily invoked from the schematic
editor. A testbench is created in the schematic editor containing the circuitry to be tested
and other needed parts such as supply voltage sources, input sources and loads. An exam-
ple of a testbench for the CMOS inverter is shown in Fig. B-3.
Different types of simulations available in Analog Artist are, for example,
1. transient analysis,
2. AC analysis,
3. DC analysis.

The simulations also lets you sweep different parameters, e.g. transistor sizes and bias
voltages, in order to find the best possible values of those parameters.
The output of a transient analysis for the testbench of Fig. B-3 is shown in Fig. B-4.

46
 Appendix B - "Integrated Circuit Design with Cadence"

Fig. B-3: Testbench schematics for the CMOS inverter

Fig. B-4: Input (lower curve) and output (upper curve) for a transient analysis of a CMOS
inverter.

B.5 LAYOUT EDITOR

Having iterated the design in multiple passes between the schematic editor and simula-
tions, a good design has been found on the schematic level. Now it is time to make a circuit
layout. This is done with the Cadence Virtouso layout editor, a tool used to place geomet-
rical shapes of different materials on the silicon surface. A layout of the inverter used as
an example in this text is shown in Fig. B-5. There is also a DRC tool, which is used to
check that the design obeys the design rules, e.g., that no wires or transistors are placed
to close to each other and prevents the circuit to be correctly manufactured.
When the layout is finished, a netlist can be extracted. The netlist is then compared with
the schematic view to ensure that the layout really corresponds to the circuit you have sim-
ulated earlier. From the extraction you can also find parasitic components, e.g., capaci-
tances and wire resistance.

47
 Appendix B - "Integrated Circuit Design with Cadence"

Fig. B-5: Layout of the CMOS inverter.

48
Appendix C
Contribution to the NORCHIP
Conference, Nov 1999

49
 Appendix C - "Contribution to the NORCHIP Conference, Nov 1999"

50
 Modeling of the Influence of Graded Element
Matching Errors in Current-Steering DACs
K. Ola Andersson and J. Jacob Wikner
{olaa, jacobw}@isy.liu.se, Phone: +46-13-281721, Fax: +46-13-139282
Microelectronics Research Center, Ericsson Components AB
Dept. of E.E., Linköpings universitet, SE-581 83 Linköping, Sweden

Abstract — In analog and mixed-mode circuits the matching between circuit elements is cru-
cial. For example, in binary encoded digital-to-analog converters (DACs) the matching
between different bit weights can set the limit on the performance. Related to earlier work
modeling the influence of stochastic matching, the influence of graded element matching errors
on the performance of current-steering DACs is shown. Presented are calculated results that
correlate very well with simulated results. As performance measures we use both static mea-
sures as DNL and INL as well as frequency domain parameters as SNDR and SFDR. This dis-
cussion can also be applied to other DAC structures, for example switched-capacitor.

1. INTRODUCTION
The requirements on today’s telecommunication circuits are in the order of 25MHz bandwidth
and 14-bit resolution or even more [1]. A crucial bottle-neck is the interface between the digital
signal processing circuits and the transmitting/receiving amplifiers and filters. In the interface
we also have the digital-to-analog converter (DAC) and analog-to-digital converter (ADC).
In this paper we focus on the DAC, and especially the binary weighted current-steering DAC as
presented in Sec. 2 and in [2, 3, 4]. In binary weighted structures, the matching error is more or
less setting the performance of the DAC. The matching errors are both of stochastic nature and
determined by gradients in for example the oxide thickness and voltage drops over supply
wires [5, 6]. In Sec. 3 we discuss the modeling of the mismatch error for a certain DAC topol-
ogy. This type of modeling has previously been reported in for example [4]. The DAC analyzed
in this paper has a very simple structure known to be bad in suppressing deterministic mis-
match, but the approach to deterministic mismatch that we present can be applied to other
types of DACs and help us comparing different layout styles.
Mostly, wideband DACs are characterized by their behavior in the frequency domain [1]. Espe-
cially we use the signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic
range (SFDR). Some important formulas determining the SFDR and SNDR have been derived
and they are presented in Sec. 5. In Sec. 4 we also briefly address the static measures in means
of the differential nonlinearity (DNL) and the integral nonlinearity (INL).

2. CURRENT-STEERING DAC STRUCTURE

The current-steering CMOS DAC, as sketched in Fig. 1a), is suitable for high-speed and high-
resolution [2, 3, 7-8]. The basic structure needs no feedback loops and no operational amplifier
and the power efficiency is almost 100% since all current is directed to the output, where it is
terminated over a resistive load. The N -bit DAC in Fig. 1a) is constructed by using N binary
weighted current sources, I k . To improve matching, each current source I k utilizes 2 k parallel
unit current sources, I unit . The bits b i choose which current sources to connect to the output.
b 0 is the least significant bit (LSB) and b N – 1 is the most significant bit (MSB), hence the total
output current is given by
I out(n) = [ b N – 1(n) ⋅ 2 N – 1 + … + b 1(n) ⋅ 2 + b 0(n) ] ⋅ I unit = X (n) ⋅ I unit (1)
where X (n) is the binary input code X (n) = { b N – 1(n), …, b 0(n) } at the sampling instant n .

51
 a) b)
I0=Iunit I1=2Iunit IN-1=2N-1Iunit
∆k
Ik=2k-1. Iunit

b0 b1 bN-1 bk

Iout Iout,k

Figure 1: a) Current-steering DAC and b) unit current source with matching error ∆k.
M N–M
The unit sources are arranged in an array with 2 sources in the x-direction and 2
sources in the y-direction, indexed as in Fig. 2a). Although it is not a very good design strategy,
we now can form the binary weighted current sources as shown in the example of a 6-bit DAC
in Fig. 2b), where M = 3 .
i(1,1)
i(-1,1)
I5
a) b)

I4
i(-2M-1,-2N-M-1)
i(1,-1) I3
y
x dummy
I2 I1 I0 source
Figure 2: a) Array of unit current sources with defined directions and positions.
b) Assignment of unit sources to specific bits for a 6-bit DAC.

Actually, it is commonly known how to select unit current sources from an array to minimize
the influence of gradient matching errors [7-8]. However, there is much less knowledge in how
the errors really effect the output signal and the overall performance.

3. MISMATCH ERROR MODELING

The mismatch error associated with a weighted current source, I k , is modeled as an additional
current source with amplitude ∆ k in parallel as shown in Fig. 1b). Further, we model the unit
current sources in the same way as the binary weighted sources, hence a nominal current
source in parallel with an error source
i ( a, b ) = I unit + δ ( a, b ) (2)
With this notation we have:
I k = 2 k ⋅ I unit and ∆ k = ∑( a, b ):i( a, b ) ∈ I δ ( a, b )
k
(3)

Assuming that the matching errors are linearly distributed over the chip area [5, 6, 7] (current
source array) we can express the error sources as
δ ( a, b ) = k x ⋅ ( a – sgn ( a ) ⁄ 2 ) + k y ⋅ ( b – sgn ( b ) ⁄ 2 ) (4)
where k x and k y are constants describing the linearly graded matching properties of the unit
source array. The terms sgn ( a ) ⁄ 2 and sgn ( b ) ⁄ 2 compensate for the fact that there are no
unit sources with index a = 0 or b = 0 . We will use the unit [ LSB ] for all currents
( 1 [ LSB ] = I unit ) , and thus k x and k y will have the unit [ LSB ⁄ unit source ] . Combining Eq.
(3) and Eq. (4) we achieve an expression for ∆ k

52
  ∆k = ( k x ⋅ ( 2
M – 1 – 2 k + 1 + 2 k – 1 ) – ( k ⋅ ( 2 N – M – 1 – 2 – 1 ) ) ) ⋅ 2 k, 0 ≤ k ≤ M – 1
y
 (5)
 ∆ k = – k y ⋅ ( 2 N – M – 1 – 2 k – M + 1 + 2 k – M – 1 ) ⋅ 2 k, M≤k≤N–1
From Eq. (5) we can see that the gradient in the x-direction, as could be expected, only affects
the M LSBs. Due to the 2 k factor in Eq. (5) the largest errors will occur for the MSBs, pro-
vided that k x is not very large compared to k y , which probably is a valid assumption.

4. ERRORS IN THE CODE-DOMAIN

First, we use the differential nonlinearity (DNL) and integral nonlinearity (INL) to illustrate
how graded mismatch error effects the output amplitude levels. DNL and INL are defined by
DNL X = I out(X ) – I out(X – 1) – 1LSB and INL X = ∑x ≤ X DNL x (6)
where X is the input code. Since in most cases we can neglect the influence of a dc error and a
linear gain error, the DNL and INL are calculated with respect to a best-fit line (absolute error
is minimized) found using the least mean-square method and the actual output I out(X ) .
The simulated DNL and INL for an 8-bit DAC is shown in Fig. 3a) and b). There is an error
a) DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0 b) INL for an 8−bit DAC with M=4, ky=0.001 and kx=0
1 0.5

0.9 0.4

0.8 0.3

0.7 0.2

0.6 0.1
DNL

INL

0.5 0

0.4 −0.1

0.3 −0.2

0.2 −0.3

0.1 −0.4

0 −0.5
50 100 150 200 250 0 50 100 150 200 250
Input word Input word

c) DNL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001 d) INL for an 8−bit DAC with M=4, ky=0.001 and kx=0.001
1 0.5

0.9 0.4

0.8 0.3

0.7 0.2

0.6 0.1
DNL

0.5
INL

0
0.4
−0.1
0.3
−0.2
0.2
−0.3
0.1
−0.4
0
−0.5
50 100 150 200 250 0 50 100 150 200 250
Input word Input word

Figure 3: Typical DNL and INL plots for an 8-bit DAC with linearly graded matching errors (a and
b) only in the y-direction and (c and d) in both the x and y direction.
gradient only in the y-direction (compare Fig. 2a), with value k y = 0.001 [ LSB ⁄ unit source ]
and the width of the unit current source array is given by M = 4 . In Fig. 3a) we clearly see
that DNL is largest when turning on the MSB. The same holds for the simulation result in Fig.
3b). The INL is largest for X around 2 N – 1 , where the mismatch error also is largest (about
± ∆ N – 1 ). In Fig. 3c) and d) we show the DNL and INL when introducing a gradient error in
the x-direction as well. The gradients are given by k x = k y = 0.001 [ LSB ⁄ unit source ] . As
expected these plots are similar to those in Fig. 3a) and b). Even though the M LSBs no longer
are mutually matched, the dominating errors are still those from MSB, MSB-1 etc.

53
 5. ERRORS IN THE FREQUENCY-DOMAIN
Most of the characterization of the high-speed DAC is done in the frequency-domain. Since the
distortion of a converter is dependent on input dc and amplitude level, the information on DNL
and INL is insufficient. We have to find models for the frequency-domain properties as well.
When applying a full-scale sinusoid to the DAC, the output current, I out(n) , can be written as
I out(n) ≈ 2 N – 1 ⋅ sin ( 2π ⋅ f 0 ⁄ f s ⋅ n ) + e ( n ) + I DC (7)
where f 0 is the signal frequency, f s is the sample or update frequency, I DC is the signal’s dc
level, n is the sequence index, and e ( n ) is the error signal due to the linearly graded mis-
match. Using the description of error sources from Fig. 1b) and considering all current sources,
we have that the total error signal can be written as

∑k = 0 bk(n) ⋅ ∆k
N–1
e(n) = (8)
It can be shown that

∑k = 0 ∆k ≈ –∆ N – 1
N–2
(9)
Using this information we approximate the error signal with a piecewise linear signal, ẽ(n) , as
shown in Fig. 4. Making a Fourier series expansion on the approximated error signal gives us
2

1.5 input signal

1 ∆N – 1
0.5

−0.5 ẽ(n)
−1 –∆ N – 1

−1.5

−2
0 1 2 3 4 5 6

Figure 4: Input signal (dashed) and approximative error signal (solid) plotted in different scales

∞ f0
∑k = 1 Ak sin  2πk -----n with A k = ∆ N – 1 ------  1 – ------ for odd k and 0 else. (10)
4 2
ẽ ( n ) =
fs  πk  πk
Besides A 1 , the largest coefficient A k is given by the 3rd harmonic, A 3 , and because we have
applied a full-scale sinusoid at the input, the signal amplitude is approximately
A sig ≈ 2 N – 1 (11)
Combining Eq. (10) and Eq. (11) gives us the spurious-free dynamic range (SFDR) as
2
A signal ⁄2 9π 2  2 2 2 ( N – 1 )
 -----------------------
SFDR ≈ ----------------------- = ⋅ ------------------
- (12)
A 32 ⁄ 2  4 ( 3π – 2 ) ∆ N2 – 1
Using Eq. (5) for ∆ N – 1 in Eq. (12) we get
9π 2 2
2 N – 1 ⋅ 2 M + 1 2 –2 9π 2  2 2 2M –2
SFDR =  ---------------------------- ⋅  -------------------------------
- ⋅ k =  --------------
- ⋅ --------- ⋅ k (13)
 4 ⋅ ( 3π – 2 )  2 2 ( N – 1 )  y  3π – 2 2 2N y

54
Rewriting Eq. (13) in dB yields
SFDR ≈ 21.6 + 6 ( M – N ) – 20 log k y (14)
The dependence on M and N has been verified in simulations. In Fig. 5a) the theoretical value
a) b)
SFDR as a function ky, kx=0 SNDR as a function of ky, kx=0
150 90

80

70

100 60

SNDR [dB]
SFDR [dB]

50 61

60.95
40
65.5 60.9

50 65 30 60.85

60.8
64.5 20 10
−4

64
−4 10
10

0 −8 −7 −6 −5 −4 −3 −2
0 −7 −6 −5 −4 −3 −2
10 10 10 10 10 10 10 10 10 10 10 10 10
Gradient in the y−direction [LSB/(unit source)] Gradient in the y−direction [LSB/(unit source)]

Figure 5: Theoretical (solid) and simulated (dashed) values of (a) SFDR and (b) SNDR as a function
of ky for a 14-bit DAC with M=8.

of SFDR is plotted as a function of k y together with a simulated value for a 14-bit DAC with
an array width of M = 8 . We see a very good agreement between theoretical and simulated
values for larger gradients, for smaller gradients the simulated values are limited by the quanti-
zation noise, which is dependent on the FFT length used in the simulations.
In order to calculate the signal-to-noise-and-distortion ratio (SNDR) we need to find the error
signal power. We could use the same approximation of the error signal as before and sum the
squares of the Fourier coefficients, but examining Eq. (10) we see that this is not easily done,
so a statistical approach is preferred. Using Eq. (8) and defining e k(n) = b k(n) ⋅ ∆ k , we get

∑k = 0 Var ( ek(n) ) + ∑( i, k ):i ≠ k Cov ( ei(n), ek(n) )

N–1
Var ( e(n) ) = (15)

When applying a full-scale sinusoid, the dominating covariance term, appearing twice in the
sum above, is
Cov ( e N – 1(n), e N – 2(n) ) = – ∆ N2 – 1 ⁄ 48 (16)
With a few minor approximations we also find

∑k = 0 Var ( ek(n) ) ≈ ∆ N – 1 ⋅ ( 32 + 140 ⋅ 4 M – N ) ⁄ 105

N–1 2
(17)

Now we can rewrite Eq. (15) as

2
Var ( e(n) ) ≈ ∆ N – 1 ⋅ ( ( 32 + 140 ⋅ 4 M – N ) ⁄ 105 – 1 ⁄ 24 ) (18)
We are now ready to express the power of the noise and distortion, P ND , as
P ND = Var ( e(n) ) + P q – A 12 ⁄ 2 (19)
In Eq. (19), the power of the quantization noise P q is included, and also subtracted the power
of the error signal that appears at the signal frequency f 0 (compare Eq. (10)). It is known that
P q = 1 ⁄ 12 , and from Eq. (10) the value of A 1 follows. We can thus write Eq. (19) as

55
 32 + 140 ⋅ 4 M – N 1 2 2 8
P ND = ------ + ∆ N – 1 ⋅  ----------------------------------------- – ------ –  1 – --- ⋅ -----2
1 2
12  105 24  π π  (20)
Using Eq. (5) and Eq. (11) we now get
2 ⁄2
A sig 2 2N – 3
SNDR = ----------------- = -----------------------------------------------------------------------------------------------------------------------------------------------
- (21)
P ND 1 2 4 ( N – 1 ) 32 + 140 ⋅ 4 M – N 1  2 2 8
------ + k y ⋅ -------------------
2 - ⋅ ----------------------------------------- – ------ – 1 – --- ⋅ -----2
12 22( M + 1) 105 24  π π
In Fig. 5b) SNDR is plotted in the same way as for the SFDR. We see a very good agreement
between the theoretical expression and the simulated values. At small gradients, the SNDR is
determined by the signal-to-quantization noise ratio SQNR ≈ 6 ⋅ 14 + 1.76 ≈ 86 dB. We also
see that at larger gradients when M – N ≥ 3 , Eq. (21) may be approximated by
SNDR ≈ 17 + 6 ( M – N ) – 20 log k y (22)

6. CONCLUSIONS
We have derived formulas describing the frequency-domain performance of current-steering
CMOS DAC when applying linearly graded matching errors to unit current source elements.
Calculated and simulated results correlate very well. To decrease the influence of linearly
graded matching properties, different techniques and layout styles have been proposed (e.g.
[7]). However, it is desirable to make the design as simple as possible, and given expected
parameter variations one can predict what type of technique or layout style that is needed to
reach a certain goal in terms of DAC performance. The DAC structure analyzed in this paper is
rather naive. For example the lack of segmentation may increase glitches, but the approach
used to treat deterministic mismatch could also be applied to other structures and combined
with models of other error sources such as random mismatch, wire resistance, and finite output
impedance we are able to find a very good model of current-steering DACs, a model that can
be used to design high performance DACs without too much trial and error.
The authors would like to thank Niklas U. Andersson and Pierre Dalheim-Lander at
Linköpings universitet, Sweden, for their help.

7. REFERENCES
[1] P. Hendriks, “Specifying communication DACs,” IEEE Spectrum, Vol. 34, No. 7, pp. 58-
69, July 1997
[2] D.A. Johns and K. Martin, Analog integrated circuit design, John Wiley & Sons, New
York, NY, USA, 1997
[3] R.J. van de Plassche, Integrated analog-to-digital and digital-to-analog converters, Klu-
wer Academic Publishers, Boston, MA, USA, 1994
[4] J.J. Wikner and N. Tan, “Modeling of CMOS D/A Converters for Telecommunication,”
IEEE T. of Circuits and Systems II, May 1999
[5] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching Properties of
MOS Transistors,” IEEE J. of Solid-State Circuits, vol. 24, pp. 1433-39, Oct. 1989.
[6] J. Bastos, et al, “Mismatch Characterization of Submicron MOS Transistors,” Analog
Integrated Circuits and Signal Processing, Vol. 12, pp. 95-106, 1997
[7] H. J. Schouwenaars, et al, “A Low-Power Stereo 16-bit CMOS D/A Converter for Digi-
tal Audio,” IEEE J. of Solid-State Circuits, Vol. 23, pp. 1290-1297, Dec. 1988.
[8] T. Miki et al, “An 80 MHz 8-bit CMOS D/A Converter,” IEEE J. of Solid-State Circuits,
Vol. 21, pp. 983-988, Dec. 1986.

56
 References
[1] T. Starr, J.M.Cioffi, and P.J. Silverman, Understanding Digital Subscriber Line
Technology, Prentice Hall PTR, Upper Saddle River, NJ, USA, 1999, ISBN 0-13-
780545-4

[2] D.A. Johns and K.Martin, Analog Integrated Circuit Design, John Wiley & Sons, New
York, NY, USA, 1997, ISBN 0-471-14448-7

[3] P.Hendriks, “Specifying Communications DACs”, IEEE Spectrum, vol. 34, no. 7, pp.
58-69, July 1997.

[4] J.J. Wikner, Digital-to-Analog Converters for Telecommunication Applications,

Linköping Studies in Science and Technology, Thesis no.715, 1998, 91-7219-277-1

[5] S. Söderkvist, and L.-E. Ahnell, Tidsdiskreta Signaler och System

[6] R.J. van de Plassche, Integrated analog-to-digital and digital-to-analog converters, Klu-
wer Academic Publishers, Boston, MA, USA, 1994
[7] K. Lin, and C.H. Bult, “A 10b 250MSample/s CMOS DAC in 1mm2”, in Proc. of the
1998 IEEE Int’l Solid-State Circuits Conf. (ISSCC’98), pp.214-15, San Fransisco, CA,
USA, Feb 1998

[8] B.G. Streetman, Solid State Electronic Devices, Prentice-Hall Inc, Englewood Cliffs,
NJ, USA, 1995, ISBN 0-13-436379-5

[9] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching Properties of
MOS Transistors”, IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-9, Oct 1989

[10] C.A.A. Bastiaansen, D.W.J. Groeneveld, H.J. Schouwenaars, and H.A.H. Termeer
“A 10-b 40-MHz 0.8 µ m CMOS Current-Output D/A Converter”, IEEE J. of Solid-
State Circuits, vol. 26, no. 7, pp. 917-21, Jul 1991

[11] N.U. Andersson, and J.J.Wikner, “A Comparison of Dynamic Element Matching in

DACs”, in Proc. of Norchip 1999, Oslo, Norway, Nov 1999

[12] H.J. Schouwenaars, D.W.J. Groeneveld, and H.A.H. Termeer “A Low-Power Stereo
16-bit CMOS D/A Converter for Digital Audio”, IEEE J. of Solid-State Circuits, vol.
23, no. 6, pp. 1290-7, Dec 1988

[13] H. Tuinhout, M.J.M. Pelgrom, R. Penning de Vries, and M. Vertregt, “Effects of

Metal Coverage on MOSFET matching”, in Proc. of the Int’l Electron Devices Meeting,
pp. 735-8, San Fransisco, CA, USA, Dec.8-11, 1996

[14] MatLab Reference Guide, ver. 5.2.1.1420, MathWorks Inc., 1998

[15] Private communications, J.J. Wikner, Ericsson Components AB, 1999

[16] P. Dahlheim Lander, Design of an MSB Randomizer for Wide Band CMOS DAC,
Final Work, Linköping University, Sweden, 1998, LiTH-ISY-EX-ET-0159

[17] S.M. Kang, and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,
McGraw-Hill, Singapore, 1996, ISBN 0-07-114423-4

[18] N.H.E. Weste, and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Per-
spective, Addison-Wesley, USA, 1994, ISBN 0-201-53376-6
 Design of 12-bit 100-MHz Current-Steering DAC for SOC Applications
Chun-Yueh Huang Tsung-Tien Hou, and Chi-Chieh Chuang
Department of Electronic Engineering
Kun Shan Universiv of Technology
Yung-Kang, Tainan, 71003 Taiwan, R.O.C.
cyhun@,mail.ksut.edu.tw
Abstract
In this paper, we propose a 12-bit 100-MHz
current-steeringdigital-to-analog converter (DAC) for
system-on-a-chip (SOC) applications. We adapt the
segmented architecture to design this DAC to obtain
better perJ?ormances of LVL, Glitch energy, and
monotonicity. The segmented architecture includes 7-
MSBs which are decoded into 127 equally weighted
current sources and 5-LSBs which are corresponding
to binary-weighted current sources. Based on the
TSMC 0.35um 2p4m CMOS technology, we use
HSPICE to simulate the proposed DAC. The
simulation results show that the proposed DAC has the
following characteristics: INL< B.4LSB, DNL< f
0.25LSB, and settling time less than 9ns. The proposed
converter’s spuriousfree dynamic ranges (SFDfi) for
are larger than 80 dB and 65 dB at an update rate
fc& lOOMHz and its output frequencies are I MHz
and 49 MHz, respectively. The power consumption is
47 m W at the maximum conversion rate.
1. Introduction
In the applications of HDTV, video and modern
communication systems, high-speed and high-accuracy
digital-to-analog converters are indispensable
components. In the past years, many researchers have
devoted to developing the high-speed and high-
accuracy DACs [ 1-91. While designing DACs for SOC
applications, an important issue must be considered.
We need to consider how to integrate analog circuits
with memory and digital signal processing (DSP)
circuits on the same chip, and use CMOS technology
This work was supported by the MOE Program for
Promoting Academic Excellence of Universities, under Grant
EX-93-E-FA09-5-4.
117
0-7695-2403-6/05$20.00 0 2005 IEEE
Hung-Yu Wang
Chip Implementation Center,
National Applied Research
Laboratories,
Taiwun, R.0.C.
ted@,tn.cic.edu.tw
to fabricate the SOC. To design the high-speed and
high-accuracy DACs to meet the requirement of SOC
applications, a current-steering DAC architecture is
particularly suitable for SOC applications, because it
can be implemented by standard CMOS technology.
In this paper, we design a 12-bit 100-MHz current-
steering DAC. In order to reduce glitch and to ensure
monotonicity, the segmented architecture is used to
design the DAC. The common-centroid layout
approach is used to realize the layout of most
significant bits’ (MSB) unary cells current source
transistors to reduce the process graded error and
symmetrical error.
2. Design of a current-steerign DAC
Figure 1 shows the block diagram of the proposed
segmented DAC architecture. In this DAC, the
segmented architecture consists of 7-MSBs and 5-
LSBs, which are thermometer coded and binary
weighted coded, respectively. The segmented current-
steering topology is used to guarantee monotonicity for
the MSBs and to improve the performance of DNL.
The 7-MSB digits (bll * b5) are decoded by a
thermometer decoder into 127 thermometer codes, and
-
the 5-LSB binary digits (b4 bO) are directly fed to
the second D-latch array. Two D-latch array and clock
driver are used to synchronize the DAC and to reduce
glitch energy. In the current source array, there are 127
unary current cells and 5 binary weighted current cells.
According to the digital inputs, the outputs of the
second D-latch array from the 127 thermometer codes
and 5 binary codes are used to determine the DAC
output value by switching the currents of unary current
source array and binary current source array into the
output load (50 n),respectively.
 For ease of understanding the design methodology,
the basic components of the current-steering DAC are
discussed in detail as follows.

0
CLK
$j-M2
Do 1
1

NOT3 NOT4

Figure 2. The circuit diagram of D-latch

r-tw-c
Figure 1. The block diagram of the proposed current- Master
steering DAC

A. D-latch

The circuit diagram of D-latch is shown in Fig. 2. Figure 3. The clock tree structure
The D-Latch, which is the simplest digital storage
element, is a samplehold circuit and can be used to I". .+. ................................ i
keep the synchronizationof control signals in the DAC.
Basically, in the D-Latch, two cross-coupled inverters thermometer s1, sz, .... s,".,
(NOTl and NOT2) are acted as a storage unit and two encoder
inverters (NOT3 and NOT4) as buffers. When CLK is . s,"
high, transistors M 2 and M3 are turned on, and the thermometer s,"+,,s,",,, .... S F ' 4
input signal D through transistors M 2 and M3 are encoder
... ............................. ................... I..........
."

transmitted to latch output Q. The signal of Q is

dependent on the value of input D. When CLK is low,
transistors M 2 and M3 are turned off, and the Q of the
D-latch will be dependent on the input value of D just
before CLK is turned low.
Considering the circuit implementation, when CLK
is high, the input signal through transistors M2 and M3
must dominate over the positive feedback through
NOTl. In order to meet the above requirement, the
widths of the transistors of NOTl must be designed as
small as possible, i.e., at their minimum widths. With
this condition, the input signal can correctly change the
state of the D-latch.
B. Clock driver
In order to reduce the global clock timing skew, we
need to develop a good clock distribution approach to
align the switching signal with the D-latch array. In the
DAC, the clock tree structure as shown in Fig.3 is used
to improve buffering and equal clock delay to the D-
latch array and to optimize the speed and clock edge
Figure 4. Iterative implementation of a thermometer
decoder
C. Thermometer decoder
Basically, a binary code consisting of k bits is
converted into a thermometer code of 2k-1 bits.
Based on the iterative approach, a (k+l)-to- (2'+' -1)
binary-to-thermometer decoder can be constructed by
using a (&to- (2k -1) decoder as shown in Fig. 4,
where there are (2' -1) AND gates and (2' -1) OR
gates. In the proposed DAC, the input binary codes of
7-MSBs are converted into 127 bits thermometer codes.
The total delay through the thermometer decoder is the
propagation delay of six gates with inverter buffers at
the output, The difference in the delay is small enough
to guarantee over 100 MHz operation. All the decoded
data are latched at the second D-latch array before
driving the current switches.

118

......
. n.nnmn
 D. Current cell
In the DAC, the current source cannot be
completely turned off and therefore the switching
signals have to be properly matched to improve the
glitch performance. A proper switching scheme for the
PMOS differential current switch is implemented by
transistors M3 and M5 as shown in Fig.5. Two
transistors M4 and M6 with self-bias are used to
increase the output impedance of the current cell.
The output impedance of the current cell has a great
influence on the specifications of INL (integral non-
linearity) and SFDR [9,10]. The relationship between
the impedance and the achievable INL specification is
given by [ 101
T R AT2
where RL is the load resistor, runitis the LSB current,
and N is the total number of unit current sources.
Considering the frequency dependency of the
output impedance, the relation between the SFDR
specificationis given by [9]
R,, =-NRL
4s
where S is the ratio between the fundamental signal
and the second harmonic component caused by the
output impedance effect. According to Eq. (2), for a
12-bit current steering DAC, the ratio has to be at least
equal to 72 dB. If the load resistor is a 50!2 double
terminated cable and N is equal to 4095, the value for
required output impedance Routhas to be at least lOOM
!2 in the Nyquist frequency range. In order to make
the output impedance of the current cell large enough,
and to satisfy the specification of INL and SFDR, the
cascade current source configuration and the cascade
switching transistors as shown in Fig. 5 are used to
design the current cell.
Figure 5. The circuit diagram of a current cell
119
I ..
In Fig. 5 , the output impedance of the current cell
Routis approximately calculated as
Rout gm4gm3gm2ro4ro3ro2rol (3)
In the current cell, the device dimensions of the
channel width W and the channel length L for M1-M2
and M3-M6 are 6.Y2.5 and 3/0.35 pm, respectively.
Next, when we implement the DAC layout, we have
to think of some questions. For instance, the current
cell will exist transistor matching errors, i.e., size
errors, threshold voltage variations, supply and bias
voltage variations, oxide thickness variations, output
voltage variations, etc. In order to improve transistor
matching errors, in the current source array, we use
basic unit current sources from different positions to
construct this array by means of common-centroid
technique as shown in Fig. 6. This approach can
reduce the problem of process graded and systematic
errors, but it will increase the wire resistance and
capacitance as well. The shaded area is the dummy
cells for avoiding over etching of process.
Figure 6 . The floor plan common-centroid technique
of current source
E. Bias circuit
In Fig.5, the cascade current mirror in the current
cell can be used to reduce short-channel effects and
increase the output impedance, but it will limit the
signal swings. In order to reduce this limitation, a
wide-swing cascade current mirror bias scheme as
shown in Fig. 7 is used to provide the accurate bias
voltages for the current cells. In the bias circuit, the
diode-connected transistors M1, M2, M3 and M8, M9,
M10 provide a bias to transistor M4 and M12,
respectively. The transistors M4 and M12 are used to
increase the gate-source voltages of transistor M5 and
M11 and control the drain-source voltages of transistor
M5 and M11 in edge of saturation.
 The above approach can reduce the variations in the
drain-source voltage of M5 and M7 with changes in
VDD,and hence can make the bias current rout more
accurately equal to the reference current Im~. The
reference current IREF depends on external resistor R
and the device dimensions of the transistor M5.The
value of IREF can be derived as follows
‘DLI = ‘REF + G‘ S5 (4)
where K = O.S,uu,C,W I L , V,, and VT are the
transconductance parameter, the gate-to-source voltage,
and the threshold voltage, respectively. Then, the gate-
to-source voltage of V,,, can be rewritten as
0.25 LSB and 0.4 LSB, respectively, as shown in Fig.
9 andFig. 10.
For the SFDR simulation, the converter is simulated
at the condition of the update rate for a full-scale input
signal with a fkequency of 1 MHz sine wave. Fig. 11
shows that the SFDR remains above 80 dB at the
update rate of 100 MS/s. Furthermore, Fig. 12 shows
that the SFDR is above 65dE3, for Nyquist fi-equency
range simulation, in the condition of a full-scale input
signal with a frequency of 49 MHz under the sampling
rate of 100 MHz.
The settling time of the DAC is less than 911s.The
power consumption is 47 mW at the maximum
conversion rate. The summary of the performance of
the proposed DAC is shown in Table 1.

Finally, we can use Eq. (4) and Eq. (6) to determine

the reference current based on the resistor R and W/L
of transistor M5.

M1

M2

M3

Figure 8. The layout diagram of DAC

Figure 7. The biasing scheme of the current cells

3. Simulation results
The layout of the proposed 12-bit lOOMHz current-
steering DAC has been finished as shown in Fig. 8.
This circuit is simulated by HSPICE based on TSMC
standard 0.35um 2p4m CMOS process [ll]. The
power supply is 3.3 Volts and the output load resistor
is 50 SZ. The current of LSB is designed as 3 pA.The
post layout simulation results show that the static
performances of DAC in DNL and INL are less than
Figure 9. Post layout simulation for DNL of DAC

120

. . -,
. , I I..
 Table 1. Summary of the DAC performance

, . * .

4. Conclusion
. , " ~ .
~ .^ In this paper, a 12-bit 100-MHz current-mode
digital-to-analog converter (DAC) for system-on-a-
chip (SOC) applications is presented. The SFDR is
larger than 65dB for a Nyquist fimdamental signal.
Based on the TSMC 0.35um 2p4m CMOS technology,
the proposed DAC is simulated by HSPICE. The post
layout simulation results show that the proposed DAC
has the following characteristics: INL,< kO.4LSB,
DNL<3.25LSB, and settling time less than 9ns. The
power consumption is 47mW at the maximum rate.
The chip area is 6.9mm2. In the near hture, the chip
Figure 1 1. The SFDR for a 1MHz signal at a will be fabricated. After finishing the chip fabrication
1OOMHz update rate. and testing the chip's function, we will develop the
corresponding Verilog-A model of DAC in SOC
applications.

.. .. . . .. . ^. . ... . .* .
" *
5. References
[l] J. Vandenbussche, G . Van der Plas, et al., "Systematic
Design of High-Accuracy Current-Stecring D/A Converter
Macrocells for integrated VLSI System", IEEE Trans.
Circuit and Syst. II, vol. 48 NO. 3, March 2001.

[2] A. Torralba, R. G . Carvajal, J. Ramirez - Angulo and F.

Munoz, "Output stage for low supply voltage, high-
performance CMOS current mirrors," Electron. Lett. vol. 38
NO. 24 November 2002.

[31 A. Van den Bosch, M. Borremans et al., "A 12-bit

2OOMHz low glitch CMOS D/A converter," IEEE 1998
Figure 12. The SFDR for a 49MHz signal at a Custom Integrated Circuits Con$ (CICC), May 1998, pp.
IOOMHz update rate 249-252.

121
[4] B. J. Tesch and J. C. Garcia, “A Low Glitch 14-b
lOOMHz DIA Converter,” IEEE J. Solid-state Circuit, Vol.
32, pp. 249-252.
[5] M. Gustavsson, J. J. Wilner and N. N. Tan, CMOS Data
Converters For Communications. Boston, Kluwer Academic
Publishers, 2000.
[6] C. H. Lin and K. Bult, “A lob 250Msmapleh CMOS
DAC in lmm2,” in Proc. 1998 Int. Solid-state Circuit Con$
(ISSCC),pp. 214-215, Feb. 1998.
[7] C. H. Lin and K. Bult “A 10-b, 500-Msampleh CMOS
DAC in 0.6 m 2 , ” IEEE J. Solid-state Circuits, Vol. 33, No.
12, Dec. 1998.
[8] A. Van den Bosch et al., “A 10-bit 1-Gsamplesls nyquist
current-steering CMOS DIA converter,” IEEE J. Solid-state
Circuits, ~01.36,pp. 3 15-324, Mar. 2001.
[9] A. Van den Bosch, M. Steyaert and W. Sansen “SFDR-
bandwidth limitations for high speed high resolution current
steering cmos d/a converter,” in Proc. IEEE Int. Con$
Electronics, Circuit and System (TCECS), Sept. 1999, pp.
1193-1196.
[lo] B. Razavi, Principles of Data Conversion System
Design, IEEE Press, 1995. ISBN 0-7803-1093-4.
[l11 R. Gregorian, An Introduction to Mixed- ,Signal IC Test
and Measurement. New York, Oxford, 2001.
 ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

THE EXTRACTION OF TRANSISTOR MISMATCH

PARAMETERS :THE CMOS CURRENT-STEERING D/A
CONVERTER AS A TEST STRUCTURE
A. Van den Bosch, M. Steyaert and W. Sansen
K.U. Leuven,
Department of Electrical Engineering, ESAT-MICAS,
Kard. Mercierlaan 94, B-3001 Heverlee, BELGlUM
e-mail : anne.vandenbosch @ esat.kuleuven .ac.be

high measurement accuracy, ...). Furthermore, it is

ABSTRACT
Since transistor mismatch directly affects the performances
of a broad class of analog CMOS devices such as
comparators, A/D and D/A converters, it is of the utmost
importance to determine these parameters for every
available CMOS technology. Nowadays, this is done by
processing and evaluating a large number of especially
designed test structures that have no further use. This paper
presents a technique to extract the transistor mismatch
parameters from the performance of a simple current-
steering CMOS D/A converter.
1. INTRODUCTION
Due to the “explosion” of the wireless telecommunication
market a lot of effort is recently put in the integration of
digital and analog blocks on one chip. However, the
success of a mixed analog-digital system depends on the
correct operation of every system component. The analog
circuits have to be fully compatible with the digital
technology with its trend towards higher operation
frequency and higher accuracy. The matching parameters
impose a limit on the highest attainable accuracy
performance of an analog circuit in a given technology.
During the fabrication process small variations will occur
that result in a statistical variation of the transistor
properties. This variation depends on the dimensions of the
matched component and its biasing conditions. When only
a limited amount of information is available, the analog
designer has to introduce large safety margins to guarantee
the required performance of the circuit leading however to
an unnecessary power consumption and an operation speed
reduction [ 11.
For the VLSI manufacturer, it is very important to be able
to provide his customers with the necessary quantitative
data of the matching quality of his technology. This can
only be achieved by the use of dedicated test circuits that
are especially designed for this purpose (low parasitics,
necessary to follow the evolution of the matching
performance of the technology over different runs in time.
This requires a test circuit that gives a good indication of
the matching technology for a low cost. However, these
circuits are of no further use to the manufacturer or the
designer and therefor an alternative structure has been
sought for. A high performant current-steering D/A
converter is highly dependent on the matching quality of
the technology. Furthermore, the evaluation of the D/A
converter’s performance poses no problem since there
exist standardized test procedures. In this paper, the D/A
converter’s performance will be directly translated in the
matching characteristics of the technology.
The paper is organized as follows. In the section 2 the test
structures as they exist now will be shortly discussed. In
the next section the D/A converter approach will be ‘
presented. In this section the architectural choice and the
design of the D/A converter is discussed as well as the
transistor mismatch extraction procedure. In section 4
some measurement results will be shown and evaluated.
Finally, a conclusion will be formulated.
draln 1 dmlnZ drdn m
-’
4 4
&
Fig.1 : example of the test structure approach [2]
2. TEST STRUCTURE APPROACH
Until now the test circuits are constructed using an array of
about fifty to one hundred transistors with some additional

0-7803-5482-6/99/$10.0002000 E E E

11-745
digitallselection logic to be able to automate the
measurements to a large extent [2,3]. The dimensions of
VTniUraM A*c-725>mv”m
l/sqrt(area)(l/um)
Fig.2 : the quadratic standard deviation of the threshold
voltage in function of the inverse of the square root of
the area of the measured transistors
the transistors are chosen in such a way that the
the transistors span a wide interval. By measuring a large
number of chips, an accurate determination of the
mismatch parameter coefficients A, and AVT of the
Pelgrom equation[4] is possible. The test chip normally
exhibits a large geometrical symmetry and consists of an
array of identical cells. Furthermore, the chip area has to
be kept as small as possible to reduce the cost.
In this paragraph the transistor mismatch parameters of the
CMOS 0.5 Fm technology are extracted. The schematic of
the used test structure is given in fig.1. The test chip
contains 10 rows of 12 nM0S transistors with different
sizes : W L - 0.810.5, 111.4, %, 1013.2, 20120, 3.2110,
2.810.5, 110.7, 0.8120, 2010.5 pmlpm. Fifty test chips were
measured giving the results depicted in fig2 and fig.3. In
these figures, the ‘+’ indicate the results for the standard
deviations extracted from the measurements and the ‘*’
give the mean value of the mismatch parameter
coefficients.
11-746
Fig.3 : the quadratic standard deviation of the current
factor in function of the inverse of the square root of the
area of the measured transistors
The extracted values of the threshold voltage and current
factor mismatch parameter coefficients are :
AvT = 1.3mVpm
Ap =1.3%pm
As is mentioned earlier, these test chips have no other
function than the mismatch determination of the
technology and as such are a cost overhead to the
manufacturer. Therefor, both designers as manufacturers
are looking for alternative structures to determine the
transistor mismatch parameters.
3. D/A CONVERTER APPROACH
3.1 Choice of the D/A converter architecture
’
A current-steering DIA converter is based on an array of
identical current cells. The achievable resolution ultimately
relies on the matching properties of these cells which are
determined by the used process and can only be improved
by increasing the current source transistor sizes orland
adjusting the bias voltages. The close relationship between
the DIA converter’s performance and the transistor
mismatch parameters makes this circuit the ideal process
monitor.
An unary architecture is chosen because in this
implementation every current source can be accessed
separately while in a binary implementation the current
sources are grouped bit by bit. Furthermore, this
architecture has the extra advantage that it has good
dynamic specifications.
The resolution of the D/A converter is chosen to be seven
or eight bits so that enough measurements are available to
be able to work with gaussian distributions when
processing the data. Furthermore, such a DIA converter
can also be used in applications in the area of e.g. video,
HDTV and so on. This leads us to the major advantage of
using a current-steering DIA converter as a test structure.
This chip has further use, no silicon area has gone to
waste. Furthermore, the chip area can be made in the order
of a few mm2 which is considerably smaller than any test
chip reported in literature. This enables the manufacturer
to place it on every wafer having in this way a continuous
monitoring of his technology.
3.2 Design issues for the D/A converter
In this paragraph, the design plan for a current-steering
DIA converter will be shortly discussed. The circuit
schematic for one unit current cell is depicted in fig.4. The generator (HP80000)so that for different values for the
design parameters of the D/A converter will be calculated (VGs-VT)csthe current at the output of the D/A converter
for a yield estimation of 99.7 % and an output voltage will be measured (HP3457 multimeter) and
swing of 1 Volt peak to peak into a 50 R load. This leads
to a full scale drain-source current specification of 20 mb.
(=IFS).

Table 1 : the current source dimensions for different

values of the gate overdrive voltage for a DIA converter
processed in the 0.5 km technology with 1, = 20 mA

stored. At this point, for every gate overdrive voltage of

Fig.4 : the unit current cell and the biasing circuit
The dimensions of the current source transistors are
determined by the following formulas :
the current source transistors 2N-1 measured currents are
available leading to 2N-2transistor pairs (I,,I,+,)with i=l to
2N-1. Using MATLAB the values for the relative current
difference (AH) and the relative current standard deviation
o(AI/I) can be easily calculated. This gives us a curve as is
depicted in fig.5.

(3)
I line fined through the
measurement points /
Since the transistor matching parameters seem to improve
for smaller gate-length technologies, the parameters of the
0.7 pm technology can be used in a first approximation for
the design of a 0.5 pm D/A converter. Apart from the
mismatch parameters, the gate overdrive voltage of the
current source transistors has to be determined. An
l/(vGs-<T)z
appropriate value can be found by making a trade-off
between the settling time of the D/A converter and the chip Fig.5 : the quadratic relative standard deviation in
area [5]. The optimal value for the gate-source voltage of function of the inverse quadratic gate overdrive voltage
the current source is then given by a value of of the current source transistors
approximately 1.6V. If the operation frequency of the D/A
converter is of minor importance, the value of the From the IDs-V~s characteristic, the formula for the relative
overdrive voltage can be increased leading to the use of a current standard deviation is easily derived :
smaller silicon area.
The values for the dimensions of the current sources
(4)
(implemented in the 0.5 pm technology) for both the
optimal gate overdrive voltage and for a larger value can For large values of the gate overdrive voltage this formula
be found in table 1. simplifies to :

3.3 Measurement and extraction procedure of

the transistor mismatch parameters
Using Pelgrom's equation a value for the current factor
The measurements of the D/A converter can be fully mismatch coefficient can then be calculated :
automated. A program has been written that drives the data

11-747
On the other hand, for small values of ( V G S - V ~the )~~
influence of the current factor is negligible and the relative
unit current standard deviation is given by :
Since the characteristic of fig.3 is a straight line, a fitting of
d(AI/I) calculated from the measurement data gives us the
threshold voltage mismatch coefficient.
The distance term in Pelgrom’s equation can be neglected
because the current sources are switched following an S
pattern. The current source that in the layout is placed
beside to the previous measured current source is measured
next. Furthermore, to avoid the influence of edge effects
dummy rows and columns are used in current-steering D/A
converters. This guarantees the fact that all measured
transistor pairs have identical surroundings.
3.4 Measurement Results
As an example a six bit current-steering D/A converter has
been measured. The chip has been processed in a CMOS
0.5 pm technology. The results of the extraction procedure
described in the previous paragraph are given in fig.6.
Fig.6 : the measured quadratic relative current standard
deviation in function of the inverse of the quadratic gate
overdrive voltage of the current sources
From this figure the following values for the mismatch
parameter coefficients can be obtained using equations 6
and 8 :
11-748
These results are in good agreement with the results
obtained from the test structures described in paragraph 2.
This proves that the D/A converter can indeed be
successfully used as a process monitor for mismatch.
4. CONCLUSION
In this paper the CMOS current-steering D/A converter has
been presented as a test structure for matching purposes.
Using a D/A converter as a test structure has a large cost
advantage since no especially designed test structures will
be necessary anymore. The time to implement the.se
circuits and the silicon area they consume can now be used
to design a chip (=DAC) that can be further used in e.g.
telecommunication applications.
The extraction procedure of the transistor mismatch
parameters has been described and is verified by
comparing the measurement results of a six bit current-
steering D/A converter and the results obtained from the
classical test structures.
5. ACKNOWLEDGEMENT
The authors wish to thank Alcatel Microelectronics for
their support.
6. REFERENCES
[I] P. Kinget and M. Steyaert, “Impact of Transistor Mismatch
on the Speed-Accuracy-Power Trade-off of Analog CMOS
Circuits”, Proceedings of the IEEE Custom Integrated
Circuits Conference (CICC), May 1996
[2] J. Bastos and al., “Mismatch Characterization of Small Size
MOS Transistors”,Proceedings ofthe IEEE 1995 Int. Conf: ,
Microelectronic Test Structures, vol. 8, March 1995, pp.
27 1-276
[3] T. Serrano Gotarredona and B. Linares Barranco, “Cheap
and Easy Systematic CMOS Transistor Mismatch
Characterization”, Proceedings of the IEEE International
Symposium on Circuits and System (ISCAS), California,
June 1998
[4] M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching
Properties of MOS Transistors”, IEEE Journal of Solid
State Circuiri, vol. SC-24, Oct. 1989, pp. 1433-1439
[5] A. Van den Bosch and al., “Modeling and Realization of
High Accuracy, High Speed Current-Steering CMOS DIA
Converters”, Accepted for publication in the Elsevier
Measurement Journal
Folded-Current-Steering DAC: An Approach to Low-
Voltage High-Speed High-Resolution D/A Converters
Soheil Radiom Behzad Sheikholeslami
Integrated Systems Lab., IC-Design Lab.,
EE Dept. ECE Dept.
Ferdowsi University University of Tehran
Mashhad, I.R.Iran Tehran, I.R.Iran
soheil_radiom @ieee.org
Abstract- In this paper, a new topology for CMOS current
steering DAC, i.e. folded current-steering structure, suitable
for low-voltage applications is presented. Using the folded
structure, more voltage headroom will be available for the
current-source devices increasing the output impedance of the
current sources. The DAC linearity is thus improved. Also this
novel topology improves the value of PSRR and output voltage
swing without SFDR degradation and results in more constant
load for current cell. Also a current-steering logic decoder with
differential outputs is suggested. Besides, gain boosting is
applied to increase the output impedance of current source.
These techniques are used to design a 12-bit 200MS/s DAC
with 1.5-V power supply and more than 72dB SFDR is
achieved in all frequencies. Also Monte-Carlo simulations show
that the probability of an SFDR of more than 65dB is more
than 90% for an input frequency of 100MHz.
I. INTRODUCTION
The recent growth in the market demand for VLSI
circuits and also the advance in implementing digital
integrated circuits have made the interface between the
analog and digital parts of a system as one of the most
challenging blocks of the system to design. Applications in
the area of video and wireless communications need DACs
with high performance. For these applications, among
different architectures, the current-steering configuration is
frequently chosen due to its superior performance from the
speed, resolution and power consumption points of view. On
the other hand, designing high-speed high-resolution data
converters is more challenging with lower supply voltages,
Although at low frequencies the output impedance and
mismatch between current sources have the main influence
on linearity [1], in high-speed, high- resolution DACs, the
most important parameter for evaluating the performance is
Spurious Free Dynamic Range (SFDR) which is mostly
limited by finite output impedance, charge feedthrough,e
major carry glitches and spikes in common switch nodes and
power supply noise.
0-7803-9390-2/06/$20.00 ©2006 IEEE 4783
Hamed Aminzadeh Reza Lotfi
Integrated Systems Lab., Integrated Systems Lab.,
EE Dept. EE Dept.
Ferdowsi University Ferdowsi University
Mashhad, I.R.Iran Mashhad, I.R.Iran
In section II, the current-steering D/A converters, their
basics and their conventional structure are described. Section
III introduces the proposed folded structure. In section IV
simulation results confirming the effectiveness of the
proposed approach are presented following by conclusions in
section V.
I VARIOUS CURRENT-STEERING TOPOLOGIES
Current-steering DACs are based on an array of the
matched current sources that are switched to the output node
based on the input digital code. Three different ways of
implementation are available, namely binary, unary and
segmented architecture. Each of the architectures will be
briefly discussed.
A. The Binary Weighted Architecture
In the binary implementation, the binary digital input
codes directly control N binary-weighted current sources, i.e.
each switch conveys a current to the output node that is twice
larger than the current of the previous least significant bit.
This architecture suffers from the poor matching
performance of non-equal current sources. Large glitches are
also expected in this structure.
B. The Unary Architecture ( Thermometer coded)
In the unary architecture, the current sources are switched
to the output node based on the thermometer version of the
input binary code. 2N -1 unit current sources, equal to ILSB
are switched. The matching performance is much better than
the binary architecture and the glitches are smaller and code
dependent; however the decoder complexity is added to the
circuit.
C. Segmented Architecture
th
In order to employ the advantages of both architectures
the segmented topology is proposed, i.e. the binary
architecture is employed for less significant bits whereas the
ISCAS 2006
unary structure for more significant bits. The degree of
segmentation in a current-steering DAC has major influence
on both the structure ofthe converter and on its performance.
Segmentation rather than binary-weighted architecture is
often used for improving DNL, glitch and SFDR
performance [2] at the expense of exponential increase in the
area and much more complexity because ofthe thermometer
decoder. A brief overview of advantages and disadvantages
of each architecture is given in Tablel.
Table 1: Advantages and disadvantages of various architectures
I D
Architecture N N Glitch Power Area Complexity
L L
Binary = |++ ++ ++
- u ±++ _ - +
Unary _ +
Segmented = +
This also increases the power consumption and the
required design time. Of course one should consider that
increasing the digital part will increase the digital noise and
also time skews get bigger that mostly degrade the dynamic
performance. It is obvious that a good segmentation choice is
very important and of course application dependent. Yet the
choice is often based on experience rather than on founded
decisions [3]. We have chosen 6 bits for segmentation for
our designed DAC.
D. DAC Building Blocks
Fig. 1. shows the block diagram of the segmented D/A
converter. It consists of 6 bits in the binary and 6 bits in the
unary sub-DACs. The thermometer decoder turns the binary
code into the thermometer code. The dummy decoder
compensates the delay of the thermometer decoder. Current
sources are implemented in this way for matching reasons.
B6 B7 l i
Thermometer Decoder
CLK Switch Matrix I H Latch
_ £
_~ *,(D___
f~~~~iI
Illllll
ca
Figl. Block diagram of a segmented architecture
4784
E. Conventional Structure
In Fig.2 the conventional structure of a cell is shown.
Although one can use single-ended output for current-
steering DACs, the use of differential output signal is more
favorable. Not only the common mode noise is attenuated,
but also the output impedance requirement for each current
cell is significantly reduced. To have high output impedance
in the current sources for better performance, it's common to
use transistors with channel lengths much longer than the
minimum available length in the process. This results in a
small W/L which in turn yields relatively large VGS. The
consequence ofthis choice is that, in order to bias the current
source transistors in the saturation region which is required
to get high output impedance, the VDS of those transistors
must be relatively large which limits the output swing. While
higher output impedance limits the swing, it has a major
effect both on SFDR and on the linear behavior of the DAC
[4]. On the other hand, higher output impedance decreases
the effect of input signal glitching on the performance ofthe
current source. In this structure larger swing cause the
voltage drops on switches and current sources become
smaller, so the operation region ofthem gets closer to linear,
thus the performance degrades effectively. Also the output
swing directly affects the load of the current source which
causes degradation in its ideal performance.
In order to overcome these issues, effective solutions are
pt
VDD
* * *
£
||.
III. PROPOSED ARCHITECTURE
Fig.3 shows the proposed architecture for current-
~~~~~~~~~~~~steering
DAC that considerably reduce the challenges
mentioned in previous section about conventional design.
Here transistors MFOLD provides a constant current. Thus the
current ofthe load resistors is again proportional to the input Vdd
digital code. However, there are several advantages.
As the drain-source voltage of the fold transistors can be
adjusted, the headroom voltage on the switches and current
sources is increased, i.e. larger VDS for CS, CAS and switch
transistors are provided, so higher SFDR and more linearity
as a result of increase in current source output impedance is
obtained. Also, this increase in their VDS leads to better Gate of Mca
PSRR. On the other hand, increasing the output impedance Source of Mcas
will improve the performance of the current sources as well
and make their behavior more robust against the data-
dependent transitions caused by input signal variations on
node V, [5]. Moreover what transistor Mk does is to shield 'r
the critical node (Y) from loading effect of Rload and the
effect of the output voltage swing on the performance of
current sources and thus to provide a more constant load for Fig.4. The applied gain booster for increasing output impedance
current cell. Also it reduces the effect of input code spikes on
the output nodes. VDD
Here the effect of charge feedthrough which seriously
degrades the performance of conventional DACs [6] is
considerably decreased in the output node as there is no CLK CLK
direct path to the output. So there is no need for the cascode VIP T_'_L__
transistor above switches that was offered in [4] which limits
the swing. Also here one can get more swing without SFDR
degradation as a consequence of any limitation on VDS of
current cell transistors.
The CMFB used in the folded branch is for compensating
the variations in various temperatures.
Another technique applied to the circuit is gain boosting
which effectively increases the output impedance and leads Fig.5. Latch circuit
to more SFDR and better linear behavior. For obtaining more
gain the boosting amplifier of Fig. 4 is used in the circuit. Another proposed technique employed in the circuit is
using current-steering logic with differential outputs for
binary to thermometer decoder that significantly reduces the
effect of the decoder output voltage spikes in the circuit.
VDD
Faster transitions push the spurious outputs to out-of-
band frequencies. Besides, fast switching can decrease the
transition energy. The charge injected by the capacitive
FVCMFB + coupling ofthe digital signals to the output is independent of
1.I /1 I_ MFOLD the switching speed, but the time ofunbalanced switching is
reduced [3] and this is the reason of choosing NMOS
0 * 0 0 yswitches here. Considering the fact that in the offered
r -./-11-/ 1MK structure the direct path between input signal and output is
F,,
> rl removed, the effect of glitch energy in the output node
IV\
x I @ _ substantially decreases.
dump
Lg out The circuit depicted in Fig.5 has been employed for the
CAS 41-0 T tlatch circuit, previously proposed in [7].

IV. SIMULATION RESULTS

, = The proposed DAC has been simulated using HSPICE
using BSIM3v3.1 model parameters of a 0.1 8-pim CMOS
Fig.3. Folded current steering cell process. DAC SFDR is depicted vs. output signal frequency
in Fig.6. The minimum value ofthe SFDR obtained for input
signals with frequencies up to 100MHz is 72dB. The output

4785
swing is 1.2 Vp-p,djf with a 25-Q load and a power-supply V. CONCLUSION
voltage of 1.5V. At 200 MSample/s the analog and digital In this paper, a new topology for current steering DACs
parts consume 85mW. Monte-Carlo simulations considering was presented. This topology results in larger VDS on
the mismatches of the current sources show that the current-source transistors which causes higher output
probability of an SFDR of more than 65dB for a Nyquist-
frqecipti mor tha 900 frequenc input is more impedance and as a consequence better performance and
than90PSRR. Also this method provides constant load for current
cells and improves output voltage swing without SFDR
Resolution 12 degradation. Also the proposed techniques for the binary to
thermometer decoder, using current steering logic with
Decoding Segmented (6+6) differential outputs, as well as gain-boosted current sources
Nyquist update frequency 200MS/s improve the circuit behavior considerably. Simulation results
Differential output signal 1.2Vpp of a 12-bit 200MHz DAC confirm the effectiveness of the
Supply voltage 1.5V proposed techniques.
Iload 25mA
SFDR up to Nyquist freq. > 72 dB
INL 1LSB ACKNOWLEDGMENT
DNL 0.7 LSB The authors would like to express their appreciation for
Total power consumption @ 85 mW Dr. Robert Neff and Dr.Ola Anderson for providing ongoing
Nyquist rate guidance.
Technology 0.18prm CMOS

77 REFERENCES
[1] K.Doris, J.Briaire, D. leenaerts, M.Vertregt, A.van Roermund "A 12b
76 - 500MS/s DAC WITH >70dB SFDR up to 120 MHz in 0.18um
CMOS," IEEE International Solid-State Circuit Conference 2005.
75 - \ [2] Chi-Hung Lin and Klaas Bult " A 10-b 500-MSample/s CMOS DAC
in 0.6mm2," IEEE JOURNAL OF SOLID-STATE
74 - \ CIRCUITS,VOL.33, NO 12 ,DECEMBER 1998.
[3] Jurgen Deveugele, Michiel Steyaert " A 10b 250 MS/s Binary-
Weighted Current-Steering DAC," IEEE International Solid-State
a_ \; / , _+,Circuit Conference 2004.
72 - [4] A.Van den Bosch, M.Steyaert and W.Sansen "SFDR-Bandwidth
Limitation for high speed high resolution Current Steering CMOS
71 - D/A Converter,"
[5] W.Schofield "A 16b 400MS/s DAC with <-8OdBc IMD to 300MHz
70 - and <-160dBm/Hz Noise Spectral Density," ISSCC Dig.Tech.papers,
Feb.2003.
69 I_ I_ I_ I_ I_ I_I [6] Van Beek, K.Doris, J.A.Hegt and Van Roermund "Optimum
3/64 7/64 11/64 15/64 19/64 25/64 29/64 31/64 Segmentation for high speed current steering Digital-to-Analog
Converters,"
f/fs
[7] A.Van den Bosch, F.Borremans, Michel Steyaert , Willy Sensen " A
10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A
Converter," IEEE JOURNAL OF SOLID-STATE
Fig.6 SFDR VS signal frequency. The sample rate is 200MS/s CIRCUITS,VOL36,No.3, MARCH 2001.

4786
 Linköping Studies in Science and Technology
Thesis No. 715

CMOS Digital-to-Analog Converters

for Telecommunication Applications

J Jacob Wikner

LiU-Tek-Lic-1998:50

Department of Electrical Engineering

Linköpings universitet, S-581 83 Linköping, Sweden

Linköping August 1998

 Linköping Studies in Science and Technology
Thesis No. 715

CMOS Digital-to-Analog Converters

for Telecommunication Applications

J Jacob Wikner

LiU-Tek-Lic-1998:50

Department of Electrical Engineering

Linköping University, S-581 83 Linköping, Sweden

Linköping, August 1998

 CMOS Digital-to-Analog Converters
for Telecommunication Applications

Copyright  1998 J Jacob Wikner

Department of Electrical Engineering

Linköpings universitet
S-581 83 Linköping
Sweden

ISBN 91-7219-277-1 ISSN 0280-7971

Printed in Sweden by UniTryck, Linköping, 1998
 Abstract

In telecommunication systems, most of the information processing is performed in the

digital domain, but the signal carrying the information must be transmitted using analog
signals. Therefore, the use of digital-to-analog and analog-to-digital converters is
unavoidable.

The general basics of digital-to-analog converters are described in this thesis. A combi-
nation of behavioral-level, circuit-level, and layout-level descriptions, as well as design
methodologies are presented. A thorough description of the design of a CMOS Nyquist-
rate digital-to-analog converter chipset for wideband radio and VDSL applications, and
of a CMOS oversampling digital-to-analog converter for ADSL applications is given.
Measurement results are presented as well as suggestions on how to improve perfor-
mance.

In these kinds of applications, it is the dynamic performance of the converters that deter-
mines the quality of the device. Commonly, the characterization of the converters is done
in the frequency domain. We have focused on how static and dynamic properties are
affecting the output spectrum. In the thesis we present important work on how these
effects are modeled and how they apply to a CMOS current-steering digital-to-analog
converter structure as used in the Nyquist-rate chipset. It is shown how the output imped-
ance, matching, and noise are affecting the performance when changing fundamental
component values of the circuit. This work has resulted in four publications, and the
results can be used as a guide when designing high-resolution converters.

Since large mixed analog/digital circuits contain both complex analog and digital parts
it is important to be able to simulate and vary parameters on a higher behavioral-level.
This makes it possible to use faster simulation tools to find structures near the optimum.
With time-consuming circuit-level simulations these structures are only verified. This
allows a faster design flow. Especially during the design of the oversampling converter
this design strategy has been used and MatLab models have been developed.
 Part A: Acknowledgment

I would like to thank my supervisor, Ph. D. Nianxiong Tan, for all the great help and
encouragement he has given me. As he said, “... before you know how to drive a car, you
first have to crash it some times ...”

The help with discussions and to make the working day more interesting, the whole
group, Electronics Systems at Linköping University, with our supervisor Prof. Ph. D.
Lars Wanhammar, is acknowledged. I would especially like to thank Mikael Gustavsson
for valuable discussions and great help. All the help from former Ph. D. students at
Electronics Systems (former Applied Electronics) is acknowledged.

Very much thank you, the Ericsson people; Gunnar Björklund and Jan-Erik Eklund
(MERC, Ericsson Components AB), and Bengt E. Jonsson (Ericsson Radio AB). Thanks
for the great help with Cadence; Helge Stenström (Ericsson Radio AB), and for the guide
into the mysterious world of measurements; Peter Pettersson (Ericsson Radio AB).

The work is financially supported by the Swedish National Board for Industrial and
Technical Development (NUTEK) and the Strategic Research Fund (SSF).

To my family and especially my wife, Ulrica.

 Table of Contents

CMOS
Digital-to-Analog Converters for
Telecommunication Applications
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Outline of the Thesis ................................................................................ 1
1.2 Papers and Conference Contributions ...................................................... 2
1.3 Nomenclature, Acronyms, and Abbreviations ......................................... 3

Part A:
Overview:
Digital-to-Analog Converter Design
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Research Background .............................................................................. 5
1.1.1 The DAC 5
1.1.2 The Telecommunication Situation 6
1.1.3 Higher-Level Design 8
1.2 Signals and Coding Schemes ................................................................... 9
1.2.1 Signal Definitions 9
1.2.2 Digital Numbers and Representation 10
1.3 xDSL Standards ..................................................................................... 12
1.4 The CMOS Transistor ............................................................................ 14
1.4.1 Operation Regions and Small Signal Characteristics 15

i
 Table of Contents

1.4.2 Parasitic Capacitors 16

1.5 Circuit Noise .......................................................................................... 17
2 The Ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Discrete-Time Properties ....................................................................... 19
2.2 Quantization and Discrete-Amplitude Properties .................................. 21
2.2.1 Quantization Types 21
2.2.2 Quantization Noise 22
3 DAC Performance Measures . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Static Measures ...................................................................................... 25
3.1.1 Differential Non-linearity, DNL 26
3.1.2 Offset Error 27
3.1.3 Gain Error 28
3.1.4 Integral Non-linearity, INL 28
3.1.5 Monotonicity 29
3.2 Dynamic Measures ................................................................................ 30
3.2.1 Glitch 30
3.2.2 Clock Feedthrough, CFT 32
3.2.3 Non-linear slewing 32
3.3 Frequency-Domain Measures ................................................................ 32
3.3.1 Signal-to-Noise Ratio, SNR 33
3.3.2 Harmonic Distortion, HDk 33
3.3.3 Total Harmonic Distortion, THD 33
3.3.4 Signal-to-Noise-and-Distortion Ratio, SNDR 33
3.3.5 Spurious-Free Dynamic Range, SFDR 34
3.3.6 Effective Number of Bits, ENOB 34
3.3.7 Inter-Modulation Distortion, IMD 34
3.3.8 Multi-Tone Power Ratio, MTPR 35
3.3.9 Peak-to-Average Ratio, PAR 35
3.4 DAC Comparison .................................................................................. 36

Part B:
Nyquist-Rate Digital-to-Analog
Converters for VDSL Applications
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2 Nyquist-Rate DAC Structures . . . . . . . . . . . . . . . . . . . . . . . 39
2.1 Charge-Redistribution DACs ................................................................ 39
2.2 Current-Steering DACs ......................................................................... 40
2.3 R-2R Ladder DACs ............................................................................... 41

ii
 Table of Contents

2.4 Comparison ............................................................................................ 42

3 DAC Performance Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Influence of Amplitude Level Uncertainties ......................................... 44
3.2 Influence of Output Impedance Variations ............................................ 45
3.3 Influence of Current Source Mismatch .................................................. 48
3.3.1 Deterministic Variations of the Mismatch 49
3.3.2 Stochastic Variations of the Mismatch 51
3.4 Influence of Circuit Noise ...................................................................... 54
3.5 Influence of Timing Uncertainties ......................................................... 57
4 A CMOS DAC Chipset
for VDSL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1 Practical Design Considerations ............................................................ 59
4.1.1 Unit Current Sources 60
4.1.2 Current Switches 63
4.1.3 Segmentation of the MSBs 66
4.1.4 Digital Circuits 67
4.2 Chip Implementation ............................................................................. 67
4.3 Simulation and Measurement Results .................................................... 69
4.3.1 Test Signal Generation 70
4.3.2 Measurement Results 72
4.3.3 Measurement Conclusions 73
5 Improvements of
the DAC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1 Digital Correction .................................................................................. 75
5.1.1 Intentional Pre-Distortion 75
5.1.2 Calibration and Trimming Techniques 77
5.2 Dithering ................................................................................................ 78
5.2.1 Randomization of Segmented Current Sources 78

Part C:
Oversampling Digital-to-Analog
Converters for ADSL Applications
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2 Oversampling DAC
Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.1 Interpolation Filters ................................................................................ 84
2.2 Modulator ............................................................................................... 86

iii
 Table of Contents

2.2.1 Signal Feedback Modulator 87

2.2.2 Error Feedback Modulator 89
2.2.3 Higher-Order Signal Feedback Modulators 90
2.3 Semi-Digital FIR Filter .......................................................................... 91
2.4 Analog Smoothing Filter ....................................................................... 92
2.5 Trade-Off Discussion ............................................................................ 93
3 A CMOS Oversampling
DAC for ADSL Applications . . . . . . . . . . . . . . . . . . . . . . . . 95
3.1 Practical Design Considerations ............................................................ 95
3.1.1 Interpolation Filters 95
3.1.2 Modulator 96
3.1.3 Semi-Digital FIR Filter 99
3.1.4 Analog Smoothing Filter 103
3.2 Simulation Results ............................................................................... 104
3.3 Chip Implementation ........................................................................... 107
3.4 Improvements of OSDAC Design ....................................................... 108
3.4.1 Interpolated FIR Filter 108

Conclusions

References

iv
 CMOS
Digital-to-Analog
Converters for
Telecommunication
Applications

1 Introduction
This thesis is divided into five parts and is outlined in Sec. 1.1. Except this introduction
and the conclusions’ part, the thesis consists of three major parts as described below.

1.1 Outline of the Thesis

The three major parts of the thesis describe the different stages of the research concern-
ing digital-to-analog converters (DACs) for telecommunication applications.
The first part, Part A: Overview: Digital-to-Analog Converter Design, introduces the
reader to the background and problems concerning the DAC. We also give a brief descrip-
tion of different signals, telecommunication standards, digital codes, and CMOS transis-
tors. The DAC as a black box is discussed and the ideal DAC with its properties on a
behavioral-level is presented. In this part the important static and dynamic performance
measures are discussed as well as frequency domain measures. This thesis part functions
as a background and overall description of the DAC and is only elementary introduction
for the reader that is already familiar with the concepts of digital-to-analog conversion.

1
 CMOS Digital-to-Analog Converters for Telecommunication Applications

In Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications the wide-

band DAC is presented. For very high data rate digital subscriber line (VDSL) and wide-
band radio, wideband converters are needed. The “simplest” way to construct this type of
DAC is to use a binary weighted source structure – a structure without feedback. How-
ever, to meet high performance specifications, certain improvement techniques, e.g., cal-
ibration, digital correction, etc., may be needed. This implies a certain redundancy and
feedback. These issues are discussed in this part. The design of a 1.5V - 5V CMOS DAC
chipset for VDSL and wideband radio applications is presented. It has been done in co-
operation with Nianxiong Tan (GlobeSpan Semiconductor, Red Bank, NJ, USA, for-
merly Ericsson Components, Kista, Sweden). Important contributions concerning work
on modeling and simulation on behavioral-level of the binary converter structure are pre-
sented. The results may be used to understand fundamental limitations of the performance
and to give a design guide in general.
Presented in Part C: Oversampling Digital-to-Analog Converters for ADSL Applica-
tions is the oversampling technique which offers possibilities to reach a very high
dynamic performance. However, this technique also introduces some other problems that
have to be analyzed. In this part, the design of a 3V - 5V CMOS 14-bit oversampling dig-
ital-to-analog converter (OSDAC) for asymmetric digital subscriber line (ADSL) appli-
cations is presented. The design has been done in co-operation with Yonghong Gao
(ESDLab, KTH, Stockholm, Sweden) and N. Tan. There are important issues concerning
simulation on behavioral-level of the whole converter presented in this part.
The thesis is concluded in the Conclusions part.

1.2 Papers and Conference Contributions

In this section papers and publications with Wikner as author/co-author are presented.
For overall background description of design, simulation, telecommunication standards,
etc., we use papers as
• N. Tan, J. Erlands, and J. J. Wikner, “Fully Differential Line Driver,” Pending
Swedish Patent, [67].
• N. Tan and J. J. Wikner, “A CMOS Digital-to-Analog Converter Chipset for
Telecommunications,” IEEE Magazine on Circuits and Devices, vol. 13, no. 5,
pp. 11-16, Sept. 1997, [68].
• H. Träff and J. J. Wikner, “Snapshot Sampling for ultra-high speed data
acquisition,” Electronics Letters, vol. 33, no. 13, pp. 1137-9, June 1997, [72].
• J. J. Wikner and N. Tan, “Influences of Circuit Imperfections on the Dynamic
Performance of DACs,” in Proc. of the 15th Norchip Sem., pp. 336-43, Tallin,
Estonia, Nov 10-11, 1997, [75].
• J. J. Wikner and N. Tan, “Influences of Circuit Imperfections on the
Performance of DACs,” Analog Integrated Circuits and Signal Processing, to
be published, 1998, [76].
• J. J. Wikner and N. Tan, “Modelling of CMOS digital-to-analog converters
for telecommunication,” in Proc. of the 1998 IEEE Int’l Symp. on Circuits and
Systems, Monterey, CA, USA, May 31 - June 3, 1998, [77].
• J. J. Wikner and N. Tan, “Modelling of DACs for telecommunication,”
Internal Report, Linköping University, Sweden, 1997, [78].

2
 Introduction

1.3 Nomenclature, Acronyms, and Abbreviations

Notation Description
F{ } Fourier transform
L{ } Laplace transform
R Set of real numbers

 t≥0
u(t ) Step function, u ( t ) =  1
 0 t<0
Z Set of integer numbers
β Transconductance parameter, β = K' ⋅ ( W ⁄ L )
C ox Oxide capacitance per gate area

fN Nyquist frequency, f N = f s ⁄ 2
f OSR Oversampling frequency, f OSR = OSR ⋅ f s
fs Sampling or update frequency

gm Small-signal transconductance

g ds Small-signal output conductance, g ds = 1 ⁄ r ds

k Boltzmann’s constant, k = 1.321 pJ/K
K' Transconductance parameter, K' = µ 0 C ox
µ0 Charge mobility

q Fundamental electron charge, q = 0.1602 aC

r ds Output resistance of the transistor, r ds = 1 ⁄ g ds
t ox Oxide thickness
ADC Analog-to-digital converter
ADSL Asymmetric digital subscriber line
BP Bandpass (filter)
CDMA Carrier division multiple access
CFT Clock feedthrough
DAC Digital-to-analog converter
DMT Discrete multi-tone
DNL Differential non-linearity
DSP Digital signal processor
DWMT Discrete wavelet multi-tone
FIR Finite-length impulse response
FFT§ Fast Fourier transform
HD k Harmonic distortion given by the k -th tone

3
 CMOS Digital-to-Analog Converters for Telecommunication Applications

Notation Description
HDSL High data rate digital subscriber line
HDTV High definition television
HP Highpass (filter)
IIR Infinite-length impulse response
IFFT Inverse fast Fourier transformation
IMD Intermodulation distortion
INL Integral non-linearity
LP Lowpass (filter)
LSB Least significant bit
MSB Most significant bit
NTF Noise transfer Function
OFDM Orthogonal frequency division multiplexing
OSR Oversampling ratio
PAM Pulse amplitude modulation
PCM Pulse code modulation
PSD Power spectral density
THD Total harmonic distortion
SC Switched capacitor
SI Switched current
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
STF Signal transfer function
VDSL Very high data rate digital subscriber line
Table 1-1: Constants, values and variables used in the thesis.

4
 Overview:
A
Part A:

Digital-to-Analog
Converter Design

1 Introduction
In this introductory part we describe and motivate the research background to the mate-
rial presented in the thesis. An overall view of the telecommunication situation is given,
and especially the roles that the digital-to-analog converter (DAC) and analog-to-digital
converter (ADC) play in the front-end and back-end of a transceiver are discussed. In
some way, the digitally processed information has to be transmitted over a channel using
only analog signals and a certain transmission technique. Therefore, the use of ADCs and
DACs is unavoidable in telecommunication applications, and the converters may very
well be the bottleneck of the whole system.
The research background, digital codes, xDSL standards, the CMOS transistor, and cir-
cuit noise are discussed in this chapter.

1.1 Research Background

We present a short background to the research focused on DACs for telecommunication
applications.

1.1.1 The DAC

At the behavioral-level the function of the DAC is a mapping function from a digital sig-
nal to an analog signal. The converter may be described by a black box with a number of
inputs and outputs, Fig. 1-1, and a transfer function describing how the output will react
on the input (1-1).

5
 Part A: Overview: Digital-to-Analog Converter Design

For a single ended output Nyquist-rate converter with an input word length of N bits, the
amplitude level at the output for an offset binary code would be

A out = A ref ⋅ ( x 0 + x 1 ⋅ 2 + x 2 ⋅ 2 2 + … + x N – 1 ⋅ 2 N – 1 ) (1-1)

where A ref is the reference level for the least significant bit (LSB), x 0 , i.e., the amplitude
value at the output when only the LSB is active, and x N – 1 is the most significant bit
(MSB) in the digital input word X = ( x N – 1, x N – 1, …, x 1, x 0 ) . Naturally, there are sev-
eral ways to implement a converter of this kind [23, 37, 56, 58]. This is further discussed
in Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications.

Digital Digital-to-Analog Analog

Input Conversion Output
Figure 1-1: The digital-to-analog converter as a black box.

The converter may also be constructed as a finite-state machine where the output
depends on previous states of the converter. This is used in feedback strategies or special
assigned converters as for example an oversampling digital-to-analog converter
(OSDAC) that uses pulse coded modulation (PCM) [11, 56]. It is further described in
Part C: Oversampling Digital-to-Analog Converters for ADSL Applications.
Future research will focus on how the signal information can be used to improve the per-
formance of the converter. With feedback strategies the output of the circuit is sensed and
with that information we vary parameters controlling the transfer function of the converter
and the performance may be improved. A use of redundancy can also improve the results.
By extending the digital code into more bits and use a higher resolution we can use redun-
dant parts of the converter to correct errors (non-linearities) that are generated [56]. Cal-
ibration techniques have been implemented in audio DACs which have a smaller
bandwidth [11]. For wideband DACs where the bandwidth is large there might be prob-
lems with using feedback since it limits the bandwidth and reduces speed. Some transmis-
sion schemes use time-slots during which no information is sent. For some calibration
techniques it may be possible to use samples of the generated output signal at a slower
rate than the transmission rate, i.e., using the time-slots where no information is sent. The
problem still, is that the output of a DAC is analog and that the correction most often is
done digitally. In an implementation, extra analog-to-digital conversion that might be
needed for a specific correction technique should be avoided, since this may increase the
complexity dramatically.

1.1.2 The Telecommunication Situation

A classical telecommunication system is divided into a transmitter, a channel, and a
receiver [26]. As shown in Fig. 1-2, the transmitter consists of a source, an encoder, and
a modulator. Correspondingly, the receiver consists of a demodulator, a decoder, and a
sink. This thesis focuses on the modulator and especially the final circuits putting the sig-
nal on the channel; the digital-to-analog converters.
From a circuit designer’s perspective, we can divide the different blocks into digital
parts, mixed analog/digital, and pure analog parts. The digital part can further be divided
into hardware and software components. For the mixed analog/digital part stands convert-

6
 .

ers, filters, and amplifiers, which have to interact with each other. In the transmitter, the
digital code vectors are transformed into a proper analog representation and then put on
the channel, which finally is reversely transformed by the receiver.

Digital Mixed Analog/Digital Analog

Source Encoder Modulator

Channel

Sink Decoder Demodulator

Figure 1-2: Classical view of communication system. The system can be divided into digital parts,
mixed analog/digital parts, and analog parts.

Mixed analog/digital circuits also introduce some additional problems [33], e.g., inter-
ference from the digital circuits on the analog circuits, noise from supply lines, etc. Spe-
cial care has to be taken during design and simulation of these circuits.
Another approach is the so called coded modulation, where the source, encoder, and
modulator are no longer optimized separately. Instead the ambition is to optimize the
whole transmitter (and receiver) as one unit. This also implies new possibilities for the
design of mixed analog/digital parts, where new simulation and design methodologies
may be used.
In this thesis we focus on the digital subscriber line standards [83-88], which commonly
are referred to as xDSL which is the overall notation for several standards (or de facto
standards) as ADSL, HDSL, VDSL, etc. The general structure of a transceiver for wide-
band radio and very high data rate digital subscriber line (VDSL) is sketched in Fig. 1-3
and a block view of a modem for asymmetric digital subscriber line (ADSL) is shown in
Fig. 1-4. Generally, the existing copper wire telephone nets are to be used for the xDSL
applications, as is further described in Sec. 1.3.

Analog Wideband Digital

RF Filter A/D Filter
DSP

Digital Wideband Analog

DSP Filter D/A Filter
RF
Mixed Analog/Digital System
Figure 1-3: Transceiver for VDSL applications.

Traditionally, video DACs have been used in telecommunication applications, since the
transmission speed for earlier applications has been low enough [17, 22, 52]. As the trans-
mission speed increases as well as the number of users, the requirements on the converters
are much higher. The converters are specially designed, assigned for this specific situa-

7
 Part A: Overview: Digital-to-Analog Converter Design

tion. In the future we will probably see more specific circuits optimizing the whole system
with the converters, amplifiers, and filters at the front-end and back-end of the transceiver,
with the goal to minimize a cost function as for example the overall power consumption.
The ambition is also to be able to put the DAC and/or ADC directly on the line or antenna
to minimize the number of analog components, such as mixers, modulators, and amplifi-
ers [15].

Wideband Analog Line

D/A Filter Driver
Front End

Splitter
Digital

Subscriber

Pots
Line
Interface
Wideband Analog
AGC
A/D Filter
Pots Interface
Mixed Analog/Digital System
Figure 1-4: Modem for ADSL applications over the existing telephone system.

We also see varying sensitivity to performance in different transmission schemes. Some

allow more noise, but less distortion and vice versa. Among dynamic performance mea-
sures, we find the signal-to-noise ratio (SNR), the total harmonic distortion (THD), the
spurious-free dynamic range (SFDR), and the signal-to-noise-and-distortion ratio
(SNDR). It can be shown that in principle from a certain degree of non-linearity, it is the
SFDR that determines the SNDR and THD, and thereby the total performance of the con-
verter.
For most telecommunication applications it is the dynamic performance of the converter
that determines the quality of the transceiver [6]. The converter could limit the total qual-
ity of the transmission channel and be the bottleneck of the system.

1.1.3 Higher-Level Design

Due to the high complexity of a converter or in general, a mixed analog/digital circuit, it
is important to have good models. We now see more exhaustive models on behavioral-
level that are used in higher-level simulation tools as for example MatLab or similar [1,
48, 74, 80]. Simulations on circuit-level or layout-level are very time-consuming and a
faster design flow can be achieved by using higher-level simulation methods, Fig. 1-5.
The models are verified using results from measurements and simulations.
Using a circuit-level description of the converter, the signal types used may be current,
e.g., current-steering DAC, voltage, e.g., resistor-string DAC, and/or charge, e.g.,
switched-capacitor DAC. On a higher level we do not have to consider signal types, only
the basic principle of the converter. In this way, the influence of noise, non-linearity, and
other circuit imperfections can be analyzed in a more fundamental way.
When designing analog circuits we have to consider all levels of the design. At behav-
ioral-level we can improve results by using different coding techniques and at circuit- or
layout-level the skills of experienced analog designers are used. The combination of
knowledge in behavioral-level simulation and design, and knowledge in layout-level sim-
ulation and design is very attractive. In this thesis we are trying to combine the knowledge
of the behavior of the converter with simulation, modeling, implementation, and measur-

8
 .

ing, with focus on the use in telecommunication applications.

Simulation &
Specifications Verification

Layout-Level
Implementation
Behavioral-Level
Description & “Faster”
Simulation Design
Circuit-Level
Flow
Circuit-Level Implementation
Models
Layout-Level
Models

Figure 1-5: Behavioral-level design and simulation provides a faster design flow.

1.2 Signals and Coding Schemes

We define a signal as a current, charge, or voltage that carries information. Different sig-
nal types as well as different digital codes are presented in this section.

1.2.1 Signal Definitions

A signal can be divided into a number of groups depending on its properties, i.e., dis-
crete-time, continuous-time, discrete-amplitude, and continuous-amplitude signals [37].
As combinations of these we find the analog or the digital signal, Fig. 1-6.

a(t) T
a(n)

a) t b) n

Figure 1-6: Signals with a) analog and b) digital representation.

With an analog signal we understand a signal that is both continuous-time and continu-
ous-amplitude. The analog signal is described by a mapping function, f , from the time
point, t , to the amplitude A = f ( t ) as

t → ( A = f (t)) (1-2)

where t, A ∈ R and R is the set of real numbers.

With a digital signal we understand a signal that is both discrete-time (uniform sam-
pling) and discrete-amplitude. The digital signal is described by a mapping function, f ,
from the discrete-time point, nT , to the amplitude A = f ( nT ) as

nT → ( A = f ( nT ) ) (1-3)

where n ∈ Z and A ∈ A L , Z is the set of integer numbers, A L is the set of possible am-
plitude levels determined by the digital code used, and T is the time period between two

9
 Part A: Overview: Digital-to-Analog Converter Design

consecutive values.

1.2.2 Digital Numbers and Representation

There is a number of different codes with their special purpose and properties [42].
Examples on different codes are given in Table 1-1, they are also further described in this
section.
Assume that the digital number, X , can be written as

X = ( x N – 1, x N – 2, …, x 2, x 1, x 0 ) (1-4)

where x N – 1 is the MSB and x 0 is the LSB. For signed digital numbers we refer to x N – 1
as the sign bit. We only discuss the integer numbers in this thesis.
In an offset binary code a number is given by
N–1
X = ∑ 2k ⋅ xk = x 0 + 2x 1 + … + 2 N – 1 ⋅ x N – 1 (1-5)
k=0

Using the offset binary code we cannot represent negative numbers. The range of the
code is

0 ≤ X ≤ 2N – 1 (1-6)
In the thesis we focus on using offset binary codes. In current-steering DACs this is a
convenient method, Chapter 4 in Part B: Nyquist-Rate Digital-to-Analog Converters for
VDSL Applications .
The signed-magnitude code uses the MSB as sign bit. x N – 1 = 0 indicates a positive
number and x N – 1 = 1 a negative. The other bits indicate the magnitude as for an offset
binary code. A number is given by
N–2
X = ( –1 ) xN – 1
⋅ ∑ 2k ⋅ xk (1-7)
k=0

One effect is that there are two representations for the zero value; 0…00 and 10…00 .
The signed-magnitude code also may have operand sign-dependent operations which
introduces extra control logic and computation time [42]. The range of the code is

X ≤ (2N – 1 – 1) (1-8)
The signed-magnitude allow though some special structures for binary weighted current-
steering DACs [56].
In a one’s complement code we define the number as
N–2
X = –xN – 1 ⋅ (2N – 1 – 1) + ∑ 2k ⋅ xk (1-9)
k=0

Also with this representation there is a situation with two zeros; 0…00 and 1…11 . The

10
 .

range of the code is

X ≤ (2N – 1 – 1) (1-10)

Offset Two’s One’s Signed-

Value Therm.
Binary compl. compl. Magn.
7 111 1111111
6 110 0111111
5 101 0011111
4 100 0001111
3 011 011 011 011 0000111
2 010 010 010 010 0000011
1 001 001 001 001 0000001
0 / -0 000 000 000 / 111 000 / 100 0000000
-1 111 110 101
-2 110 101 110
-3 101 100 111
-4 100
Table 1-1: Different types of digital codes.

The two’s complement code also utilizes a sign bit in the MSB position. The digital
number is given by
N–2
X = – 2N – 1 ⋅ xN – 1 + ∑ 2k ⋅ xk = x 0 + 2x 1 + … – 2 N – 1 ⋅ x N – 1 (1-11)
k=0

and the range of the code is

–2 N – 1 ≤ X ≤ ( 2 N – 1 – 1 ) (1-12)
The two’s complement code has good properties for arithmetic operations and therefore
used in several applications.
In the thermometer code, the number of ones in the code determines the represented
number. The number is given by
2N – 1
X = ∑ xk (1-13)
k=1

and in an order set we have that

( xk + 1 = 1 ) ⇒ ( xk = 1 ) (1-14)

The thermometer code is suitable for segmentation of sources, when a number of equally
large sources is desired.

11
 Part A: Overview: Digital-to-Analog Converter Design

1.3 xDSL Standards

The telecommunication industry forms new standards to meet the requirements on
higher speed and the demands from more and more users. Naturally, there is a large num-
ber of different standards for different applications. A few of them are described in this
thesis, although it should be emphasized that several telecommunication standards still
not have found their final acceptance as a standard and they only work as de facto stan-
dards.
All xDSL techniques are intended to be used on the existing copper wires and the trans-
mission rate is highly dependent on the length of the wire [83]. There is a large need to
use the already existing plain old telephone system (POTS) as an information channel for
higher speed, Fig. 1-7. The normal speech channel is separated from the high-speed data
channel with splitters, and the other information is handled by specially assigned modems
and switches [12, 83]. The channels using the xDSL techniques bridges the gap between
the local network and the broadband network.

Broadband Splitter
Network Local
e.g., Radio, Network
Fibre, etc. “existing”
copper wires
Telephone
(Voice)
Figure 1-7: Applications of the xDSL technique. The information from a broadband network is
transferred to the local network via copper wires of the existing telephone net.

Since the transmission speed for ADSL can be around 6Mb/s, it is a suitable standard for
internet access, services as video-on-demand and similar. For VDSL the transmission
rates are even higher and therefore it may be used for broadband network.

ADSL
POTS
HDSL
VDSL
f [Hz]
4.3k 1.1M 50M
Figure 1-8: Frequency domain characteristics of different xDSL techniques.

The frequency ranges for different standards are shown in Fig. 1-8 and summarized in
Table 1-2.

Standard Transmission Rate [Mbit/s]

ADSL Downstream: 1.5 - 9 Upstream: 0.016 - 0.640
HDSL Both ways: 1.544 - 2.048
VDSL Downstream: 13 - 52 Upstream: 1.6 - 2.3
ADSL-Lite Downstream: 0 - 1 Upstream: 0 - 0.8
Table 1-2: Transmission rates for different standards.

12
 .

The xDSL standards use modulation techniques as for example discrete multi-tone
(DMT), carrierless amplitude phase (CAP), and discrete wavelet multi-tone (DWTM).
The DMT technique is basically a version of orthogonal frequency division multiplexing
(OFDM). We briefly discuss the standards; ADSL and VDSL:
• Asymmetric digital subscriber’s line (ADSL)
The ADSL uses an asymmetric transmission scheme, since for most applications from
the single user’s point of view, the downstream transmission speed is higher than the
upstream, which is utilized in ADSL. With the DMT modulation the data is associated
with a number of carriers. The carriers are individually orthogonal and are at the positions
fk = k ⋅ f0 (1-15)

where f 0 = 4.3125 kHz and k is an integer. The number of carriers used is determined
by the quality of the line and the mode of operation. If the line is perfect 249 tones are
used in the frequency range from 25.875kHz to 1.104MHz. The output spectrum of a
DMT signal with 240 tones is shown in Fig. 1-9. Shown in the figure is also the frequency
domain specification according to the ANSI T1E1.4 working group [83] as summarized
in Table 1-3.

ADSL Specifications

−40

−60

−80

−100

−120

−140

−160

−180

4 5 6 7
10 10 10 10
Figure 1-9: Output amplitude spectrum of a 240-tone DMT signal shown with frequency domain
specifications for the ADSL standard [83].

The number of bits associated with a certain carrier is given by the signal-to-noise ratio
within a 4.3125kHz bandwidth centered around the specific carrier. According to the
specifications [82, 83], the SNDR has to be given (in dB) by
SNDR ≥ 3N + 20 and SNDR ≥ 38 (1-16)

where N is the number of bits that can be associated with the carrier.
Since the ADSL specifications still are hard to meet, the ADSL-Lite standard (Table 1-
2) with reduced requirements has evolved. The reader can find more information about
the overall ADSL techniques in [82-90].

13
 Part A: Overview: Digital-to-Analog Converter Design

Frequency Band [kHz] Upper Bound [dB] (f in kHz)

0-4 – 97.5
4 - 25.875 – 92.5 + 21 ⋅ log ( f ⁄ 4 ) ⁄ log 2
25.875 - 1104 – 36.5
1104 - 2208 – 36.5 – 36 ⋅ log ( f ⁄ 1104 ) ⁄ log 2
2208 - 3660 – 72.5 – 24 ⋅ log ( f ⁄ 2208 ) ⁄ log 2
3660 - 11040 – 90
Table 1-3: Specifications on the ADSL output spectrum.

• Very high data rate digital subscriber’s line (VDSL)

As for ADSL, the VDSL also uses an asymmetric transmission scheme, and in the begin-
ning, the VDSL standard evolved from the ADSL. However, the ambition is to reach the
same data rate for the downstream as the upstream rate, since VDSL more is to use within
a larger network. The transmission schemes are basically, CAP, DMT, or DWTM, and the
frequency range for the VDSL technique is from 300kHz to 700kHz (upstream) and
1MHz to 100MHz for downstream.
As for the ADSL, the standard is not really set and committees are trying to find a com-
mon standard. The VDSL is suitable for package handling as ATM, and the applications
are for example HDTV, internet access, etc.
The reader can find more information about the VDSL technique in [86-90].

1.4 The CMOS Transistor

In this thesis, we focus on the complementary metal oxide semi-conductor (CMOS) pro-
cess. The CMOS process is relatively simple and cheap as well as very high integration
of complex circuits is provided, hence suitable for low power and high-speed [57]. The
vision is that the CMOS transistor soon will be able to reach the same speed as the bipolar
device.
The MOS device has four terminals; gate, source, drain, and bulk, Fig. 1-10. The bulk is
connected to the substrate and the gate is separated from the substrate by a gate silicon
oxide layer.

a) D b) S
B G B G

S D
Figure 1-10: Circuit symbols for the a) NMOS and b) PMOS transistor.

For the PMOS transistor we use heavily p-type doped source and drain. The substrate is
of n-type. For the NMOS transistor the source and drain are heavily n-type doped, and the
substrate is p-type doped.

14
 .

1.4.1 Operation Regions and Small Signal Characteristics

Dependent on the voltage applied on the terminals, different operation regions are found.
In this description we use the NMOS transistor and by inverting all voltages correspond-
ing results for the PMOS transistor are achieved. Also see Fig. 1-11a) for description of
voltages.
iD Gate (G) iD
Drain (D)
a) b)
vDS vgs
gmbsvgs gmvgs gds
vSB
vGS
Source (S)

Figure 1-11: NMOS a) circuit symbol and b) small-signal schematics.

In weak inversion (subthreshold region) the transistor is cut-off and only a very small
current (leakage current) is flowing through the transistor. In strong inversion the gate-
source voltage, v GS , is higher than the threshold voltage, v T , and a considerably larger
current, i D , may flow from source to drain. When the drain-source voltage, v DS , is lower
than the effective voltage, v eff = v GS – v T , the current is linearly dependent on the gate-
source voltage. When the drain-source voltage, v DS , is higher than the effective voltage,
v eff , the channel will become pinched-off, i.e., saturated, and the current is no longer lin-
early dependent on the gate-source voltage. The drain current, i D , for the NMOS transis-
tor in the different operating regions is approximately given by [37]:
• Cut-off region, ( v GS < v T ) :

iD ≈ 0 (1-17)

• Linear region, ( v GS > v T ) and ( v DS < v eff ) :

µ 0 C ox W
i D ≈ --------------- ⋅  ----- ⋅ ( 2 ( v GS – v T ) – v DS ) ⋅ v DS ⋅ ( 1 + λv DS ) (1-18)
2  L

• Saturation region, ( v GS > v T ) and ( v DS > v eff ) :

µ 0 C ox W
i D ≈ --------------- ⋅  ----- ⋅ ( v GS – v T ) 2 ⋅ ( 1 + λv DS ) (1-19)
2  L

where λ is the channel length modulation factor, µ 0 is the charge mobility, C ox is the
oxide capacitance per gate area, W is the channel width and L is the channel length. The
threshold voltage, v T , is given by

v T = V T 0 + γ ⋅ ( 2 φ F + v SB – 2 φ F ) (1-20)

where V T 0 is a constant given by the material, γ is the body-factor, and 2 φ F is the sur-
face potential at strong inversion. The notations

15
 Part A: Overview: Digital-to-Analog Converter Design

K' = µ 0 C ox , S = W ⁄ L , and β = K' ⋅ S (1-21)

are also used throughout the thesis.

It should be noted that the equations (1-17) through (1-20) are approximations of the first
order. Short channels give rise to second-order effects that strongly may modify the
results derived by using the equations above.
In analog design we try to use the transistors in their saturated region (except switches),
since the drain current is approximately only determined by the gate-source voltage (1-
19). This gives a better control over linearity and operation of the circuits [33].
We also need to know the small signal parameters of the MOS transistor, Fig. 1-11b),
which are derived in the quiescent point. The transconductance, g m , of the transistor is
defined as
∂i D
g m = ----------
- (1-22)
∂v GS
Q

In the linear and saturation regions the transconductance is

g m, lin ≈ β ⋅ V DS and g m, sat ≈ 2β ⋅ I D (1-23)

The output conductance of the transistor, g ds , is given by

∂i D
g ds = ----------
- (1-24)
∂v DS
Q

which in the linear and saturation region is

g ds, lin ≈ β ⋅ ( V GS – V T – V DS ) and g ds, sat ≈ λ ⋅ I D (1-25)

The influence of the source-bulk voltage also gives rise to a gain factor of

∂i D ∂v T
g mbs = ----------
- = g m ⋅ ----------- (1-26)
∂v BS ∂v SB
Q Q

which in the different regions is

γ
g mbs, lin ⁄ sat ≈ ------------------------------------------- ⋅g = η ⋅ g m, lin ⁄ sat (1-27)
2 ( 2 φ F + V SB ) 1 / 2 m, lin ⁄ sat

1.4.2 Parasitic Capacitors

A fundamental limit to the performance is the capacitive load at circuit nodes. With the
MOS transistor a number of capacitors is associated, as shown in Fig. 1-12. In general
they are divided into three kinds, those associated with the depletion regions, those asso-
ciated with the gate and the operation region, and finally those associated with irregular-
ities and unwanted overlaps in the geometrical structure of the MOS transistor.
When designing analog circuits it is necessary to analyze the influence of these capaci-
tors carefully. Increasing the transistor sizes also increases the capacitors and thereby the

16
 .

bandwidth of the circuit is affected. In Table 1-4 the capacitor sizes in different operation
regions are summarized.

Cgs Cgd
S D
Csb Cgb Cdb
B
Figure 1-12: Capacitors associated with the terminals of the transistor, Cgs, Cgd, Csb, Cgb, and Cdb.

Operation region Gate-Bulk, C gb Gate-Source, C gs Gate-Drain, C gd

Cut-off C ox WL 0 0

Linear 0 C ox WL ⁄ 2 C ox WL ⁄ 2
Saturation 0 2C ox WL ⁄ 3 0
Table 1-4: Variations of capacitors associated with the transistor in different working conditions.

The charges at C gs and C gd are changing when the switching voltage at the gate is
changing. This forces extra charge to redistribute to the drain and source. When switching
analog signals using digitally controlled switches, e.g., sample-and-hold circuits, the
capacitors may introduce glitches and current spikes in the analog signal. This clock
feedthrough (CFT) gives rise to noise and distortion in the analog signal [71].

1.5 Circuit Noise

We consider the noise to be an unwanted and, in principle, undeterminable voltage, cur-
rent, or charge [20]. Noise is a fundamental limit to the performance of analog circuits. In
DACs the signal-to-noise ratio (SNR) determines the resolution of the converter. The
noise is characterized by its power spectral density (PSD) as

i2
S ( f ) = ------ (1-28)
∆f

where i 2 is the average normalized mean-square noise current and ∆f is the frequency
variable. The shot noise, thermal noise, and 1 ⁄ f noise (flicker noise) are briefly dis-
cussed:
• The shot noise PSD, arising when a dc current, I , is applied to a pn-junction, is
given by
S ( f ) = 2qI
where q is the fundamental electron charge.
• The thermal noise PSD through a resistance, R , is determined by
4kT
S ( f ) = ----------
R

17
 Part A: Overview: Digital-to-Analog Converter Design

where k is the Boltzmann’s constant and T is the absolute temperature. For the
CMOS channel we have an extra correction factor to the expression. The PSD of
the noise current through the drain of the transistor is given by
8
S ( f ) = --- kT g m
3
where g m is the transconductance of the transistor.
• The flicker noise (or 1 ⁄ f noise) PSD is determined by
Ia
S ( f ) = K f ⋅ -----b
f
where a , b , and K f are material-dependent variables. For a and b , typical values
are a ≈ 1 and 0.8 ≤ b ≤ 1.3 .
For high-speed CMOS applications it is the thermal noise that is dominating. For dis-
crete-time circuits we also have to consider the concept of sampled noise or switched
noise.

18
 2. The Ideal DAC

2 The Ideal DAC

It is important to understand the properties of an ideal digital-to-analog converter. The
ideal reconstruction of a discrete-time signal is made by ideal lowpass (LP) filtering [37].
In the time domain, this implies pulse amplitude modulation (PAM), i.e., weighting of the
discrete-time values with sinc functions, Sec. 2.1. Due to the non-causal properties of a
sinc function, this operation is practically impossible to fulfil.
Further on, we discuss the resolution of an ideal DAC. If the resolution is limited, i.e.,
the number of bits in the converter is finite, the output signal is discrete-amplitude, hence
there is a quantization noise in the output signal if the number of bits is large enough. With
an infinite number of bits, the noise and distortion disappear.

2.1 Discrete-Time Properties

The output of the DAC with a finite number of bits is a discrete-amplitude and discrete-
time signal. It is denoted x ( nT ) where T is the update cycle time or T = 1 ⁄ f s . The fre-
quency spectrum of the output is given by

X ( e jωT ) = ∑ x ( nT ) ⋅ e – jωTn (2-1)

∀n

The spectrum is repeated over the frequency range, since

X ( e jωT ) = X ( e j ( ωT + 2π ) ) (2-2)
The amplitude spectrum is shown in Fig. 2-1. For a discrete-amplitude signal, as dis-
cussed above, there would be a noise floor, or even distortion terms, through out the fre-
quency range as well.

|X(ejωT)|

ejωT
−2π −π π 2π
Figure 2-1: Discrete-time amplitude spectrum.

The generation of the continuous-time signal, hence the extraction of the wanted infor-
mation, from the discrete-time spectrum is performed with an ideal lowpass filter as
shown in Fig. 2-2. The frequency spectrum of the continuous-time signal, X ( ω ) , is

X ( ω ) = T ⋅ X ( e jωT ) where ωT ≤ π (2-3)

19
 Part A: Overview: Digital-to-Analog Converter Design

|X(ejωT)|

ejωT
−2π −π π 2π
Figure 2-2: Ideal lowpass filtering with pulse amplitude modulation.

In the time-domain, (2-3) corresponds to the operation

x(t ) = ∑ x ( nT ) ⋅ sinc ( f s ( t – nT ) ) (2-4)

∀n

where the discrete-time values are weighted with the sinc functions, i.e., pulse amplitude
modulation (PAM). This is however impossible to accomplish in a real implementation
since the sinc function is non-causal. In the real case, the common way to reconstruct the
signal is to use sample-and-hold circuits on the output, hence the output is described by
pulse waves. Let x̂ ( t ) be the reconstructed output signal as

x̂ ( t ) = ∑ x ( nT ) ⋅ [ u ( t – nT ) – u ( t – ( n + 1 )T ) ] (2-5)
∀n

where x ( nT ) are the discrete-time values and u ( t ) is the step function. The frequency
spectrum of the reconstructed signal is

1 – e – jωT
X̂ ( ω ) = F { x̂ ( t ) } = ---------------------- ⋅ ∑ x ( nT ) ⋅ e – jωnT =
jω ∀n
T
– jω ---
= e 2 ⋅ sinc ( ωT ⁄ 2 ) ⋅ X ( e jωT ) = C ( ω ) ⋅ X ( ω ) (2-6)

The amplitude spectrum of the sinc weighting function, C ( ω ) , is shown in Fig. 2-3. As
is seen from the figure there is an attenuation of the original signal spectrum within the
Nyquist frequency band, f N = f s ⁄ 2 . Images also occurs since C ( ω ) is non-zero at fre-
quencies above the Nyquist frequency and the discrete-time signal is repeating, (2-2). The
images are removed or attenuated with an LP filter with cut-off frequency at the Nyquist
frequency. To compensate the attenuation within the signal band, an anti-sinc filter at the
output may be used as well. At the Nyquist frequency, f N , there is an attenuation of

C ( 2π ⋅ f N ) = C ( π f s ) = 2 ⁄ π ≈ 0.637 (2-7)

A simple approach to compensate the distortion is to use a filter, H as , that fulfils the
approximate equation

H as ( ω ) ⋅ C ( ω ) ≈ 1 (2-8)

fs
in the frequency range ω ≤ 2π ⋅ ----- .
2
The filter can be implemented in the digital domain at the input of the digital-to-analog
conversion as well as using an analog filter at the output [7, 17, 30, 47].

20
 2. The Ideal DAC

|C(ω)|
1

0.64

ω
πfs 2πfs 3πfs 4πfs
Figure 2-3: Sinc weighting characteristics due to sample-and-hold elements.

2.2 Quantization and Discrete-Amplitude Properties

The representation of the digital code can be given in different ways, as was discussed
in Sec. 1.2.2. Generally, we can chose whatever representation or mapping function we
want. In most cases, however, we use two different ways to represent the signal; by uni-
form or non-uniform quantization. The quantization give rise to noise, so called quantiza-
tion noise. If the number of bits is small, distortion components are also visible in the
spectrum. In an OSDAC, where the number of bits often is small, the quantization noise
and distortion terms are highpass (HP) filtered. This is further discussed in Part C: Over-
sampling Digital-to-Analog Converters for ADSL Applications.
Let the codes used by the N -bit converter be given by the ordered set of codes

X ∈ { X 0, X 1, …, X ( 2 N – 2 ), X ( 2 N – 1 ) } (2-9)

Each code is given by an ordered set of bits

X = ( x N – 1, x N – 2, …, x 1, x 0 ) (2-10)

Let the function describing the transfer function of the converter be given by A ( X )
where A ( X ) is the amplitude level generated for the code X . For a specific code, X i , we
denote the amplitude as
A ( X i ) = Ai (2-11)

2.2.1 Quantization Types

In this thesis, we focus on offset binary code and uniform quantization which provides a
regular quantization structure as sketched in Fig. 2-4a). Let the transfer function be given
by
A ( X i ) = A i = i ⋅ A ref (2-12)

where A ref is the reference level and i ≤ 0, …, 2 N – 1 . Further, the reference level is the
amplitude level for the LSB and the notation

21
 Part A: Overview: Digital-to-Analog Converter Design

A ref = A LSB (2-13)

is also used. As described in equation (1-1) the output amplitude for a binary weighted
converter is given by

A ( X ) = A LSB ⋅ ( x 0 + x 1 ⋅ 2 + x 2 ⋅ 2 2 + … + x N – 1 ⋅ 2 N – 1 ) = A LSB ⋅ X (2-14)

where the result from (2-12) is applied. The maximum output amplitude is given by

A max = A ( X ( 2 N – 1 ) ) = A ( 2 N – 1 ) = ( 2 N – 1 ) ⋅ A LSB (2-15)

Assuming that the input signal is statistically equal distributed over the whole amplitude
range, the uniform quantization intuitively provides a minimum error, hence a minimum
quantization noise.

A(Xi) A(Xi)
a) b)

Ak+1 Ak+1
Ak X Ak X

Figure 2-4: Transfer function with a) uniform and b) non-uniform quantization.

When the signal is not equally distributed over the amplitude range it may be more useful
to use non-uniform quantization, Fig. 2-4b). With this method some amplitude levels are
quantized with a larger error, but statistically a minimum quantization noise is achieved
since the probability for these amplitude levels is lower. The output level using non-uni-
form quantization can be written as
A ( X ) = x0 ⋅ A0 + x1 ⋅ A1 + x2 ⋅ A2 + … + x N – 1 ⋅ A N – 1 (2-16)

where A ( X i ) = A i ∈ A L and A L is the set of possible amplitude levels of the converter.

The non-uniform quantization may give rise to a more complex converter structure.

2.2.2 Quantization Noise

The expected transfer function of an ideal converter using offset binary coding should
be a straight line from the minimum zero value; A min = 0 , to the maximum value (in this
case); A max = 2 N ⋅ A ref . Quantization noise, defined as the deviation from the straight
line, is introduced when the number of bits, N , is finite. Note that the error is defined
within the minimum and maximum amplitude levels. Assume that we sweep through the
codes, X i , consecutively as a function of time, i.e., sweeping a ramp, with period T . Each
code are represented during a certain time interval given by ∆T = T ⁄ 2 N . The true output

22
 2. The Ideal DAC

is given by a stairs function, Fig. 2-5, and can be written as

2N – 1
A true ( t ) = ∑ A k ⋅ { u ( t – k∆T ) – u ( t – ( k + 1 )∆T ) } (2-17)
k=0

where A k = k ⋅ A ref is the amplitude level for the code X k , and u ( t ) is the step function.
The wanted output signal, A want ( t ) , should be a ramp function, Fig. 2-5, as

t t t
A want ( t ) = --- ⋅ A max = --- ⋅ ( A ref ⋅ 2 N ) = ------- ⋅ A ref (2-18)
T T ∆T
‘

Aout
8Aref Awant

7Aref Atrue
6Aref

5Aref
4Aref

3Aref
2Aref

Aref
X
000 001 010 011 100 101 110 111
Figure 2-5: Transfer characteristics for an offset binary conversion and uniform quantization.

The quantization error as function of the time, shown in Fig. 2-6, is written as

A err ( t ) = A want ( t ) – A true ( t ) (2-19)

We can now find the error r.m.s. value, A err, rms , by using

1 T
T ∫0 want
2
A err , rms = --- [A ( t ) – A true ( t ) ] 2 dt (2-20)

It can easily be seen that the total r.m.s. error (over the time T ) must be the same as the
r.m.s. error during half a single time period of ∆T ⁄ 2 , therefore (2-20) can be written as

2 ∆T ⁄ 2 2
A ref t 2 A ref
2
A err , rms = --------------
∆T ⁄ 2 ∫ ------- dt = ---------
∆T 12
- (2-21)
0

which gives the r.m.s. value as

23
 Part A: Overview: Digital-to-Analog Converter Design

A ref
A err, rms = ---------
- (2-22)
12

a) Aerr(t) T
t
A ref
– ---------
-
2
Aerr(t)
b)
Awant(t) Atrue(t)

Figure 2-6: Quantization error as a) function of time and b) modeled as an error signal. Awant(t) is the
wanted signal, Atrue(t) is the true output, and Aerr(t) is the quantization noise.

Further, it is assumed that the noise can be considered to be signal-independent, hence a

large number of bits and fine quantization. A sinusoidal of full amplitude for an offset
binary code, i.e., dc value of A max ⁄ 2 and amplitude of

A sig, ampl = A max ⁄ 2 = 2 N – 1 ⋅ A ref (2-23)

The r.m.s. value of the sinusoidal is

1 1
A sig, rms = ------- ⋅ A sig, ampl = ------- ⋅ 2 N – 1 ⋅ A ref (2-24)
2 2
We define the peak signal-to-noise ratio (SNR) as

A sig, rms 1 ⁄ 2 ⋅ 2 N – 1 ⋅ A ref 3 N

------------------- = ----------------------------------------------- = --- ⋅ 2 (2-25)
A err, rms A ref ⁄ 12 2

and in dB, this is approximately

SNR ≈ 6.02N + 1.76 (2-26)

For a small number of bits (2-26) has to be slightly corrected [56]. For telecommunica-
tion applications the resolution should be high, hence a large number of bits and therefore
this consideration is not further discussed.

24
 3. DAC Performance Measures

3 DAC Performance Measures

Several different measures are used to characterize the quality and performance of the
digital-to-analog converter. Different applications may request good linearity and not so
hard requirements on noise, and vice versa. For several telecommunication applications a
multi-tone signalling system is used. In this case, for example the total harmonic distor-
tion may not give all the information we want about the quality of the DAC. We have to
find other measures that determine the non-linearity and noise that are introduced by
irregularities of the converter.
The performance measures can be divided into two groups; static and dynamic measures
[28, 29, 56]. To the static performance we count the signal-independent values as offset
error, gain error, differential non-linearity (DNL), integral non-linearity (INL), monoto-
nicity, etc. Dynamic performance is described by signal-dependent values as non-linear
slewing, clock feedthrough (CFT), glitches, overshooting, etc.
Both static and dynamic properties can be investigated in the frequency domain [28].
Static errors may give rise to distortion at frequencies that are multiples of the fundamen-
tal signal frequency. CFT gives frequency components in multiples of the Nyquist fre-
quency and glitches give higher frequency components, etc. We use the signal-to-noise
ratio (SNR), total harmonic distortion (THD), spurious-free dynamic range (SFDR), sig-
nal-to-noise-and-distortion ratio (SNDR), and some more measures as powerful tools to
determine and characterize the DAC performance.

3.1 Static Measures

When a step is applied to the input of the DAC, hence digital bits are switching, the ana-
log output will tune from the start value, A i , to the final value, A i + 1 , see Fig. 3-1. The
settling time, T s , describes the time between for example the 5% and 95% value of the
ideal step value. The final value (after complete settling) is defined as the static value. The
highest possible speed of the circuit is determined by the settling time, T s , which may be
signal-dependent and will in that case be referred to as non-linear slewing.
The static performance measures are given by the deviations from the wanted values, A i
and A i + 1 . The deviations are denoted, d i and d i + 1 , respectively, as shown in Fig. 3-1.

When the code is switching, clock feedthrough (CFT), glitches, overshoot, etc., may
arise. CFT arises due to the capacitive coupling between the digital switching signal and
the analog output signal [71]. The glitch depends on how the internal switches are indi-
vidually skewed. It may be an erroneous code connected to the output for a short period
of time. This is further described in Sec. 3.2.

25
 Part A: Overview: Digital-to-Analog Converter Design

By using the known deviations, d i , we can characterize the performance and behavior
of the converter.

Aout Glitch / CFT / Overshoot

di+1
Slewing
Ai+1

di

Ai Ts t

Figure 3-1: True output signal compared with wanted output signal (dashed). The deviation from the
start-value, di, and the end-value, di+1, determine the static value of the specific code.
Settling time is given by Ts.

For a large number of bits, it may be inconvenient to find all static values by pure mea-
surement, since the number of amplitude levels grows exponentially. Therefore statistical
methods can be used to find the deviation values and use them to derive static measures
[16].

3.1.1 Differential Non-linearity, DNL

As was discussed, a basic error definition is the deviation from the wanted value, see Fig.
3-2. The differential non-linearity (DNL) indicates how non-linearly distributed these
errors are. Assume that the wanted output value for a certain code, X i , is

A want ( X i ) = A i (3-1)

The true value generated by the converter for the same code is given by

A true ( X i ) = A˜ i (3-2)

The deviation is directly given by

d i = A true ( X i ) – A want ( X i ) = Ã i – A i (3-3)

The deviation is normalized with respect to the LSB value, A LSB from (2-13), as

di A˜ i – A i
d i = -----------
- = ---------------- (3-4)
A LSB A LSB

and the deviation gets the unit “LSB”. The DNL, D i , is the difference between the two
deviations at a certain code transition, X i – 1 → X i , as

A˜ i – A i à i – 1 – A i – 1 à i – à i – 1
D i = d i – d i – 1 = ---------------- – ------------------------------ = ----------------------
-–1 (3-5)
A LSB A LSB A LSB

26
 3. DAC Performance Measures

Note that in this case, A i and A i – 1 are the amplitude levels of two consecutive codes
and the difference between them is ideally one LSB.

Aout
7Aref
6Aref

5Aref
4Aref d4
A4
3Aref
2Aref

Aref
X
000 001 010 011 100 101 110 111
Figure 3-2: Possible errors in amplitude levels for a 3-bit DAC.

If all deviations are equally large, the DNL is D i = 0 for all code transitions, and there
will only be an offset error at the output. A basic observation is that if the DNL is increas-
ing, the deviations from the true code is also increasing and the transfer function is non-
linear.

3.1.2 Offset Error

The offset error, A offset , may be defined as the deviation from the wanted minimum
value of the output.
A offset = d 0 (3-6)

In most configurations the converter is constructed with differential outputs where offset
errors (between two channels) are cancelled, and it may in that case be useful to define
the offset value, A offset , as the average value of all deviations. The offset value is found
by minimizing the expression d i – A offset for all i , with the least square method as

2N – 1
∂ 1
∂ A offset
-----N-
2 ∑ ( d i – A offset ) 2 = 0 (3-7)
k=0

which gives
2N – 1
1
A offset = -----N- ⋅
2 ∑ di (3-8)
k=0

The new deviation values are given by

27
 Part A: Overview: Digital-to-Analog Converter Design

dˆi = d i – A offset (3-9)

and the DNL values are not affected by this modification, see (3-5).

3.1.3 Gain Error

The gain error of the converter may influence the transfer function severely. The gain
can basically be of two kinds, linear and non-linear, as sketched in Fig. 3-3. Compared to
the wanted straight line, A want ( X ) = A LSB ⋅ X , the actual output deviates with a stronger
slope (Fig. 3-3a) or with even higher order of non-linearity (Fig. 3-3b).

Aout Aout
Atrue(X) Atrue(X)

Awant(X) Awant(X)

X X

Figure 3-3: Characteristics of a) linear and b) non-linear gain error.

Linear gain error does not introduce extra distortion as long as the output signal is not
clipping or similar effects arise, compare with (2-14). The true output with a different
slope and with offset error can be written as
A true ( X ) = a ⋅ X + A offset (3-10)

where a is the gain.

The non-linear gain error introduces distortion. The code can no longer be described with
a binary offset code and the weights are no longer given by a factor as 2 i . The true output
for a non-linear gain can for example be given by

A true ( X ) = a ⋅ X + b ⋅ X 2 + c ⋅ X 3 + … + A offset (3-11)

The non-linear errors may be reduced by using pre-distortion [54], see Sec. 5.1.1 in
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications.

3.1.4 Integral Non-linearity, INL

The integral non-linearity (INL) describes the overall deviation from a wanted straight
line. The INL values, I i , can also be calculated using the DNL values as

i
Ii = ∑ Dk (3-12)
k=1

Using (3-4) and (3-5) the equation above is rewritten as

28
 3. DAC Performance Measures

à i – A˜0 i ⋅ A LSB
i
à i – à i – 1 di – d0
Ii = ∑ ----------------------- – 1 = ----------------- – ------------------ = ---------------
A LSB A LSB A LSB A LSB
- (3-13)
k=1

As was discussed in the previous sections, offset errors and linear gain errors may be
neglected since they do not necessarily degrade the performance. Therefore, compensa-
tion for offset and linear gain error gives a more understandable value of the INL and
DNL. The wanted straight line can be defined in two ways, either using the start and end
values as reference or using a best-fit straight line, which minimizes the error. The first
guarantees a true zero code definition and the latter is more useful when using differential
structures.
The deviation values are compensated as (3-9) but now the gain error, a , is included as
well

dˆi = A˜ i – ( A offset + a ⋅ i ) = ( d i – A offset ) + ( A LSB – a ) ⋅ i (3-14)

The gain and offset errors, a and A offset , are found by minimizing and using the least
square method as
2N – 1 2N – 1
∂ 1 ∂ 1
∑ ∑ [ A˜ i – ( A offset + a ⋅ k ) ] 2 = 0
2
------ dˆi = ------ (3-15)
∂a 2N ∂a 2N
k=0 k=0

and
2N – 1
∂ 1
∂ A offset
-----N-
2 ∑ [ A˜ i – ( A offset + a ⋅ k ) ] 2 = 0 (3-16)
k=0

If we assume a large number of bits, the following approximate values are found
2N – 1 2N – 1
4 6
A offset ≈ -----N-
2 ∑ A˜k – --------
2 2N
- ∑ k ⋅ A˜k (3-17)
k=0 k=0

2N – 1 2N – 1
12 6
a ≈ --------
2 3N
- ∑ k ⋅ A˜k – --------
2 2N
- ∑ A˜k (3-18)
k=0 k=0

The line A offset + a ⋅ X expresses the best-fit straight line with respect to the true output
values, A˜ i . The compensated values, dˆi from (3-14), are used to find the DNL and INL
values as was given in equations (3-5) and (3-12).

3.1.5 Monotonicity
If the output amplitude level of the converter is increasing with increasing input and if
there is a one-to-one mapping from the input to the output, the converter is monotonic.
Otherwise there is a situation when a specific output value may be represented by two dif-
ferent input codes, see Fig. 3-4.

29
 Part A: Overview: Digital-to-Analog Converter Design

1 LSB

di+1
di

Figure 3-4: Transfer function illustrating when monotonicity is not fulfilled (solid line).

Monotonicity implies that all DNL values have to be less than one LSB [56] as
D i ≤ 1 LSB for all i (3-19)

This also implies that the deviation from the best-fit straight line must never be more
than a half LSB [56], hence the converter is monotonic if the INL values fulfil the ine-
quality
1
I i ≤ --- LSB for all i (3-20)
2
Monotonicity can be improved by segmenting the bits, i.e., using a thermometer code.
This is further discussed in Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL
Applications.

3.2 Dynamic Measures

Especially for telecommunication applications it is the dynamic performance that deter-
mines the quality of the converter. The dynamic performance is determined by phenom-
enon such as glitching, skew, slewing, etc. This may also affect the static value of the
converter but in general they do instead affect higher frequencies and therefore limit the
bandwidth of the converter.

3.2.1 Glitch
Glitches occur when the time of switching between different bits in the converter is
unmatched. For a short period of time a false code could be represented at the output. For
example if the code transition is
0111…111 → 1000…000

If the MSB is switching faster than the LSBs, the code 11…111 may be present for a
short time. This code represents the maximum value and hence the glitch would be large.
It is important to understand how the glitches may affect the performance. We use glitch
energy as a measure of their impact.
We model the glitch as a pulse, Fig. 3-5, with a certain amplitude height, A g , and with
a time duration, T g . The normalized average power, P g , of the glitch distributed over the

30
 3. DAC Performance Measures

shortest possible code duration, i.e., the update time interval, T s = 1 ⁄ f s , is described by

Tg
P g = A g2 ⋅ ------ (3-21)
Ts

Ag
Aj

Tg
Ak
t
Figure 3-5: Glitch modeled as a pulse with height Ag and duration Tg.

Assume that the maximum peak glitch amplitude, i.e., the amplitude of the MSB, is

A g, max = 2 N – 1 ⋅ A LSB (3-22)

which gives the maximum glitch power over one clock cycle
Tg
P g, max = 2 2N – 2 ⋅ A LSB
2 ⋅ ------ (3-23)
Ts

This should be compared with the power of the quantization noise, P Q , (2-21), during
the same period of time
2
A LSB
P Q = -----------
- (3-24)
12
The power of the glitch should be smaller than the quantization in order to not decrease
the SNR too much, hence

T g A LSB 2
P g, max = 2 2N – 2 ⋅ A LSB
2 ⋅ ------ < ------------ = P Q (3-25)
Ts 12

which gives a bound on the time duration of the glitch as

Ts
T g < ---------------
- (3-26)
3 ⋅ 2 2N
It should be noted that the glitches are naturally very hard to model since it depends on
a short time and an error code that is hard to predict. It should also be mentioned that the
error generated by glitches may more or less randomly vary when code transitions are not
repeated periodically. The power of the glitch error is spread over the frequency range as
noise, dependent on the probability for the excitation of the certain code transition.
The glitch impulse is also commonly specified by the glitch area, or its amplitude times
the duration-time, with the unit pV ⋅ s [9, 56].

31
 Part A: Overview: Digital-to-Analog Converter Design

3.2.2 Clock Feedthrough, CFT

Due to capacitive coupling or Miller effect in switches (see Sec. 1.4.2) the clock (or dig-
ital switching signals) will affect the analog output signal [71]. This clock feedthrough
(CFT) will arise at both rising and falling edge of the switching signal, and it will force
charge to redistribute, hence a small current will flow in some direction in the analog wire.
In the frequency domain there will be a frequency component at the Nyquist frequency,
f N = f s ⁄ 2 , since CFT occurs twice a clock period.

The CFT error may be modeled in a similar way as was done for glitches. Naturally, the
CFT is reduced when reducing the capacitive coupling. The transistor sizes may be
reduced to decrease the size of the parasitic capacitances. With smaller transistors, the on-
resistance increases and may degrade the result in other ways, i.e., voltage drop over the
switch, etc.

3.2.3 Non-linear slewing

Signal-dependent capacitance and resistance give rise to the non-linear slewing. This
implies that for different signals there are different settling times and therefore the static
value may not be reached within one clock period, or at least the performance will degrade
with higher sampling frequency.
By modeling the converter as a first order RC model, the magnitude of the error arising
when switching from one code to another may be approximated. When switching the dig-
ital input at the time t 0 , the output amplitude is given by

t
A out ( t 0 + t ) = A out ( t 0 ) + A step ⋅  1 – e RC
– --------
(3-27)
 

where A step is the wanted step and τ = RC is the time constant determined by the resis-
tance and capacitance associated with the output of the converter. R and C are both de-
pendent on the input code (and the output amplitude as well). Assume that the true output
value should be found within one clock period, T s . The error at the output, d ( T s ) , is giv-
en by

T
A out ( T s ) – A out ( t 0 )  – -------s-
d ( T s ) = ----------------------------------------------- =  1 – e RC
A step  

For example, for an error less than 1%, d ( T s ) < 0.01 , the clock period must be

T s > τ ⁄ 100

This indicates the maximum speed of the circuit and it also gives a guide how to design
the circuit according to the specifications. It is further discussed in Sec. 3.5 in Part B:
Nyquist-Rate Digital-to-Analog Converters for VDSL Applications.

3.3 Frequency-Domain Measures

Since in most cases we use the frequency domain to characterize the devices, it is impor-
tant to have useful measures. In many applications the information extraction is also done

32
 3. DAC Performance Measures

in the frequency domain using FFT and IFFT operations.

Several standards for telecommunication applications use multi-tone signals. Therefore,
the frequency domain measures are divided into single-tone, dual-tone, and multi-tone
measures. It can also be seen that the single-tone measures are not enough to characterize
converters for multi-tone applications [28].

3.3.1 Signal-to-Noise Ratio, SNR

The signal-to-noise ratio (SNR) of the system is simply defined as the power ratio of the
signal and the noise within the Nyquist bandwidth.
2
A rms
SNR = ----------
2
- (3-28)
B rms

where A rms is the signal r.m.s. value and B rms is the noise r.m.s. value. With a full-scale
sinusoidal signal and quantization noise only, the SNR was derived in section 2.2 to be
SNR ≈ 6.02 ⋅ N + 1.76 (3-29)

where N is the number of bits.

3.3.2 Harmonic Distortion, HDk

The harmonic distortion with respect to the k -th harmonic ( HD k ) is the power ratio
between the k -th harmonic and the fundamental as

A k2 ⁄ 2 A k2
HD k = ------------
- = -----
- (3-30)
A 02 ⁄ 2 A 02

where A k is the amplitude of the k -th harmonic and A 0 is the fundamental’s amplitude.

3.3.3 Total Harmonic Distortion, THD

Another measure of non-linearity is the total harmonic distortion (THD), which is the
sum of all harmonic distortions from (3-30) as

A k2 1
THD = ∑ HD k = ∑ A 2- = -----
-----
A 2 ∑ k
-⋅ A2 (3-31)
k≥1 k≥1 0 0 k≥1

where A k is the amplitude of the k -th harmonic and A 0 is the fundamental’s amplitude.

3.3.4 Signal-to-Noise-and-Distortion Ratio, SNDR

When including the non-linearity with the noise, the signal-to-noise-and-distortion ratio
(SNDR) is given

A 02 ⁄ 2 SNR
SNDR = ------------------------------------- = ------------------------------------- (3-32)
1 1 + THD ⋅ SNR
--- ∑ A k2 + B rms 2
2k ≥ 1

33
 Part A: Overview: Digital-to-Analog Converter Design

where A 0 is the amplitude of the fundamental, A k is the amplitude of the k -th harmonic,
and B rms is the noise r.m.s. value.

3.3.5 Spurious-Free Dynamic Range, SFDR

The spurious-free dynamic range (SFDR) is defined as the power ratio between the fun-
damental and the second largest frequency component (except the dc)

A 02 ⁄ 2
SFDR = ------------
- (3-33)
P max

where A 0 is the amplitude of the fundamental and P max is the power of the second largest
component. The SFDR mostly determines the quality of the converter. Assume that the
maximum peak is one of the harmonics, P max = A max 2 ⁄ 2 . Then (3-31) is rewritten as

2
A max  A k2 
THD = -----------
A 02 
- ⋅  1 + ∑ 2 - ----------- (3-34)
k ≠ maxpos A max 

If the sum in expression (3-34) is small enough, the THD is determined by the SFDR.
Using (3-32) we also see that if the distortion is larger than the SNR, also SNDR will be
determined by the SFDR.

3.3.6 Effective Number of Bits, ENOB

When applying a full-scale sinusoidal to the DAC, the peak SNR is found from (3-29).
By using the expression on SNDR (3-32) with (3-29) we derive the effective number of
bits (ENOB) as
SNDR – 1.76
ENOB ≈ -------------------------------- (3-35)
6.02
ENOB gives a hint on the performance of the converter. The ENOB value is however
mostly used when characterizing the performance of ADCs.

3.3.7 Inter-Modulation Distortion, IMD

With inter-modulation distortion (IMD) we understand the distortion when several tones
are applied to the circuit. Assume that two tones with the frequencies f 1 and f 2 are
applied to the converter. Intermodulation is given by the components in the frequencies
( k ⋅ f 1 + m ⋅ f 2 ) mod ( f s ⁄ 2 ) (3-36)

where k and m are integer numbers, and further k ≠ 0 , m ≠ 0 , and f 1 ≠ f 2 . The inter-
modulation distortion is found by

IMD =
∑ A k2, m
------------------- (3-37)
A 02

where A 0 is the amplitude of the fundamental and A k, m is the amplitude of the tones in

34
 3. DAC Performance Measures

the frequencies given by (3-36).

For some multi-tone applications the tone frequencies are multiples of a specific funda-
mental frequency and hence the intermodulation terms will interfere with other tones, see
Sec. 3.3.8 below.

3.3.8 Multi-Tone Power Ratio, MTPR

It is hard to find the distortion for multi-tone transmission schemes (DMT, OFDM, etc.),
since tones often are multiples of a fundamental frequency. This implies that distortion
terms, harmonics, are added to true information carriers. A method to find out the distor-
tion is to apply a number of tones (that are multiples of a fundamental, ω 0 ), all with the
same amplitude, A . Some tones are left out, and the distortion terms that occur at these
positions determine the quality and the multi-tone power ratio (MTPR) is defined as.

A2 ⁄ 2
MTPR = ------------------------------------------------------------------------------------------------------------- (3-38)
Power of tones at left-out frequency positions
This is also depicted in Fig. 3-6, where 25 tones have been applied. At two frequencies
tones have been excluded. The non-linearity of the converter introduces harmonics at
these positions, and MTPR can be determined by the power of these harmonics.

Spectrum of summed sines. (Non−linear converter).

80

60

40

MTPR
20
Signal power.

−20

−40

−60

−80

−100

−120
0 0.1 0.2 0.3 0.4 0.5
Normalized frequency.
Figure 3-6: Illustration of the impact of MTPR. Two tones are left out and the non-linearity can be
found by observing the power of the tones appearing at the left-out positions.

3.3.9 Peak-to-Average Ratio, PAR

For multi-tone measurements we also use the peak-to-average ratio (PAR) or crest fac-
tor. Since PAR describes the peak power to the average power ratio, it also slightly
describes how the signal is distributed over the amplitude range. A low PAR indicates a
more uniform distribution. The PAR can be written as
2
A max
PAR = -----------
2
- (3-39)
A rms

35
 Part A: Overview: Digital-to-Analog Converter Design

2
where A max is the normalized peak power and A rms is the signal r.m.s. value. For a si-
nusoidal the PAR = 2 since A max = A 2 and A rms
2 = A 2 ⁄ 2 where A is the amplitude
of the sinusoidal.

3.4 DAC Comparison

The general consideration for telecommunication applications such as ADSL and VDSL
is that the effective resolution of DACs should be around 12-14 bits, [27, 83]. For some
applications the effective number of bits does not have to be that high.
In Fig. 3-7 a sketched overview over DAC types found in the literature (in general terms)
[2-79, 84, 85] vs. resolution and bandwidth. Since the resolution of the converter is
strongly dependent on the bandwidth (and vice versa), the overview should be seen as an
approximation.

Resolution
(bits)
20 Oversampling DACs

Current-Mode
Nyquist-Rate DACs
12

Voltage-Mode

Audio Video Telecommunication Bandwidth

[Hz]
16k 5M 200M
Figure 3-7: DAC types vs. speed and resolution.

Basically, it can be seen that Nyquist-rate converters are the most suitable converter
structures for high-speed telecommunication applications. For audio applications and
lower-speed telecommunication applications the oversampling converter is a suitable
structure. The current-mode Nyquist-rate versions are suitable for high-speed applications
[2, 3, 9, 13, 30-32, 39, 44, 49, 53, 61, 64-66, 68, 70] and voltage-mode oversampled ver-
sions for lower-speed applications [40, 46, 51, 59, 62, 79].

36
 Nyquist-Rate
B
Part B:

Digital-to-Analog
Converters for
VDSL Applications

1 Introduction
The Nyquist-rate digital-to-analog converter is defined to have its signal frequency range
from zero (dc) up to the Nyquist frequency, f N = f s ⁄ 2 , with f s as the update frequency
of the DAC [37, 56]. In Fig. 1-1 the amplitude spectrum is shown where the sinc weight-
ing from sample-and-hold elements has not been considered. Images of the signal are also
found in the spectrum.

|X(f)| Image

Quantization
Noise
fs /2 fs f

Figure 1-1: Amplitude spectrum within the Nyquist frequency range. The signal’s images are situated
above the Nyquist frequency. The quantization noise is equal over all frequencies.

The quantization noise within the Nyquist band determines the signal-to-noise ratio as
discussed in the previous part of the thesis. With a normalized full-scale input sinusoidal

37
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

(single-side peak at 0dB) the average quantization noise power, Q avg, pwr , is found at a
level of

Q avg. pwr ≈ – [ 6.02N + 1.76 + 10 log f N ] (1-1)

From (1-1) we have the intuitive conclusion, that the higher bandwidth, f N , the lower
noise floor. The output from the converter when using sample-and-hold circuits also has
images and attenuation of the signal spectrum due to the sinc weighting in the frequency
domain as sketched in Fig. 1-2. Lowpass filters and anti-sinc filters can be used to remove
images and reduce the distortion.

|X(ω)|
1 1st Nyquist
band Images

fs/2 fs 2fs f

Figure 1-2: The output amplitude spectrum with images and the effect of sinc weighting.

In general the Nyquist-rate converter is required for wideband applications, e.g., wide-
band radio, VDSL, etc., where oversampling techniques are impossible due to the high
clocking frequencies needed.
A brief description of different DAC structures is given in Chapter 2. The R-2R ladder,
charge-redistribution, and current-steering structures are discussed. This thesis’ part con-
centrates on the CMOS binary weighted current-steering DAC which provides a simple
and straight-forward structure suitable for high-speed telecommunication applications as
mentioned in Sec. 3.4 in Part A: Overview: Digital-to-Analog Converter Design.
In Chapter 3 we model the performance of a current-steering DAC. Important aspects
concerning output impedance, matching, and noise are discussed. It is very important to
have a knowledge about the overall behavior of the circuit and how irregularities and dif-
ferent circuit variations will affect the result. Therefore, the modeling results are used to
iterate the design of the converter using behavioral-level descriptions.
The design of a DAC chipset is presented in Chapter 4. Behavioral-level descriptions and
simulations concerning the design is given, as well as results from circuit simulations and
measurements.
From the design of the chipset as well as the modeling it can be concluded that several
different improvements may be done. Some of these are discussed in Chapter 5.

38
 2. Nyquist-Rate DAC Structures

2 Nyquist-Rate DAC Structures

Various kinds of converter structures are used for different applications. They are most
often trade-offs between area, power consumption, accuracy, and speed. We focus on the
binary weighted converter structure implemented in a CMOS process. This uses a number
of binary scaled elements that together generates the output value, dependent on the input
digital code to the converter.
Most DAC solutions use a straight-forward approach. With some kind of feedback struc-
ture, e.g., calibration, trimming, etc., the effective resolution may be improved. This
might however decrease the bandwidth of the converter, as well as increasing chip area
and design complexity. These aspects are further discussed in Chapter 5.
There is a limited number of DAC structures that are good candidates for high-speed and
high-performance applications, see Sec. 3.4 in Part A: Overview: Digital-to-Analog Con-
verter Design. The advantages and disadvantages of wideband converter types as charge-
redistribution, current-steering, and R-2R ladder, are discussed in this chapter.

2.1 Charge-Redistribution DACs

The charge redistribution DAC is a switched capacitor version, where the charge stored
on a number of binary scaled capacitors is used to perform the conversion [37]. See Fig.
2-1 for an example of a 4-bit converter.

φ1
16C

φ2

8C 4C 2C C v0(t)
φ1
x3 x2 x1 x0
Vref φ1
C0
φ2
φ2

Figure 2-1: A 4-bit charge-redistribution DAC.

This switched capacitor version uses two non-overlapping clock phases, φ 1 and φ 2 . The
operation is determined by the discrete-time events controlled by the clocks. During the

39
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

initializing phase; time point nT – T ⁄ 2 and clock phase φ 2 , all inputs are shorted and no
charge is found on the binary weighted capacitors. T = 1 ⁄ f s is the update time. The
16C capacitor is charged with q 16 ( nT – T ⁄ 2 ) = 16C ⋅ v 0 ( nT – T ⁄ 2 ) and C 0 is
charged with q 0 ( nT – T ⁄ 2 ) = C 0 ⋅ v 0 ( nT – T ⁄ 2 ) .

During clock phase φ 1 and at time point nT , the binary weighted capacitors are charged
with the reference voltage, V ref . The switches controlled by the digital input
X = ( x 3, x 2, x 1, x 0 ) , determine what capacitors to charge, i.e., the total charge on those
capacitors is given by q tot ( nT ) = X ( nT ) ⋅ C ⋅ V ref

Since the 16C capacitor is discharged and C 0 is connected to the input of the opera-
tional amplifier at this point, they will provide the binary weighted capacitors with charge.
Charge conservation at the virtual ground state that
X ( nT ) ⋅ C ⋅ V ref + C 0 ⋅ v 0 ( nT ) = 16C ⋅ v 0 ( nT – T ⁄ 2 ) + C 0 ⋅ v 0 ( nT – T ⁄ 2 )

After one clock period, during clock phase φ 2 and at time point nT + T ⁄ 2 , the binary
weighted capacitances are discharged and their charge is redistributed to the 16C capac-
itor. This implies that
q 16 ( nT + T ⁄ 2 ) = 16C ⋅ v 0 ( nT + T ⁄ 2 ) = X ( nT ) ⋅ C ⋅ V ref

forcing the output voltage to be given by

V ref
v 0 ( nT + T ⁄ 2 ) = X ( nT ) ⋅ ----------
16
which gives the wanted transfer function at the output.
This structure is insensitive to offset voltage and finite gain of the amplifier. However,
it is clear that the limitations of the converter is given by a number of factors: the matching
of the capacitors, the switch on-resistance, the finite bandwidth of the amplifier limit the
performance of the overall DAC. Noise is basically given by the kT ⁄ C noise and the
influence of the 1 ⁄ f noise is decreased with the switching used in Fig. 2-1.

2.2 Current-Steering DACs

The use of switched current sources is a straight forward approach in a CMOS process,
since the construction of linear resistors and capacitors may be limited by the process and
therefore, the current-steering DAC is a natural choice.
The general structure of a binary weighted current-steering DAC is shown in Fig. 2-2
and discussed in [56, 66]. The switches are controlled by the input bits, x i , where
i = 1, 2, …, N , and N is the number of bits. x 0 is the LSB and the corresponding current
source has the dc value I LSB . The source controlled by bit x i , i.e., the i -th LSB current
source, is formed by connecting 2 i – 1 LSB current sources (unit current sources) in par-

40
 2. Nyquist-Rate DAC Structures

allel, hence the MSB current source therefore has the dc value I MSB = 2 N – 1 ⋅ I LSB .

Vref

IMSB ILSB

xN-1 xN-2 x0

Iout
Figure 2-2: An N-bit current-steering DAC.

The output current, I out , of the DAC shown in Fig. 2-2 is given by

I out ( X ) = I LSB ⋅ x 0 + 2I LSB ⋅ x 1 + … + 2 N – 1 I LSB ⋅ x N – 1 = I LSB ⋅ X (2-1)

where X is the digital input given by

N–1
X = x1 + 2 ⋅ x2 + … + 2N – 1 ⋅ xN – 1 = ∑ 2k ⋅ xk (2-2)
k=0

The current-steering DAC has the advantages of being quite small for resolutions below
10 bits and it may be very fast. The major disadvantage is its sensitivity to device mis-
match and glitching. To increase monotonicity and reduce the influence of glitches, a ther-
mometer code can be used. This is further discussed in Sec. 5.2.1. The current-steering is
suitable for high-speed wideband applications when special care is taken to improve the
matching of the converter.
Results from modeling of the current-steering DAC is given in Chapter 3 where the fun-
damental impacts of matching error, output impedance, noise, etc., are discussed.

2.3 R-2R Ladder DACs

The R-2R ladder structure provides a structure suitable for processes capable of imple-
menting linear resistances. The general structure of the R-2R ladder DAC is sketched in
Fig. 2-3 and further discussed in [8, 25, 37, 56, 65]. The current sources are all equally
large, I 0 , and the switches are controlled by the digital input, X = ( x N – 1, …, x 0 ) , where
N is the number of bits and x N – 1 is the MSB.

If the input is zero, X = 0 and hence all x i = 0 , it is seen that the output resistance of
the ladder is 2R . When terminating the output with 2R to the V ref voltage, the wanted
transfer function is achieved and by determining the contribution from each source, the
operation of the converter is easily understood.
Due to the fact that the current sources are equally large, the matching can be improved.
The resistors are however often non-linear and contains signal-dependent capacitances
yielding distortion. The ladder also introduces a time-delay between the MSB and LSB
which generates glitches and distortion. There is the same amount of current through all

41
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

switches which makes the design of the switches simpler, however, the internal voltage
nodes are swinging and therefore the current sources will have varying terminal voltages,
hence a poorer matching, further introducing distortion.

Vref
R 2R 2R

R R R Iout

x0 x1 xN-1

I0 I0 I0

Vss
Figure 2-3: An N-bit R-2R ladder DAC.

One of the major advantages is that we only have a few number of different component
types to implement, i.e., two resistor sizes, R and 2R , one current source size, I 0 , and
one type of current switch. This allows a more regular layout and since the current sources
all have the same size, trimming or calibration can be applied [8, .

2.4 Comparison
The properties of the different DAC structures described in Sec. 2.1 through Sec. 2.3 are
approximately given in Table 2-1. The values are found from reported results in literature
and data sheets from vendors [2, 3, 9, 13, 30-32, 39, 44, 49, 53, 61, 64-66, 68, 70].

Current- Charge- R-2R

Issue
Steering Redistribution Ladder
Speed > 30MHz < 30MHz > 30MHz
Area < 12 bits < 12 bits > 10 bits
Accuracy < 12 bits > 10 bits > 8 bits
Noise 8kT kT
4kT  --- + --- g m
---------- g m ------ 1 2
3 C R 3 
Table 2-1: Comparison of performance for DAC structures for telecommunication applications.

One way to improve the overall performance is to combine different DAC structures into
a hybrid DAC. Naturally a large number of hybrid DACs can be found. For example the
LSBs can be converted using a current-steering structure and the MSBs are converted
with an R-2R structure, since the impact of matching errors are larger on the MSBs. Fur-
ther improvements are discussed in Chapter 5.

42
 3. DAC Performance Modeling

3 DAC Performance Modeling

It is important to know in advance how the converter will react on circuit non-idealities.
Behavior models of the DAC are used to find fundamental limits and possible perfor-
mance of the converter can be approximated. This gives indications on how to design the
circuit, how to identify bottle-necks, how to find possible improvements, etc.
It is also attractive to avoid time-consuming circuit-level simulations and instead use C
or MatLab models to do higher-level simulations of the whole converter and the system
in which it is used [48, 68, 74, 80].
In Part A: Overview: Digital-to-Analog Converter Design the different performance
measures are given. Most characterization of DACs for telecommunication applications
is achieved by using the frequency domain information [28, 29] of the measurement or
simulation results, i.e., SFDR, THD, SNDR, MTPR, etc. This is further emphasized in
this chapter.
Fundamental limits on the performance are set by three properties:
• Output impedance. The influence of a finite output impedance of the DAC, or in
general; a finite output over termination impedance ratio strongly effects the linear-
ity of the converter.
• Matching errors. Since variations of the process force the oxide thickness and
threshold voltage, t ox and V T , to vary over the die area, the binary weighted
sources become unbalanced which affects the linearity.
• Circuit noise. The fundamental limit on the performance is given by the SNR and
we have to guarantee that the noise is below the quantization noise floor.
This thesis focuses on the Nyquist-rate binary weighted DAC, hence the sources gener-
ating the wanted output are binary weighted, as discussed in Chapter 2. The three issues
mentioned above are investigated for the current-steering converter type (Sec. 2.2) [75-
78]. In Fig. 3-1 we briefly sketch the main idea of this modeling.

W/L

Rout

Iout

Figure 3-1: Illustration of conflicts when choosing design parameters in a current-steering DAC.

43
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

Linearity is affected by the output impedance R out , the noise is affected by the output
current, I out , and matching is practically determined by the transistor size W ⁄ L or gate
area WL . There is however a relation between the three properties and a trade-off has to
be done to find a solution that is meeting the specifications. When increasing the output
current with the ambition to improve the SNR, the output impedance is decreasing and
thereby the non-linearity increase, etc.

3.1 Influence of Amplitude Level Uncertainties

In the previous part of the thesis we focused on the DNL and INL to describe errors in
the conversion levels of the DAC’s transfer function, Fig. 3-2. It is also important to find
out how the frequency domain measures are dependent on the errors in transfer levels.

Output Level
Aout
Wanted transfer function
7Aref
Actual transfer function
6Aref

5Aref
4Aref
Errors or deviations
3Aref
2Aref

Aref
Code X
000 001 010 011 100 101 110 111

Figure 3-2: Wanted transfer characteristics (dashed line) and with example of errors in different
conversion levels caused by the actual transfer characteristics (solid line).

If one assumes that the level errors of the transfer function caused by matching errors are
frequency-independent (which is not the case) the total error at the output is signal-depen-
dent as well. This implies the non-linearity of the transfer function. Mainly, the SFDR and
the SNR are used to characterize the converter. In principle, the SFDR determines the
THD, SNDR, and MTPR if the converter is not too non-ideal, i.e., not too much noise and
not too non-linear, compare with the formulae given in Part A: Overview: Digital-to-Ana-
log Converter Design.
The SFDR can be deduced from DNL and INL values if the input signal is known, and
especially how the input signal is sweeping over all transfer function levels. If the input
signal is not full-scale, all DNL values will not affect the linearity of the output signal, etc.
Basically, current sources used in a current-steering DAC is constructed by using a num-
ber of unit current sources (binary weighted) in parallel. This property is used throughout
the following sections.

44
 3. DAC Performance Modeling

3.2 Influence of Output Impedance Variations

Using the current-steering DAC (Sec. 2.2), it is easily seen that the output impedance of
the converter is signal-dependent, since any non-ideal current source has a finite output
impedance. Dependent on what code is applied, different numbers of current sources are
connected to the output. The whole DAC can briefly be modeled as a current source,
shown in Fig. 3-3, where the output is terminated with a load resistance R L .

VDD
IS(X)
RS(X)

RL
IL

Figure 3-3: Current source, IS(X), with finite output resistance, RS(X). The termination, RL, is signal-
independent.

We only show the impact of output resistance, since the influence of capacitive elements
strongly affects the complexity of the modeling (Sec. 3.5). The finite output resistance
reduces the current delivered to the load. The current delivered to the load from a non-
ideal current source as well as the supply voltage V DD is given by

RS 1
I L = ------------------- ⋅ I S + ------------------- ⋅ V DD (3-1)
RS + RL RS + RL

where I S is the nominal current value in the current source given by (2-1), R S is the out-
put resistance of the current source, and R L is the load (or termination) resistance.

From (3-1) it is seen, that if the output resistance were constant, there would only be a
loss of gain and a dc current in the output signal, which would not degrade the perfor-
mance. However, as was discussed earlier, the total output resistance is dependent on the
number of sources connected to the output. This dependency give rise to distortion. Using
a notation describing the code dependency, (3-1) can be rewritten as
I S ( X ) + G S ( X ) ⋅ V DD
I L ( X ) = ---------------------------------------------------
- (3-2)
1 + GS ( X ) ⋅ RL

where X indicates the DAC’s digital input given by (2-2) and G S ( X ) = 1 ⁄ R S ( X ) is the
code-dependent output conductance of the sources. It will be shown that this affects the
second harmonic strongly for reasonable high ratios of R S ⁄ R L , for lower ratios also high-
er order harmonics will be large in the output signal spectrum.
The termination resistance, R L , is assumed to be fixed and signal-independent. The out-
put resistance, R S , and the output conductance, G S , are determined by studying the
DAC’s structure shown in Fig. 2-2. The output conductance, G S ( X ) , is related to the

45
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

number of parallel current sources that are currently connected to the output node. The
output conductance associated with the LSB current source is assumed to be G LSB and
therefore the output conductance of the i -th LSB must be given by G i = 2 i – 1 ⋅ G LSB .
The total output conductance, G S ( X ) , of the converter is given by

G S ( X ) = G LSB ⋅ x 0 + G LSB ⋅ 2 ⋅ x 1 + … + G LSB ⋅ 2 N – 1 ⋅ x N – 1 =

= G LSB ⋅ [ x 0 + 2 ⋅ x 1 + … + 2 N – 1 ⋅ x N – 1 ] = G LSB ⋅ X (3-3)

where X is the input code (offset binary code) given by (2-2), and N is the number of bits.
Combining (2-1), (3-2) and (3-3), we have

I LSB + G LSB ⋅ V DD 1
I L ( X ) = --------------------------------------------- ⋅ 1 – ----------------------------------------- (3-4)
G LSB ⋅ R L 1 + X ⋅ G LSB ⋅ R L

Assume that within the Nyquist band, the input signal, X , is a full-scale sinusoidal with
an offset and can be written as

X = X ( k ) = A ⋅ [ 1 + sin ( Ωk ) ] + e (3-5)

where e is the deviation from an ideal sinusoidal due to truncation, i.e., quantization
noise, Ω is the normalized angular frequency, k is a sequence index, and the amplitude,
A , is given by

2N – 1
A = --------------- (3-6)
2
since the input is an offset binary code. Combining (3-5) with (3-4) gives the expression
of the current through the load resistance due to the current division.

I LSB + G LSB ⋅ V DD 1
I L ( k ) = --------------------------------------------- ⋅ 1 – -------------------------------------------------------------------------------- (3-7)
G LSB ⋅ R L 1 + G LSB ⋅ R L ⋅ A ⋅ [ 1 + sin ( Ωk ) ]

The deviation, e , is modeled as white noise and is neglected in (3-7). The notation is
simplified by letting

1 1 2 R LSB 1
K = --- ⋅ ----------------------- = --------------
- ⋅ -----------
- and L = ------------- (3-8)
A G LSB ⋅ R L N
2 –1 R L 1 + K

which gives the expression of the current through the termination load as

L⋅K
I L ( X ) = A ⋅ ( I LSB + G LSB ⋅ V DD ) ⋅ K ⋅ 1 – ------------------------------------- (3-9)
1 + L ⋅ sin ( Ωk )

Since K > 0 , then L < 1 , and therefore

L sin ( Ωk ) < 1 (3-10)

Using the relation in (3-10), a converging Taylor series can be used to rewrite the term
from (3-9) as

46
 3. DAC Performance Modeling

∑ [ – L sin ( Ωk ) ] n
1
--------------------------------- = =
1 + L sin ( Ωk ) n≥0

= 1 – L sin ( Ωk ) + ∑ [ L sin ( Ωk ) ] 2n – ∑ [ L sin ( Ωk ) ] 2n + 1 (3-11)

n≥1 n≥1

When determining the SFDR, the gain and dc level of the signal are neglected, and by
using trigonometric formulae (3-11) becomes

--------------------------------- = f ( Ωk ) – sin ( Ωk ) ⋅ L  1 + ∑ ( L ⁄ 2 ) 2n ⋅ 
1 2n + 1 
–
1 + L sin ( Ωk )   n 
n≥1

– cos ( 2Ωk ) ⋅ 2 ∑ ( L ⁄ 2 ) 2n 
2n 
(3-12)
 n – 1
n≥1

where f ( Ωk ) denotes a function containing the dc component and higher frequency com-
ponents that do not affect the SFDR and  p = ------------------------ .
p!
 q q! ( p – q )!
The SFDR is found as the power ratio between the fundamental and the harmonic as

 1 + ∑ ( L ⁄ 2 ) 2n  2n + 1 
2

L  2  n  1 + 1 – L2
2
n≥1
SFDR = -----  ------------------------------------------------------------
- =  ---------------------------- (3-13)
2n  2n   
 n∑
4  L
( L ⁄ 2 )
 n – 1 
≥1

By substituting back L and K from (3-8) in (3-13) this becomes

R LSB ⁄ R L 2N – 1 
2
SFDR =  1 + 2 ---------------------
- ⋅ 1 + 1 + ---------------------
- (3-14)
 2N – 1 R LSB ⁄ R L 

When the impedance ratio R LSB ⁄ R L and the number of bits, N , are large, (3-14) is
approximated by

1 R LSB 2
 -----------
SFDR ≈ ------------------
- ⋅ - (3-15)
22( N – 2)  RL 

Express (3-15) in dB, we have

R LSB
SFDR ≈ 20 log -----------
- – 6( N – 2) (3-16)
RL

This gives a hint on how to choose the output impedance of the LSB current source,
when knowing the specified number of bits, N . The average output resistance, R DC , is
given by

2
R DC = R LSB ⋅ --------------
N
- (3-17)
2 –1
Using (3-17) in (3-16), it is seen that the SFDR also can be expressed as

47
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

2N – 1
R DC ⋅ --------------- R DC
2
SFDR ≈ 20 log ------------------------------- – 6 ( N – 2 ) ≈ 20 log ---------
-+6 (3-18)
RL RL

In Fig. 3-4 we show the simulated and calculated SFDR for a 12-bit DAC. It is seen that
the calculated values fit the simulated curve very well. For high resistance ratios,
R LSB ⁄ R L , the spurious tones are hidden in or below the average quantization noise floor,
equation (1-1), and therefore the simulated curve is saturated, since peaks from noise
components are higher than the spurious tones.

SFDR vs. R /R for a 12−bit DAC.

LSB L
120

Calculated Value
100

80
SFDR [dB]

60
Simulated Value

40

20

0 2 4 6 8
10 10 10 10
RLSB / RL
Figure 3-4: SFDR vs. resistance ratio when varying the output resistance of a 12-bit DAC.

The important aspect is that if the number of bits should be increased without decreasing
the SFDR, the output impedance for the unit current source has to be approximately dou-
bled for each extra bit of resolution (3-16).
The influence of the output impedance may be minimized by using an operational ampli-
fier at the output which has a very low input impedance, hence the output impedance over
termination impedance is very large [37, 56]. However, in wideband applications the
operational amplifier will limit the performance, due to its limited speed and bandwidth.

3.3 Influence of Current Source Mismatch

Due to process variations the oxide thickness, t ox , and threshold voltage, V T , vary for
different current sources. Naturally, it is important to lay out so that the influence of these
variations is minimized. The matching error can be modeled as a stochastic variation over
the die area [9, 55, 71], which was also briefly mentioned in Part A: Overview: Digital-
to-Analog Converter Design. To find a suitable model, first deterministic mismatch is
investigated, Sec. 3.3.1, and then the results are generalized to examine the impact of sto-
chastic mismatch, Sec. 3.3.2.
For a current-steering DAC, the first, rather naive, approach is to model the mismatch

48
 3. DAC Performance Modeling

error as a current source in parallel with the nominal current source, as shown in Fig. 3-5.
All error sources can be summed and modeled as one error current source connected to
the output of the DAC.

IMSB ILSB

∆IMSB ∆ILSB

Figure 3-5: Current sources with modeled mismatch.

The number of error sources connected to the output is determined by the digital input
code, X . Since the mismatch error is considered to be fixed for a certain current source,
the total error is signal-dependent and distortion is introduced.
The matching issue is also further discussed in Sec. 4.1.1 where the current sources used
in the implementation of the Nyquist-rate DAC are discussed.

3.3.1 Deterministic Variations of the Mismatch

When neglecting the influence of the resistance ratios, the ideal nominal output current,
I out ( X ) , is given by (2-1) and dependent on the input code X given by (2-2). An output
current, Ĩ out ( X ) , is given by the sum of the nominal current, I out ( X ) , and the error cur-
rent, ∆I ( X ) , caused by a deterministic error in some of the current sources.

Ĩ out ( X ) = I out ( X ) + ∆I ( X ) (3-19)

Suppose in the simplest case that there is an error current, ∆I i ( X ) , in the current source
controlled by the i -th LSB, we have

Ĩ out ( X ) = I out ( X ) + ∆I i ( X ) = I out ( X ) + I LSB ⋅ 2 i – 1 ⋅ δ i ( X ) ⋅ x i (3-20)

where δ i ( X ) is the relative current error in the i -th LSB, and x i is the bit controlling the
i -th LSB. If δ i ( X ) = δ i for all inputs, X , (i. e., the size of the error current in a specific
bit position, i , is signal-independent), the total output current is

Ĩ out ( X ) = I out ( X ) + I LSB ⋅ 2 i – 1 ⋅ δ i ⋅ x i (3-21)

The error will have the characteristics of a pulsed signal, with different duration and
amplitude, depending on the error position, i . It is seen that mismatch errors in the more
significant bits (when i is large) will affect the signal stronger, due to the 2 i – 1 term. Due
to pulsed error currents in the MSBs, harmonics of odd order occur. The amplitude, A e, i ,
of such an error pulse in the i -th LSB position, as found in (3-21), is given by

A e, i = δ i ⋅ I LSB ⋅ 2 i – 1 (3-22)

If the nominal output current is a sinusoidal as given in (3-5) with period M = 1 ⁄ Ω ,

the mismatch current associated with the MSB current source will be a periodic square

49
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

wave with period M and have a duration of M ⁄ 2 (as the MSB current source is switched
to the output). The Fourier transform of the error current in the i -th LSB current source,
F em ( ω, i ) , is approximately given by

∞
2 A e, i 2π
F em ( ω, i ) ≈ ------
jπ ∑ 2k – 1
- ⋅ δ ω – ------ ⋅ ( 2k – 1 )
--------------
M
(3-23)
k = –∞

where M is the signal period and ω is the angular frequency variable, in (3-23) δ [ … ]
describes the Dirac function. The normalized power of the largest harmonic, P k = 2 , (third
order), found by letting k = 2 in (3-23), is given by

1  δ i ⋅ I LSB ⋅ 2 
i 2
P k = 2 ≈ --- ⋅ ---------------------------- (3-24)
2  3π 

Suppose a sinusoidal input with an amplitude given by (3-6), the normalized signal
power can be written as
2
1 2N – 1
P signal = --- A 2 = --- ⋅  --------------- ⋅ I LSB
1
(3-25)
2 2  2 

where A is the amplitude of the signal, and N is the number of bits. The power ratio the
sinusoidal (3-25) and the largest harmonic (3-24) is the SFDR given by
2 N–1 2
1  2N – 1
--- ⋅ --------------- ⋅ I LSB  2---------------
 3π   2 i 
2
2  2   3π  ⋅ (-------------------
2 2 N – i )2
SFDR ≈ ---------------------------------------------- ≈ 2 
-----
- ⋅ ----------------------- ≈ -----
- (3-26)
1  δ i ⋅ I LSB ⋅ 2 
i 2 δ i2  2 δ i2
 
--- ⋅ ----------------------------
2  3π 

The approximation is true when N is large. Expressing this in dB, we have

3π
SFDR ≈ 20 log ------ + 6 ( N – i ) – 10 log δ i2 (3-27)
2
Since for square wave signals the third harmonic dominates the other harmonics, (3-27)
is valid for errors in more significant bits. For errors in the least significant bits, the for-
mula is approximately true.
It is seen that for an increase of number of bits, N , the SFDR is improved by approxi-
mately 6 dB, if the increase of the number of bits does not affect the mismatch in the given
bit position. For a one per cent error, δ 14 = 0.01 , in the MSB of a 14-bit DAC, (3-27)
gives SFDR ≈ 53 dB. It can also be seen from (3-27) that if there is mismatch in the MSB
( i = N ) the SFDR is not depending on the number of bits, since the largest mismatch at
the MSB does not decrease with the increase of number of bits. This is also verified in
simulations.
Shown in Fig. 3-6 is the simulation result for a 14-bit DAC. It can be seen that if the rel-
ative error current in the MSB current source is δ 14 = 0.01 , the simulations show
SFDR ≈ 53 dB. For smaller deterministic mismatch errors in the least significant bits, the

50
 3. DAC Performance Modeling

error can not be modeled as contribution to the distortions. In this case the spurious tones
are hidden in the noise floor as shown in Fig. 3-6.

SFDR vs mismatch & bit position

110

100

90
SFDR [dBc]

80

70

60

50

40
0

0.5 2
4
1 6
8
1.5 10
12
2 14
Mismatch (%)
Figure 3-6: Deterministic variations of mismatch over bit positions in a 14-bit DAC. SFDR is shown
as a function of the mismatch error bit position and size. For small errors the spurious
tones are hidden in the noise floor.

3.3.2 Stochastic Variations of the Mismatch

In reality mismatch due to process variations are more or less of a stochastic nature [55].
By using the results from Sec. 3.3.1, we can model the impact of stochastic mismatch as
well. The errors are modeled as error current sources in parallel with nominal current
sources as shown in Fig. 3-5. The stochastic error, δ LSB , in the LSB current source is
assumed to be a normal distribution with a mean value, µ LSB = E { δ LSB } = 0 , and stan-
dard deviation given by σ LSB
2 = E { δ LSB
2 } . In the i -th LSB source, 2 i – 1 LSB current

sources are connected in parallel. Suppose all mismatch errors in each LSB current source
are uncorrelated. Then, the mismatch error in the i -th LSB current source, δ i , has the
mean value
2i – 1 2i – 1
 
µi = E  ∑ δk  = ∑ E { δk } = 0 (3-28)
k = 1  k=1

and standard deviation given by (uncorrelated sources)

2i – 1 2 2i – 1
    
σ i2 = E   ∑ δ i  = E  ∑ δ i2  = 2 i – 1 ⋅ σ LSB
2 (3-29)
k = 1   k = 1 

One of the main issues is actually to find out how the correlation between two error
sources affects the result. Since the current sources generally are laid out close to each
other, the matching errors can be highly correlated. The mean value of the error sources
can in any case be neglected since its influence only give rise to a linear gain or offset

51
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

error.
The total error current due to the stochastic mismatch can be summed into one source
and the expectation value of the total generated error power can be expressed by using the
equations from the previous section. If it is assumed that the third harmonic dominates
other harmonics, with (3-24) and (3-25), the expectation value of the SFDR can be ana-
lyzed. Due to the summation of 2 i – 1 stochastic sources, the amplitude, A i , in the i -th
LSB, for the third harmonic as was seen in (3-23) is
2
A i = ------ ⋅ δ LSB ⋅ I LSB ⋅ 2 i – 1 (3-30)
3π
The normalized signal power is given by (3-25) and the normalized power of the third
harmonic, E { P k = 2, tot } , is derived, by summing the error current amplitudes as given in
(3-30)
2

N
 
N
δ LSB ⋅ I LSB ⋅ 2 i – 1 
E { P k = 2, tot } = E  ∑ x i ⋅ A i  = E  ∑ x i ⋅ 2 ----------------------------------------------  =
i = 1   3π 
i=1
N 2
I LSB 2  
=  ------------- ⋅ E  ∑ xi ⋅ 2i – 1 ⋅ δ LSB  (3-31)
 3π ⁄ 2
 i=1 

Noting that x i = x i2 since x i ∈ { 0, 1 } and that the error sources are uncorrelated, the
expression in (3-31) is rewritten as
N
 I LSB  2  
E { P k = 2, tot } = ------------- E  δ LSB ⋅ ∑ x i2 ⋅ 2 i – 1  =
2
 3π ⁄ 2
 i=1 
I LSB 2
=  ------------- E { δ LSB
2 ⋅ ( x 1 + 2x 2 + … + 2 N – 1 ⋅ x N ) } =
 3π ⁄ 2
I LSB 2
= σ LSB
2 ⋅  ------------- ⋅ E { X } (3-32)
 3π ⁄ 2

where the digital input signal, X , was defined in (2-2). The mean value, E { X } , is the dc
value of the sinusoidal and given by

2N – 1
E { X } = --------------- (3-33)
2
Combining (3-32) and (3-33), we have

I LSB 2 2N – 1
E { P k = 2, tot } =  ------------- ⋅ σ LSB
2 ⋅ --------------- (3-34)
 3π ⁄ 2 2
The expectation value of the SFDR can be derived by combining (3-25) and (3-34)

52
 3. DAC Performance Modeling

2
1  2N – 1
--- ⋅ --------------- ⋅ I LSB
2  2   3π
2 2N
 ⋅ -----------
E { SFDR } = ----------------------------------------------------------
- ≈ -----
- - (3-35)
I 2 N–1  4 σ 2
 ------------- ⋅ σ 2 ⋅ ---------------
LSB 2 LSB
 3π ⁄ 2 LSB 2
In dB, this becomes

3π
E { SFDR } ≈ 20 log ------ + 3N – 10 log σ LSB
2 (3-36)
4

SFDR dist. Mismatch dev.: 1/128 SFDR dist. Mismatch dev.: 1/512
40 45

a) Yield (SFDR > 104dB) = 90% 40

b)
35
Yield (SFDR > 116dB) = 90%
Mean = 110 dB
Mean = 122 dB
Number of occurences

Number of occurences
35
30

30
25

25
20
20

15
15

10
10

5 5

0 0
95 100 105 110 115 120 125 130 110 115 120 125 130 135 140 145
SFDR [dBc] SFDR [dBc]
SFDR dist. Mismatch dev.: 1/1024 SFDR dist. Mismatch dev.: 1/2048
35 45

c) Yield (SFDR > 122dB) = 90% 40

d) Yield (SFDR > 128dB) = 90%
30
Mean = 128 dB Mean = 134 dB
Number of occurences

Number of occurences

35

25
30

20
25

20
15

15
10

10

5
5

0 0
115 120 125 130 135 140 145 120 125 130 135 140 145
SFDR [dBc] SFDR [dBc]
Figure 3-7: Histograms showing the variation of the SFDR vs. mismatch for a 12-bit DAC. a) σLSB =
1/128 b) σLSB = 1/512 c) σLSB = 1/1024 d) σLSB = 1/2056

Histograms, shown in Fig. 3-7, using 1000 FFTs of the output of a 12-bit DAC are sim-
ulated to find the expectation value of the SFDR. Each FFT uses 57643 points. The values
are given for different mismatch error standard deviations (which are rather small com-
pared to a real process [4, 9]). The different SFDR expectation values found are
a) σ LSB = 1 ⁄ 128 gives E { SFDR } ≈ 110 dB
b) σ LSB = 1 ⁄ 512 gives E { SFDR } ≈ 122 dB
c) σ LSB = 1 ⁄ 1024 gives E { SFDR } ≈ 128 dB
d) σ LSB = 1 ⁄ 2048 gives E { SFDR } ≈ 134 dB

53
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

It is seen that the SFDR is decreased with approximately 6dB for every time the standard
deviation is doubled. In the figures the yield of the circuits is shown as well. The 90%
yield implies that 90 per cent of the chips will have a better SFDR than the value shown
in the figures.
In Fig. 3-8 we see the comparison between the calculated values from (3-36) and simu-
lated values from histograms as shown in Fig. 3-7. The curves fit well together. For low
values of error standard deviation the spurious tones are hidden in the noise floor and
therefore the curve is saturated. The simulation results from a 20-bit DAC are also
reported in [76].

Simulated and calculated mean value of SFDR.

110

105
Calculated Value
100

95

90
Simulated Value
SFDR [dB]

85

80

75

70

65

60

55
−4 −3 −2 −1 0
10 10 10 10 10
Deviation in the LSB current
Figure 3-8: Summary of the histograms for a 12-bit DAC compared with the calculated values.
Expectation value of SFDR vs. standard deviation for the mismatch error. For low errors
the simulated spurious tones are hidden in the noise floor.

To the matching error we can also include influence of voltage drops over internal wires
as well as the influence of non-linear switches, etc. This also affects the value of the cur-
rent fed to the output, hence can be modeled as matching errors.

3.4 Influence of Circuit Noise

The fundamental limit of the performance is the noise found in the output signal [37].
The resolution of the converter is guaranteed as long as the circuit noise is less than the
average quantization noise. Using different processes and layout styles, or techniques, the
noise may influence the signals in different ways. However, we model the noise as an
error current source in parallel with all unit current sources as described in Fig. 3-5 or
more specific as in Fig. 3-9.
For an ideal N -bit DAC, the SNR (determined by the quantization noise) over the
Nyquist band is (in dB)
SNR ≈ 6.02 ⋅ N + 1.76 (3-37)
assuming uniform quantization steps and a full-scale sinusoidal input.

54
 3. DAC Performance Modeling

ILSB
ilsb

Figure 3-9: Nominal unit current source, ILSB, with included noise source, ilsb.

With each unit current source (equal to the LSB current source) a normal distributed
noise source, i lsb , is associated. Within a certain bandwidth, BW , the mean value is
2
E { i lsb } = 0 and its variance is given by E { i lsb } = i lsb
2 . The expectation value of the

2 , within the bandwidth, BW , can be described

normalized total output noise power, i tot
by the sum of all noise current sources. If we assume that the noise sources are uncorre-
lated, the normalized total noise power can be described by


2 = E  2
P noise = i tot   ∑ i lsb, k  = i lsb
2 ⋅X (3-38)
 k 

where X is the mean value of the digital input, hence the number of sources that are in
mean connected to the output. Assuming that X is a full-scale sinusoidal, the mean value
is given by

2N – 1
E { X } = X = --------------- (3-39)
2

where N is the number of bits. Combining (3-38) and (3-39) gives the expression of the
total normalized noise power, P noise , as

N–1
2 = 2
P noise = i tot --------------- ⋅ i lsb
2 (3-40)
2
The normalized signal power for the full-scale sinusoidal is given by

1 2N – 1 2 2
P signal = --- ⋅  --------------- ⋅ I LSB (3-41)
2  2 

Combining (3-40) and (3-41), the SNR determined by the noise is expressed as

1  2 N – 1 2 2
--- ⋅ --------------- ⋅ I LSB
P signal P signal 2  2  2 N I LSB
2
SNR = -------------- = -------------- = ----------------------------------------------
- ≈ -----
- ⋅ ---------- (3-42)
P noise 2 2N – 1 2 4 i2
i tot --------------- ⋅ i lsb lsb
2

The approximation is valid when the number of bits, N , is large. The SNR in dB is

SNR ≈ 3 ( N – 2 ) + 20 log I LSB – 10 log i lsb

2 dB (3-43)

For wideband CMOS DACs it is the thermal noise from the channel resistance that dom-

55
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

inates other noise sources [37]. The power spectral density (PSD) of a thermal noise cur-
rent source as modeled in Fig. 3-9, is described by

i n2 8
------ ≈ --- kT g m (3-44)
∆f 3

where k is the Boltzmann’s constant, T is the absolute temperature, and g m is the small-
signal transconductance of the current source transistor. Equation (3-44) holds for both
single transistor current sources and cascoded current sources if the impedance at the
source of the cascode transistors is very low. The unit current is approximately given by
β
I LSB = --- ( v SG – v T ) 2 (3-45)
2

where β is the transconductance parameter, V SG is the source-gate voltage, and V T is

the threshold voltage. This also gives the linearized transconductance, g m , determined by

g m ≈ 2β ⋅ I LSB (3-46)

Using the noise and transconductance definitions in (3-44) and (3-46) and assuming that
the thermal noise in the transistors dominates, the noise spectral density in the unit current
source is
8
i n2 ⁄ ∆f ≈ --- kT 2β ⋅ I LSB (3-47)
3

If we assume a certain noise bandwidth of BW , the normalized total output noise power,
2 , from the unit current source is
i lsb

2 = 8
i lsb --- kT ⋅ BW ⋅ 2β ⋅ I LSB (3-48)
3
All the thermal noise associated with the switched current sources degrades the SNR.
Substituting the values from (3-48) into (3-43) gives the approximate expression

SNR ≈ 15 log I LSB + 3N – 5 log  ----- – 10 log BW – 10 log  --- kT 2K'

W 8
(3-49)
 L 3 

In Fig. 3-10 the simulated and calculated SNR for a 12-bit and a 14-bit DAC vs. the cur-
rent through the unit current source, I LSB , are shown. In the simulations process data from
Ericsson’s 0.6µm CMOS process were used. It can be seen from Fig. 3-10 that for high
unit currents, the thermal noise is lower than the quantization noise. The simulated curves
fit well to the calculated values.
The formulae in this section give a guidance on how to choose the current of the unit
(LSB) current source.

56
 3. DAC Performance Modeling

Simulated and calculated SNR. 12−bit DAC. Simulated and calculated SNR. 14−bit DAC.

100 120
Sim
Calc
100
80

80
SNR [dB]

SNR [dB]
60

60

40
40

20
20

0 0

a) −12
10 10
−10 −8
10 10
−6 b) −12
10
−10
10 10
−8 −6
10 10
ILSB [A] ILSB [A]
Figure 3-10: Simulated and calculated SNR vs. the ILSB current for a) 12-bit and b) 14-bit DAC.

3.5 Influence of Timing Uncertainties

Timing uncertainties, skews between current switches of different positions generate
temporary codes. These temporary codes may create a large current spike, glitch, at the
output. If the current spike energy is input signal-dependent they may also introduce dis-
tortion, but most often they appear as noise [28, 56]. It is very hard to model what errone-
ous codes that may temporarily arise on the output. Therefore, we briefly discuss how the
converter reacts on variations of settling time, as was discussed in Sec. 3.2.3 in Part A:
Overview: Digital-to-Analog Converter Design. The output resistance and the output
capacitance are signal-dependent, since the number of current sources that are switched
to the output are dependent on the input code which gives non-linear slewing.
VDD
IS(X) Rout(X)

Cout(X)
RL

iL(t)

Figure 3-11: Generalized view of the converter with output capacitance and resistance.

When the input switches from one code X i – 1 to a consecutive code X i = X i – 1 + 1 , the
output will ideally be given by a step function. However, due to reactive parts of the out-
put and load impedance, the signal will settle towards an end value. In Fig. 3-11 the first
order model of the output of the DAC is shown. In this brief discussion, the influence of
a load capacitance is neglected.
The output current, i L ( t ) , through the termination resistance, R L , is described by

V DD – R L ⋅ i L ( t ) d
i L ( t ) = I S ( X ) + --------------------------------------
- – C out ( X ) ⋅ R L ⋅ ----- i L ( t ) (3-50)
R out ( X ) dt

57
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

which with the initial conditions ( X i – 1 and X i ) gives

i L ( t ) = I i – 1 + ( I i – I i – 1 ) ⋅ ( 1 – e –t ⁄ τi ) (3-51)

where

I LSB + V DD ⋅ G LSB
I i = --------------------------------------------- ⋅ X i (3-52)
1 + R L ⋅ G LSB ⋅ X i

as from (3-2) with the assumption that the start value also has settled to its final value. The
time constant is given by

R L ⋅ C LSB
τ i = ------------------------------------------- ⋅ X i (3-53)
1 + R L ⋅ G LSB ⋅ X i

where C LSB is the capacitor associated with the LSB current source. Obviously τ i is sig-
nal-dependent, and therefore the slewing is non-linear. The maximum value of the time
constant is found when X i is maximal, hence when X i = 2 N – 1 . For the maximum val-
ues at the output the slewing is more crucial, yielding a lower bandwidth. This is also
found in measurements, since non-full-scale signals can give rise to a better SNR and
SFDR than a full-scale input signal. The result in (3-53) may be used to find out the max-
imum possible sampling frequency as well.
If the converter is well designed with respect to the output impedance, (3-53) may be
approximated by

τ i ≈ R L ⋅ C LSB ⋅ X i (3-54)

The knowledge about the time-constant gives the designer information how to construct
the current sources in order to reach the specified update frequency. The error in ampli-
tude level is determined by the time the signal is allowed to settle.

58
 4. A CMOS DAC Chipset for VDSL Applications

4 A CMOS DAC Chipset

for VDSL Applications
In this chapter we discuss the issues behind the design and implementation of a CMOS
digital-to-analog converter chipset for VDSL and wideband radio applications. The
chipset contains three generations of converters and the ad hoc specification is given in
Table 4-1.

Supply Voltage 1.5 - 5 V

Bandwidth 20 MHz
Update Frequency 50 MSps
Peak Output Current < 20mA
Power Dissipation < 20mW
Nominal Resolution 10 - 14 bits
Dynamic Resolution 8 - 12 bits
Table 4-1: Specifications on the CMOS DAC chipset for wideband radio applications.

The first generation focuses on a low-voltage converter and is designed by N. Tan [64].
The second generation focuses on a wideband version and the third generation focuses on
improved matching for the wideband applications [68]. The design of the second genera-
tion converters is presented in this chapter and the target was to design a 14-bit converter
with low power consumption, high-resolution, and high bandwidth. For the second and
third generation, also the knowledge from the modeling work as described in Chapter 3
has been applied. We have however found out that matching was not considered properly
for the second generation and this will also have a large impact on the achieved results
(Sec. 4.3), especially the linearity of the converter.
The first and second generation converters have been measured and the third generation
is still to be measured. The structure used for all converters in the chipset is the current-
steering DAC as discussed in Sec. 2.2.

4.1 Practical Design Considerations

As was mentioned above, the knowledge about the fundamental limits given by behav-
ioral-level modeling, was used to design the DACs. Knowing how the output current
affects transistor sizes, output impedance, and noise, lets us choose a proper value, etc.
The overall structure of the converters is given in Fig. 4-1. Naturally, we have three dif-
ferent parts of the converter:

59
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

• The digital part consisting of clock, flip-flops stabilizing the digital input, and an
MSB segmentation part.
• The analog part consisting of an array of unit current sources.
• The mixed analog/digital parts consisting of current switches.
These issues are further discussed in the following subsections.

M Clock Tree Distribution

bits
Delay Flip-Flops Flip-Flops MSB N-M
Switches Switches Segm. bits

Unit
Current
Mixed Digital/Analog Parts
Sources

I- I+
Dummy Sources
Figure 4-1: Overall structure of the converters in the chipset.

For the i -th LSB, 2 i – 1 unit current sources from the array are connected together and
their output is fed to the current switch controlled by the i -th bit. The output is a differ-
ential current output and if the corresponding bit is a “1” or “0”, the current is routed to
the positive, I + , or the negative output, I - . Differential signals will decrease the influence
of even harmonics (due to non-linearity) in the output.
The segmentation of the MSBs introduces a delay for the MSBs and to avoid skew
between the bits, a digital delay line is used for the LSBs. A clock tree is implemented to
get proper clock delay to all flip-flops controlling the current switches.

4.1.1 Unit Current Sources

The current source used in especially current-steering converters can be constructed in
different ways. A simple structure using a different number of PMOS cascode transistors,
Fig. 4-2, is used in the current source array. Also note that the bulk is connected to the
same potential for all transistors. The use of cascode transistors increases the output
impedance of the current source which affects the performance and linearity of the DAC,
as discussed in Sec. 3.2.
Two versions of the second generation chipset were designed. One containing single cas-
code current sources and one containing double cascode current sources, see Fig. 4-2. The
output resistances of the sources are given by R I and R II , respectively, as [78]

60
 4. A CMOS DAC Chipset for VDSL Applications

2β 2 ( 1 + η ) 2β 3
R I ≈ ( 1 + η ) ⋅ ------------------- and R ≈ R ⋅
I ------------------------------- (4-1)
λ 2 ⋅ I src 3/2 II
λ ⋅ I src

where I src is the output current of the source, λ is the channel length modulation (ap-
proximately equal for all the transistors), β i is the transconductance parameter of transis-
tor i , and η is a parameter given by the bulk-source connection of the transistor (Sec.
1.4.1 in Part A: Overview: Digital-to-Analog Converter Design).

VDD
VDD
M1
M1
M2
M2
Isrc M3
a) b) Isrc
Figure 4-2: Schematic view of PMOS current sources with a) single and b) double cascode.

According to (4-1), the output impedance of the double cascode is higher than for the
single cascode. However, there is one additional internal node, which increases the capac-
itive part of the output impedance and hence introducing extra poles and longer settling
time and therefore this constellation may degrade the performance.

a) b)

Gates M1
M1

M2
M2
M3
Outputs

Figure 4-3: Layout view of PMOS current sources with a) single and b) double cascode.

The transistors all have the same width, W = 2µm , and the lengths are given by
L 1 = 8µm , L 2 = 2µm and L 3 = 1.2µm , for the transistors M1, M2, and M3, respec-
tively.
In the 14-bit DAC the binary weighted current sources were constructed by using unit
current sources from the array by starting in one corner and use one unit current source
for the LSB, the next two attaching unit sources for the second LSB, etc. This will how-
ever not give good matching properties and improvements will be discussed in Chapter 5.

61
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

A part of the second generation array containing the unit current sources is given in Fig.
4-4a). In the figure the internal nodes of the current sources are connected together,
increasing the output capacitance of the sources. The V DD connections are routed over
the M1 transistors, which influences the matching of the source transistors [73]. This were
changed in the third generation DAC as shown in Fig. 4-4b). The internal connections
were also removed to reduce the capacitance.

a) b)
VDD Connections
moved away
VDD Connections from M1
over M1 transistors
M1

Connected Unconnected
Internal M2 Internal
Nodes Nodes
M3
Output Output

Figure 4-4: Part of current source array for the a) second and b) third generation DAC with double
cascode current sources.

For a 14-bit DAC with the peak output current of 20mA, the output current for the unit
current source is
–3
20 ×10
- ≈ 1.22µA
I unit = ------------------- (4-2)
2 14 – 1
Consider the approximate drain current in saturation region for the PMOS transistor

β
i D ≈ --- ⋅ ( v SG – v T ) 2 (4-3)
2
There are several components that are affected by matching errors, i.e., transistor size,
threshold voltage, supply voltage, oxide thickness, bias voltage, output voltage, etc. By
differentiating (4-3) the influence of the matching errors can be seen as

∆i D ∆β ∆V SG – ∆V T
- = ------- + 2 -------------------------------
-------- (4-4)
iD β V SG – V T

When assuming that the deviation of the source-gate voltage is very small, (4-4) approx-
imately becomes

∆i D ∆β ∆V T
- ≈ ------- – 2 ---------------------------
-------- - (4-5)
iD β ( V SG – V T )

The β and V T matching are given by the following terms from (4-5)

∆β 2∆V T
------- and ----------------------
- , respectively (4-6)
β V SG – V T

62
 4. A CMOS DAC Chipset for VDSL Applications

From studies in the literature [4, 9, 55, 71], we know that the β and V T matching are
uncorrelated and that their variance is inversely proportional to the transistor area, WL

Since low power consumption and saturated transistors are wanted, V SG – V T is kept
low and therefore the expression (4-6) may be large.
From a geometrical point of view the term ∆β ⁄ β in (4-4) are dependent on the layout
style. Large transistors and special layout styles are used to reduce the influence of these
kinds of mismatch, i.e., common-centroid and interdigitized layout styles. In the current
source array the matching errors between two neighboring unit current sources may be
strongly correlated and therefore the binary weighted current sources should actually be
constructed by using unit current sources from different positions in the array [9, 39]. This
may however increase wire resistance and capacitance.
If the SFDR of the converter should be guaranteed to be higher than for example 80dB,
equation (3-16) states that
6 ( N – 2 ) + 80
----------------------------------
R LSB ≥ R L ⋅ 10 20 (4-7)

With a 50Ω termination the bound on the output impedance of the current source is
found to be
R LSB ≈ 2GΩ (4-8)

which is hard to accomplish. The output impedance is also dependent on the bias current
controlling the source-gate voltage of the current source (4-1). These voltages are simply
generated using a cascoded current mirror and the reference current through the primary
side of the mirror is determined by a terminating resistance (at an approximate size of 3-
5kΩ). The cascoded current source has an (simulated) output impedance of approximately
R out ≈ 600MΩ (4-9)

corresponding to an SFDR of 70dB for the 14-bit version, which is sufficient for the want-
ed applications.

4.1.2 Current Switches

Naturally, the switch is crucial in a switched system. The properties of the switch may
affect the transfer function and overall performance of the circuit. For example, in feed-
back loops we have to be extra careful with parasitic capacitances and on-resistance of the
switch, otherwise unwanted ringing or unstable circuits can arise. The switch may also
limit the bandwidth of the system, since it basically is an RC-circuit. CFT must be mini-
mized since extra noise and distortion are introduced [71].
The current switches are the mixed analog/digital circuit parts. In the converters a differ-
ential switch has been used, as shown in Fig. 4-5. For larger currents through the switches
(MSBs), larger switches are needed. NMOS transistors are used since the charge mobility
is higher than for the PMOS transistors, hence higher speed. The larger switch, the more
transistors are connected in parallel, as illustrated in Fig. 4-5b). The conductance of an
NMOS switch is given by

63
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

G sw ≈ β ⋅ ( V G – V T – V D ) (4-10)

where β is the transconductance parameter of the transistor, V G is the gate voltage, V T

is the threshold voltage, and V D is the drain voltage. As given in Fig. 4-5, the drain volt-
age is V D = V C and V G is given by the switching signals, φ, φ , whose amplitude most
often is the supply voltage (except for charge-pump versions as in the first generation low-
voltage DACs [64]). It is wanted to keep the conductance of the switch proportional to the
current.

VDD
VDD
Ii = 2i-1 Iunit
Ii = 2i-1 Iunit
VC
VC
φ φ
φ φ

I+ I- I+ I-
Figure 4-5: Differential current switch as a) circuit model and b) transistor implementation.

In principle, to keep the voltage drop over all switches and current sources nearly con-
stant, hence proper matching simpler, the voltage node V C must be constant and equal
for all bits. For the i -th LSB we let this node voltage be denoted V C, i and it is approxi-
mately given by

2 i – 1 ⋅ I unit + G sw, i ⋅ V DC + 2 i – 1 ⋅ G unit ⋅ V DD

V C, i ≈ --------------------------------------------------------------------------------------------------------------
- (4-11)
G sw, i + G unit ⋅ 2 i – 1

where I unit is the output current of one unit current source, V DC is the average voltage
at the output, G sw, i is the conductance of the switches, and G unit is the output conduc-
tance of the unit current source. Equation (4-11) is rewritten as

G sw, i
I unit + G unit ⋅ V DD + ------------ - ⋅ V DC
2i – 1
V C, i ≈ -------------------------------------------------------------------------------- (4-12)
G sw, i
G unit + ------------ -
2i – 1

In order to keep the V C, i equal for all bits, G sw, i ⁄ 2 i – 1 must be equal for all bits, hence

G sw, i = 2 i – 1 ⋅ G sw, unit (4-13)

where G sw, unit is the conductance of a certain unit switch, i.e., the switch corresponding
to the LSB. This implies that the sizes of the switches must be chosen so that their con-
ductance is increasing exponentially with higher LSBs. This will however give very large
switches for the MSBs and too large clock load as well as too high CFT due to the larger
Miller capacitance. A trade off has to be done.

64
 4. A CMOS DAC Chipset for VDSL Applications

The layout of the current switch for the LSB is shown in Fig. 4-6, where one of eight
transistors in parallel is used as switch for each channel. To achieve equal capacitive load
for all switches, the number of NMOS transistors (eight) in the switches is the same for
all bits, although some of the transistors are shorted for LSBs, as shown in Fig. 4-6. A
shielding ground plane around all switches is also used.

Shielding
Ground
Positive switch input Positive Output

Current Input

Negative switch input Negative Output

Short

Figure 4-6: Layout view of a differential current switch.

The inverse switch signal is generated with a simple CMOS inverter. A better glitch per-
formance can be found with a more proper switching scheme. When both switches are
turned off at the same time, the voltage at the output of the current source, V C, i , will
increase and the glitch will be larger when one of the switches is turned on again. There-
fore, it should be guaranteed that both switches are not completely off at the same time
[9, 71], as sketched in Fig. 4-7.
Switch
Ampl.
Positive Switch Signal
VDD

0 Negative Switch Signal

time
Figure 4-7: Wanted switching scheme for the differential current switch.

The possible switching voltage swing, V s, max , of the switches is determined by the max-
imum threshold voltage of the NMOS transistors, V T , max , and the maximum output volt-
age, V out, max , since

V s, max = V out, max + V gs, switch > V out, max + V T , max (4-14)

For a standard process with a maximum output current of 20mA terminated with a 50Ω
load, the minimum switching voltage is approximately V s, max ≈ 1.7 V. For the low-volt-
age ( V DD = 1.5 V) versions of the DACs a charge-pump circuit is used to increase the
voltage swing of the switching signals to overcome these problems.

65
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

4.1.3 Segmentation of the MSBs

To improve monotonicity and reduce glitching, segmentation of the most significant bits
has been used in the design of the converters. A binary code consisting of k bits is trans-
formed into a thermometer code of 2 k – 1 bits and the new switch controlling signals,
[ φ a, φ b, φ c ] , are derived from the old [ φ 1, φ 2 ] by

[ φ a, φ b, φ c ] = [ φ 1 ∧ φ 2, φ 1, φ 1 ∨ φ 2 ] (4-15)

Using the thermometer code we can use a number of equally large current sources, Fig.
4-8. The layout can be more regular and current source sizes as well as current switch
sizes are equally large for the segmented bits. The digital circuitry that transforms the
binary code into the thermometer code introduces delay and therefore the LSBs have to
be delayed correspondingly long time as shown in Fig. 4-1.

I 2I I I I

φ1 φ2 φa φb φc

Figure 4-8: Example of segmentation of two binary weighted sources into three equally large sources.

The current that will flow through one switch will be smaller than for the MSB without
segmentation and therefore a smaller voltage drop over the switches which further
reduces the distortion.
When segmenting the four MSBs in the 14-bit DAC, they will turn into 15 equally large
current sources, each one containing 1024 unit current sources. This is also a disadvantage
since the number of switches, the extra introduced logic, and wires are exponentially
growing with number of bits to segment.
The glitches are roughly dependent on how many bits that are switching between two
consecutive values at the input. By setting up a cost function, i.e., the power of the glitches
or the number of switching bits, we can examine how the power of the glitches are varying
with the number of segmented bits. Simulation results for a 14-bit DAC, shown in Fig. 4-
9, state that about 4-5 segmented bits give a large improvement. For more segmented bits,
the improvement is not that high, and more digital circuitry is also introduced, hence
higher complexity and power consumption.
The segmentation guarantees monotonicity (for the MSBs) and improved DNL since for
an increasing input additional current sources are connected to the output. When only
some of the bits are segmented, the INL is not improved. Matching of the segmented bits
may further be improved by using randomization, averaging techniques, or calibration, as
described in Chapter 5.

66
 4. A CMOS DAC Chipset for VDSL Applications

Glitch Power vs. number of segmented bits.

54

53

52

Power [dB]
51

50

49

48

47

46
1 2 3 4 5 6 7 8 9 10
Number of segmented bits
Figure 4-9: Power of glitches as a function of the number of segmented bits in a 14-bit DAC.

4.1.4 Digital Circuits

The digital circuits implemented in the DAC are constructed in a straight forward way
and they consist of
• logic performing the segmentation of the MSBs, as given in Sec. 4.1.3. The logic
functions are realized with unclocked CMOS circuits.
• digital delay of the LSBs consisting of four cascaded inverters in the delay line.
• flip-flops to stabilize the digital input, realized with clocked CMOS circuits. The
input is aligned with a set bit as well.
• tree-formed clock distribution with buffers.

4.2 Chip Implementation

The whole layout of the second and third generation DACs was done with Cadence, Fig.
4-11. The core size is approximately 2x2 mm2 and the chips were fabricated in Ericsson’s
0.6µm CMOS process.
To improve the supply distribution to the current sources a VDD plane is covering the
whole array. This also improves the V T matching as was discussed in Sec. 4.1.1. Espe-
cially for CMOS current sources, where the current is controlled by the gate-source volt-
age, special care has to be taken. A true supply voltage for all current sources of the array
has to be guaranteed [38].
Consider the example shown in Fig. 4-10. The currents, I ( V i ) , generated from current
sources implemented with transistors, are determined by the source-gate voltage, hence
dependent on the supply voltage and should all be equally large. If we assume a wire resis-
tance, there will be a voltage drop over the supply line, V DD < V 1 < … < V N , and the cur-
rents, I ( V i ) , become non-equal since the gate-source voltages are different.

67
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

VDD R V1 R V2 R R VN
IDD

I(V1) I(V2) I(VN)

Figure 4-10: Model of the voltage supply line connected to a number of current sources.

In high-performance circuits the reference current errors have to be very small. There-
fore, we cannot distribute the supply along a single wire due to the voltage drop. For the
supply distribution it is also necessary to analyze the peak current to avoid breakdown of
the wires.

Digital Inputs

Digital
Circuitry

Interconnection
Wires
Current
Source Array

Analog Inputs
Current Outputs
Figure 4-11: Chip layout of the third generation DAC.

In mixed analog/digital design, disturbances from the digital to the analog part (or vice
versa) spread along supply lines and the substrate. The substrate coupling may be strong.
It is therefore necessary to do careful designs with proper shielding, which may be done
in different ways [33], i.e., guard rings, grounding, etc.
At board level it is also needed to shield and separate the signals [20]. The chip analog
pins are separated from the digital as far as possible. As well as grounding pins are used
in-between. The pin configuration of the chip is equal to the Analog Devices’ 14-bit DAC:
AD9764 (member of the TxDAC series) and hence a 28-bit SOIC socket [84].
A good clock distribution is needed to minimize the influence of clock skew, which
strongly affects the performance of the converter. The energy of the glitches are depen-
dent on the skew between the different bits. Shown in Fig. 4-12 are two examples on good
clock distribution that reduce the skew between different subcircuits.

68
 4. A CMOS DAC Chipset for VDSL Applications

Subcircuits

Subcircuits
Master Master

Figure 4-12: Clock tree structures to improve buffering and equal clock delay to the circuit.

4.3 Simulation and Measurement Results

When simulating the converter it is important to know what to simulate and how to
extract information about the device from the measurement and simulation data. As was
stated in the previous part, there are static and dynamic properties. These can be analyzed
in the time and frequency domain.
We can use different structures when measuring the DAC, depending on the measure-
ment equipment. The simple structure in Fig. 4-13a) uses a digital input stimuli generator
and the analog output is analyzed using spectrum analyzers and oscilloscopes. This is also
the structure that have been used during the measurements of the chipset DACs.
Since some of the information about the converter under test has to be found by using a
large number of measurements it may in some cases be useful to use a reference converter
to compare the output results instead, Fig. 4-13b-d). To perform a DNL or INL measure-
ment of a 14-bit DAC with 2 14 = 16384 levels that has to be recorded, a reference ADC
as in Fig. 4-13d) is used. The digital data is recorded and analyzed by a computer, further
reducing time and complexity [16]. The reference converters have to have higher resolu-
tion than the DAC under test and their performance behavior must be known to be able to
analyze the result from the converter under test.

a) b) ADC DAC
DAC
Test Ref Test
c) d)
DAC DAC
Test Test

DAC ADC
Ref Ref
Figure 4-13: General measurement setups. a) Input is generated with a stimuli generator b) Input signal
is generated using an ADC c) Output is compared with a reference DAC d) The output is
converted back to an analog signal and can be compared with the original input signal.

At the behavioral-level, MatLab or similar tools are used (Chapter 3), on the circuit-
level, Spice, Spectre or similar [43] are used. Since DACs are mixed analog/digital cir-
cuits mixed-mode simulations are performed. It may be necessary to partition the circuit
into digital and analog parts to increase the speed of the simulation [43]. The digital cir-
cuits may be simulated with event driven simulators, using simplified models for transis-

69
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

tors. However, at the interface between the digital parts and analog parts the analog
signals may be affected by digital switches, e.g., current switches driven by digital switch-
ing signals. In order to analyze glitches, supply noise, substrate coupling, etc., it may be
preferred to perform the whole simulation with a more accurate analog simulator using
continuous-time models.
We will also divide the measurements into single-, dual-, and multi-tone measurements
since all necessary information about the converter may not be extracted from single-tone
measurements [5].

4.3.1 Test Signal Generation

For single-tone measurements an update frequency that is relatively prime with the sig-
nal frequency is used to guarantee that all codes are used (for a full-scale tone). Otherwise
all information about the converter’s performance is not extracted. This ensures also that
no distortion term is folded back and interferes with other frequency components and
causing errors in the measurement. For dual-tone measurements the signal frequencies are
relatively prime, and they are relatively prime with respect to the sampling frequency. For
multi-tone measurements we apply a number of tones with frequencies at multiples of a
fundamental frequency.
The test pattern has to be long and accurate enough, since irregularities in the input signal
can give rise to odd phenomena. If the signal is clipped, this will affect the output spec-
trum, see Fig. 4-14. With a signal clipped at 99.5% of its maximum value, the SFDR is
approximately only 70dB for a 14-bit DAC, Fig. 4-14b).

Output of unclipped sinus Spectrum of clipped sinus (0.5%)

a) 80 b) 80

60 60

40 40
Magnitude [dB]

Magnitude [dB]

20 20

0 0

−20 −20

−40 −40

−60 −60

0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4

Normalized frequency Normalized frequency
Figure 4-14: Output amplitude spectrum from a 14-bit DAC with a) an unclipped signal and b) clipped
signal at 99.5% of its maximum value.

A signal that is not completely periodic will also give rise to distortion in the output. In
Fig. 4-15b) the amplitude spectrum of the output signal from a 14-bit DAC when leaving
out only one single sample of the whole period containing 1917 points is shown.

70
 4. A CMOS DAC Chipset for VDSL Applications

Output with full−length vector Output with truncated vector

80 80
a) b)
60 60

40 40

Magnitude [dB] 20 20

Magnitude [dB]
0 0

−20 −20

−40 −40

−60 −60

−80 −80

−100 −100

0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4

Normalized frequency Normalized frequency
Figure 4-15: Output amplitude spectrum of a sinusoidal with a) full-length test vector and b) truncated
test vector.

For the discrete multi-tone (DMT) we use a signal equal to orthogonal frequency divi-
sion multiplexing (OFDM) where the signal, y ( t ) , should be given by
N – N0 – 1
1
y ( t ) = --------
N
∑ c n ⋅ e jn∆ωt (4-16)
n = N0

where c n is the complex value given by the code word assigned to the n -th carrier. ∆ω
is the spacing between the carriers, N 0 ⋅ ∆ω is the starting frequency, and N is the num-
ber of carriers.
When simulating the DMT signal, the first approach would be to simply use the expres-
sion where no information has been applied to the c n terms from (4-16)

K
y(t ) = A ⋅ ∑ sin ( kω0 t ) (4-17)
k=1

where ω 0 is a fundamental angular frequency, A is the amplitude of each carrier, and K

is the number of tones. This will however give rise to large peaks in the time-domain out-
put, Fig. 4-16a). It gives non-equal distribution of the amplitude levels which is unwanted
[14, 50, 69], since the input codes are not used equally often and hence the output signal
is hard to analyze. Therefore, by adding a random variable (phase) to each sinusoidal, a
better crest factor is achieved. This also simulates random information applied to the c n
terms. The new approach gives the signal
K
y(t ) = A ⋅ ∑ sin ( kω0 t + φk ) (4-18)
k=1

71
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

where φ k ∈ [ 0, 2π ] is uniformly distributed. Applying a random phase on the signals,

gives a multi-tone signal that is better suited for simulation, see Fig. 4-16b). The ampli-
tude spectrum of the both signals, (4-17) and (4-18), is the same.

Sines without random phase. Sines with random phase.

200 50
a) b)
40
150
30
100
20
Signal amplitude.

Signal amplitude.
50
10

0 0

−10
−50
−20
−100
−30
−150
−40

−200 −50
0 0.02 0.04 0.06 0 0.02 0.04 0.06
Time. Time.
Figure 4-16: The output signal for a DMT system with a) fixed phase and b) random phase. The crest
factor is improved by changing to random phase. Note the different scales.

These are some of the aspects that have to be considered when analyzing the output sig-
nal. With an erroneous input signal the output cannot be trusted.

4.3.2 Measurement Results

Measurements have been done at Ericsson Radio AB, Kista-Stockholm, and at the
department of Physics and Measurements (IFM), Linköping University. As evaluation
board the Analog Devices’ AD976x-EB board has been used [84]. The results have been
compared with the corresponding results from the Analog Devices’ DAC AD9764.
To characterize the performance of the converters mostly the frequency domain has been
studied and the measurement results are briefly summarized in Sec. 4.3.3.
In Fig. 4-17a) we see the output spectrum for the 10-bit single cascode DAC when apply-
ing a full scale single-tone at supply voltage 3.3V. The signal frequency at the output is
approximately 3.43MHz and the update frequency is 20MHz. It is found that the third har-
monic is the one determining the SFDR to be 48dB. Harmonics of even order are reduced
due to the use of differential signals.
A dual-tone measurement result from a 14-bit double cascode DAC at 5V supply is
shown in Fig. 4-17b). The update frequency is 20MHz and the signal frequencies are
approximately 3.43MHz ( f 1 ) and 3.51MHz ( f 2 ). The SFDR is 49dB and the IMD given
by the 2 f 1 – f 2 frequency component is -54dB.

72
 4. A CMOS DAC Chipset for VDSL Applications

a) b)

Figure 4-17: a) 10-bit single cascode DAC. 3.3 V supply. Single tone. 20 MHz clock frequency.
b) 14-bit double cascode DAC. 5 V supply. Dual tone. 20 MHz clock frequency.

The SFDR vs. clock frequency for the single cascode 10-bit DAC, single cascode 14-bit
DAC, and double cascode 14-bit DAC is shown in Fig. 4-18a) through c), respectively.
In the figures the results from both 3.3V and 5V supplies are shown.

4.3.3 Measurement Conclusions

There are some results found by observing the measurement results:
• During the measurements of the chipset we have seen that there are practically no
larger variations of performance when changing the supply voltage from 5V to
3.3V.
• There are no larger variations between the single and double cascode implementa-
tions, hence the output impedance of single cascodes is large enough.
• Matching errors that degrade the performance origin from:
→ Matching of current sources
→ Voltage drop over internal wires
→ Too high on resistance of the current switches
• The bandwidth is rather low indicating a high capacitive part at the output of the
converters, probably origins from the internal wires as described in Sec. 4.1.1.
• Time-domain simulation results show low glitching behaviour, probably due to
good clock distribution and segmentation of the MSBs.
The results can be improved by doing a more careful layout with respect to parasitic
resistance and capacitance [33] as well as improving the matching of the current sources
with a different assignment of unit current sources [9, 39].
From measurements of the 1.5V 10-bit DAC [64], we know that the performance can
further be improved with the same CMOS process. An SFDR over 60dB has been mea-
sured.

73
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

SFDR vs. Clock Frequency. 10−bit DAC.3.3 and 5−V supply.

52

50 (49)

48

SFDR [dB]
46

(44)
44

42

40
0 5 10 15 20 25 30 35 40 45 50 55
Clock Frequency [MHz]
SFDR vs. Clock Freq. 14−bit DAC (Single Casc.) 3.3 and 5−V supply.

50
(49)

48
SFDR [dB]

46

44

(42)
42

40

0 5 10 15 20 25 30 35 40 45 50 55
Clock Frequency [MHz]
SFDR vs. Clock Freq. 14−bit DAC (Double Casc.) 3.3 and 5−V supply.
51

50
(49)
49

48

47
SFDR [dB]

46

45

44

43 (42)
42

41

40
0 5 10 15 20 25 30 35 40 45 50 55
Clock Frequency [MHz]

Figure 4-18: SFDR vs. Clock frequency for the a) single cascode 10-bit DAC, b) single cascode 14-bit
DAC, and c) double cascode 14-bit DAC. (*) at 3.3 V supply. (o) at 5 V supply. The
signal-to-clock frequency ratio is approximately 1/6.

74
 5. Improvements of the DAC Design

5 Improvements of
the DAC Design
It has been shown that the performance of the converter is dependent on matching, noise,
and output impedance. In measurements (Chapter 4) it has also been found that it is the
non-linearity due to matching errors that limits the performance of the implemented con-
verter chipset. In this chapter we present some techniques that can be used to improve the
performance of the wideband converters. Some of the techniques will be implemented in
future versions of the chipset.
The most common techniques to further improve the performance are
• Digital correction; calibration and trimming of sources, etc. [8, 10, 13, 54, 56]
• Dithering; randomization of segmented sources and dynamic element matching,
etc. [11, 24, 35, 56]
In some cases, a kind of an observer is needed. For the use in DACs it has to be analog
and it is therefore often hard to design due to its use in wideband applications.

5.1 Digital Correction

Naturally, the output of the current sources can be used to determine the non-linearity of
the converter. By using this information the digital input can be changed in such a way
that the non-linearity can be reduced, i.e., error compensation. This introduces more com-
plexity and in some cases even more noise since non-linearity components is spread out
like noise. The digital correction needs some kind of feedback to change the input data to
compensate for errors. This feedback loop slows down the converter and limits the band-
width. Another drawback is, that some kind of analog-to-digital conversion is needed.

5.1.1 Intentional Pre-Distortion

It is possible to eliminate some of the distortion by using intentional pre-distortion [54].
Assume that the output signal of the converter, A out ( X ) , should be a linear function of
the input, X , as

A out ( X ) = A ref ⋅ X (5-1)

With fine quantization, hence a large number of bits, the quantization error is considered
to be white noise and can therefore be neglected in this discussion. Suppose that the con-
verter is non-linear of the first order and that the output amplitude can be written as

A out ( X ) = A ref ⋅ X + a ⋅ X 2 (5-2)

75
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

Note that no delay skew is assumed in this simple model. Suppose that a new input, X̃ ,
which is described by

X̃ = X + b ⋅ X 2 (5-3)
is applied to the input. By inserting (5-3) in (5-2), the output signal becomes

A out ( X ) = A ref ⋅ X̃ + a ⋅ X 2 = A ref ⋅ [ X + b ⋅ X 2 ] + a ⋅ [ X + b ⋅ X 2 ] 2 =

= A ref ⋅ X + [ A ref ⋅ b + a ] ⋅ X 2 + 2ab ⋅ X 3 + ab 2 ⋅ X 4 (5-4)

It is obvious that even more distortion components appear in the output. However, if
A ref b + a = 0 ⇒ b = – a ⁄ A ref (5-5)

the influence of the X 2 component is eliminated. Therefore we have

a2 a3 4
A out ( X ) = A ref ⋅ X – 2 ---------- X 3 + ---------
2
-X (5-6)
A ref A ref

If it is guaranteed that

a2 a3 4
a ⋅ X 2peak > 2 ---------- X 3peak and a ⋅ X 2peak > ---------
2
- X peak (5-7)
A ref A ref

the SFDR is improved since the higher order harmonics are smaller than the first order
harmonic as the example shows in Fig. 5-1, where the improvement in SFDR is approxi-
mately 27dB with pre-distortion.

Output without predistortion Output with predistortion

20 20

0 0

−20 −20
Magnitude [dB]

Magnitude [dB]

∆SFDR
−40 −40

−60 −60

−80 −80

−100 −100

0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4

Normalized frequency. Normalized frequency.
Figure 5-1: Output amplitude spectrum from a non-linear DAC a) without and b) with pre-distortion.
The improvement, ∆SFDR, is approximately 27dB.

Note that for a sinusoidal input, we may have components that are folded back onto the
fundamental frequency, X 3, X 4, … , and interference occurs.

76
 5. Improvements of the DAC Design

Intentional pre-distortion is most often only suitable for measurement, where it is rela-
tively easy to distort the input signal. In a real chip implementation, digital squaring cir-
cuits are needed (5-3), as well as analog observers to determine the magnitude of the
actual non-linearity. This introduces more complexity to the design of the circuit, higher
power consumption, etc.

5.1.2 Calibration and Trimming Techniques

The output of the converter can be modified by using additional current sources, or in
fact an additional DAC. Using a method similar to the structure sketched in Fig. 5-2 the
output current is changed using a compensating DAC. The error current resulting from
matching errors in the original DAC can be reduced by adding or subtracting an equally
large amount of current from the compensating DAC [56].

Delay Current Sources

Original DAC

Outputs have to
be observed.
Logic Current Sources

Compensating DAC

Figure 5-2: Use of extra current sources to compensate and calibrate errors.

This method will however require an observer that performs an analog-to-digital conver-
sion, which is undesired. An automatic compensating routine that works at the same speed
as the original converter is also needed. This implies that the observer must know the
input signal and hence it may be necessary to generate special calibration vectors inter-
nally. This further slows down the converter and increases the complexity. It should also
be noted that the compensating DAC cannot only be set for static errors, since it is the
dynamic errors that determine the quality at higher frequencies.
Calibration or trimming techniques can be used to minimize the influence of mismatch
[8]. The basic principle is that the source-gate voltage, V SG , can be held by using the
source-gate capacitance, C sg , see Fig. 5-3. When switch S 1 and S 2 are conducting (in
the positions opposite to the ones shown in the figure), the capacitance, C sg , is charged.
The V SG will now take a value corresponding to the reference current, I ref , which is the
wanted nominal output current of the current source. Mismatch errors of the transistor will
not affect the output current since V SG is dependent on the reference current only. When
S 1 and S 2 are not conducting the V SG is set by the charge on C sg . However, due to the
leakage currents and CFT the true value cannot be guaranteed, the source-gate voltage has
to be refreshed at regular basis.
The advantage of this technique is that the matching errors of the transistors no longer
affect the result. Disadvantages are that additional switches are needed (hence larger load)
and for high resolutions a large number of current sources have to be calibrated. This also
implies that the calibration phase may take a long time, which may not be possible for cer-

77
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

tain applications. Still we also have to guarantee that the errors in switches, leakage cur-
rents, etc., are smaller than the original matching errors.

Cgs

Vbias S1

S2
Iref
To current
switches

Figure 5-3: Circuit solution to calibrate the current sources at certain time points.

The technique can be used for the segmented MSBs, but than their mismatch with the
binary weighted LSBs may be even worse, hence the reference current source must be
very accurate. The technique is also suitable for R-2R ladder structures where there is only
a number of equally large current sources [8].

5.2 Dithering
The main principle of dithering technique is to smooth distortion into noise or generally
forcing matching errors (or similar) that generate non-linearity to be signal-independent.

5.2.1 Randomization of Segmented Current Sources

When segmenting the sources of a current-steering DAC, a number of equally large cur-
rent sources is used. The digital input controlling the current switches corresponding to
these sources is a thermometer code. In the conventional design, the input number,
X = 1 , is represented by using one specific current source, X = 2 is represented by
using two specific sources, etc. With this structure the matching errors are strongly signal-
dependent. The digital circuit can be designed so that, at different times, different sources
are used to represent X = 1 . The sources that should be used, can be chosen in a random
way, using a pseudo-random binary sequence (PRBS), and they can be chosen by sweep-
ing through sources in a cyclic way, using the clock, see Fig. 5-4.

Binary Therm.
Input Code
Current
Segmentation Switches

Randomizer
Figure 5-4: Randomization of bits. The matching error becomes uncorrelated with the signal.

The matching errors become more or less uncorrelated with the signal and therefore, the

78
 5. Improvements of the DAC Design

errors turn into noise instead of distortion. Assume that there are K segmented current
sources. Each current source, I k , k = 1…K , has the same nominal size, I src . For each
source a relative mismatch error, δ k , is associated, hence

I k = I src ⋅ ( 1 + δ k ) (5-8)

Without the randomization the relative error for the code X M = M = 0011…11 ( M
number of “1”:s) would be
M
1
δ Xi = -----
M ∑ δk (5-9)
k=1

Hence the relative errors for the codes X 1, X 2, X 3, …, X K would be

δ1 + δ2 δ1 + δ2 + δ3 δ1 + … + δK
δ X 1 = δ 1, δ X 2 = ----------------
-, δ X 3 = ----------------------------
-, …, δ XK = -----------------------------
-
2 3 K
The DNL and INL values are given by

D i = δ i and I i = ∑ Di = ∑ δi (5-10)

With randomization we have the same relative error for all codes X i as

K
1
δX = ----
K ∑ δk (5-11)
k=1

since for each code all current sources are used equally many times (in mean) due to the
random assignment of sources. Since all codes give the same error, this will only be seen
as an offset error for all the segmented current sources

1
D 0 = ---- ( δ 1 + … + δ K ) and D i = 0 for i ≥ 1 (5-12)
K
and hence the average DNL will be improved. The DNL error at the gap between the seg-
mented MSB sources and the LSBs may increase. The INL values become
1
Ii = ∑ Di = D 0 = ---- ( δ 1 + … + δ K )
K
(5-13)

In the frequency domain the distortion terms are reduced to the cost of a higher noise
floor, Fig. 5-5. The increase of noise is dependent on the matching error sizes, δ k . In the
simulation a mismatch error with standard deviation of approximately 12% was used.
For clock driven assignment of the sources, the errors may still be slightly signal-depen-
dent, but the linearity errors are reduced. It should be noted that these results are very hard
to predict and derive. The clock driven (cyclic shift) has the advantage of not needing any
random sequence. The output signal using this technique will still contain distortion
terms, they are however reduced to the cost of a higher noise floor.

79
 Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications

Output without randomization Output with randomization

0 0

−10 −10

−20 −20

−30 −30
Magnitude [dB]

Magnitude [dB]
−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90

−100 −100
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
Normalized frequency Normalized frequency
Figure 5-5: Output amplitude spectrum from 256 segmented sources a) without randomization and b)
with randomization.

In fact, the principle of randomization can be generalized to be used on the entire DAC.
The current sources in a current source array are addressed basically in the same way as
a RAM. To achieve a simple and regular layout, this forces digital circuits to be included
with the current source in the array, since each current source has to have its own current
switch. This also increases the wire lengths and noise between digital and analog parts.
For DAC structures with resolutions higher than 8-10 bits this technique is hard to apply
due to area and complexity. Hybrid versions use this digital control for the MSBs and a
binary weighted structure for the LSBs, very similar to randomization of segmented
sources.
Another technique is to use dynamic element matching (DEM) where the main principle
is to divide the converter into a number of subconverters with a lower resolution. The
input to the subconverters are modified so that the matching errors (noise) is shaped as
well [24, 35]. Using the randomization technique, the noise floor is increased (see Fig. 5-
5b). To reduce the noise floor within a certain signal band, the noise can be shaped and be
moved to other (higher) frequencies. This higher noise is filtered out by an analog filter
at the output. However, this implies an oversampling converter structure, which is
described in the next part of the thesis, Part C: Oversampling Digital-to-Analog Convert-
ers for ADSL Applications.

80
 Oversampling
C
Part C:

Digital-to-Analog
Converters for
ADSL Applications

1 Introduction
In this part of the thesis we present an overall description of the oversampling digital-to-
analog converter (OSDAC) with theory and implementation. First we give a general intro-
duction to the principle of oversampling and in Chapter 2 a description of building blocks
associated with an OSDAC. The design of a 3.3V-5V CMOS OSDAC for ADSL appli-
cations is described in Chapter 3.
A Nyquist-rate converter has the peak SNR (within the Nyquist bandwidth), f N , given
by SNR ≈ 6.02N + 1.76 dB. The sampling frequency, f OSR , for the OSDAC is given by
the oversampling ratio (OSR) and the original sampling frequency, f s , as

f OSR = OSR ⋅ f s (1-1)

The quantization noise will now be given by the bandwidth determined by f OSR . With
a lowpass filter, Fig. 1-1, the signal within the wanted original bandwidth, f N = f s ⁄ 2 ,
is filtered out and, ideally, the SNR within this frequency range is now given by [37]
SNR ≈ 6.02N + 1.76 + 10 log OSR (1-2)

81
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

The OSDAC can obviously be designed for low noise and high resolution if the over-
sampling ratio is high due to the term: 10 log OSR in (1-2). However, the increase of SNR
is still only 3dB for every doubling of the OSR and when increasing the dynamic range a
higher resolution of the DAC still is required to meet the specifications on the linearity.
In a 14-bit DAC with an OSR = 4, the linearity of the converter must correspond to a 15-
bit DAC [37].

L DAC LP

Figure 1-1: Naive use of oversampling. The input signal is oversampled L (= OSR) times. Images that
occur due to the oversampling is filtered out using the lowpass filter.

By using noise shaping with a modulator (Fig. 1-2), the linearity and the SNR of the con-
verter may be improved significantly, as is further described in Chapter 2. In fact, the
improvement in SNR is approximately given by (in dB)
( 20 ⋅ M + 10 ) log OSR (1-3)

where M is the order of the modulator.

L Σ∆ DAC LP

Figure 1-2: Oversampling DAC using modulation to improve linearity and signal-to-noise ratio.

The modulator is purely digital and it reduces the number of bits of the signal. This intro-
duces a higher quantization noise which is highpass filtered and the original signal infor-
mation is lowpass (or allpass) filtered. The reduced number of bits also relaxes the
requirements on the DAC used in the converter and hence the number of analog building
blocks may be decreased. By reducing the number of bits to only one single bit, i.e., pulse
code modulation (PCM), the DAC can be designed to be completely linear since it has
only two threshold values [11]. Noise shaping is also referred to as sigma-delta (Σ∆) or
delta-sigma (∆Σ) modulation.
The ADSL standard as described in Part A: Overview: Digital-to-Analog Converter
Design has a bandwidth of approximately 1.1MHz [83]. Since the OSDAC contains a few
number of analog elements, the oversampling ratio can be large. With an oversampling
ratio of 32, the sampling frequency is approximately 71MHz for the OSDAC for ADSL
(Chapter 3) and basically there are no bigger problems designing digital circuitry for these
speeds. The OSDAC is implemented in Ericsson’s 0.6µm CMOS process.
In this part we focus on and describe a behavioral-level design of an OSDAC where the
trade-offs between different building blocks are highlighted and discussed.

82
 2. Oversampling DAC Structures

2 Oversampling DAC
Structures
Several different oversampling converter structures can be found [11, 37, 41, 46, 56, 59,
60, 63]. We show a general topology (Fig. 2-1) which is divided into a number of basic
building blocks; interpolation filter, modulator, M-bit DAC, and analog filter.

N bits @ f OSR
X2(kTo)
Interpol. Modu- DAC Analog
X1(kTs) Filter lator (M bits) X4(kTo) LP filter Aout(t)
X3(kTo)
N bits @ f s M bits @ f OSR
Figure 2-1: General structure of the oversampling digital-to-analog converter. Interpolation filter,
Modulator, DAC, analog lowpass filter (smoothing filter). The interpolation filter fulfils
the oversampling of the signal and the modulator the reduction of bits in the circuit.

The input signal, X ( kT s ) , is given by N bits at a certain clock frequency f s = 1 ⁄ T s .

An interpolation filter is used to increase the clock frequency to f OSR = 1 ⁄ T o , as well
as filter out higher frequency components in the signal. This is further discussed in Sec.
2.1. The interpolated signal, X 2 ( kT o ) , is modulated by the modulator (Sec. 2.2) which
reduces the number of bits from N to M in its output signal X 3 ( kT o ) . The DAC can now
be designed for M bits and its output X 4 ( kT o ) is lowpass filtered by the analog filter
(Sec. 2.4) which removes images and compensates for sinc weighting of the output signal
A out ( t ) . The DAC is a Nyquist-rate DAC with the Nyquist frequency f OSR . Note that
the linearity of the M -bit DAC still has to correspond to N bits.

N bits @ f OSR
X (kT )
Interpol. 2 o Modu- Semi-digital Analog
X1(kTs) Filter lator X3(kTo) FIR filter X4(kTo) LP filter Aout(t)
N bits @ f clk 1 bit @ f OSR
Figure 2-2: Structure of the oversampling digital-to-analog converter when reducing the number of
bits to one.

When letting the modulator reduce the number of bits to only one single bit, see Fig. 2-
2, the DAC can be replaced by a semi-digital FIR filter (Sec. 2.3), that both converts from

83
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

a digital to an analog representation and filters the signal as well [34, 63]. The semi-digital
FIR filter can be considered to be a number of cascaded single-bit DACs with different
reference levels. With this method the analog smoothing filter can be designed with less
complexity. However, the modulator must be designed more carefully with respect to sta-
bility since the loop gain is high.

a)

fs / 2 fs
b) Interpolation
filtering

2fs = fOSR / 2 4fs = fOSR

c)
Shaped noise

d)
Lowpass filtering

e)

fs / 2

Figure 2-3: Frequency spectrum for different stages of the oversampling with noise shaping. In this
example OSR=4. a) Original spectrum. b) Oversampling spectrum. c) Noise is shaped. d)
Lowpass filtering the original signal e) Wanted output spectrum.

The amplitude spectrum of a signal at different stages in an oversampling converter with

OSR = 4 is shown in Fig. 2-3. The original signal within the Nyquist band, f N = f s ⁄ 2 ,
Fig. 2-3a), is interpolated and the spectrum is repeated over the oversampling frequency
range. The interpolating filters attenuate the images as illustrated in Fig. 2-3b). With the
noise shaping function the noise is attenuated at lower frequencies (< f N ) and amplified
at higher frequencies ( f N < f < 0.5 f OSR ), Fig. 2-3c). A lowpass filter (semi-digital FIR
filter and analog LP filter) is used to filter out images and the amplified noise, Fig. 2-3d).
As is illustrated in Fig. 2-3e) the quantization noise is lower than for the original case, Fig.
2-3a).

2.1 Interpolation Filters

The purpose of the interpolation filters is to interpolate and reduce the influence of the
images (Fig. 2-3b) that arise due to the oversampling [21, 11]. The internal filtering func-
tion reduces the requirements on the next following building blocks as given in Fig. 2-1
and Fig. 2-2. When implementing the interpolation filter, the oversampling is most often
done in steps, i.e., multi-stage filters, as sketched in Fig. 2-4.

84
 2. Oversampling DAC Structures

H0(z) L1 H1(z) L2 H2(z) LN HN(z)

Figure 2-4: Principle description of multi-stage interpolation filtering.

The oversampling ratio (OSR) is given by the individual oversampling ratios, L i , as

OSR = L 1 ⋅ L 2 ⋅ … ⋅ L N (2-1)

The interpolation function is described by


y ( kT ) =  x ( kT ) k = m⋅L (2-2)
 0 k≠m⋅L

where y ( kT ) is the output signal, x ( kT ) is the input signal, L is the oversampling ratio,
m = 0, 1, 2, … is an integer, and T is the update time interval. In the frequency domain
(2-2) corresponds to

Y (z) = X (zL ) (2-3)

The total transfer function, H OSR ( z ) , of the filters in Fig. 2-4 is given by

H OSR ( z ) = H 0 ( z OSR ) ⋅ H 1 ( z L 2 ⋅ … ⋅ L N ) ⋅ H 2 ( z L 3 ⋅ … ⋅ L N ) ⋅ … ⋅ H N ( z ) (2-4)

where H i ( z ) are the subfilters of the multi-stage filter. By using interpolation in stages or
frequency masking techniques [36] the filters H i ( z ) may be designed easier and with less
complexity and less power consumption. A simple structure of a one-stage interpolation
filter is shown in Fig. 2-5. It is an FIR filter with K taps and the output is given by

Y ( z ) = H ( z ) ⋅ X ( z ) = [ a 0 + a 1 z –OSR + … + a K – 1 z –OSR ⋅ ( K – 1 ) ] ⋅ X ( z ) (2-5)

The implementation of long filter coefficients may cost much and therefore filter struc-
tures with simple coefficients are wanted.

x(nT)
T/OSR T/OSR T/OSR

a0 a1 a2 aK-2 aK-1
y(nT)

Figure 2-5: General one-stage interpolation filter.

If the oversampling ratio is high, the interpolation filter has to be narrow banded which
increases the number of coefficients in the filters and the complexity [36].

85
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

2.2 Modulator
Basically, the modulator in an OSDAC is designed to reduce the number of bits repre-
senting the signal, i.e., to use a pulse code modulation (PCM). This implies that the quan-
tization noise will increase, but the noise can be shaped in such a way that it is highpass
filtered. The transfer function from the noise to the output will be referred to as the noise
transfer function (NTF) and for the signal we will refer to the signal transfer function
(STF). The STF is either an allpass or lowpass filtering function.
Generally, the modulator contains a feedback loop and IIR filters to shape the noise. The
feedback is of two kinds:
• Signal feedback (Sec. 2.2.1)
• Error feedback (Sec. 2.2.2)
The filters used in the modulator are different in the two structures. Dependent on the
number of bits at the output the modulator structures are divided into two groups:
• Multi-bit modulators
• Single-bit modulators
In this thesis, we focus on the single-bit modulator, which has a large loop gain and
therefore the stability must be carefully considered [56, 60]. In the single-bit modulator,
a certain value at the input is represented by the average value of the pulses at the output,
hence the average duty cycle. Hence the maximum value of the input is represented by a
stable maximum output value on the output. The mean value of the input is represented
by a square waved signal with 50% duty cycle. In Fig. 2-6 the simulation result for a first
order modulator using signal feedback (Sec. 2.2.1) is shown. The input is sweeping from
a value near the minimum amplitude to a value near the maximum (dashed line) and the
output signal is described by the square waves (solid line).

Input Ramp and Output Signal.

0.8

0.6

0.4
Normalized Amplitude

0.2

−0.2

−0.4

−0.6

−0.8

−1
0 50 100 150
Sequence Index
Figure 2-6: The average value of the output approximates the input signal. The simulation results are
achieved with a first order signal feedback modulator.

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 2. Oversampling DAC Structures

2.2.1 Signal Feedback Modulator

The signal feedback modulator uses the output signal to feed back [37], as shown in Fig.
2-7. For a single-bit output, the output signal, y ( nT ) , is equal to the MSB of the quan-
tizer’s input, w ( nT ) , and the quantization noise is q ( nT ) = y ( nT ) – w ( nT ) .

x(nT) + w(nT) y(nT)

H(z)
-

G(z)

Figure 2-7: Basic principle of a signal feedback modulator.

In the frequency domain, the input to the quantizer, W ( z ) , is given by

W (z) = H (z) ⋅ [ X (z) – G(z) ⋅ Y (z)] (2-6)

where Y ( z ) is the output signal and can be written as

Y (z) = Q(z) + W (z) (2-7)

where Q ( z ) is the error signal caused by the quantization. Therefore, we have

Y (z) = Q(z) + H (z) ⋅ [ X (z) – G(z) ⋅ Y (z)] (2-8)

or

H (z) ⋅ X (z) Q(z)

Y ( z ) = ------------------------------------- + ------------------------------------- (2-9)
1 + H (z) ⋅ G(z) 1 + H (z) ⋅ G(z)

The signal transfer function, STF ( z ) , is

H (z)
STF ( z ) = ------------------------------------- (2-10)
1 + H (z) ⋅ G(z)

and the noise transfer function, NTF ( z ) , is

1
NTF ( z ) = ------------------------------------- (2-11)
1 + H (z) ⋅ G(z)
The signal should be lowpass (or allpass) filtered and the noise highpass filtered. This
states the requirements on the filters H ( z ) and G ( z ) , and the order of the modulator is
determined by the filter orders.
Assume that we want the STF to be described by a delay only, hence an allpass filter

STF ( z ) = z –1 (2-12)
and for the first order modulator the NTF is described by the highpass filter

NTF ( z ) = ( 1 – z –1 ) (2-13)

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

Using the equations (2-10) through (2-13) the filters become

z –1
G ( z ) = 1 and H ( z ) = ---------------
- (2-14)
1 – z –1
For the second order modulator the NTF is

NTF ( z ) = ( 1 – z –1 ) 2 (2-15)
Using (2-12) and (2-15) in (2-10) and (2-11), the filters are set to

z –1
G ( z ) = 2 – z –1 and H ( z ) = ----------------------
- (2-16)
( 1 – z –1 ) 2
In Fig. 2-8 the NTFs for the first and second order modulator are shown. The second
order modulator (dotted line) shows a better noise attenuation at lower frequencies than
the first order modulator (solid line).

1st and 2nd order NTF. Signal Feedback.

−5
|NTF(z)|2 [dB]

−10

−15

−20

−25

−30

−35
0 0.1 0.2 0.3 0.4 0.5
Normalized Frequency
Figure 2-8: NTF of a first order (solid line) and second order (dotted line) modulator.

The NTF for the second order modulator (when neglecting the sinc weighting from sam-
ple-and-hold elements) is

f 2
 – j ⋅ 2π -----------
NTF ( f ) = ( 1 – z –1 ) 2 j ⋅ 2π ⋅ ( f ⁄ f OSR ) = 1 – e f OSR
 =
z=e  
f
– j ⋅ 2π -----------
⋅ sin2  π ------------
f
= –4 ⋅ e f OSR
(2-17)
 f OSR

and its PSD is given by

NTF ( f ) 2 = 16 ⋅ sin4  π ------------ ≈ 2π ⋅ ------------

f f 4
(2-18)
 f OSR f OSR

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 2. Oversampling DAC Structures

where it is assumed that the OSR is high. Within the interesting frequency range, f N , the
noise power can be calculated by using the NTF and the known, original, quantization
noise error PSD
2
A ref
1
S q ( f ) = ------------ ⋅ ---------- (2-19)
f OSR 12

where A ref is the reference step value. The total power of the shaped noise within the
Nyquist band is found by combining (2-18) and (2-19)
fN fN

P noise = ∫ S q2 ( f ) ⋅ NTF ( f ) 2 d f = S q2 ( f ) ⋅ ∫ NTF ( f ) 2 d f =

–fN –fN
2 f N5
1 A ref 1 4 2 ( 2π ) 4 1
= ------------ ⋅ ---------- ⋅ ------- ⋅ 2π ⋅ ------------ = ------ ⋅ A ref
2 ⋅ -------------
5
- ⋅ -------------5- (2-20)
f OSR 12 5 f OSR 60 2 OSR

where
f OSR = OSR ⋅ 2 f N (2-21)

The signal’s normalized power is

1
P signal = --- ⋅ 2 2N – 2 ⋅ A ref
2 (2-22)
2
which gives the SNR as the ratio of the signal power (2-22) and the noise power (2-20)

 1--- ⋅ 2 2N – 2 ⋅ A 2 
P 2 ref 
SNR = 10 log  ---------------- = 10 log  ---------------------------------------
signal
- =
 P noise   A 2 ⋅ ----- π4 1 
 ref 60- ⋅ ------------- OSR 5
-

= 10 log  --- ⋅ 2 2N ⋅ -----4 ⋅ OSR 5 ≈ 6.02N + 1.76 – 12.90 + 50 log OSR

3 5
(2-23)
2 π 

From (2-23) it is seen that for each doubling of the OSR, the SNR is improved by 15dB,
corresponding to 2.5 bits. The improvement is approximately given by M + 0.5 bits for
each doubling of the OSR [56]. M is the order of the modulator. For the single-bit mod-
ulator the linearity is also guaranteed since a single-bit DAC is used at the output [37].

2.2.2 Error Feedback Modulator

The error feedback modulator uses the quantization error to feed back [37], as shown in
Fig. 2-9. The quantization error, q ( nT ) = y ( nT ) – w ( nT ) , is given by the LSBs of the
input signal to the quantizer, w ( nT ) , and the output signal y ( n ) is the MSB of w ( nT ) .
In the frequency domain, the quantization error signal is
Q(z) = Y (z) – W (z) (2-24)
and

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

W (z) = H (z) ⋅ [ X (z) – G(z) ⋅ Q(z)] (2-25)

which gives

Y (z) = H (z) ⋅ X (z) + [1 – H (z) ⋅ G(z)] ⋅ Q(z) (2-26)

x(nT) + w(nT) y(nT)

H(z)
-

-
+
G(z) q(nT)
Figure 2-9: Basic principle of an error feedback modulator.

The signal transfer function, STF ( z ) , is

STF ( z ) = H ( z ) (2-27)

and the noise transfer function, NTF ( z ) , is

NTF ( z ) = 1 – H ( z ) ⋅ G ( z ) (2-28)
Since the signal should be lowpass or highpass filtered and the noise should be highpass
filtered, the requirements on the filters H ( z ) and G ( z ) are set. Assume that the STF is
described by a unity function

STF ( z ) = H ( z ) = 1 (2-29)
For the first order modulator the NTF is described by

NTF ( z ) = ( 1 – z –1 ) (2-30)
and by using (2-29) in (2-28) with (2-30) we have

G ( z ) = z –1 (2-31)
For the second order modulator the NTF is

NTF ( z ) = ( 1 – z –1 ) 2 (2-32)
and therefore

G ( z ) = z –1 ( 2 – z –1 ) (2-33)
The feedback filters have practically the same structure as those for the signal feedback
configuration and the gain in SNR as function of the OSR is also the same.

2.2.3 Higher-Order Signal Feedback Modulators

For single-bit modulators the loop gain is high and for higher order modulators the sta-
bility has to be carefully investigated [11, 56, 60]. In Fig. 2-10 a general structure of an
N -th order modulator is shown. The filters A ( z ) are given by discrete-time integrators
(accumulators) as

90
 2. Oversampling DAC Structures

z –1
A ( z ) = ---------------
- (2-34)
1 – z –1

The coefficients a i and b i determine the NTF and STF.

aN/2 a1

x(nT) + - y(nT)
A(z) A(z) A(z)
- - -
bN bN-1 b1

Figure 2-10: General structure of a higher order modulator using signal feedback structure.

For a fourth order modulator the STF is given by

A4
STF ( z ) = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ (2-35)
1 + b1 A + ( a1 + a2 + b2 ) A + ( a2 b1 + b3 ) A 3 + ( a1 a2 + a2 b2 + b4 ) A 4
2

and the NTF is given by

( 1 + a1 A 2 ) ( 1 + a2 A 2 )
NTF ( z ) = -------------------------------------------------------------------------------------------------------------------------------
----------------------------------------- (2-36)
1 + b1 A + ( a1 + a2 + b2 ) A 2 + ( a2 b1 + b3 ) A 3 + ( a1 a2 + a2 b2 + b4 ) A 4

where A = A ( z ) is the filter given by (2-34). The zeros of the NTF in (2-36) are

z 1, 2 = 1 ± j a 1 and z 3, 4 = 1 ± j a 2 (2-37)

and the a i :s are used to move the poles of the NTF to improve the stability. The poles are
given by complex expressions and the overall complexity of the synthesis of the filter
structures increases dramatically with increased modulator order. Simulation results of
stability issues are also discussed for the implemented fifth order modulator in Sec. 3.1.2.

2.3 Semi-Digital FIR Filter

For multi-bit modulators, the digital output signal is converted into an analog using a
DAC with a smaller resolution than the input signal to the whole OSDAC. As was dis-
cussed in Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications the
linearity is dependent on the reference currents in the DAC. For the single-bit modulators,
the output consists of only two levels and the DAC converting this signal can be consid-
ered to be completely linear since the two conversion levels determine a straight line and
therefore no DNL and INL errors can occur [37].
Let w ( nT ) be the output from the single-bit modulator. It can be considered to be a dis-
crete-time signal, i.e., pulse waves, and with a very good analog lowpass filter the noise
can be filtered out. This requires a high order analog filter which further increases the
complexity of the design. By using a semi-digital filter the modulator output signal,
w ( nT ) , can be filtered more or less digitally, and the requirements on the analog lowpass
filter are reduced. A semi-digital FIR filter structure is shown in Fig. 2-11, and its output

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

is given by

y ( nT ) = a 0 ⋅ w ( nT ) + a 1 ⋅ w ( nT – T ) + a K – 1 ⋅ w ( nT – ( K – 1 )T ) (2-38)

where K is the number of taps in the FIR filter and T = 1 ⁄ f s is the clock cycle time.
The coefficients are generated with analog components, for example current sources in a
current-steering version [45]. The output, y ( nT ) , is a pulse-shaped signal since in general
the multiplication by the coefficients is done with sample-and-hold elements. This will
generate images that have to be filtered out by the analog smoothing filter.

w(nT)
T T T

a0 a1 a2 aK-2 aK-1
y(nT)

Figure 2-11: K-tap FIR filter structure.

The number of coefficients in an FIR filter is inversely dependent on the width of the
transition band [36], as

1 1
K ∼ ------------ = --------------------------- (2-39)
∆ωT ωa T – ωc T

where ω c T is the normalized cut-off frequency of the passband and ω a T is the normal-
ized stopband frequency. If the coefficients are signal-independent, naturally no distortion
will be introduced, only the filter’s transfer function will change if there are matching er-
rors in the current sources. With an FIR filter a linear phase is guaranteed as well. Long
FIR filters naturally introduce a large delay through the shift register (Fig. 2-11).

2.4 Analog Smoothing Filter

The output of the semi-digital filter still contains images in the frequency domain due to
the sample-and-hold elements. With an analog continuous-time lowpass filter (CT LP),
Fig. 2-12, the images and noise at higher frequencies above the original wanted bandwidth
are attenuated.

FIR CT LP

Figure 2-12: Images and noise are attenuated using the continuous-time filter

In addition, in front of the continuous-time filter, also an additional discrete-time low-

pass filter (DT LP) can be used to attenuate the shaped noise, Fig. 2-13. For high-speed
telecommunication applications, it can however be hard to design a discrete-time filter
(switched-capacitor or switched-current) that meets the requirements.

92
 2. Oversampling DAC Structures

FIR DT LP CT LP

Figure 2-13: Images and noise are attenuated further by using a discrete-time filter (DT LP) between
the FIR filter and the continuous-time filter (CT LP).

Naturally, the structure of the filters (Butterworth, Cauer, etc.) and circuit-technique
(current-mode, voltage-mode, etc.) are dependent on the application and the specification.

Sinc weighting
FIR Filter

Analog LP

fN fOSR/2 fOSR
Figure 2-14: Filtering stages occurring in the OSDAC, illustrated in the frequency domain.

As is sketched in Fig. 2-14 there are actually three filtering functions occurring at the
back-end of the OSDAC; the semi-digital FIR filter, the sinc weighting of the output spec-
trum and the analog continuous-time lowpass filter. When determining the order of the
analog filter, these aspects should be considered. If the OSR is high, the influence of the
sinc weighting in the signal band is very low.

2.5 Trade-Off Discussion

As was mentioned previously, by choosing a good semi-digital filter the requirements on
the analog lowpass filter may be relaxed significantly. Further, with good interpolation
filters at the input, the requirements on the semi-digital filter may be relaxed, etc. A trade-
off; complexity versus area, etc., has to be done. The basic idea is sketched in Fig. 2-15.

Interpolation Modulator Semi-digital Analog LP

Filter Length Order Filter Length Filter Order

Figure 2-15: Trade-off discussion between parts of the OSDAC.

To find the suitable trade-off the different building blocks are modeled and simulated on
a higher-level and at least a local optimum solution may be found with the models used
[1]. The circuit implementation will not give the same result, but it will be close to the
local optimum found by behavioral-level modeling and simulation.
All the design issues can briefly be summarized for the different building blocks as
• Using higher order interpolation filter introduces
→ higher complexity, filter structures, filter orders, etc.
→ higher power consumption
→ decreased out-of-band noise (and attenuation of images)
→ relaxed requirements on the modulator

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

• Using higher order modulator introduces

→ higher complexity, careful stability considerations, etc.
→ higher power consumption
→ larger chip area
→ improved SNDR
• Using higher order semi-digital FIR filter introduces
→ larger chip area
→ larger delay through the filter
→ higher sensitivity to coefficient errors
→ larger glitches
→ improved SNDR
→ relaxed requirements on the analog continuous-time filter
• Using higher order continuous-time filter introduces
→ higher complexity
→ larger chip area
→ improved SNDR
All these issues have to be considered during the design, and one of the major problems
is to find a good cost function that should be minimized. It could for example be chip area,
power consumption, etc.

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 3. A CMOS Oversampling DAC for ADSL Applications

3 A CMOS Oversampling
DAC for ADSL Applications
In this chapter the design of a 14-bit 3V-5V CMOS OSDAC for ADSL applications is
presented. The work is done by J. J. Wikner (Linköping University), Y. Gao (ESDLab,
KTH), and N. Tan (GlobeSpan Semiconductor). The converter is fabricated in Ericsson’s
0.6µm CMOS process.
As a very important design issue, the simulation of the whole converter on higher level
will be discussed. We show the impact of different filter orders (interpolation, FIR and
analog), and how this applies to the ADSL standard.
In the following sections the building blocks of the OSDAC (Sec. 3.1), simulation results
(Sec. 3.2), and the chip implementation (Sec. 3.3) are presented. Finally, in Sec. 3.4, the
drawbacks and the possible improvements of the implementation are discussed.

3.1 Practical Design Considerations

The whole OSDAC was simulated in MatLab with models for the individual parts of the
converter, i.e., interpolation filter, modulator, FIR filter, and analog smoothing filter. We
present a short description of each component.

3.1.1 Interpolation Filters

Cascade accumulators, shown in Fig. 3-1, were used as interpolation filter. The transfer
function for the H 1 ( z ) filter is given by

z–1 J
H 1 ( z ) =  ----------- = ( 1 – z –1 ) J (3-1)
 z 

and the filter H 2 ( z ) is given by

1 J z –1  J
H 2 ( z ) =  ----------- =  ---------------
- (3-2)
 z – 1  1 – z –1

X(z) Y(z)
L z-1 z-1

z-1 H1(z) z-1 H2(z)

Figure 3-1: Interpolation filter structure used in the OSDAC.

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

The exponent J from (3-1) and (3-2) is set to J = 0, 1, 2 in the different versions. For
even higher J :s the stability cannot be guaranteed in the simulations due to the pole on
the unit circle at dc level. The total transfer function of the interpolation filter, H ip ( z ) ,
describes a lowpass filtering and is given by

z –1  J
H ip ( z ) = H 1 ( z L ) ⋅ H 2 ( z ) = ( 1 – z – L ) J ⋅  ---------------
- (3-3)
 1 – z –1

where L is the oversampling ratio and L = OSR . Using a series expansion, (3-3) can be
rewritten as

z –1  J
H ip ( z ) = ( 1 + z –1 + … + z –( L – 1 ) ) J ⋅ ( 1 – z –1 ) J ⋅  ---------------
- =
 1 – z –1
= ( z –1 + z –2 + … + z –L ) J (3-4)
and the poles in the expression are cancelled. The magnitude response of the filter func-
tion (3-4) with J = 1 is displayed in Fig. 3-2. The attenuation of the signal at f N (dashed
line) is approximately 3.9dB.

Interpolation Filter Frequency Response

40

30

20
Magnitude [dB]

10

−10

−20

−30
0 0.1 0.2 0.3 0.4 0.5
Normalized Frequency
Figure 3-2: Magnitude response of the interpolation filter as in (3-4) with J=1. The original Nyquist
bandwidth is indicated with the dashed line.

In the final version of the OSDAC chip, no interpolation filter was implemented.

3.1.2 Modulator
In the OSDAC single-bit, signal feedback modulators of the fourth and fifth order were
investigated. They are designed by Y. Gao (KTH), and a closer description of the design
of the fifth order modulator is presented in this section. The modulator’s structure is
shown in Fig. 3-3, it uses a 14-bit two’s complementary input at the frequency
f OSR = 1.104 ⋅ 64 ≈ 71 MHz.

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 3. A CMOS Oversampling DAC for ADSL Applications

There are seven coefficients, a i and b i , with their values given by

b 1 = 2 11 , b 2 = 2 10 , b 3 = 2 8 , b 4 = 2 5 , b 5 = 2 2 , a 1 = 2 –7 , a 2 = 2 –8

a2 a1

x(nT) - - y(nT)
+ - A(z) -
A(z)
-
A(z)
-
A(z)
-
A(z)
b5 b4 b3 b2 b1

Figure 3-3: Fifth order modulator structure.

The filters, A ( z ) , in Fig. 3-3, are discrete-time integrators with the transfer function

z –1 1
A ( z ) = ---------------
–
- = -----------
1
(3-5)
1–z z–1

The NTF is given by

( 1 + a1 A 2 ) ( 1 + a2 A 2 )
NTF ( z ) = -------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------- (3-6)
( 1 + a1 A ) ( 1 + a2 A ) ( 1 + b1 A ) + ( b2 + b3 A ) ( 1 + a2 A 2 ) A 2 + ( b4 + b5 A ) A 4
2 2

where A = A ( z ) from (3-5). From (2-37) the zeros of the NTF are

z 1, 2 = 1 ± j a 1 and z 3, 4 = 1 ± j a 2 (3-7)

Without a2 and a3
80

60

40

20

−20

−40

−60

−80 0 1 2 3 4 5
10 10 10 10 10 10
Figure 3-4: Output amplitude spectrum of the modulator’s output without the complex NTF zeros.
The input signal frequency is 431.25kHz and the sampling frequency is 70.66MHz.

The amplitude spectrum of the modulator’s output when applying a sinusoidal with sig-
nal frequency 431.25kHz is shown in Fig. 3-4. The SNDR is approximately 63dB.

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

With the a i parameters the SNDR is improved. The zeros further attenuate the noise
within the signal band and a sharper transition band is achieved. The simulation result
when applying a sinusoidal at a frequency of 431.25kHz is shown in Fig. 3-5 where the
SNDR is found to be approximately 79dB.
With a2 and a3
80

60

40

20

−20

−40

−60

−80 0 1 2 3 4 5
10 10 10 10 10 10
Figure 3-5: Output amplitude spectrum with the two complex pairs of NTF zeros. The input signal
frequency is 431.25kHz and the sampling frequency is 70.66MHz

The stability of the modulator was simulated using a root locus shown in Fig. 3-6. With
the locus the limits of the feedback values, b i , are found and especially the gain of the
feedback loop can be determined.

1.5

0.5

−0.5

−1

−1.5
−1.5 −1 −0.5 0 0.5 1 1.5
Figure 3-6: Root locus of the modulator when varying the feedback parameters.

The layout of the modulator is synthesized using COMPASS tools and is shown in Fig.

98
 3. A CMOS Oversampling DAC for ADSL Applications

3-7. The core size is approximately 1.2x0.8µm2.

Figure 3-7: Layout view of the fifth order modulator generated with COMPASS.

At a supply voltage of 3V and a clock frequency of approximately 71MHz, the power

dissipation of the core modulator is about 92mW. To save hardware and to reduce the
power dissipation the parameters have been scaled internally.

3.1.3 Semi-Digital FIR Filter

The FIR filter is of current-steering type [45, 63]. The principle is shown in Fig. 3-8,
where the single-bit output, w ( nT ) , from the modulator is fed into a shift register and the
contents of the shift register is used to control the current switches. For each switch a cur-
rent source with the weight a i ⋅ I unit is associated, where the a i :s are the coefficients of
the filter and I unit is a unit current size.

w(nT)
D D D

a0Iunit a1Iunit aK-1Iunit

y(nT)
Figure 3-8: Current-steering implementation of a semi-digital filter with coefficient length K.

The digital delay line or the shift register is constructed using dynamic CMOS gates [81]
with help from Magnus Karlsson (Linköping University). The D-latch (Fig. 3-9c) is
formed by using a P-gate and an N-gate as shown in Fig. 3-9a-b). The D-latch uses only

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 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

one single clock phase which simplifies the clock distribution. The outputs are comple-
mentary and hence suitable for controlling the differential current switches.

a) b) c)

Figure 3-9: Schematic of a) P-gate and b) N-gate, and c) D-latch formed by a P-gate and N-gate.

The latches are sensitive to the capacitive load on the outputs. A constant load is guar-
anteed by letting all current switches be equally large. The layout of the D-latch can be
made rather compact. In the design of the FIR filter the latches have been laid out (Fig. 3-
10) so that they are as wide as the current switches and the unit current source, hence a
regular layout is possible.

GND 1) VDD Q+ Q- GND

clk
D+ D- 2)
Figure 3-10: Layout view of a D-latch including the 1) P-gate and 2) N-gate.

The coefficients as shown in Fig. 3-8 are created by using a number of unit current
sources in parallel according to the same principle as in the design of the converters in
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications and the
matching issues apply in the same way. In this implementation single cascode PMOS
transistors are used. The layout of a unit current source is shown in Fig. 3-11. M1 and M2
are given by the sizes ( W ⁄ L ) 1 = 2 ⁄ 8 and ( W ⁄ L ) 2 = 2 ⁄ 2 [µm].

VDD M1 M2 Output

Gates
Figure 3-11: Layout view of a current source constructed by two PMOS transistors. M2 is the cascode.

100
 3. A CMOS Oversampling DAC for ADSL Applications

For the FIR filter, the cut-off frequency is approximately f c = 1.15 ⋅ f N ≈ 1.27 MHz
and the attenuation in the stopband is approximately 17dB. The FIR filter coefficients
have been generated with the Remez algorithm in MatLab. Since the original coefficients,
a i , have been amplified and truncated to integer values, ã i , there is no longer an equi-
ripple in the stopband. Proper values are found as
max a i
ã i = J ⋅ ------------------- + 0.5 ⋅ sgn { a i } (3-8)
min a i

where J is an amplification value which determines the size of the truncation error. In Fig.
3-12 the filter magnitude response for the original filter (219 taps) and the truncated ver-
sion is shown. The FIR filter in the implemented version of the OSDAC uses
• 2390 effective unit current sources in 219 nonzero taps
• 152 unit current sources in the largest tap
A large number of unit current sources in the taps increases the accuracy, since J is
larger, but it also generates a higher current which makes the design of current switches,
wires, supply, etc., harder.

FIR Filter Amplitude Characteristics

80
Increased ripple in passband
60

40
Increased
Power [dB]

attenuation
20 in stopband

−20

−40
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency 7
x 10
Figure 3-12: 219 tap FIR filter magnitude response. Characteristics with and without truncated filter
coefficients are shown.

The switches are differential and therefore also negative filter coefficients can be real-
ized. For a current source corresponding to a negative coefficient the outputs of the dif-
ferential switch is simply cross-connected to the OSDAC outputs, as shown in Fig. 3-13.
All current switches in the OSDAC are equally large with eight NMOS transistors in par-
allel for each channel. This also ensures equal load for all D-latches. The layout of one of
the switches is shown in Fig. 3-14. NMOS transistors are used since they have higher
transconductance parameter (higher mobility).

101
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

I0 = a0 I unit VDD I1 = a1 I unit IM = aM I unit

φ0 φ0 φ1 φ1 φM φM

I+
I-
a0: Positive a1: Negative aM: Negative
Coefficient Coefficient Coefficient
Figure 3-13: Differential current switches in the FIR filter. Negative coefficients are realized by cross
connecting the outputs.

The on-resistance of the switches is given by the eight transistors in parallel

G ON ≈ 8β ⋅ ( V φ – V T – V C ) (3-9)

where β is the transconductance parameter for one single NMOS transistor. V φ is the
gate or switch voltage on the transistors, V C is the output node of the current sources and
V T is the threshold voltage of the transistors. Since the output node is varying with the
signal, the source-bulk voltage, V SB , varies as well. This forces the threshold voltage to
be slightly non-linear.

φ I+

Ii

Shielding I-
φ
Ground

Figure 3-14: Layout view of differential current switch used in FIR filter.

The average output current, I out , of the FIR filter is given when the input is alternating
between “0” and “1” with a 50% duty cycle, as

I out = I unit ⋅  ∑ ai – ∑ a i ≈ 1318I unit (3-10)

 
a i odd a i even

hence the average power for one channel (standby for a zero input in two’s complement)
over a 50Ω load is given by
6
P out = I out 2 ⋅ 50 = 86.86 ×10 ⋅ I unit
2 (3-11)

102
 3. A CMOS Oversampling DAC for ADSL Applications

The output current of the unit current source is dependent on the reference current. For
the case with I unit ≈ 1.65µA we have from (3-10) and (3-11)

I out = 2.2 mA and P out ≈ 0.25 mW (3-12)

The impulse response of the semi-digital FIR filter from a circuit-level simulation is
shown in Fig. 3-15. The output current of the unit current source is approximately
I unit ≈ 1.65µA and the output is doubly terminated with 50Ω. Since the start-up phase of
the simulation was too long, the figure only displays 172 of 219 values.

Semi−digital filter impulse response

4.45

4.4

4.35
Differential output current [mA]

4.3

4.25

4.2

4.15

4.1

4.05

3.95
0 200 400 600 800 1000 1200
Time [us]
Figure 3-15: Impulse response from a circuit-level simulation of the semi-digital FIR filter.

Since the currents originally were to be terminated with an operational amplifier (input
stage to the analog smoothing filter) with low input impedance, the total output imped-
ance of the FIR filter has not been investigated. The analysis is however similar to the case
with the binary weighted sources in the Nyquist-rate converters.

3.1.4 Analog Smoothing Filter

As analog smoothing filter at the output a Butterworth LP filter or Chebyshev 2 LP filter
is used since the ripple in the passband should be kept as small as possible. The first order
LP filter is simply constructed by using an operational amplifier with R and C compo-
nents, see Fig. 3-16. It is also wanted to use the circuit as an I/V converter. The output
voltage is given by
R
V out ( s ) = I in ( s ) ⋅ -------------------- (3-13)
1 + sRC
where
V out ( s ) = V +out ( s ) – V -out ( s ) and I in ( s ) = I +in ( s ) – I -in ( s ) (3-14)

103
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

I-in R
V+out
I+out

I-out
I+in V-out
R

C
Figure 3-16: First order differential lowpass filter.

From the ADSL specification the cut-off frequency is given and therefore

1 –9
RC = -----------------------------------6- ≈ 144 ×10 (3-15)
2π ⋅ 1.104 ×10

We also know that the dc voltage drop over the resistance, R , can not be too large for
low voltage applications. With an input dc current, I dc , of 2.2mA and a maximum voltage
drop of V drop, max = 1 V, we have that

–3
I dc ⋅ R < V drop, max or R < 1 ⁄ 2.2 ×10 ≈ 455Ω (3-16)

This gives heuristically the size of the capacitance, C , to

–9
C = 144 ×10 ⁄ 455 ≈ 317 pF (3-17)

which is far too large to implement on chip since the area would be approximately 1mm2
with today’s CMOS technology. Another filter structure, where the circuit is not used as
an I/V converter, could be used as on-chip filter (see Sec. 3.4). However, no on-chip an-
alog filter was implemented in the fabricated OSDAC chip.

3.2 Simulation Results

Simulation results with different configurations are presented in this section. These dem-
onstrate how the trade-off between different parts affects the result. The simulation results
are given in Fig. 3-17 through Fig. 3-21, showing the output spectrum of the OSDAC for
the following configurations:
• 219 tap FIR filter, no interpolation filters, no LP filter, (Fig. 3-17)
• 219 tap FIR filter, second order interpolation filter, no LP filter, (Fig. 3-18)
• 219 tap FIR filter, second order interpolation filter, first order LP filter, (Fig. 3-19)
• 219 tap FIR filter, second order interpolation filter, third order LP filter, (Fig. 3-20)
• 324 tap FIR filter, second order interpolation filter, third order LP filter, (Fig. 3-21)
In all simulations a fifth order modulator is used and the oversampling ratio is OSR=32.
The number of carriers of the DMT input is only 210. The carriers are distributed over the
frequency range from 86kHz to 992kHz with an equi-distance of 4.3125kHz. Ideal con-
ditions allow 249 carriers according to the ADSL standard [83]. The cut-off frequencies

104
 3. A CMOS Oversampling DAC for ADSL Applications

of the filters are slightly above 1.104 MHz. The ripple in the passband is mainly deter-
mined by the FIR filter and the round-off errors of the coefficient truncation. The interpo-
lation filters are sinc filters as shown in Sec. 3.1.1. The analog filters are Butterworth
filters as in Sec. 3.1.4. In Fig. 3-17 we see that the images from 1.104MHz to 2.208MHz
are very large and that the noise is not attenuated as much as wanted. The ripple in the
passband of the 210 carriers are around the specified level (-36.5dB).
ADSL Specifications
−20 Images
within
New ADSL fN and 2*fN.
Specification −40

−60
Noise and
distortion
components.
PSD

−80

−100
210 carriers
−120

−140 3 4 5 6 7
10 10 10 10 10
Frequency
Figure 3-17: Output spectrum without interpolation and analog filters.

By using a second order interpolation filter the images are slightly attenuated as shown
in Fig. 3-18. The noise is not affected since it origins in the modulator. The attenuation of
the noise by the FIR filter is not large enough. It is also seen that the interpolation filters
cause a quite large attenuation near the passband edge. The FIR could be designed to can-
cel this effect by having a higher gain near the passband edge.

ADSL Specifications
−20
Drop, due to
interpolation
−40 filter.

−60
PSD

−80

−100

−120

−140 3 4 5 6 7
10 10 10 10 10
Frequency
Figure 3-18: Output spectrum with a second order interpolation filter and without analog filter.

105
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

By using the first order analog smoothing filter (Fig. 3-19) the noise is attenuated and
the images are slightly attenuated. We see an even larger attenuation of the high frequency
carriers within the passband, due to the too low cut-off frequency in the analog filter.

ADSL Specifications
−20

−40

−60
PSD

−80

−100

−120

−140 3 4 5 6 7
10 10 10 10 10
Frequency
Figure 3-19: Output spectrum with second order interpolation filter and a first order analog filter.

With a third order analog filter (Fig. 3-20) the specification is still not met, the noise is
almost attenuated to the specified level (-90dB).

ADSL Specifications
−20

−40

−60
PSD

−80

−100

−120

−140 3 4 5 6 7
10 10 10 10 10
Frequency
Figure 3-20: Output spectrum with a second order interpolation filter and third order analog filter.

By increasing the FIR filter length to 324 taps the attenuation in the stopband is
increased, hence the noise is attenuated as seen in Fig. 3-21. The specification is however
still not met. There are hard requirements and the design of the filters has to be carefully
done.

106
 3. A CMOS Oversampling DAC for ADSL Applications

ADSL Specifications
−20

−40

−60
PSD

−80

−100

−120

−140 3 4 5 6 7
10 10 10 10 10
Frequency
Figure 3-21: Output spectrum with a 324 tap FIR filter, second order interpolation filter, and a third
order analog filter.

It should be noted that the simulation results presented in the figures above are compared
with a newer ADSL standard and the fabricated OSDAC has been designed to meet the
specification of an older ADSL standard. As was discussed in Part A: Overview: Digital-
to-Analog Converter Design, the newer ADSL standard sets much tougher requirements
on the attenuation of higher frequency components and especially the frequency range
from 1.104MHz to 2.208MHz.
It is easy to understand the complexity of the choices that have to be taken when choos-
ing the filter and modulator orders.

3.3 Chip Implementation

The final chip implementation includes (on-chip)
• A fifth order modulator
• A 219 tap FIR filter
During measurements, the effect of the interpolation filters will be generated with the
test vector generator and as output analog filter a standard filter from a vendor can be
used. The layout view of the chips is shown in Fig. 3-22.
The design is similar to the implementation of the Nyquist-rate converters. A VDD plane
coves the current sources has been used to decrease the influence of the voltage drops
along supply lines [38]. For each coefficient one row of current sources has been assigned.
Unused current sources are shorted by VDD. A shielding layer between the analog current
sources and the digital delay line has been used as well. The chip is designed to have sup-
ply voltages from 3V to 5V.
The chip also contains a number of decoupling capacitors to stabilize the supply voltage
on chip, reducing the influence of parasitic inductance and resistance in the bond wires.
The modulator has been incorporated in the Cadence design via gdsII format from the
COMPASS design tool.

107
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

FIR Filter

Analog I/O
Digital I/O
Modulator

Decoupling
Capacitors

Figure 3-22: Layout view of the whole OSDAC with modulator and FIR filter included.

3.4 Improvements of OSDAC Design

The simulation results show that the implementation does not meet the requirements of
the newer ADSL standard. Some general improvements can be done by using
• on-chip interpolation filters, perhaps FIR filters with around 20 taps.
• more suitable design of semi-digital FIR filter, reducing the number of taps.
• on-chip analog filter, needing technique to remove the dc current from the output
without introducing too much distortion.
We will briefly discuss the influence of changing the structure of the FIR filter and the
analog LP filter. The specification on the SNDR is met with the fifth order modulator.
Some techniques for adaptive modulation [18] can be used to improve the performance,
however, for higher order modulators the complexity of these techniques increases.

3.4.1 Interpolated FIR Filter

The use of an interpolated FIR (IFIR) filter may be advantageous since the width of the
transition band, ∆ωT = ω s T – ω c T , can be made larger and therefore the number of
non-zero taps can be reduced (2-39), hence less current sources, chip area, etc.

108
 3. A CMOS Oversampling DAC for ADSL Applications

Assume that the original FIR filter, H 0 ( z ) , has the following specification (2-39)

ω c T ≈ 2π ⋅ 1.15 ⋅ f N ⁄ f s = 2.30π ⋅ OSR and

ω s T ≈ 2π ⋅ 1.47 ⋅ f N ⁄ f s = 2.94π ⋅ OSR (3-18)

With an attenuation in the stopband of approximately 17dB the number of taps is 219
(Sec. 3.1.3). Using an IFIR filter, H 1 ( z 2 ) , with ω c T ≈ 2.30 f N and ω s T ≈ 2.94 f N . With
the same attenuation in the stopband, the number of taps is around 109 (from Remez’
algorithm in MatLab). In Fig. 3-23 this is illustrated with a filter interpolated at an order
of eight, H 2 ( z 8 ) . The behavior within the passband is the same for both filters. The pass-
band of the IFIR filter is repeated over the frequency range and the shaped noise from the
modulator will not be filtered out. Therefore, the attenuation of the analog filter at the out-
put must be higher to remove these components and the transition band must be sharper
as well. Not that the order of interpolation may not be too large, since the design of the
following filters will be too hard.
Magnitude Response of FIR and IFIR filter
10

−10
Magnitude [dB]

−20

−30

−40

−50

−60
0 5 10 15 20 25 30 35
Frequency [MHz]
Figure 3-23: IFIR filter (interpolation order = 8) vs. FIR filter. The behavior within the passband is the
same for both filters. The IFIR filter has an offset of 5dB to illustrate the function.

It can be seen from simulation results that the order of the analog filter (to still meet the
ADSL specifications) is approximately proportional to the interpolation ratio in the IFIR
filter. In Table 3-1 the approximate filter orders are summarized. As analog filter, a But-
terworth filter is used. It is seen that the specifications on the analog filter may become
much tougher. It should also be noted that the delay through the IFIR filter still is the same
as for the original FIR filter.
The noise transfer function of the modulator could also be designed to have less noise
within the passband images that arise due to the interpolation [41].

109
 Part C: Oversampling Digital-to-Analog Converters for ADSL Applications

Interpolation Number of Analog Filter

Ratio Taps Order
1 219 3
2 110 4
4 55 5
8 28 7
16 14 8
Table 3-1: Analog filter order vs. the interpolation ratio of the IFIR filter.

To further simplify the design of the analog filter, the dc currents from the outputs of the
FIR filter can be removed by using current sinks implemented with NMOS transistors,
Fig. 3-24. The ac currents are fed into the analog LP filter. As was discussed in Sec. 3.1.4
the dc voltage drop over the resistance (Fig. 3-16) now can be removed and the resistance
can be chosen to be larger, hence the capacitance can be made smaller (3-15) and a chip
implementation may be possible.

Semi-digital FIR
Ipos Ineg Ipos,ac
LP
Ineg,ac

IDC IDC

Figure 3-24: Removing the dc current from the FIR filter output relaxes the complexity of the design
of the analog LP filter.

As was briefly mentioned an additional switched-current (SI) filter could also be used to
filter the signal [45, 71]. A frequency masking technique using an FIR filter and SI filter
(which is discrete-time) would relax the specifications on the analog filter as well.
In the trade-off discussion it was also mentioned that the complexity and power con-
sumption will increase with an interpolation filter and on-chip analog filter. This must
also be considered when changing the structure of the OSDAC.

110
 Conclusions

This thesis should be considered as an introduction to the design of digital-to-analog

converters, and especially CMOS DACs for telecommunication applications. Part A:
Overview: Digital-to-Analog Converter Design is a tutorial and elementary section. In
Part B: Nyquist-Rate Digital-to-Analog Converters for VDSL Applications and Part C:
Oversampling Digital-to-Analog Converters for ADSL Applications, both a Nyquist-rate
converter chipset suitable for wideband radio and VDSL applications and an oversam-
pling converter for ADSL applications have been implemented and presented.
The Nyquist-rate converters have been measured and conclusions about the implemen-
tation and possible improvements have been presented. We have seen that the matching
errors are dominating other error sources. The converters have an approximate SFDR of
44dB at a clock frequency of 50MHz and a signal frequency of approximately 8.2MHz.
This corresponds to roughly 7-8 bits of linearity. It could be compared with Analog
Devices’ TxDAC series, which shows an SFDR of approximately 63dB (10-11 bits) with
the same measurement configuration.
We have also briefly discussed how to improve the performance of high-speed convert-
ers by using feedback structures, digital correction, and randomization techniques. Some
of the ideas are also found in the literature, but implementations with good measured per-
formance are not yet published. By making some changes to the DACs presented in this
thesis, for example another current source assignment, their performance may be
increased significantly. The measurement results from the third generation Nyquist-rate
DAC has not been included in this thesis. We believe however, that the performance is
increased in this version, compared with the second generation.
One version of the Nyquist-rate DACs has also been successfully implemented with a
line driver designed by J. Erlands (Linköping University) and N. Tan (GlobeSpan Semi-
conductor) to illustrate a back-end of a line transmitter for xDSL [19].
A chapter showing the contributions to modeling of the performance of current-steering
CMOS Nyquist-rate converters is included. We have shown the impact of circuit irregu-
larities of the DAC on the frequency domain measures. From these results we have a
guide on how to design the circuit. This modeling can be extended to further cover
dynamic properties of converters.

111
 Conclusions

Measurement results from the oversampling converter have not been presented and
therefore some conclusions of the implementation are missing. The same issue with
matching of current sources can be applied to this converter as well, since the FIR filter
was implemented with unit current sources. Here, we have discussed some techniques to
further improve the performance to meet the specifications of the newer ADSL standards.
We have discussed the important issues of simulating and measuring circuits. It is found
that small errors in test vectors may generate large errors in the output signal of the con-
verter. From this we conclude that it is important to have good input data to trust the out-
put signal as well as be able to make the correct conclusions from this.
In general, we have pointed out the behavioral-level simulations as a very useful and
important stage of the design. It is important that the designer is aware of all stages of the
development of the chip. By using good and simple models, it is possible to find funda-
mental limits on the performance and therefore also be able to focus on improving the
components that are bottlenecks in the systems. These higher-level simulation has espe-
cially been used during the design of the oversampling converter, where extensive Mat-
Lab models have been developed.

112
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6
 Licentiate Theses
Division of Electronics Systems
Department of Electrical Engineering
Linköpings universitet
Sweden

Andersson K.-G.: Implementation and Modeling of Modular Digital Signal

Processors, Linköping Studies in Science and Technology, Thesis No. 608, 1997

Melander J.: Design of SIC FFT Architectures, Linköping Studies in Science and
Technology, Thesis No. 618, 1997.

Widhe T.: Efficient Implementation of FFT Processing Elements, Linköping

Studies in Science and Technology, Thesis No. 619, 1997.

Johansson H.: High-Speed Recursive Digital Filters, Linköping Studies in Science

and Technology, Thesis No. 620, 1997

Karlsson Rudberg M.: System Design of Image Decoder Hardware, Linköping

Studies in Science and Technology, Thesis No. 657, 1997.

Gustavsson M.: Analog Interfaces in a Digital CMOS Process, Linköping Studies

in Science and Technology, Thesis No. 662, 1997.

Karlsson M.: Distributed Arithmetic: Design and Applications, Linköping Studies

in Science and Technology, Thesis No. 696, 1998.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 159

Mismatch and Dynamic Modeling of Current Sources

in Current-Steering CMOS D/A Converters:
An Extended Design Procedure
Miquel Albiol, José Luis González, Member, IEEE, and Eduard Alarcón, Member, IEEE

Abstract—This paper presents an improved modeling of the ef-

fect of random mismatch and current source transient switching
behavior on the performance of current-steering CMOS digital-to-
analog converters (DACs). The work considers two current source
cell topologies, namely a simple cell and a cascoded cell, obtaining
the relation of transistors design parameters to the static and dy-
namic models. On the one hand, a mismatching statistical anal-
ysis is applied to all the transistors of the current source circuit,
which allows to define design expressions relating the circuit pa-
rameters to the DAC specifications without the need of arbitrary
design margins or Monte Carlo simulations. On the other hand,
improved analysis of the current source switching characteristics
provides a more realistic modeling of the relation between transis-
tors sizes and output current settling time. By including these two
improved models into the usual design procedure, circuit sizing for
optimum settling time and proper static behavior can be obtained
Fig. 1. Current-steering DAC architecture.
analytically, reverting in smaller current source area, and, hence,
in an overall DAC area reduction.
Index Terms—CMOS integrated circuits, current-steering tioned requirements. Fig. 1 shows a typical block diagram of an
D/A converters, digital–analog conversion, matching, mixed -bit current-steering DAC. The input word is segmented into
analog–digital integrated circuits, transient analysis. the least significant bits (LSBs) that switch a binary weighted
array and the most significant bits (MSBs) that con-
I. INTRODUCTION trol the switching of a unary current source array. The input
bits are thermometer decoded to individually switch each of the

M ODERN broad-band communication integrated circuits

require as fundamental subcircuits digital-to-analog
converters (DACs) exhibiting both high speed and high reso-
lution [1]. Wide bit-count DACs working at sampling clock
frequencies in the range of hundreds of megahertz will continue
to be required, hence dictating Nyquist-rate data conversion, as
for instance to convert digital bitstreams into continuous-time
signals prior to up-conversion mixers preceding RF transmitters
in wireless systems or to drive digital cable communications
modems. The development of future mobile communication
systems (including both third–generation (3G) terminals
and basestations) as well as the prospective use of ubiqui-
tous communication systems will continue the trust toward
high-performance DAC conversion stages.
A CMOS current-steering DAC is the usual choice for this
type of application since that topology best suits the aforemen-
Manuscript received January 31, 2003; revised September 30, 2003. This
work was supported in part by the Spanish MCYT and EU FEDER program
under Project TIC2001-2337 and Project TIC2001-2157-C02-01. This paper
was recommended by Guest Editors A. Rodríguez-Vázquez, F. Mediero, and
O. Feely.
The authors are with the Electronic Engineering Department, Polytechnic
University of Catalunya (UPC), Barcelona 08034, Spain (e-mail: jlgon-
zalez@eel.upc.es).
Digital Object Identifier 10.1109/TCSI.2003.821287
1057-7122/04$20.00 © 2004 IEEE
unary sources. A dummy decoder is placed in the binary
weighted input path to equalize the delay. A latch is placed just
before the switch transistors of each current source to minimize
timing errors. Latches and switches are grouped in a separated
array placed between the decoders and the current source arrays
in order to isolate these noisy digital circuits from the sensitive
analog circuits that generate precise currents.
Since all current sources have the same circuit topology, only
the sizes of their transistors are scaled from a basic current
cell circuit (usually the LSB current source) according to their
weights. Fig. 2 shows the two most usual topologies for the cur-
rent source cell circuit. The basic circuit includes the current
source transistor CS and two complementary switch transistors
(SW and ), as shown in Fig. 2(a). Some cases require an ad-
ditional cascode transistor (CAS) in series with the CS transistor
to increase the cell output impedance and improve node isola-
tion, as shown in Fig. 2(b). Bias voltages for transistors CS and
CAS are common to all current sources. Complementary con-
trol signals for SW transistors of both current sources are gener-
ated by the corresponding latch and output driver circuits. The
HIGH level of these signals is adjusted in such a way that the SW
transistor in the ON state is actually operating as a first cascode
transistor. If the CAS transistor is used, it operates as a second
cascode transistor that further increases the output impedance of
160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004

limited by the current sources settling time. Latches should also

be designed to be fast enough whilst their output driver should
be sized to generate the desired levels for the switches’ control
signals, which are determined during the current cell circuit de-
sign procedure. The timing of these control signals is also of
utmost relevance to minimize the glitches at the DAC output by
avoiding both complementary SW transistors to be switched OFF
simultaneously during the output transition [8]. Finally, special
layout techniques [4], [9] are applied to floorplan the different
DAC architecture components, especially the current source ar-
rays, so as to compensate for systematic mismatch errors and
isolate the sensitive analog section from the digital section.
This work focuses on the current cell design procedure. Two
main contributions are presented. The first one, presented in
Section II, is an extended modeling of random mismatch ef-
fects which considers statistical variations in all the transistors
of the current source circuit and studies how they impinge upon
the overall DAC static performance. The second contribution of
the work, presented in Section III, addresses the dynamic mod-
eling of current source switching transient behavior, extending
the previous work of [11]. The model presented in this sec-
tion allows us to properly describe the dynamic performance
of the DAC and calculate a realistic settling time. In Section IV,
those models are embedded within a complete design procedure
for the optimum sizing of the current source cell of high-speed
high-accuracy current-steering DACs. Finally, Section V pro-
vides the conclusions of the work.

Fig. 2. Current source cell topologies. (a) Basic unary current source. (b)
Cascoded unary current source.
II. STATIC PERFORMANCE
Static and dynamic performances of current-steering DACs
the current source. This impedance boosting is needed in order
are mostly determined by the current sources accuracy, nonin-
to fulfil requirements for high-resolution high-bandwidth cur-
finite output impedance, and switching time. In the following,
rent-steering DACs [2].
the dependencies of the DAC static performance on the cur-
DAC performance is specified both through static parameters, rent sources’ accuracy and output impedance constrained by the
namely integral nonlinearity (INL), differential nonlinearity transistors’ operating region are presented. Afterwards, the im-
(DNL), and parametric yield, as well as dynamic parameters, plications of those static and statistical constraints in the sizing
namely glitch energy, settling time, and spurious-free dynamic design procedure of the current cell circuit are presented and
range (SFDR) [3]. Static performance is mainly dominated compared with other previously published approaches.
by systematic and random mismatch errors. Systematic errors
caused by process, temperature, and electrical slow variation
gradients are almost cancelled by proper layout techniques [4]. A. Current Source Accuracy
Random errors are determined solely by random mismatch due The transistor CS of Fig. 2 sets the cell’s current. Based on the
to fast process variation gradients. statistical mismatch model of [12], a relation exists between the
The design of a DAC is carried out at three levels: architec- CS transistor area, its overdrive voltage, and its relative accuracy
ture design, circuit design, and physical design. In the usual de- (we will refer in the following to the LSB current source)
sign procedure, the degree of segmentation ( over ) is de-
cided at the architecture level by combining static and dynamic
specifications and overall minimum area requirements [5]–[7].
(1)
Subsequently, the basic current cell circuit (usually the LSB cur-
rent source) is designed by determining the sizes and bias volt-
ages for the different transistors and the voltage levels required where is the cell’s current, and are the CS
for the switches’ control signals. Most of the DAC static and transistor width and length, respectively, and are
dynamic performance is determined by the performance of the mismatch process constants for the transistor large signal gain
basic current source cell. The circuit design of the rest of the and threshold voltage, respectively, is the CS overdrive
components within the DAC architecture is mainly influenced voltage, i.e., , where is the CS gate-to-source
by speed requirements. The digital binary-to-thermometer de- voltage and is the threshold voltage, and is the
coder must be fast enough so that the converter speed is solely variance of the current source value due to random mismatch.
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 161

The aspect ratio of the CS transistors is determined by The drain-to-source impedance, considering channel length
the drain current and the overdrive voltage according to the modulation, is expressed by
MOSFET saturation drain current expression
with (7)
(2)
where is the channel length modulation parameter, the
drain-to-source saturation current, is a technology constant
The CS transistor dimensions are univocally determined once [14], is the drain-to-source voltage, and is the built-in
the overdrive voltage is chosen and vice versa, according to (1) junction potential, which is also a technology constant.
and (2). The INL of a set of theoretically equal manufactured Combining (4), (5), and (7) and expressing the
DACs is a statistical process that depends on process variations. drain-to-source voltages as function of node voltages (SW and
Systematic mismatch is addressed at the physical design phase. CAS gate bias voltage, and the output node minimum voltage
If only random mismatch is considered, the worst case INL, free , which is the worst case for output impedance) yields
of offset and gain errors, is found at the mid code in the DAC
static transfer function. In this case, the INL error for an -bit
DAC is due to the combination of LSB current sources
(independently of the DAC segmentation1 ). The LSB current
source minimum relative accuracy required to achieve a certain
INL upper bound with a given statistical yield, as a function of (8)
the DAC resolution, is [10], [13]
for the topology and
(3)

where is the inverse cumulative normal distribution,

and is the percentage of manufactured DACs with an INL
smaller or equal than the upper bound .
(9)
B. Current Source Output Impedance
The small-signal output impedance for the for the topology.
current source topology of Fig. 2(a) is given by The optimum SW and CAS gate bias voltages concerning the
output impedance are found by differentiating (8) and (9) with
(4) respect to and . For the topology, the SW
gate bias voltage that maximizes output impedance is found as
where is the small-signal transconductance and
is the drain-to-source small-signal resistance. The labels (10)
are used here and in the rest of the paper
as accompanying subscripts or superscripts to indicate the tran- whereas for the topology the SW and CAS
sistor to which the parameters, voltages, or other expressions gate bias voltages that maximize output impedance are
refer.
For the topology of Fig. 2(b), the output
impedance is given by

(5) (11)

Since the drain current is a value fixed by the DAC spec- C. Analysis of the Current Source Circuit Transistors
ifications, the only degree of freedom available to design the Operating Region
transconductances is either the overdrive voltage or the aspect
ratio Despite the fact that the overdrive voltage in (1) should
be maximized to minimize the CS area, it should be small
enough to allow the other transistors (SW and CAS if present)
(6) to work in saturation (the region in which higher output
impedance is obtained) in any situation.
1This is due to the fact that a source of value k LSBs is actually obtained by
1) Simple Current Cell : Applying the MOSFET
combining k sources of LSB value in parallel, instead of a single source with saturation condition to all transistors
transistors k times wider than the LSB source transistors. in the current source of Fig. 2(a) leads to the definition of a
162 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
voltage range in which the SW gate bias voltage must be kept in
order to allow both CS and SW transistors to work in saturation
(12)
A solution exists for (12) if and only if the difference between
the upper and lower bounds is positive (i.e., the lower bound for
the SW gate voltage is smaller than the upper bound
. This determines an upper bound for the addition of the
two transistors’ overdrive voltages
(13)
Resuming the saturation constraint of (12), note that the mid-
point between the upper and lower bounds for the SW gate bias
voltage corresponds to the optimum voltage that maximizes the
dc output impedance found in Section II-B
(14)
This is not a coincidence, since this optimum SW gate voltage
places the operating point of both SW and CS transistors at the
same voltage distance from the triode region.
If there are no other criteria for choosing the overdrive volt-
ages, such as dynamic output impedance, settling time, etc., it
would be interesting to choose the combination of overdrive
voltages that leads to the minimum area solution. This usu-
ally corresponds to an SW transistor with minimum length and
width, from which the SW overdrive voltage is derived, and the
maximum CS overdrive voltage that verifies (13), provided that
the corresponding CS transistor width and length obtained from
(1) and (2) satisfy the technology minimum size constraint. By
doing this, the operating points of both transistors are found just
at the limit between the triode and the saturation regions.
In the previously published current source sizing procedure
[10], which is representative of the usual design process for this
type of DAC, only the mismatch error of the current source tran-
sistor is considered. Hence, an arbitrary safety margin is
introduced as follows in the saturation constraint (13) to prevent
the transistors to enter triode region due to process variations:
(15)
If not only the mismatch errors of the CS transistor, but also
the switches and additional cascode transistors mismatch errors
are taken into account, the overall basic current cell circuit can
be optimized without introducing that arbitrary safety margin.
Alternatively, this safety margin can be found by performing
parametric Monte Carlo simulations. The model that will be pre-
sented in the following avoids either the arbitrary design margin
or the time-consuming Monte Carlo simulations.
In order to include the effects of process variations in the
saturation condition of (12), the statistical variation of the two
bounds for the SW gate bias voltage is modeled by means of a
normal distribution. The variance of the upper and lower bounds
is found, first by expressing these bounds as a function of the
random variables of the circuit that appear when mismatching
effects are taking into account:
(16)
and subsequently by calculating the partial derivatives of these
expressions with respect to each one of the random variables
(that are considered independent). In this way, the variance of
the upper bound for the SW gate voltage that guarantees satu-
ration when random mismatch effects are taken into account is
found as
(17)
Similarly, the variance of the lower bound yields
(18)
In (17) and (18), only node voltages (except biasing gate volt-
ages), current values, and load impedance have been considered
as being random variables affected by mismatching. In order to
take into account also die-to-die process variations, the worst
case process parameter values (min or max) should be used in-
stead of the typical ones. In the case of , the only param-
eter affected by die-to-die process variations is the SW threshold
voltage ( is always the same assuming that the full-scale
DAC output value is adjusted to eliminate offset and gain er-
rors). Therefore, the minimum SW threshold voltage should be
used. In the case of , the variation of the SW and CS
threshold voltage compensate for each other, as they appear in
(16) with opposite sign. Therefore, only the die-to-die variation
of the affects the lower bound and the worst case is the
minimum value for that process.
To find an appropriate value for the SW gate voltage, the
upper bound must be larger than the lower bound in a given per-
centage of the cases expressed by . Fig. 3 illustrates
this tradeoff. To accomplish that the saturation constraint is ful-
filled with a given probability , the optimum of the
SW gate voltage found in (10), which is now the mean value of
a random variable, has to verify that
(19)
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 163

parameters using (17) and (18), which enables us to include

(21) in an analytical optimization process.
2) Cascoded Current Cell : Applying the
MOSFET saturation condition to
all transistors in the current source of Fig. 2(b) leads to the def-
inition of two voltage ranges, one for the SW gate bias voltage,
and another for the CAS gate bias voltage as shown in (23) at
the bottom of the page.
The mid-points of the above voltage ranges also correspond
to the optimum SW and CAS gate voltages, respectively, that
maximize the current source output impedance found in Sec-
tion II-B for this topology. Each range has two bounds, and these
four bounds can also be expressed as a function of the random
variables of the design when random mismatch errors are con-
sidered. The variance of the bounds can be estimated in the same
way as that in Section II-C1. Using the same criteria as in the
topology case, we have
Fig. 3. Graphical representation of the constraint (19).

which can be expressed also by the following equation:

(20)

which is the same as

(21)

Here, since only one half of the normal distribution has to

be considered, , where is
related to the previously defined INL by

(22)
(24)

because the worst case of the bounds variance for the several
current sources of the DAC is found in the LSB current source which in this case of the topology lead to two
(since its area is the smallest of all the current sources), and its saturation conditions
two complementary SW transistors must be inside both of the
bounds with the same probability.
The expression of (21) represents a saturation constraint
more realistically than (15) for the CS and SW current cell
circuit, where an arbitrary safety margin was included. The (25)
safety margin appearing in (21) is not arbitrary nor needs to
be found using parametric Monte Carlo simulation. It can The equations in (25) are analytical expressions that depend
be related to other circuit parameters and mismatch process on circuit and mismatch parameters. They will be used in the

(23)
164 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004

design procedure of Section IV for the optimum sizing of the

current cell topology.

D. Implications of the Extended Static Performance

Constraints in the Design Procedure
In this subsection, the extended modeling of the mismatch
effects presented in Sections II-A–C (including the optimum
output impedance biasing) are related to the circuit sizing for the
two topologies. The occupied area saving that is obtained in the
design by using the proposed extended modeling is contrasted
with previous design approaches.
1) Simple Current Cell : In the case of the (a)
topology, (1) and (2) leave only one degree of freedom for
the CS transistor, namely the overdrive voltage (which univo-
cally determines the CS gate bias voltage). The SW transistor
then introduces four more design variables: , , over-
drive voltage, and gate bias voltage. For the SW transistor the
overdrive voltage and the width to length ratio are
also related by the current value, so only two of them are really
free parameters. The optimum SW gate bias voltage (i.e., the ON
gate voltage for the switch transistors) can be calculated using
(10) as a function of the overdrive voltages, so only two de-
grees of freedom are left: the SW area and its overdrive voltage.
The three degrees of freedom left for the overall circuit are con-
strained by the saturation condition of (21). They can be used
(b)
to optimize other criteria, as for example the dynamic perfor-
mance, as will be shown in Section III. Fig. 4. Comparison between sizing results using (a) the proposed extended
modeling and (b) previous sizing approaches with safety margins.
In order to compare the proposed saturation statistical model
with the literature, a usual assumption is made which is that
the minimum area current cell is a prior target (which corre- optimum gate bias voltage expressions of (11). The saturation
sponds to the worst case mismatch). In this sense, minimum conditions of (25) constrain the available design space in a sim-
area CS and SW transistor are chosen, and only the SW tran- ilar way as (21) for the basic current cell. If minimum current
sistor overdrive voltage is left as a variable. By doing this, the cell area is imposed, the maximum CS overdrive voltage and CS
SW transistor must have either minimum length or minimum minimum area can be represented against CS and CAS overdrive
width, depending on its overdrive voltage. The maximum CS voltages as discussed in [15].
overdrive voltage (its minimum area) is found as a function of
the SW overdrive voltage using (21). Therefore, the SW over-
drive voltage is the only degree of freedom left. Fig. 4 compares III. DYNAMIC PERFORMANCE
the saturation conditions of (15) and (21) for a 12-b DAC de- The dynamic performance of a segment current steering
signed in a standard 0.35- m process with a specifications sim- (SCS) DAC is mainly dependent on two characteristics of the
ilar to [10] and other smaller safety margins. Fig. 4(a) depicts current sources: settling time and dynamic output impedance.
the maximum CS overdrive voltage and Fig. 4(b) shows the min- Another contribution that will also be included in the design
imum CS and overall current cell area. Both graphs are repre- procedure of Section IV is clock-feedthrough to the outputs,
sented against the SW overdrive voltage assuming a minimum which is an important contribution to glitch energy. In this
current cell area requirement. The smallest area achieved by ap- section, however, we will concentrate in the analysis of the
plying the extended modeling and the saturation constraint of settling time for switched current sources, by extending the
(21) is almost a 70% of the smallest area that will be obtained if work presented in [11] to find the relation of this settling time
the arbitrary safety margin of 500 mV used in [10] is considered, to the current cell circuit parameters. Next the dynamic output
this indicating that the latter approach is notably pessimistic impedance modeling is reviewed.
concerning process variations effects. The use of smaller safety
margins leads to a reduction in the smallest area obtained, as
A. Settling Time Modeling
shown in Fig. 4(b). However, even for a safety margin as small as
150 mV, the extended modeling approach yields a better result. Following the same approach as in Section II, first the simple
2) Cascoded Current Cell : In the case topology of Fig. 2(a) will be analyzed, followed by an analysis
of the topology, the CS has also one degree of the cascoded topology of Fig. 2(b).
of freedom left. The four degrees of freedom of each one of the 1) Simple Current Cell : During the switching
two other transistors (SW and CAS) are reduced to two degrees process of a steered current source, two phases may be distin-
of freedom for each one, using the current value expression and guished, as discussed in [11]. During the first phase, the two
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS 165

complementary control signals drive one of the switch transis-

tors from OFF to saturation whilst its complementary is driven in
the opposite direction. This first phase of the switching process
ends when both of the control signals attain their final value.
During the second phase, only the voltages at the switch tran-
sistors drains (node in Fig. 2(a) and the common source (node
in Fig. 2(a) vary until they achieve their steady state values. If
the complementary control signals slopes are fast enough com-
pared to the dynamic response of the current source nodes al-
most all the complementary output nodes transient takes place
in the second phase of the current sources switching process,
which is analyzed in the following.
The switching output voltage waveform is obtained by ap- Fig. 5. Current source switching transient waveforms for the CS + SW
plying an incremental small-signal analysis around the steady topology.
state and node voltages at the end of the second phase
( and ) and output current . This analysis uses the
following small-signal and node voltage initial conditions:

(26)

The small-signal output voltage waveform

found by the analysis is [11]

(27) Fig. 6. Optimum as a function of poles quotient for a 12- and 10-b DAC.

exists an optimum value for that minimizes the settling

where is the pole associated with the output node , the
time, for a given and . In the figure, has been set to
pole associated with the internal node , and is the ratio be-
0.5 LSB.
tween the small-signal initial charge at the internal node and
Two important conclusions are extracted from the previous
at the output node at the beginning of phase 2. In the deriva-
analysis.
tion of (27), the following simplifications have been performed:
; . The poles and 1) There exists an optimum value of for every
initial charge ratio are related to the circuit parameters and ini- ratio that minimizes the settling time. This optimum is
tial conditions through achieved through the appropriate design of the latch and
its output driver circuit. The traditional design practice
has been hitherto to design this control signals with a
crossing point in which one of the transistors enters in sat-
uration just when the other enters OFF state [8]. However,
this is not necessarily the optimum case, because a small
and overshoot will help to speed-up the output settling time of
the D/A converter, as has been shown above. For the il-
(28)
lustrative 12-b DAC used to plot Fig. 5, and provided that
the usual criterion of minimizing the overshoot
where and are the parasitic capacitances at nodes is used, the time needed for the output voltage to settle
and , respectively, and is the SW transistor small-signal (point b) is almost 6 times larger than when the optimum
transconductance. It should be noted that . is used (point a).
Fig. 5 represents the current source output node tran- 2) The model of (27) allows the quantitative estimation of
sient waveforms obtained with (27) for a given value of the settling time. It is a more accurate model than previous
and different values of , where has ones [10], which consider the settling time to depend just
been normalized to , and the time has been normalized on the minimum of the two poles, or , without
to . This waveforms have been obtained for a 12-b cur- coupling.
rent-steering DAC using standard 0.35- m process parameters. The optimum waveform presents a negative overshooting
Considering that the settling time is the time needed by the that is equal to (note that in Fig. 5 has been also nor-
output voltage to reach its final steady state value within an malized to ). No closed-form analytical expression exists for
accuracy of volts, it is concluded from Fig. 5 that there , but it is relatively easy to solve it numerically with the use of
166 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004

Fig. 7. Optimum settling-time for the CS + SW topology. Fig. 8. Effects of the Y node in the optimum settling time for the CS+CAS+
SW topology.
differentiation, and considering that the optimum is found when
equals at the instant for which (27) is minimum:

(33)

where an additional pole ratio is defined.

(29)
In this case, an additional component exists on the transient
response, which satisfies .
Fig. 6 shows the optimum value of as a function of
The additional component effect is difficult to evaluate
for and (12- and 10-b DAC, respec-
either analytically or graphically since considering it together
tively). The figure also depicts the following boundary condition
with and implies too many degrees of freedom. Fig. 8
that must verify for overshooting to exist [11]:
shows the influence of the additional component on the esti-
mated settling time as a function of and , for a rea-
(30)
sonable value of and optimum , extracted from
Fig. 7 shows the optimum settling time against and an actual 12-b SCS DAC designed on a 0.35- m CMOS tech-
P_{X/O} obtained for 12-bits DAC and typical 0.35-CMOS nology [16].
technology parameters, assuming that the optimum is used.
B. Dynamic Output Impedance Modeling
2) Cascoded Current Cell : In this case,
the circuit model used to estimate the output transient response The current-steering DAC SFDR performance is strongly de-
is shown in Fig. 2(b). An analysis equivalent to that done for the termined by the output impedance of the current sources [1], [2],
topology leads to the following result in the Laplace as expressed by the following expression:
domain:

SFDR (34)

where is the output load to LSB cur-

rent source output impedance ratio, and are the
(31)
dc component and ac amplitude, respectively, of the sinusoidal
( and ). For proper spec-
tral performance, the SFDR has to be greater than the signal-to-
where and quantization-noise ratio, which is 86 dB for a 14-b DAC or 74
are the additional pole and initial conditions coeffi- dB for a 12-b DAC. This implies a minimum output impedance
cients due to the additional internal node in Fig. 2(b). In the requirement. Output impedance SFDR requirements are easily
time domain, the small-signal output voltage waveform derived fulfilled for low-frequency signals, but when signal frequency is
from (30) corresponds to deep in the megahertz band parasitic capacitances of the current
source strongly degrade its output impedance and, consequently,
(32) the SFDR performance of the DAC is worsened.
In Section II-B, it was mentioned that the current source
with output impedance could be estimated using (4) and (5), for the
simple and cascoded current cell, respectively. This is true for
slow variations of the output voltage. In [2], it is shown that
in the case of the simple current cell topology the effect of the
nondesired capacitances may be modeled by adding a pole and
a zero to (4) and two poles and two zeros to (5) in the case of the
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS
cascoded current cell. This yields to the frequency-dependent
output impedances of (35) and (36), shown at the bottom of
the page. In the frequency band of interest (up to Nyquist),
the zeros do not affect dynamic output impedance because
for reasonable transistor sizes.
C. Implications of the Settling Time and Dynamic Output
Impedance in the Design Procedure
In this subsection, the settling time and dynamic output
impedance dependencies on circuit poles and initial conditions
are related to the transistors sizes and other circuit parameters.
1) Simple Current Cell : Fig. 7 depicts the
estimated optimum settling time as a function of and
, assuming that the optimum is obtained by the proper
synchronization of the switches’ control signals. From Fig. 7,
the intuitive rule that maximizing both poles leads to lower
settling time is quantitatively confirmed. In order to maximize
, a minimum-length SW transistor should be used. The SW
transconductance increases as the square root of the SW tran-
sistor width, but gate-to-source capacitance increases linearly,
thus a minimum-width SW transistor also maximizes . On
the other hand, a minimum-width CS transistor minimizes the
CS drain capacitance, therefore minimizing . A minimum
width for the CS implies that it must have the maximum CS
overdrive voltage that guarantees saturation for all transistors
(Section II-C). In most cases, however, the influence of the SW
and CS transistors’ width on can be neglected. This capac-
itance is dominated by the interconnect capacitance between
the CS and SW transistors in actual circuits, as each transistor
is placed in a different array and their interconnections usually
are large enough to dominate the node parasitic capacitance.
Furthermore, a minimum-width SW transistor also maximizes
by minimizing its drain and overlap capacitances. This
is specially significant for high segmentation ratios, where a
great number of switch drains are connected together at the
output node. Apart from the benefits to the settling time, the
clock-feedthrough is reduced if the SW gate and drain overlap
capacitances are lowered, which occurs when the SW width is
minimum.
The main design implication extracted from the previous dis-
cussion is that a minimum-length and -width SW transistor and
minimum-width CS transistor (maximum overdrive voltage) is
the optimum choice for settling time. However, the effect of SW
and CS width should be evaluated for every particular case, es-
pecially when node and parasitic capacitances are not dom-
inated by the SW capacitances. In this latter case, increasing
167
the SW width will increase its transconductance without signif-
icantly affecting and , although the clock-feedthrough
will be compromised.
The previous analysis applies to the OFF–ON switching branch
of the current source. If the same criterion is considered in the
analysis of the complementary ON–OFF switching branch, the
conclusion is that during the second switching phase the time re-
sponse of the complementary output node exclusively depends
on .
Concerning the dynamic output impedance requirement, in
the case of the simple current cell , a minimum-
length SW transistor allows minimizing . Even if intercon-
nect capacitance dominates, it is not worth increasing the SW
transistor length to attempt to decrease the output impedance
zero down to the pole frequency, as this compromises settling
time and dramatically increases the current cell area and, conse-
quently, the overall DAC area. Choosing the minimum area for
the CS transistor allows to minimize CS array area and, thus, the
interconnect capacitance. Furthermore, a minimum CS width
will also reduce node capacitance.
2) Cascoded Current Cell : The same
conclusions of Section III-A1 and design implications of Sec-
tion III-C1 are applicable to with respect to and
. A minimum-length and -width SW transistor and min-
imum-width CAS transistor (instead of CS) are optimum for
the settling time. This is especially true if it is taken into ac-
count that a small interconnect capacitance exists between SW
and CAS transistors in actual circuits. In this sense, the CAS
transistor not only increases current cell dc output impedance,
but also improves settling time performance. Concerning the in-
fluence of the additional node , as discussed in Section III-A2
and from Fig. 8, it is clear that only when is low enough and
is high is the settling time compromised. This situation is not
common, since the smaller is, the smaller will be, as
opposes voltage variations at node . In general, for reasonable
values of , , and , and reasonable voltage variations at
the internal nodes, pole does not effectively affect the set-
tling time.
As far the dynamic output impedance is concerned, the same
argument than in Section III-C1 may be applied to the SW and
CAS transistors length. Also, minimum CS area is the best
choice for output impedance bandwidth. Finally, minimum
CAS width leads to better performance, as it minimizes nodes
and capacitance. Minimum transistor dimensions pro-
duce maximum bandwidth for output impedance and SFDR
performance, apart from minimizing DAC area. Note that if the
dominant pole is , adding one or more extra
(35)
(36)
168 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
Fig. 9. Current sources design procedure flow for current-steering DACs.
cascode transistors between CAS and SW may improve SFDR
bandwidth performance without compromising settling time,
although the overall DAC area is increased (especially if we
take into account that a lower CS overdrive voltage will need
to be chosen).
IV. DESIGN PROCEDURE
In Sections II and III, the DAC current sources’ static, dy-
namic, area, and statistical models have been presented. Perfor-
mance requirements are related to the DAC design specifica-
tions, such as number of bits, linearity (INL and DNL), sam-
pling frequency, spectral performance, yield, area, and tech-
nology [1].
On the basis of the models presented in Sections II and III, a
current cell design procedure can be derived for both the simple
and cascoded current cell topolo-
gies.
Fig. 9 shows the design procedures for the two topologies.
The starting point includes design specifications and tech-
nology parameters. For the two topologies there are basically
two targets driving the optimization process (indicated with
italics in the figure), namely minimize current cell area and
minimize settling time. Note that in the cascoded topology the
minimum settling time target is coincident with the optimum
clock feedthrough and driver’s load target, whereas for the
simple current source topology (left part of the figure) the
settling time optimization has some negative impact on the
clock-feedthrough (because of the required increase in the SW
transistor width). Hence, two alternatives are shown in this case
depending on whether glitch energy or sampling frequency
is priorized. Intermediate results of the design procedure are
enclosed within the boxes. The design criteria used to derive
the intermediate results are shown by the arrows. Note that, in
general, the design procedures do not require the segmentation
ratio to be chosen previously, at least not until the driver and
latches are designed. The only exception is the case in which the
output node capacitance needs to be estimated with precision
(this design path is indicated in Fig. 9 with an asterisk). The
proposed design procedure is closed and provides as a final
result the complete sizing of the DAC current source circuits.
V. CONCLUSION
This work provides an extended design procedure for cur-
rent-steering DACs through the static and dynamic study of two
usually considered current source circuit cells. On the one hand,
an extended mismatch statistical study which takes into account
random variations in all the transistors of the current source cells
yields an improved analytical static model. This refined model
permits us to tighten the required biasing margins without re-
sorting to arbitrary margins, which, given the design space of
the DAC, results in notable area reductions. Conditions for op-
timum gate bias voltages concerning output resistance are ob-
tained as well. On the other hand, an extension of the switching
transient behavior is discussed, and its relation to transistor pa-
rameters is discussed. As a consequence of the extended static
and dynamic modeling, an improved DAC design procedure is
presented. By applying the design method to a particular tech-
nology and DAC specifications, comparisons with previous de-
sign approaches clearly indicate that the improved modeling of
mismatching and dynamics effects presented in this work allow
to reduce the area and improve the settling time of the DAC.
The results of this paper may ease the automatization of the
ALBIOL et al.: MISMATCH AND DYNAMIC MODELING OF CURRENT SOURCES IN CURRENT-STEERING CMOS DACS
circuit design of future current-steering DACs with improved
performance.
REFERENCES
[1] M. Gustavsson, J. Wikner, and N. Tan, CMOS Data Converters for Com-
munications. Boston, MA: Kluwer, 2000.
[2] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-Bandwidth
limitations for high speed high resolution current steering CMOS D/A
converters,” in Proc. IEEE Int. Conf. Electronics, Circuits and Systems
(ICECS), Sept. 1999, pp. 1193–1196.
[3] P. Hendriks, “Specifying communication DAC’s,” IEEE Spectrum, pp.
58–69, July 1997.
[4] Y. Cong and R. L. Geiger, “Switching sequence optimization for gradient
error compensation in thermometer-decoded DAC arrays,” IEEE Trans.
Circuits Syst. II, vol. 47, pp. 585–595, July 2000.
[5] J. Vandenbussche, G. Van der Plas, W. Daems, A. Van den Bosch, G.
Gielen, M. Steyaert, and W. Sansen, “Systematic design of high-accu-
racy current-steering D/A converter macrocell for integrated VLSI sys-
tems,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 300–309, Mar. 2001.
[6] C. H. Lin and K. Bult, “A 10.b, 500-Msample/s CMOS DAC in 0.6
mm ,” IEEE J. Solid-State Circuits, vol. 33, pp. 1948–1958, Feb. 1998.
[7] J. L. González and E. Alarcón, “Clock-Jitter induced distortion in high-
speed CMOS switched-current segmented digital-to-analog converters,”
in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS’01), May 2001,
pp. I512–I515.
[8] H. Kohno, Y. Nakamura, A. Kondo, H. Amishiro, T. Miki, and K.
Okada, “A 350-MHz 8-bit CMOS D/A converter using delayed driving
scheme,” in Proc. IEEE 1995 Custom Integrated Circuits Conf., 1995,
pp. 211–214.
[9] G. A. M. Van der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert,
and G. Gielen, “A 14-bit intrinsic accuracy Q random walk CMOS
DAC,” IEEE J. Solid-State Circuits, vol. 34, pp. 1708–1718, Dec. 1999.
[10] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-Bit in-
trinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits,
vol. 33, pp. 1959–1969, Dec. 1998.
[11] T. Miki, Y. Nakamura, K. Okada, and Y. Horiba, “Transient analysis of
switched current sources,” IEICE Trans. Electron., vol. E75-C, no. 3,
pp. 288–295, Mar. 1992.
[12] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching
properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp.
1433–1440, May 1989.
[13] A. Van den Bosch, M. Steyaert, and W. Sansen, “An accurate statistical
yield model for CMOS current-steering D/A converters,” in Proc. IEEE
Int. Symp. Circuits and Systems (ISCAS), May 2000, pp. IV105–IV108.
[14] A. J. David and K. Martin, Analog Integrated Circuit Design. New
York: Wiley, 1997.
[15] M. Albiol, J. L. González, and E. Alarcón, “Improved current-source
sizing for high-speed high-accuracy current steering D/A converters,”
in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Bangkok, Thai-
land, May 2003, pp. 837–840.
[16] M. Albiol, “Design and implementation of a high-performance
digital–analog converter in 0.35 m CMOS technology for communi-
cations applications,” Master’s thesis, Barcelona Telecommun. School
(ETSETB), Univ. Politècnica de Catalunya (UPC), 2002.
Miquel Albiol received the M.Sc. degree in electrical
and electronics engineering from the Universitat Po-
litecnica de Catalunya, Barcelona, Spain, in 2002. He
is currently working toward the Ph.D. degreee at the
same university.
After working as a Design Engineer for the
Broadcasting Department of Mier Comunicaciones,
Barcelona, for 2001–2002, he is currently working
for the Space Department of the same company in
the frame of the SMOS ESA project. His current
research interests include the areas of analog and
mixed-signal microelectronics with particular interest in digital-to-analog
conversion and RF circuits.
169
José Luis González (M’99) received the Diploma
in telecommunication engineering from the Ramon
Llull University (URL), Barcelona, Spain, in
1992 and the M.S. degree in telecommunications
engineering and the Ph.D. degree (with honors) in
electronic engineering, both from the Polytechnic
University of Catalunya (UPC), Barcelona, in 1994
and 1998, respectively.
He is currently a full-time Associate Professor with
the Department of Electronic Engineering, Telecom-
munication Engineering School of Barcelona, UPC.
During 1999, he spent a semester at the Electrical and Computer Science De-
partment, University of Arizona, Tucson, with a Fulbright fellowship, and he
collaborated with the Motorola Wireless Infrastructure Group, Phoenix, AZ, in
the investigation of noise effects on D/A converters for communications. His re-
search interests include VLSI design, mixed-signal and RF integrated circuits,
and noise problems. He has authored or coauthored 26 scientific papers in jour-
nals and conference proceedings and one book chapter.
Dr. González received the Doctoral Excellence Award for his Ph.D. thesis
from the Polytechnic University of Catalunya in 2001. His thesis work has been
published in the book Analysis and Solutions for Switching Noise Coupling in
Mixed-Signal IC’s (Boston, MA: Kluwer, 1999).
Eduard Alarcón (S’96–M’01) received the M.S.
(with national honors) and Ph.D. (with honors)
degrees in electrical engineering from the Universitat
Politecnica de Catalunya, Barcelona, Spain, in 1995
and 2000, respectively.
From 1995 to 1997, he was awarded a research
fellowship from the Catalan Government. During
the period 1997–2000, he was an Assistant Professor
with Department of Electronics Engineering,
Telecommunication Engineering School of Barcelona, where he became
full-time Associate Professor in 2000. During the period August 2003 to
January 2004, he is holding a visiting appointment at the COPEC center,
University of Colorado, Boulder. He has participated in five Spanish national
research projects. His current research interests include the areas of analog and
mixed-signal microelectronics with particular interest in current-mode design,
theoretical aspects of fuzzy control, integrated switching dc–dc converters, and
nonlinear controller VLSI implementations. He has authored or coauthored
more than 50 scientific papers in journals and conference proceedings and two
book chapters.
Dr. Alarcón was recipient in 1998 of the Myril B. Reed Best Paper Award at
the IEEE Midwest Symposium on Circuits and Systems for a research paper on
a mixed-signal reconfigurable neuro-fuzzy processor. He is the invited co-ed-
itor of a special issue of the Analog Integrated Circuits and Signal Processing
Journal devoted to current-mode circuit techniques and co-organizer of a spe-
cial session on “New trends in switching power converters toward circuit inte-
gration” at ISCAS’03.
 MODELING OF THE IMPACT OF THE CURRENT SOURCE OUTPUT IMPEDANCE ON
THE SFDR OF CURRENT-STEERING CMOS D/A CONVERTERS

Tao Chen and Georges Gielen

K.U.Leuven, ESAT-MICAS
Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
e-mail: tao.chen@esat.kuleuven.ac.be

ABSTRACT Vb

Vb
A behavior-level model of a thermometric DAC with acceptable Ro
complexity and sufficient accuracy is presented in this paper. The Vo (t) Ro
impact of the current sources’ internal poles on the SFDR is de- Vo (t)
Vg2(t) Vg3(t)
scribed in the model. With this model, the sensitivity of the SFDR Co

to some unideal factors such as the parasitic capacitors in the inter- Vx (t)

nal point, and the variation of the internal points’ voltages, can be Internal node X Vx (t)

observed directly. Furthermore, this model can be used for the ver- Vg0 +
Ŧ

ification of the possible solutions for the output impedance prob- +

Ŧ
Io0
Cx

lem, and is therefore necessary for future work.

1. INTRODUCTION (a) The schematic of a (b) the model for analysis

current source
In order to improve the Spurious Free Dynamic Range (SFDR) of
a high-accuracy, high-speed DAC, all the limitations have to be in- Figure 1: The schematic of current sources and the model for anal-
vestigated carefully. The current source’s limited output impedance ysis in reference [2]
at high signal frequency is one of the most serious factors that im-
pact the SFDR [1]. Normally, it’s very time-consuming or nearly
impossible to simulate such an impact by a spice-like simulator. When the current source is turned on, the output voltage can
In this paper, a model with sufficient accuracy and acceptable be expressed as[2]:
complexity is presented. The nonideal parameters, such as the
parasitic parameters, the crossing point voltage of the switching »
γP2
control signals, the limited output resistance of the transistors, are vo (t) = vo0 exp (−P1 t) − exp (−P1 t)+
P1 − P2
included in this model, so that their impact on the SFDR can be –
observed directly from the results of the simulation. γP2
exp (−P2 t) (1)
Our simulation results are consistent with the results of ref- P1 − P2
erence [1]. Moreover, the impact of the variation of the internal
points’ voltages, which can be controlled by adjusting the cross- where,
ing point voltage of the switching control signals, on the SFDR is
1
simulated. The results show that decreasing the absolute value of P1 = (2)
this deviation cannot always increase the SFDR, and its impact on Ro Co
gm
the SFDR is actually quite small. P2 = (3)
In section 2, the mathematical model used in our simulation Cx
is proposed. The modeling work and the simulation results are vx0 Cx
γ = (4)
presented in section 3. At last, the conclusions are given in section vo0 Co
4.
gm is the transconductance of the switching transistors.
In equation (1), vo (t) is the difference between the output volt-
2. MATHEMATICAL ANALYSIS age and its final value. vo0 is the initial value of vo (t), physically
it’s the output difference between the two sampling cycles. Sim-
2.1. The Model Used in Reference [2] ilarly, if we define vx (t) as the difference between the voltage of
the internal node and its final value, vx0 is defined to be the initial
The transient behavior of a switched current source (shown in Fig. value of vx (t). The value of vx0 is decided by the crossing point
1(a)) is proposed in the reference [2]. The model for analysis is of the two control signals (vg2 (t) and vg3 (t) in Fig. 1(a)) and is
shown in Fig. 1(b). controllable.

;‹,((( , ,6&$6

2.2. The Extended Model and with respect to the internal nodes A and B:

In the previous model, the transition behavior of the DAC is con- −I2 + gm2 [V1 (t) − V 1F ] − go2 [Vo (t) − V1 (t)]+
tained in the two parameters vo0 and vx0 . The output conductances
d
of the transistors are approximated to zero in this model. So this I1 + go1 V1 (t) + C1 V1 (t) = 0 (8)
is not enough to predict the impact of the output impedance on the dt
DAC’s SFDR, which has been proved to be one of the main factors −I4 + gm4 [V2 (t) − V 2F ] − go4 [Vo (t) − V2 (t)]+
that limit the SFDR of a DAC [1]. We will extend the mathemat- d
I3 + go3 V2 (t) + C2 V2 (t) = 0 (9)
ical model to take the output resistances into consideration in this dt
section, and then in section 3 we will get the behavioral model
based on the results obtained. It’s convenient to express the node voltages by using the devi-
The model used is shown in Fig. 2. The left box in the figure ations from their final values VoF , V1F and V2F as variables:
is the model of the current sources which are switching on during
the current sampling cycle, and the right box is the model of the vo (t) = Vo (t) − VoF (10)
current sources which were already switched on at the beginning v1 (t) = V1 (t) − V1F (11)
of the current sampling cycle. Those current sources which remain v2 (t) = V2 (t) − V2F (12)
off are neglected since their transconductances are very small, even
when the signal frequency is high. And notice that the final values of the voltages satisfy the fol-
lowing equations:
Vb

Ro go [VoF − Vb ] + I2 + go2 [VoF − V1F ]+

Vo (t)
I4 + go4 [VoF − V2F ] = 0 (13)
g m2 g m4
−I2 − go2 [VoF − V1F ] + I1 + go1 V1F = 0
Co
g o2 g o4 (14)
−I4 − go4 [VoF − V2F ] + I3 + go3 V2F = 0
I2 (t) I4 (t)
A V1 (t) B V2 (t) (15)
+ +
Ŧ Ŧ
I1 I3
g o1 C1 g o3 C2 Using these expressions into equations (7), (8) and (9), we obtain:

The current sources switching on The current sources switched on

go vo (t) − gm2 v1 (t) + go2 [vo (t) − v1 (t)]−
d
gm4 v2 (t) + go4 [vo (t) − v2 (t)] + Co vo (t) = 0 (16)
dt
Figure 2: Extended model for analysis
d
gm2 v1 (t) − go2 [vo (t) − v1 (t)] + go1 v1 (t) + C1 v1 (t) = 0 (17)
dt
In this figure, Ro and Co are the load resistance and capacitor d
respectively. Vo (t) is the DAC’s output voltage. Take the circuits gm4 v2 (t) − go4 [vo (t) − v2 (t)] + go3 v2 (t) + C2 v2 (t) = 0 (18)
dt
in the left box as an example. They describe all the current sources
that are switching on during the current sampling cycle. gm1 and Using the Laplace transform, and taking the initial values of
go2 are the total transconductance and the total output conductance the capacitor voltages into consideration:
of the switching transistors respectively. I1 is the total DC current
of the current sources, go1 is the total output conductance of the (go + go2 + go4 + sCo )Vo (s) + (−gm2 −
current source transistors, and C1 is the total parasitic capacitance go2 )V1 (s) + (−gm4 − go4 )V2 (s) = Co Vo0 (19)
at the internal node. V1 (t) is the voltage of this node. The mean-
ing of the parameters in the right box are the same, except that −go2 Vo (s) + (gm2 + go2 + go1 + sC1 )V1 (s) = C1 V10 (20)
they describe all the current sources that have switched on at the −go4 Vo (s) + (gm4 + go4 + go3 + sC2 )V2 (s) = C2 V20 (21)
beginning of the current cycle.
When some of the current sources are switching on, Vo (t), where Vo0 , V10 and V20 are the initial values of vo (t), v1 (t) and
V1 (t) and V2 (t) are changing towards their new final values VoF , v2 (t) respectively. Physically, they are the difference of the initial
V1F and V2F respectively. Assuming the final current passing the values of Vo (t), V1 (t) and V2 (t) from their final values. They
Voltage-Controlled Current Source (VCCS) in both the boxes are will be calculated in section 2.4. With symbolic analysis tools, the
I2 and I4 respectively, their transient current can be expressed as output voltage vo (t) can be obtained from equations (19), (20) and
[2]: (21).

I2 (t) = I2 − gm2 [V1 (t) − V1F ] (5) 2.3. Some Special Cases
I4 (t) = I4 − gm4 [V2 (t) − V2F ] (6)
Some special boundary cases still need to be considered.
Applying these results, the node equation with respect to the When all the current sources are switched off at the beginning
output node is: of the current cycle, the circuits in the right box of Fig. 2 don’t
exist. The circuits equations then become:
go [Vo (t) − Vb ] + I2 − gm2 [V1 (t) − V1F ] + go2 [Vo (t) − V1 (t)]+
(go + go2 + sCo )Vo (s) + (−gm2 − go2 )V1 (s) = Co Vo0 (22)
d
I4 − gm4 [V2 (t) − V2F ] + go4 [Vo (t) − V2 (t)] + Co Vo (t) = 0 (7) −go2 Vo (s) + (gm2 + go2 + go1 + sC1 )V1 (s) = C1 V10 (23)
dt

,
 When no current source is switched on during the current cy- With equations (28) and (29), the initial value of vo (t) can be
cle, the circuits in the left box of Fig. 2 don’t exist. The circuit obtained:
equations are then: Vo0 = Vo (0) − Vdif f − Vo (∞) (31)
where Vdif f is the difference between the voltage at the end of the
(go + go4 + sCo )Vo (s) + (−gm4 − go4 )V2 (s) = Co Vo0 (24) last cycle and the ideal voltage when time is approaching infinity.
−go4 Vo (s) + (gm4 + go4 + go3 + sC2 )V2 (s) = C2 V20 (25) It describes the fact that the ideal final value can never be reached.
The value of V10 is decided by the crossing point of the two
When no current source is switched on at both the beginning control signals (Vg2 (t) and Vg3 (t) in Fig. 1(a)), and is control-
and the end of the current cycle, the circuits can be simplified into lable.
an R-C network, and: For the current sources which are always on during this cycle,
the deviation of their internal point (point B in Fig. 2) is caused by
Vo0 the deviation of the output point. Since Ro  1/go3 , we can get:
Vo (s) = (26)
s + go /Co
Vo0
V20 = (32)
1 + gm4 /(go3 + go4 )
2.4. The Initial Conditions
In order to obtain the output voltage vo (t), the initial values Vo0 , 3. MODELING WORK
V10 and V20 have to be calculated. These initial values are the de-
viations of the voltages at the beginning of the current cycle from With the mathematical model described in section 2, a behavioral
their final values. model of the DAC can be obtained. Fig. 4 shows the flow chart
At the beginning of the current cycle, only the current sources of the program. In our program, all the parameters are extracted
in Fig. 2’s right box are on. The circuits for calculating the voltage from the simulation results of a real design[3], except the parasitic
at the output node are shown in Fig. 3(a), where the cascode cur- capacitance in the internal node. For simplification of the model,
rent source is simplified into an ideal current source and an output the simulation results below are based on the assumption that the
resistance ro34 : parasitic capacitance at the internal node of every current source
is the same. The total parasitic capacitance depends on the area of
ro34 = 1/go3 + 1/go4 + gm4 /(go3 go4 ) (27) the current sources block and can be estimated. In our case, the
estimated value is about 40 pF.
The output voltage at the beginning of the cycle can be obtained
as:
ro34 ro34 Ro For every sampling cycle,
Vo (0) = Vb − I3 (28) calculate the number of current
Ro + ro34 ro34 + Ro
sources that have been on and
that will be switched on

Vb Vb Calculate the parameters of the

circuits

Ro Ro Calculate the output signal in this

sampling cycle
Vo (0) Vo ( )
Calculate the output signal in all
the sampling cycles, and get the
I3 ro34 I3 + I1 ro34 // ro12 whole output signal

Apply the window function

and do the FFT analysis
(a) At the beginning of (b) At the end of the cycle Calculate the SFDR value for
the cycle that input frequency

Figure 3: The schematics for the calculation of the initial values of Figure 4: The flowchart of the behavioral model
the output voltage
Fig. 5(a) shows the output signal of the DAC. Fig. 5(b) is the
At the end of the cycle, the current sources in both boxes of result of the FFT analysis. The SFDR can be obtained by calculat-
Fig. 2 are on. The circuits are shown in Fig. 3(b). The output ing the difference between the amplitude of the signal frequency
voltage is: and the amplitude of the second largest value in the frequency
spectrum.
ro34 ro12 (ro34 ro12 )Ro Doing the same calculation for different signal frequencies, we
Vo (∞) = Vb − (I1 + I3 ) (29)
Ro + ro34 ro12 r034 ro12 + Ro get the SFDR-fsig curve as shown in Fig. 6(a). We see from this
figure that when the signal frequency is higher than a value (which
where is quite low), the SFDR will decrease with increasing signal fre-
ro12 = 1/go1 + 1/go2 + gm2 /(go1 go2 ) (30) quency at a slope of about -20dB/dec, until it reaches a relative

,
 a real converter, the SFDR might not really decrease. But still we
The Output of the DAC The Power Spectrum Deisity of the Output Signal
0.3 40
can expect that the SFDR won’t increase a lot by optimizing the
0.2
20

0
crossing point of the control signals.
0.1
fsig=9MHz Ŧ20
Another interesting relation is the relation between the SFDR
Output Voltage (v)

Power Density (dB)

0
Ŧ40 and the total parasitic capacitance. This is shown in Fig. 6(c). We
Ŧ60
see that, when the total parasitic capacitance is bigger than 2pF,
Ŧ0.1 Ŧ80

Ŧ100
the SFDR will decrease with increasing total capacitance value
Ŧ0.2
Ŧ120 at a rate of -20dB/dec. This is because the pole of the output
Ŧ0.3 Ŧ140
impedance is reduced when the value of the parasitic capacitor is
Ŧ160
0 2 4 6
Time (s)
8 10 12
Ŧ8
x 10
0 1 2 3 4
Frequency (KHz)
5 6 7 8 9 10
4
x 10 increasing, thus the SFDR will be reduced to lower value at the
given signal frequency.
(a) The time-domain output (b) The frequency-domain
signal of the DAC output signal of the DAC 4. CONCLUSIONS

The impact of the current source output impedance on the SFDR of

Figure 5: The simulation results for one input signal frequency
current-steering CMOS D/A converters is simulated in this paper.
The results show that the limited output impedance can really limit
high frequency. This result is consistent with the bode diagram of the DAC’s SFDR property seriously.
Zimp described in Fig. 3 of the reference [1]. One possible solution to this limitation is to reduce the para-
sitic capacitance by reducing the area of the current sources. In
order to achieve enough accuracy with smaller area, calibration or
Simulation Result: Internal Poles Included
The SFDRŦv
10
Curve trimming is necessary. Recent published paper shows this trend
84
110

82
[5] [6].
The variation of the internal points’ voltages is also included
105

80
100 fsig=29MHz
78 in the model, and their impact on SFDR is also investigated. The
95

results show that the SFDR cannot improve a lot by adjusting this
SFDR (dB)
SFDR: DB

76
Ctot=40pF
90

85 V =Ŧ0.0465V
74
parameter.
10
72

80 C =40pF
tot 70

75 68 5. REFERENCES
70 66
10
3 4
10
5
10 10
6 7
10 10
8 Ŧ1 Ŧ0.8 Ŧ0.6 Ŧ0.4 Ŧ0.2 0 0.2 0.4 0.6 0.8 1

signal frequency: Hz v (V)

10
[1] A. Van den Bosch, M. Steyaert and W. Sansen, “SFDR-
Bandwidth Limitations for High Speed High Resolution
(a) The SFDR-fsig curve (b) The SFDR-V10 curve Current Steering CMOS D/A Converters,” in International
Conference on Electronics, Circuits and Systems, vol. 3,
The SFDRŦC Curve
pp. 1193-1196, Sept., 1999
tot
100

[2] T. Miki, Y. Nakamura, K. Okada and Y. Horiba, “Transient

95
Analysis of Switched Current Sources,” IEICE Trans. Elec-
90 tron, vol. E75-C, pp. 288-296, Mar. 1999
SFDR (dB)

85
f =29MHz
sig [3] G.Van der Plas, J.Vandenbussche, W.Sansen, M.Steyaert
80
v =Ŧ0.0465V
10
and G.Gielen, “A 14-bit Intrinsic Accuracy Q2 Random
Walk CMOS DAC, ” IEEE J. Solid-State Circuits, vol. 34,
75

pp. 1708-1718, Dec. 1999

70

[4] J.Bastos, A.M.Marques, M.Steyaert and W.Sansen , “A 12-

Ŧ1 0 1 2
10 10 10 10
C (pF)
tot

Bit Intrinsic Accuracy High-Speed CMOS DAC, ” IEEE

(c) The SFDR-Ctot curve J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998
[5] Y. Cong and R. Geiger, “A 1.5V 14b 100MS/s Self-
Calibrated DAC,” in IEEE ISSCC 2003 Session 7/Dacs AND
Figure 6: The simulation results
AMPs/Paper 7.2.
Changing the control signals will cause a deviation of the in- [6] J. Hyde, T. Humes, C. Diorio, M. Thomas and M. Figueroa,
ternal points (point A in Fig. 2). Designers can control the value “A 300-MS/s 14-bit Digital-to Analog Converter in Logic
of v10 by controlling the crossing point of the control signal [4]. CMOS,” IEEE J. Solid-State Circuits,vol. 38,pp. 734-740,
Naturally, it will be interesting to observe the relation between the May. 2003.
SFDR and the value of this deviation. Fig. 6(b) shows the simu-
lation results. Two conclusions can be drawn from these results.
Firstly, when the deviation changes, the variation of the SFDR is
quite small; Secondly, when the deviation is negative (this is the
normal case), reducing the absolute value of the deviation will de-
crease the SFDR. In our behavioral model, the glitches caused by
the feedthrough of the signal frequency are not considered. So in

,
 Modelling and implementation of a
10-bit 80 MSPS current-steering DAC
with internal bandgap reference
in a 0.18 µm CMOS process

Master of Science Thesis

Henrik Hassander & Christian Lindholm
in cooperation with
Acreo AB
February 2004

Department of Electroscience
Abstract
A 10-bit quadrature differential digital to analog converter has been designed in a 0.18
µm CMOS process. This DAC is a part of the SoCTRix project at Acreo. There has
been a large effort put into MATLAB modelling of DAC behaviour and errors. A
design flow was built up to systemize and simplify the layout work. To minimize
external components, a bandgap was implemented in the same design. The main
design goal was to reach high linearity while keeping power consumption low. A
secondary goal has been to keep the total chip area low. In an effort to make the DAC
commercially viable it has been designed to give a high yield.

1
2
Preface
This thesis work has been carried out at Acreo AB in Lund. The thesis is part of our
Master of Science degree from Lund Institute of Technology – LTH, Lund University.

We would like to thank our advisors Karl Norling from Acreo, Martin Anderson from
Department of Electroscience, LTH and all co-workers at Acreo.
We would also like to thank our examiner at LTH, Jiren Yuan.

3
4
1 Abbreviations........................................................................ 7
2 Introduction .......................................................................... 9
2.1 Design goals...................................................................................................9
3 Theory................................................................................. 11
3.1 DAC Theory.................................................................................................11
3.2 Performance measures .................................................................................11
3.2.1 Offset error...........................................................................................11
3.2.2 Gain error .............................................................................................12
3.2.3 Differential Nonlinearity......................................................................12
3.2.4 Integral Nonlinearity............................................................................13
3.2.5 Monotonicity........................................................................................14
3.2.6 Glitches ................................................................................................14
3.2.7 Settling time .........................................................................................14
3.2.8 Signal-to-Noise and Distortion Ratio...................................................14
3.2.9 Spurious Free Dynamic Range ............................................................14
3.2.10 Resolution ............................................................................................15
3.2.11 Accuracy ..............................................................................................15
3.2.12 Effective Number Of Bits ....................................................................15
4 DAC Architecture............................................................... 17
4.1 Choice of architecture ..................................................................................17
4.2 Current-Steering DACs................................................................................17
4.2.1 Thermometer code ...............................................................................18
4.2.2 Thermometer-Binary segmentation .....................................................18
5 Modelling of errors in a current-steering DAC................... 21
5.1 Causes of errors in current-steering DACs ..................................................21
5.1.1 Output impedance vs. SFDR................................................................21
5.1.2 Output impedance vs. gain error..........................................................21
5.1.3 Mismatch vs. SFDR .............................................................................22
5.1.4 Mismatch vs. INL ................................................................................22
5.1.5 Influence of noise on circuit performance ...........................................23
5.1.6 Influence of graded errors on performance..........................................23
5.1.7 Mismatch calculations .........................................................................24
5.2 MATLAB model..........................................................................................25
5.3 MATLAB simulations .................................................................................25
5.3.1 Simulating the nominal case ................................................................25
5.3.2 Simulating the impact of reduced matching ........................................27
5.3.3 Simulating the impact of switching schemes.......................................28
5.3.4 Simulating the impact of limited output impedance ............................30
6 System implementation ...................................................... 31
6.1 System description .......................................................................................31
6.2 Implementation of sub-circuits ....................................................................32
6.2.1 Current source......................................................................................32
6.2.2 The binary-to-thermometer decoder ....................................................35
6.2.3 Latches .................................................................................................37
6.2.4 Bandgap reference ...............................................................................40
6.2.5 Voltage-to-current converter................................................................45
6.2.6 Voltage-to-current converter bias circuitry..........................................48

5
7 Results and conclusion ....................................................... 49
7.1 The complete system....................................................................................49
7.2 Challenges of system simulations................................................................49
7.3 Simulation results.........................................................................................50
7.4 Conclusions..................................................................................................50
7.5 Possible improvements for future development ..........................................51
8 Measurements ..................................................................... 53
8.1 Introduction..................................................................................................53
8.2 Static measurements.....................................................................................53
8.3 Dynamic measurements ...............................................................................54
9 References .......................................................................... 57
Appendix A............................................................................... 59
Appendix B............................................................................... 63
Appendix C............................................................................... 69

6
1 Abbreviations

Abbreviation Explanation

ADC, A/D Analog-to-Digital Converter

DAC, D/A Digital-to-Analog Converter

DNL Differential Non-Linearity

DRC Design Rule Check

ENOB Effective Number Of Bits

FFT Fast Fourier Transform

INL Integral Non-Linearity

LSB Least Significant Bit

LVS Layout Versus Schematic

MSB Most Significant Bit

MSPS Mega Samples Per Second

OP Operational Amplifier

PSRR Power Supply Rejection Ratio

SE Silicon Ensemble

SFDR Spurious Free Dynamic Range

SNDR Signal to Noise and Distortion Ratio

SNR Signal to Noise Ratio

SR-flip-flop Set reset flip flop

VLSB Voltage amplitude of one quantization step

7
8
2 Introduction

Wireless communication systems today require more and more digital signal
processing. But somewhere along the line of a transmitter or a receiver there is a radio
signal, an analog signal. This requires the use of a digital-to-analog converter in a
transmitter or an analog-to-digital converter in a receiver. These communication
systems are often mobile and thus require all of the circuits involved to have low
power consumption.

In IC manufacturing today, the trend is to keep shrinking the processes as much as

possible. For digital circuits this is a good thing since it means smaller circuits with
lower power consumption. For analog circuits however it is starting to become a bit of
a problem. The smaller the process becomes the more the power supply voltage is
lowered. This means that the signal headroom is decreased and the number of circuits
that are possible to implement are reduced.

In this thesis a DAC was designed in a 0.18 um process at Acreo AB in Lund.

MATLAB models were developed to study the behavior of current-steering DACs
and how different errors affects the performance. An internal reference in the form of
a bandgap has also been implemented. The actual design was created and simulated in
Cadence custom IC design tools.

2.1 Design goals

The goal is to design a quadrature 10-bit DAC with good linearity and low power
consumption. The architecture chosen was a current-steering DAC, more information
on this later on. The load was decided to be 60 Ω with a full-scale differential current
of 10 mA(each output supplying 0 to 5mA). This equates to a differential voltage
swing of 600 mV. The filter following the DAC set these requirements.
The requirement on update rate was set to 80 MSPS.

9
10
3 Theory

3.1 DAC Theory

The digital to analog converter converts a discrete time signal with discrete amplitude
to a continuous time signal with discrete amplitude. In the case where the digital word
is binary and there is a given voltage (or current) reference, the output is
N
Vout = Vref ∑ 2− k bk ( 3.1 )
k =1

where the vector b is the binary word and N is its length (the DAC’s resolution). The
minimum voltage change on the output, corresponding to a change of 1 LSB, is
Vref
VLSB = ( 3.2 )
2N
The maximum output signal can be calculated from equation ( 3.1 ). The decimal
value is
N

∑2
k =1
−k
= 1 − 2−N ( 3.3 )

which gives the maximum output voltage

VMAX = Vref − VLSB ( 3.4 )
These equations give us the output as shown in Figure 3.1, where the input signal is a
2-bit ramp from 00 to 11.

Figure 3.1 Digital to analog conversion with a 2-bit DAC.

3.2 Performance measures

Due to nonlinearity, noise, mismatch, power supply etc, the output signal is not ideal.
The unit used when defining the following errors is LSB.

3.2.1 Offset error

The output when the input vector, B, is 0 is defined as the offset error, Eoffset [1].

11
 Vout (B )
Eoffset ≡ ( 3.5 )
VLSB B = 0

3.2.2 Gain error

The gain error is defined as the output deviation from the ideal output with a full-scale
input, minus the offset error.
Vout (B )
E gain ≡
VLSB B = 2 N −1
( )
− 2 N − 1 − Eoffset ( 3.6 )

The offset and gain errors are described graphically in Figure 3.2.

Figure 3.2 DAC gain and offset errors.

These two errors are disregarded when describing differential and integral
nonlinearity errors.

3.2.3 Differential Nonlinearity

The difference between each output step of a real and an ideal DAC is the DNL error.
The vector of DNL errors is
Vout (B ) − Vout (B − 1)
DNLB ≡ 1 − ( 3.7 )
VLSB 0 < B ≤ 2 N −1

The vector’s maximum is often used in specifications to show the worst-case error.

12
 Figure 3.3 Transfer curve with errors on the left, and the DNL vector on the right.

3.2.4 Integral Nonlinearity

The INL errors are calculated as the deviation from a straight line, which is adapted to
the transfer curve. The line could be between the start and end points of the curve, or
calculated with some kind of linear regression. As for the DNL, the vector’s
maximum is often used to specify the INL.

Figure 3.4 INL errors compared to a straight line between start and end points.
The equation for the INL vector is

13
 Vout (B ) − Vout _ fit (B )
INLB ≡ ( 3.8 )
VLSB 0 ≤ B ≤ 2 N −1

where Vout_fit is the straight line from zero to full-scale. If the DNL and INL formulas
are combined we get an expression for DNL and INL.
DNL B = INLB − INLB −1 ( 3.9 )
B
INLB = INL0 + ∑ DNLk ( 3.10 )
k =1

3.2.5 Monotonicity
A DAC has monotonic behaviour if the output always increases with an increasing
input. Monotonicity is guaranteed if the maximum INL error is smaller than 0.5 LSB
and the DNL error less than 1 LSB. The non-monotonicity often occur when the input
is changed from “01…1” to “10…0” in binary weighted DAC’s.

3.2.6 Glitches
If there is skew between the input bits or the clock, glitches can occur. For example, if
an input word is changed from “1000” to “0111” and the MSB is slower than the
other bits. Then the input is “1111” before it changes to “0111”. The LSB step will
begin with a peak and then settle to the desired voltage.

3.2.7 Settling time

Since the output is a step and there is always parasitic capacitance, it needs time to
settle within the error margin (usually 0.5 LSB). The time it takes will limit the
maximum number of samples per second.

3.2.8 Signal-to-Noise and Distortion Ratio

SNDR is the most important dynamic specification. It depends on the resolution of the
DAC and most of the other errors such as mismatch, nonlinearity, clock jitter, noise
and settling time. SNDR can be calculated with equation ( 3.11 ), where VQ_RMS is a
LSB and Vdist_RMS is the distortion.
⎛ Vout _ RMS ⎞
SNDR = 20 log⎜ ⎟ ( 3.11 )
⎜ V 2 Q _ RMS + V 2 noise _ RMS + V 2 dist _ RMS ⎟
⎝ ⎠

3.2.9 Spurious Free Dynamic Range

SFDR is the ratio between the signal amplitude and the largest spurious tone of the
output signals’ spectrum.

14
 Figure 3.5 Frequency spectrum showing SFDR.

3.2.10 Resolution
The resolution is defined as the number of analog levels. Which is 2N for a converter
with N physical input bits. However, this does not say anything about the actual
performance of the DAC.

3.2.11 Accuracy
The absolute accuracy of the converter is the difference between the ideal and the
actual performances, where the offset, gain and nonlinearity errors are included.
Relative accuracy is the absolute accuracy without the gain and offset errors.

3.2.12 Effective Number Of Bits

A converter with N-bits resolution has most likely not an accuracy of N effective bits.
When calculating the ENOB, the formula for the maximum SNR with a quantized
input signal is used [1].
SNR = 6.02 N + 1.76 ( 3.12 )
Distortion is added to the noise, which results in the equation for ENOB.
SNDR − 1.76
ENOB = ( 3.13 )
6.02

15
16
4 DAC Architecture

4.1 Choice of architecture

There are four different architectures that are suitable for the required sampling rate.

• Pipelined
• R-2R ladder
• Resistor string
• Current steering

The pipelined converter would need to use 10 fairly fast operational amplifiers for 10-
bit operation. These would consume a lot of power to operate at the speeds required.
The output from the pipelined converter is voltage and would therefore have to be
converted into current in order for the next stage to work.
The R-2R and resistor string architecture have the same basic flaw. It does not make
efficient use of the power. This is caused by the fact that here is always a current
flowing through the resistive network. It is also hard to match the resistors for 10-bit
accuracy without a significant penalty in either area or power.
This leaves only the current steering architecture, which is chosen because it is
possible to reach 10-bit accuracy at the required speed.

4.2 Current-Steering DACs

The basic principle of a N-bit current-steering DAC is N current sources connected in
parallel. The digital input word controls which source that is connected to the load. A
larger digital word gives more current sources in parallel that results in a larger output
signal. One big advantage with this architecture is that almost all current goes through
the output, and that makes this architecture power efficient. This type of converter is
also superior when it comes to high-speed D/A converters. A 1-bit differential
converter is shown in Figure 4.1. The complementary input signals make the current
pass through the left or the right output. The differential voltage on the output is
Vout = RL (I P − I N ) ( 4.1 )

Figure 4.1 A 1-bit current-steering DAC with current source and digital input b.

17
The power losses for this type of converter come from generating the bias and
synchronization of the input signal. This also means that the power consumption will
scale fairly well with the update frequency since the power consumption in a digital
net is proportional to the frequency.

4.2.1 Thermometer code

A way, different from the binary, to represent a digital word is with thermometer
code.
Decimal Binary Thermometer

0 000 0000000

1 001 0000001

2 010 0000011

3 011 0000111

4 100 0001111

5 101 0011111

6 110 0111111

7 111 1111111

Table 4.1 Decimal numbers coded with binary and thermometer code.
The number of bits required for the thermometer code is
NT = 2 N B − 1 ( 4.2 )
where NB is the number of binary bits. This results in a larger amount of hardware
when there is a large word-length. However, the thermometer coded D/A converter
also has positive qualities. For example, if a binary number changes from “100” to
“011” there may be a glitch. If the same change is done with the thermometer code it
just changes one bit, and this glitch problem is gone and the DNL errors are reduced.
If the converters current sources have different current, the “011” level might give
more current than the “100” level, which means that the converter is non monotonic.
This is impossible with a fully thermometer coded current-steering converter because
the number of active current sources always increases with the input, and this
guarantees monotonicity.

4.2.2 Thermometer-Binary segmentation

Due to fast increasing number of inputs for high accuracy fully thermometer coded
DACs, it is common with segmented converters [2] where the LSBs are binary and
the MSBs thermometer coded. A segmented DAC is used to get most of the
advantages with fewer of the disadvantages from both coding techniques.
Below are some positive and negative things about thermometer and binary coding.

18
Thermometer
Positive
• Low glitch energy
• Monotonicity
• Small DNL errors
Negative
• Digital decoding with more area and power consumption
• Increased number of control signals

Binary
Positive
• Low digital power consumption
• Smaller area
• Small number of control signals
Negative
• Monotonicity not guaranteed
• Larger DNL errors

The price in digital power and area was rather small compared to the benefits of
smaller glitch energy and DNL errors, so a split with 8 thermometer and 2 binary bits
was chosen for this DAC. This results in a thermometer unit current, It, equal to four
binary units, Ib. One can either represent the thermometer unit as 1 current source with
4 times the binary unit current, 2 sources with 2 times the unit current or 4 unit
sources. With 1 source, the standard deviation for the transistor mismatch on a wafer
is
N ∈ (4m,4σ ) ( 4.3 )
and with 4 sources of the same size as above
( )
N ∈ 4m, 4σ 2 = (4m,2σ ) ( 4.4 )
Therefore it is better to use 4 thermometer sources because the required matching is
decreased, and it is easier to apply different layout techniques such as common-
centriod. It is also easier to match the sources because they are the same size as the
binary sources and they will have the same bias.

19
20
5 Modelling of errors in a current-steering DAC

In this chapter the cause of some of the errors causing performance degradation will
be discussed. Some approximate formulas for estimating performance are shown.
Both static and dynamic errors are taken into consideration. A MATLAB model of a
current steering DAC is shown. Some simulation results from this model are
presented.

5.1 Causes of errors in current-steering DACs

5.1.1 Output impedance vs. SFDR

The limited output impedance of the current source will cause an error in the output
signal. This is caused by the fact that the output impedance is dependant on how many
current sources that are on at any given time. This will cause a signal dependent
current sharing between the load and the output impedance of the current source. It
can be shown [3] that the output voltage as a function of time can be written as below:
N (sin(ωt ) + 1) I
V (t ) =
2 N (sin(ωt ) + 1) ( 5.1 )
+
RL Z imp
where I is the current through one current source, RL is the load resistance, Zimp is the
output impedance of one current source and N is the total number of current sources.

By doing a taylor series expansion and identifying the harmonics it’s possible to
decide the influence of Zimp on SFDR. The series expansion was done in maple for
both the single-ended case and the differential case. In Appendix A the complete
maple code can be seen for both cases. In the single-ended case the SFDR is
dependant on the second order harmonic, which is the dominant overtone. In the
differential case, assuming perfect matching, the second order harmonic is cancelled
and the SFDR is dominated by the third overtone.

The ratio between the signal and the second order harmonic in the single-ended case
is, according to [3], approximately given by:
N
Z imp
SFDR = ( 5.2 )
4 2N
+
RL Z imp
For a 10-bit converter SFDR should be at least 60 dB. In this case with RL=60 Ω this
would mean that Zimp would have to be at least 15.3 MΩ in the desired frequency
range. In the differential case an output impedance of 455 kΩ is enough to meet the
demands. A demand that is much easier to meet, especially if high frequency
operation is desired.

5.1.2 Output impedance vs. gain error

Since the current is shared between the load and the output impedance of the current
source array a gain error will occur. The size of this error is decided by how many

21
current sources are on and the value of the load resistor. The worst case occurs when
all current sources are conducting. The full-scale gain error is easily determined by
the following equation:
Vout Z imp
= ( 5.3 )
Vin 1023RL + Z imp
The only problem with this simple equation is that it doesn’t take the frequency
dependence of Zimp into consideration. Since the frequency behaviour of Zimp is hard
to determine analytically one has to rely on simulations for this.

5.1.3 Mismatch vs. SFDR

Variations in the manufacturing process causes mismatch between current sources.
This means that there will be a variation in current over the area of the chip. A
detailed analysis has been performed in [2] and the result is shown below
⎛ 3π ⎞
SFDR ≈ 20 log⎜ ⎟ + 3N − 10 log σ unit
2
( 5.4 )
⎝ 4 ⎠
where σunit is the mismatch between current sources, for instance 4% mismatch means
that σunit equals 0.04. This is only an approximate equation because it only takes the
mismatch in the MSBs into account. But it gives an idea of what to expect and it can
be used to calculate an approximate demand on mismatch.
For an average SFDR of 65 dB in a 10-bit DAC less than 4.2 % mismatch is required.

5.1.4 Mismatch vs. INL

The mismatch also affects the DC performance. The mismatch causes each current
source to deliver a slightly different current. This causes non-linearity in the transfer
function. To determine the tolerable mismatch based on INL performance the
following equation can be used [4]
σI 1 ⎛ yield ⎞
= with C = inv _ norm⎜ 0.5 + ⎟ ( 5.5 )
I 2C 2 N
⎝ 2 ⎠

where σI/I is the standard deviation of a unit current source, N is the number of bits,
inv_norm is the inverse cumulative normal distribution and yield specifies the
percentage of DACs with an INL below ½ LSB. Figure 5.1 shows the yield plotted
versus the current source mismatch.

Figure 5.1 Yield versus mismatch.

22
In a 10-bit DAC this means that the matching has to be around 0.5% to get a
reasonable yield.

5.1.5 Influence of noise on circuit performance

There are basically two types of noise on the output of the DAC. One is thermal noise
from the load resistor. The other one is the noise from the current sources. The
thermal noise for a resistor is given by the formula below:
Vrms = 4kTR ⋅ BW ( 5.6 )
where k is Boltzmann’s constant, T is the temperature, R is the resistor value and BW
is the noise bandwidth. The noise from the current source is harder to analyze
analytically and therefore has to be computed from simulations.
These noise sources should be compared with the quantization noise. The quantization
noise exists because the input signal is quantized. The general formula for calculating
the SNR caused by quantization noise is given below.
⎛ Vref ⎞
⎜ ⎟ ⎛ ⎞
SNR = 20 log ⎜ 2 2 ⎟ = 20 log⎜ 3 2 N ⎟ = 6.02 N + 1.76dB ( 5.7 )
⎜ VLSB ⎟ ⎜ 2 ⎟
⎜ ⎟ ⎝ ⎠
⎝ 12 ⎠
In order to calculate the total SNR of the DAC one has to add up all noise sources.
The formula will then look like below
⎛ Vref ⎞
⎜ ⎟
SNR = 20 log⎜ 2 2 ⎟ ( 5.8 )
⎜ VLSB
2 ⎟
⎜ + 4kTRLOAD ⋅ BW + 1023VIunit ⎟
2
⎝ 12 ⎠
where VIunit is the RMS noise voltage from one current source. When the noise level
is the same as the quantization noise level a 3 dB loss in SNR occurs and if the noise
level is half that of the quantization noise the loss in SNR is 1 dB.

5.1.6 Influence of graded errors on performance

In the above analysis the mismatch errors are assumed to be uncorrelated. This is not
entirely true in a real implementation. The fabrication process causes linear graded
errors. These can be caused by a linear graded thickness in gate-oxide for instance.
There are also symmetrical errors caused by resistance in interconnect wires on chip.
In addition to these errors there are also parabolic errors that emerge during
manufacturing. All these errors degrade the performance of the DAC.
To lessen the impact of these errors a hierarchical symmetric switching scheme is
used as described in [5]. The basic concept is to switch the current sources so that
they as a group cancel the linear and symmetrical errors. An illustration of this can be
seen in Figure 5.2 below.

23
 Figure 5.2 Illustration of the hierarchical symmetric switching scheme.
First current source 1 is switched on and then when number 2 is switched on it cancels
out the symmetrical error. Number 3 and 4 cancel their symmetrical error in the same
way and together with 1 and 2 they cancel the graded error as well.
As described earlier each thermometer coded current source is divided into four
separate current sources. This means that there will be four arrays of 255 current
sources. Each one of these arrays has their current sources placed according to the
switching scheme above. To further reduce the impact of gradients a common-
centroid layout scheme is used, meaning that all current sources will have a common
centre. This is accomplished by mirroring the four arrays about the centre. This
method works well to cancel linear gradients but does less to cancel parabolic
gradients.

5.1.7 Mismatch calculations

The mismatch model used was described in [6]. The reason for using this model is the
fact that it has been verified by measuring on a large amount wafers so that the results
are reliable. The model takes the VT and β mismatch into account where β = µCoxW/L
is the current factor. The VT mismatch is modelled as follows:
σVT 0 AVT 0
= ( 5.9 )
VT 0 WL
and β as
σβ A
= β0 ( 5.10 )
β WL
where AVT0 and Aβ are process dependent constants. This is where problems arise. To
find out what value these constants have. In the best case the value of these constants
are supplied by the manufacturer. If they are not one has to resort to approximations.
Fortunately the constants are mostly dependent on the process technology (gate size)
and not so much on the particular manufacturer.
In a current-steering DAC the mismatch of interest is that between current sources.
The formula below describes the mismatch in current in relation to VT and β
mismatch:
σ 2Id 4σ 2VT 0 σ 2β
= + ( 5.11 )
I d2 (VGS − VT 0 ) 2 β2
From this formula the current mismatch can be calculated given the size of the
transistor and its bias point (overdrive voltage).

24
5.2 MATLAB model
To study the impact of all the errors above together a MATLAB model was created.
The model consists of three files DAC.m which is the model of the DAC, swmatris.m
which generates the matrix for the switching scheme and run_DAC.m in which
simulation parameters are entered. The code for these files can be seen in Appendix
B. At first an ideal ADC is used to create the input signal to the DAC. Some noise is
added to the input signal of the ADC to avoid spurious tones in the final spectrum.
Parameters like those described above are fed into the model. These include noise,
gradients and output impedance for instance. A current source matrix is created in
MATLAB using the data on gradients and random errors (mismatch). An example of
how this matrix may look can be seen in Figure 5.3 below.

Figure 5.3 Distribution of current in sources depending on the location on chip

What it shows is the current distribution as a function of the location on chip.
To create the output current the currents from the different current sources are added
according to input signal and switching scheme. The current is then converted into a
voltage taking the limited output impedance into account. Finally the noise is added to
the output signal. A spectrum of the output is created using an FFT. The spectrum can
then be analyzed to calculate dynamic performance such as SFDR, SNDR and ENOB.
The advantage of MATLAB simulations as opposed to circuit simulations is speed.
MATLAB simulations are many times faster than a circuit simulator. This makes it
possible to run many simulations and look at yield figures.

5.3 MATLAB simulations

During all simulations the sample frequency was kept at 80 MHz, the input signal was
an 11 MHz sine wave (or ramp in the case of INL and DNL simulations). The current
source output impedance has a value of 8 MΩ if nothing else is stated. The noise
applied was extracted from cadence simulations and inserted into the model. The
linear and parabolic gradients were arbitrarily chosen to a value that seems reasonable
since there was no data available on such errors.

5.3.1 Simulating the nominal case

The figures below were simulated with a current source mismatch of 0.5 % and using
a hierarchical symmetric switching scheme. To look at yield figures 10000
simulations were run and the result was plotted as a histogram.

25
 Figure 5.4 Output spectrum.

Figure 5.5 SFDR. Figure 5.6 ENOB.

Figure 5.7 INL. Figure 5.8 DNL.

In Figure 5.4 a typical output spectrum from one of these simulations can be seen.
Figure 5.5 shows the number of DACs with a certain SFDR. Up to around 72 dB it
looks like normal distribution. After that there is a significant peak in number of
DACs. This is caused by the fact that the SFDR is limited by other factors than
mismatch. This causes the normal distribution to peak around 72.5 dB because there
is another spurious tone that is larger than the one caused by mismatch and noise.
Figure 5.6 shows the ENOB yield. It behaves more like normal distribution since it’s
dependent on SNDR, which is integrated over the entire spectrum and therefore more
dependent on noise and mismatch. Figure 5.7 and Figure 5.8 shows the static
performance in form of INL and DNL respectively. They also behave like normal
distributions although slightly skewed toward a lower value.

26
5.3.2 Simulating the impact of reduced matching
In the next following figures the impact of increased mismatch is shown by changing
current source matching from 0.5% to 1.5%.

Figure 5.9 Output spectrum.

Figure 5.10 SFDR. Figure 5.11 ENOB.

Figure 5.12 INL. Figure 5.13 DNL.

In Figure 5.9 the output spectrum is shown. It shows that there are a bit more and
larger spurious tones than before. Figure 5.10 shows the SFDR and it can be seen that
the result is still skewed toward a higher value but there are more DACs at lower
values. What is also interesting to note from this figure is that some DACs actually
have better SFDR than at 0.5 % mismatch. This is due to the fact that in a few cases
the mismatch actually cancels the effect of gradients. The ENOB plot in Figure 5.11
shows the same behaviour.

27
Figure 5.12 and Figure 5.13 showing INL and DNL shows more of a deterioration in
performance when mismatch increases. Not very many of the DACs are below the
wanted level of 0.5 LSB INL. At 1.5 % mismatch the equation ( 5.5 ) shown earlier
predicts that only 70 % of the DACs will be below 0.5 LSB INL. The simulations
suggest that it’s even fewer than that. This is most probably caused by the gradients
which aren’t taken into account in equation ( 5.5 ).

5.3.3 Simulating the impact of switching schemes

The next step is to study the impact of the switching scheme. For the results below the
current source matching is decreased to 0.5 % again. Instead of using the hierarchical
symmetric switching scheme the current sources are just placed in increasing order so
that the first current source resides in the upper left corner and the second one is one
step to the right an so on. The current source matrix still comprises of four quadrants
laid out in a common-centroid manner. From now on this will be referred to as the
conventional switching scheme.

Figure 5.14 Output spectrum.

28
 Figure 5.15 SFDR. Figure 5.16 ENOB.

Figure 5.17 INL. Figure 5.18 DNL.

As can be seen from the spectrum in Figure 5.14 the second harmonic overtone
becomes dominant and other spurs have also increased in amplitude. This is caused by
gradients that are not cancelled well in the conventional switching scheme. Since a
common-centroid layout is used the linear gradients are perfectly cancelled, the
parabolic gradients however, are not. From Figure 5.15 showing SFDR it can be seen
that the mean value has gone from around 72.5 dB to around 56 dB. That equates to a
loss of 16.5 dB in SFDR.
Looking at Figure 5.16, showing the ENOB, a significant loss in performance is seen
here as well. It has gone from 9.8 bits to 8.8 bits, which equates to a loss of 6 dB in
SNDR so it is not as bad as the SFDR.
In Figure 5.17 and Figure 5.18 where INL and DNL are shown it can be seen that the
INL has gone from around 0.5 LSBs to 2.9 LSBs. This is also caused by the fact that
gradients aren’t cancelled well in the conventional switching scheme. The DNL
however is not any different with this switching scheme. This is easily understood
since DNL is the difference between two adjacent current sources. This means that the
error is not that big since the distance between two sources is fairly small which
means that the change in current caused by gradients will be fairly small as well.

29
5.3.4 Simulating the impact of limited output impedance
Another interesting simulation that can be done is testing the impact of output
impedance. By lowering the output impedance in the model to 455 kΩ and looking at
the output spectrum. Figure 5.19 below shows the spectrum from this simulation.

Figure 5.19 Output spectrum.

The spectrum clearly shows that the third harmonic overtone is now the dominating
one as expected from the previous calculations. SFDR is around 60 dB, also expected
from the calculations above.

30
6 System implementation

6.1 System description

Since the DAC is meant for a zero IF transceiver, with the data stream modulated on
quadrature I and Q carriers, there are actually two DACs on the same chip. A
functional diagram of the DAC can be seen in Figure 6.1.

Figure 6.1 Functional diagram of the DAC.

The input signal passes through the input DFFs to make sure that the signal is in
synch with the clock. It is then split up so that 2 bits are passed directly to the latches
and 8 bits go through the binary-to-thermometer decoder. The binary-to-thermometer
decoder generates 255 control signals, which are then put in to the latch network.
From the latches the 2 binary bits are fed to their respective switch and the 255
control signals go into their switches. The switches are connected to the current
sources. The main matrix consists of 1020 thermometer current sources and 3 binary
current sources. When it comes to the thermometer coded current sources there are 4
sources connected to each switch. The binary switches have 1 and 2 current sources
for their respective bits. The switches are placed outside the current source matrix to
avoid interference between digital and analog parts.
To ensure that the control signals arrive to the switches at the same time a clock tree
is used to distribute the clock signal.
The two DACs have a common reference for better matching between the two. The
reference consists of a bandgap reference that generates a voltage, which is fed to the
voltage-current converter. The bandgap has a control signal that allows an external
reference to be used. This feature is realised by having a switch in series with the
bandgap output, which allows the bandgap to be disconnected from the voltage-
current converter. The voltage-current converter utilizes an external resistor to
generate the reference current. The reason for this is that an off-chip resistor has better
tolerance and less temperature dependency. It also gives the opportunity to measure

31
the voltage in that node. Since both input and output voltages from the voltage-to-
current converter are measurable the offset voltage in it can be calculated.

6.2 Implementation of sub-circuits

The sub-circuits in this chapter are tested under widely varying conditions. The first
step is usually to test on a schematic level. When a working circuit is made on the
schematic level a layout is created. From this layout the parasitic resistances and
capacitances are extracted. A simulation is done to see that the layout version behaves
the same as the schematic or at a level that is acceptable. To make sure that the final
fabricated circuit will work it is tested in the corners of the process. A corner is
defined as a worst case of sorts. It can be either a high/low temperature or some
maximum/minimum value specified in the process from the manufacturer or a
minimum/maximum supply voltage. The manufacturer guarantees that all process
variables will be within a certain interval and the corner defines the end point of this
interval. The process corners in this report are specified as typical, ff, ss, sf and fs
where typical is as the name implies the typical case. The rest are defined as where a
transistor N- or P-MOS is either fast or slow. For example ss means that both N- and
P-MOS are at their slowest. On top of this there is usually a worst-case corner as well.
In an amplifier this is usually ss, maximum temperature and minimum supply voltage
because this will give a minimum amount of voltage swing and slowest performance.

6.2.1 Current source

The main task for the current source is to provide a constant current over the entire
frequency and output voltage range. This means that the output impedance should be
as large as possible.

6.2.1.1 Theory
In its simplest form a current source for a differential current-steering DAC might
look like in Figure 6.2 below.

Figure 6.2 A simple current source.

The top transistor PM0 is the current source and PM1 and PM2 are the switches. The
signals driving the switches are complementary so that only one of the two switches is
on at any given time. The problem with the simple current source is its limited output
impedance. The output impedance can be increased by cascoding the current source.
In Figure 6.3 a cascode current source is shown.

32
 Figure 6.3 A cascoded current source.
In order to bias this current source and get the maximum possible voltage swing
available on the output, a wide-swing architecture is used [1]. It works by biasing
PM0 so that its drain-source voltage is as close to the minimum voltage possible
without going into the triode region. In order to achieve this the bias circuit shown in
Figure 6.4 is used.

Figure 6.4 Bias generation circuit.

6.2.1.2 Implementation
The size of the current source transistor is determined by mismatch calculations. It has
to have a certain area to achieve the required matching as described in section 5.1.7.
The size of the cascode is determined by simulations to achieve maximum output
impedance. The cascode will also have some impact on matching but the exact
numbers are hard to determine. The switches are made as small as possible to reduce
glitches on the output. One difference from the theory above is the fact that there are
four current sources connected to each switch for layout technical reasons.
When it comes to the bias circuitry there are some differences from the theory above.
Since there are only four bias circuits per DAC, because of area and power
constraints, each bias circuit is loaded by 255 current sources. To keep the reference
voltages stable the current in each bias circuit is 8 times the current in one current
source. This lowers the output impedance of the bias circuit. To further help keeping
the voltage stable both Vb1 and Vb2 are decoupled to VDD_A. The reason for
connecting the decoupling capacitor to VDD instead of GND is that the output current
is determined by Vgs-PM0, which is referred to VDD.

6.2.1.3 Results
Shown in Figure 6.5 is the result from a simulation on output impedance. In order to
achieve 10-bit performance the output impedance in one current source has to be
larger than 455 kΩ. The smallest unit is four current sources connected through one
switch and that is what has been simulated. This means that in the figure below the

33
value has to be above 113,75 kΩ in order to achieve 10-bit performance. This is true
for all frequencies below 635 MHz. Which means that theoretically this is the limit on
the analog bandwidth.
This limited output impedance causes a gain error at higher frequencies as described
earlier. In Table 6.1 the gain error in % can be seen versus frequency.
Another important parameter when it comes to the current source is the amount of
noise that one current source produce. As describe earlier in section 5.1.5 the noise
level has to be lower than the quantization noise. Simulations show that one current
source has about 303 nV RMS noise. Using equation ( 5.8 ) one can calculate the
SNR of the DAC. The load resistor is 60 Ω and differentially this equates to a voltage
noise of 8.9 µV RMS with a bandwidth of 40 MHz. The quantization noise has a
value of 169 µV RMS with a 600 mV full-scale voltage. Putting these numbers into
the equation for SNR yields a value of 61.94 dB, which is very close to the theoretical
maximum of 61.96 dB.

Figure 6.5 Output impedance versus frequency.

Output frequency [MHz] Gain error [%]

1 0.02

8.125 0.2

16 0.38

32 0.77

64 1.53

128 2.95

256 5.66

Table 6.1 Gain error versus frequency.

34
6.2.2 The binary-to-thermometer decoder
6.2.2.1 Theory
A systematic approach of the binary to thermometer decoder is based on a 2-bit
converter [7]. To increase the number of binary inputs, a new logic level is added for
each extra bit. Truth tables and De Morgan’s laws are used between every stage to
find the optimum number of gates.

Figure 6.6 A 2-bit inverting binary to thermometer decoder.

This results in an arbitrary equation for every level of even or odd binary bits. The
equations are shown below. The left equation is for even, and the right for odd bits. N
is the number of binary bits, and tx inside the brackets is the output from the previous
stage.
⎧t x + bN −1 ,0 ≤ x < 2 N −1 − 1 ⎧t ⋅ b ,0 ≤ x < 2 N −1 − 1
⎪⎪ N −1
⎪⎪ x N −1
t x = ⎨bN −1 , x = 2 − 1 t x = ⎨bN −1 , x = 2 N −1 − 1
⎪ N −1 ⎪
⎪⎩t x − 2 N −1 ⋅ bN −1 ,2 − 1 < x ≤ 2 − 1
N
N −1
⎪⎩t x − 2 N −1 + bN −1 ,2 − 1 < x ≤ 2 − 1
N

( 6.1 ) ( 6.2 )
This method makes it easy to automatically generate a schematic with the desired
number of inputs.

Figure 6.7 Even respectively odd binary number of inputs at schematic level.

35
6.2.2.2 Design

A SKILL script was written to generate the decoder schematic. The script can be
found in Appendix C. When adding an input bit, it gets a large fan-out, 2 N − 1 . In this
8-bit converter the binary MSB’s were buffered to compensate for the increasing rise
and fall time.

Verilog-XL produces a verilog netlist when a simulation is executed, and that netlist
was used to import the design into Silicon Ensemble.

The matrix signals must be rearranged somewhere between the Flip-Flops and
switches to fit our switching scheme. To facilitate the layout work, the output pins
placements were changed in SE.

By combining GDS and DEF-exports from SE, the design was imported back to
Cadence Virtuoso for DRC, extraction, LVS, simulation and some post route
optimization [8].

Figure 6.8 Design flow for the binary to thermometer decoder.

6.2.2.3 Results
The simulated maximum delay through the decoder was 645 ps on a schematic level,
which is more than enough with our clock strategy. Since there is a delay of 50 ps
between the clock to the flip-flops and the latches the actual delay will be 695 ps. This
delay sets the DAC’s highest update rate to 720 MHz. The extra delay is there to
make sure that the latch is in its non-transparent mode when new data is clocked in.
The flip-flop is triggered on the positive edge and the latch is in its transparent mode
when the clock is high and in its latched mode when the clock is low.

36
 Figure 6.9 The decoder’s maximum tolerated delay at 80 MSPS.

6.2.3 Latches
6.2.3.1 Theory

A matrix of latches is used to synchronize all thermometer-coded bits with the binary
ones. The output bits are differential and connected to the switch array. The outputs
are designed to switch on one side before it switches off the other because we want to
keep the current sources from turning off during switching. The outputs intersect just
above zero volts since the switches are made with PMOS transistors.

Figure 6.10 Desired outputs from the latches.

8 bits converted to thermometer code and 2 binary bits results in 257 latches, which
will dominate the total digital power consumption. This, combined with the desired
intersection point of the outputs, made it impossible to use standard cells.

6.2.3.2 Design
The latch is based on a modified clocked SR-flip-flop [9]. The set and reset inputs are
replaced with data and inverted data, D and DN in Figure 6.11 below.

37
 Figure 6.11 Schematic of the latch.
The first inverters have slow N and fast P-transistors to delay signals with rising
edges, and the last inverters buffers the outputs. NM8 and NM9, the clock transistors,
are minimum size to reduce clock feed through. The buffers also contribute to this.

The current source matrix layout sets the switch array height, which is equal to the
height of the latches to simplify their connections. There are 32 rows of latches in the
array, the same as the switches and current sources. Since there are 8 thermometer and
2 binary bits, it results in 8 latches per row, and one row with an extra latch. To
prevent skew between the outputs of this large block, a clock tree was implemented.

6.2.3.3 Results
The output delays when receiving a positive edge from the clock tree are shown in
Table 6.2. The arrows stand for rising or falling edges of the signal.

clk ↑ t [ps]

D↑ 225

DN ↓ 163

D↓ 216

DN ↑ 291

Table 6.2 The maximum output delay without clock tree.

38
The switch is on when Vg drops below 180 mV, which is the maximum required
intersection point. This was achieved at all corners. See Table 6.3.

VDD T Intersection point [mV]

[V] [°C]
Typical ss sf fs ff

0 6 4 30 4 9
1.65
110 17 11 68 7 26

0 9 6 44 5 14
1.8 27 12 8 52 6 17

110 25 17 86 11 36

0 13 9 56 6 19
1.9
110 30 22 100 13 44

Table 6.3 The intersection points at all process and environmental corners.
There is clock feed through when data is stored on the latch. The first inverter reduces
this spike by 23.4 dB. And the buffer decreases it with 17.3 dB.

39
6.2.4 Bandgap reference
6.2.4.1 Theory
The basic idea behind a bandgap reference is to create a stable voltage reference
independent of process variations and temperature. The basic principle of the bandgap
is to use a forward biased diode (base-emitter junction) as a base for the reference
voltage. Because the voltage over the base-emitter junction has a negative temperature
coefficient one has to compensate for this by adding a voltage that is proportional to
absolute temperature (PTAT). The PTAT is realized by amplifying the voltage
difference between two forward biased junctions biased at different current densities.
Figure 6.12 below shows the conventional bandgap architecture in a CMOS process.
Although independent bipolar transistors are not available in CMOS, well transistors
with their collector connected to the substrate (ground in a p- substrate) usually are.

Figure 6.12 The conventional bandgap architecture.

It can be shown [1] that to get a zero temperature coefficient at some temperature T
the following demand must be met:
∂Vref ⎛ ⎞
=
1
(VBE 0−2 − VG 0 ) + K k ln⎜⎜ J 2 ⎟⎟ + (m − 1) k ⎛⎜⎜ ln⎛⎜ T0 ⎞⎟ − 1⎞⎟⎟ = 0 ( 6.3 )
∂T T0 q ⎝ J1 ⎠ q⎝ ⎝T ⎠ ⎠
where T0 is the reference temperature, VBE0-2 is the base emitter voltage for Q2 at the
reference temperature, K is a factor dependent on the different current densities, k is
Boltzmann’s constant, q is the elementary charge and m is a temperature constant
approximately equal to 2.3.
By solving ( 6.3 ) and identifying Vref it can be shown that:

Vref −0 = VG 0 + (m − 1)
kT0
( 6.4 )
q
where VG0 is the bandgap voltage of silicon at 0 K (equal to 1.206 V).
In the case where T0 = 300 K this implies that:
Vref −0 = 1.24V ( 6.5 )
for zero temperature dependence. Which is basically the bandgap voltage plus a
correction term for second order effects, hence the name bandgap reference for this
type of reference.

The problem with the conventional bandgap is that in a 0.18 µm process the 1.24 V
output voltage referred to ground leaves little headroom to the supply voltage, which
normally sits at 1.8 V. In the DAC, the bandgap reference voltage is fed to a voltage-

40
to-current converter, which creates the reference current for the current sources. Since
getting this converter to work with an input voltage that close to the supply voltage is
fairly hard it is desirable to have an output voltage from the reference that is closer to
ground.
For reasons stated above the architecture chosen for the bandgap is a low-voltage one
[10]. The advantage with this kind of architecture is that it gives a larger margin to the
supply voltage. Another nice feature of this architecture is the fact that the output
voltage is easily changed.

6.2.4.2 Implementation
The low voltage architecture implemented is shown below in Figure 6.13. The basic
principle of this architecture is the same as for the conventional one. It uses two
junctions biased at different current densities. Since PM1 and PM3 are biased equally
and are of the same size the current through Q0 and Q1 is identical. To get a different
current density through Q0 and Q1 transistor Q1 is made larger than Q0. Practically,
this is solved by paralleling a number of identical devices. The output voltage from
the bandgap can, according to [10], be written as:
⎛V dV ⎞
Vref = R3 ⎜⎜ f 0 + f ⎟⎟ ( 6.6 )
⎝ R2 R5 ⎠

where Vf0 is the voltage over Q0 and dVf is the voltage over R5. For a more detailed
description of the bandgap see [10]. As seen from ( 6.6 ) the output voltage is only
dependent on the ratio between the resistors and not on the absolute value.

Figure 6.13 Schematic of the low-voltage bandgap architecture.

Other things that can be noticed in the schematic are the three rightmost transistors
that work as a startup circuit for the bandgap. It is simply made up of an inverter
where PM5 has a small W/L ratio and NM1 has a fairly large W/L ratio. If Vref is
lower than the threshold voltage for NM1 the inverter output will go high which will
turn on transistor NM5. NM5 pulls the gate voltages on PM1, PM2 and PM3 low,
which force the bandgap to reach its normal bias point. When the output reaches its
nominal value the inverter will go low and turn off NM5 and the bandgap returns to
its normal operation. Another detail to be noted is C0, which sits there to stabilize the
circuit.

41
With this type of circuit in an on-chip environment it’s hard to analytically calculate
the values of the resistors. This is because the resistor values are also dependent on
temperature. To solve this problem the optimizer function in cadence was utilized. It
works by giving it a number of variables to sweep and a few demands to meet. In this
particular case the values of R4 and R2 were set and R5 and R3 were swept. The
demands to meet were set as an absolute value as close to 500 mV as possible and
Vref-max –Vref-min lower than 300 µV from 0 to 110º C.
During the layout phase a few things were taken into consideration. Since the ratios
between the resistors sets the output voltage and also affects the temperature stability
it’s important that the resistors are well matched. To assure adequate matching the
resistors were divided into unit blocks of similar size. These unit blocks are then
distributed evenly over the total area that the array of resistors consumes. To ensure
that the matching is adequate after all the unit blocks are connected together one has
to consider the impact of parasitic resistance. The parasitic resistance comes from
interconnect wires and contacts. The resistor array has been laid out so that the
relative error caused by parasitic resistance is the same for all resistors.
The bipolar transistors also have to be well matched. To ensure good matching a
common centroid layout scheme was used. By placing Q0, which is a single
transistor, in the middle and the individual blocks that make up Q1 around it a square
matrix with a common centre for both Q0 and Q1 was created. An outer ring of
dummy transistors ensures that all transistors have an equal surrounding environment.

6.2.4.3 Results
Simulations were run over the specified temperature range of 0-110 ºC to verify its
function. In Figure 6.14 below the output voltage vs. temperature can be seen in the
typical case with a supply voltage of 1.8 V. Simulations were also run in the different
process corners and different supply voltages to make sure that the bandgap operates
properly under worst case conditions. The results of these simulations can be seen in
Table 6.4 below.
For future reference it was also interesting to see how low the supply voltage could go
before the output strays to far from the nominal value. The result of this can be seen in
Figure 6.15 below. The conclusions that can be drawn from this figure is that the
bandgap works very well down to around 1.2 V supply voltage.
The influence of power supply noise was investigated by looking at the power supply
rejection ratio, PSRR. The simulation was run with an external capacitor of 470 pF
through a model of the bond wire. A plot of PSRR versus frequency can be seen in
Figure 6.16. The PSRR is good at low and medium frequencies. At low frequencies
because the opamp gain is high there and the feedback loop will eliminate a lot of the
noise. At medium frequencies the capacitor on the output will attenuate the noise. At
high frequencies it’s very hard to eliminate the noise because the external capacitor’s
effectiveness is limited by the bond wire.
Finally a test was made to see how long it takes for the output voltage to stabilize
after power on. The simulation was done with an off-chip capacitor with a value of
470 pF. This value was chosen because up to this value the increase in PSRR is
notable. Any larger than this provides very little gain in PSRR and only increases
startup time. The result is shown in Figure 6.17 below. The first part of the curve is
where the startup circuit is still on and provides extra current to charge the external
capacitor. Around 350 mV the startup circuit deactivates and the capacitor is charged
with a constant current.

42
 Figure 6.14 Reference output voltage versus temperature.

Corner VDD [ V ] Absolute Vout @ 27 °C ∆Vout ∆Vout/(Vout Power

resistance for 0 –110 °C @ 27 °C) consumption
variation [mV] [mV] [%] @ 27 °C
[µW]

typical 1.65 -15 % 502.4 0.73 0.15 166

typical 1.8 -15 % 502.3 0.85 0.17 185

typical 1.9 -15 % 502.2 0.9 0.18 199

typical 1.65 0% 500.3 0.33 0.066 160

typical 1.8 0% 500.2 0.28 0.056 179

typical 1.9 0% 500.2 0.3 0.060 193

typical 1.65 + 15 % 499.0 0.64 0.13 156

typical 1.8 + 15 % 498.9 0.57 0.11 174

typical 1.9 + 15 % 498.9 0.53 0.11 187

ss 1.9 -15 % 502.2 0.9 0.18 195

ff 1.9 -15 % 502.2 0.9 0.18 201

sf 1.9 -15 % 502.3 0.9 0.18 202

fs 1.9 -15 % 502.1 0.9 0.18 193

Table 6.4 Output voltage and relative error in different process corners.

43
Figure 6.15 Output voltage versus supply voltage.

Figure 6.16 PSRR versus frequency.

Figure 6.17 Transient response during startup.

44
6.2.5 Voltage-to-current converter
6.2.5.1 Theory
Since the reference has a voltage output and a current reference is needed for the
current sources a design is needed to convert between the two. Figure 6.18 below
shows the basic concept behind the converter [11].

Figure 6.18 Schematic of voltage-to-current converer

The same basic function could be performed using only the transistor and resistor.
However it would not be as accurate and not as temperature stable. The simple circuit
would have a transfer function like below:
1⎛ 1 ⎞
I ref = ⎜⎜ ⎟Vin ( 6.7 )
R ⎝ 1 + 1 / g m R ⎟⎠
So what the opamp in the above figure does, is to work as a gain-boost for the
transistor and it essentially increases the transconductance of the overall circuit so that
the transfer function looks like below instead:
⎛ ⎞
⎜ ⎟
1⎜ 1 ⎟
I ref = ⎜ ⎟Vin ( 6.8 )
R⎜ 1⎛ 1 ⎞⎟
⎜ ⎟
⎜ 1 + A ⎜1 + g R ⎟ ⎟
⎝ ⎝ m ⎠⎠
where A is the open-loop gain of the opamp. If the gain is large enough it can be
approximated by:
V
I ref = in ( 6.9 )
R
so that the current is only dependent on the input voltage and the resistor value.

6.2.5.2 Implementation
In this design the opamp was realized with a folded-cascode architecture [11]. The
advantage of this is that the converter is fully functional down to 0 V input voltage. In
Figure 6.19 the schematic of the converter is shown.

45
 Figure 6.19 Schematic of the complete voltage-to-current converter
The purpose of the converter is, as stated, to generate the reference currents for the
DAC. Each DAC needs 8 reference currents since the bias is distributed over the chip.
Since there are two DACs the total number of currents needed is 16. In Figure 6.19,
only three of these are shown. To generate all these currents the output current from
the converter is mirrored through PM11 and PM12 down to NM20, which forms a
current mirror with the 16 output transistors.
The capacitor on the output of the opamp is there to stabilize the circuit. Since Vout is
fed to an off-chip resistor it will have to pass through a bond-wire. This will make the
whole circuit susceptible to instability by decreasing the phase margin. It is therefore
important to make the capacitor slightly larger than it would be with an on-chip
resistor.

6.2.5.3 Results
Important things to check for in a design like this are stability, linearity and
temperature stability. In Figure 6.20 below the AC response is shown. Phase margin
in this figure is around 82º. With a model of the bond wire and external parasitic
capacitance connected to Vout, phase margin is degraded to around 75º leaving plenty
of margin for unforeseen effects.
Linearity in this case means how well the output current tracks the input voltage. The
easiest way to verify this is by looking at the output voltage versus input voltage since
the voltage over the resistor determines the output current. The results of this can be
seen in Figure 6.21. The converter is linear within 0.5% from 100 mV to 850 mV. The
error around its intended working voltage of 500 mV is 0.02%. The degradation in
performance at lower and higher voltages is caused by lower loop-gain in the opamp
when its output voltage comes closer to the supply.
Temperature versus out current if plotted in Figure 6.22. It shows that the output
current changes around 90 nA from 0-110ºC. This equates to a 0.2 % change in output
current.

46
Figure 6.20 Bode plot of the voltage-to-current converter

Figure 6.21 Output versus input voltage

Figure 6.22 Reference current versus temperature

47
6.2.6 Voltage-to-current converter bias circuitry
6.2.6.1 Theory
The opamp used in the V-I converter is a folded-cascode architecture. This means that
it needs four different bias voltages. Two for the current source on the N- and P-side
respectively and two for the cascodes on each side.
The bias net used is depicted in Figure 6.23 below.

Figure 6.23 Schematic of the bias circuitry.

This type of bias circuit is called stable transconductance [1]. This is because it keeps
gm of the transistors in the opamp stable regardless of supply voltage, process and
temperature variations. It works by stabilizing the transistors transconductance to the
resistors conductance as shown in [1].

6.2.6.2 Implementation
The four rightmost transistors work as a startup circuit. The startup circuit is
necessary because the bias circuitry has two stable states, one being its normal
operating region the other being zero current.
R0 is the resistor that stabilizes the transistor transconductance. In this case it’s
realized with an on-chip resistor. It could be realized with an off-chip resistor but the
external parasitics can cause oscillation. The disadvantage to using an on-chip resistor
is the fact that its value is dependant on temperature and that its absolute value will
have a large variation. The temperature coefficient is fairly low and shouldn’t be a
problem though.

6.2.6.3 Results
The performance aspects of interest can only be tested together with the V-I
converter. If it works the way it’s supposed to it shouldn’t have any effect on the
performance of the V-I converter.

48
7 Results and conclusion

7.1 The complete system

A layout of the complete system can be seen in Figure 7.1 below.

Figure 7.1 Layout of the complete chip

The bandgap reference and voltage-to-current converter resides in the middle of the
chip. On each side of it there is one DAC, one for the I-channel and one for the Q-
channel as described earlier. The lower part of the DAC is the current source matrix.
The part above that, that resembles an arrow, is just the interconnect wiring from the
matrix to the switches. The next part above that consists of switches, latches, digital
decoding net and DFFs. Everything outside the main layout consists of decoupling
capacitors.

7.2 Challenges of system simulations

The complete quadrature DAC and bandgap ends up being around 19000 transistors.
This makes simulations on the complete system fairly difficult and mostly time
consuming. It is not too difficult on a schematic level but the results provided from it
are not good enough to accurately predict the final chip behavior. This is because
parasitics in interconnect wires and circuits to a large extent determine the
performance of the system. The problem encountered when trying to simulate with
extracted parasitics is that it is extremely time consuming. Another problem is the fact
that the layout of the complete system is so complex that the extraction tools can not
do an extraction of the whole chip. The only way to get somewhat accurate results is
by running the most critical blocks with extracted parasitics and less critical blocks in
schematic.

49
Another difficulty during the final stages of simulation is the impact of bond wires on
performance. This is mainly because there are no good models for the bond wires and
a small change in the model leads to large changes in performance.

7.3 Simulation results

The DAC was tested with the specified load of 60 Ω at 80 MSPS. The input signal
was an 11 MHz sine wave. The outcome of this simulation can be seen in Figure 7.2.

Figure 7.2 Differential sine wave current output.

As can be seen from this plot the response is fairly controlled with some minor
glitches before a transition. The simulation was done without bond wires for reasons
explained earlier.
Estimated power consumption is around 22 mW for both DACs and bandgap
reference. Of these 22 mW 2mW is consumed in the digital parts and 20 mW is
consumed in the analog parts. The power wasted in the pads is not included in this
figure.

7.4 Conclusions
Is has been shown that it’s possible to design a 10-bit DAC in a 0.18µm CMOS
process. It has been shown that there are three limits on the update rate of the
converter and one of them will decide the final update rate. The first limit is output
impedance, which places a limit on the highest output frequency that can be
reproduced without too much distortion. This doesn’t really limit the update rate
unless operation up to Nyquist is wanted. In this converter the maximum output
frequency is limited to 635 MHz, which, if operation up to Nyquist is desired, limits
the update frequency to 1.27 GHz. The second limit is imposed by the digital net
because of its delay. The data from the digital net must be available within half a
clock cycle. The delay through the digital net is 695 ps, which limits the update rate to
720 MHz. Another limiting factor is the slew-rate of the output or settling time. The
DAC has to settle before the next step is taken. The settling time is around 2 ns, which
limits the update frequency to 500 MHz. Finally there is actually one more limit on

50
update frequency that is much harder to decide. That is the one caused by noise on
supply lines and ringing on the output both of which are caused by bond wires.
The biggest challenge is to accurately model all errors that are not shown in a circuit
simulator such as noise and mismatch. There are also many other unknown factors
that might degrade performance such as substrate coupling, crosstalk between digital
and analog and the impact of bond wires.

7.5 Possible improvements for future development

The most probable cause of error in the chip is power supply noise. Preliminary
simulations show that noise from the digital supply can get coupled over to the output
signal. So in future versions some way of isolating the digital supply from the analog
parts might have to be implemented. Measurements will show how much of a
problem this really is.

51
52
8 Measurements

8.1 Introduction
All measurements have been performed with a single-ended load of 50 Ω and a full-
scale current of 5 mA. During dynamic measurements the differential signal was
converted to a single-ended signal using a balun. The output signal was analyzed
using a spectrum analyzer. During the static measurements the differential-to-single-
ended conversion was done with a precision opamp and the output was measured with
a multimeter.

8.2 Static measurements

To verify the function of the bandgap reference its output voltage was measured on
two different chips. The nominal output was 500 mV. On one chip it was measured to
499 mV and the other was measured to 511 mV.
INL and DNL were measured by using a ramp as input signal to the DACs. The
results are presented below:

Figure 8.1 I-DAC DNL Figure 8.2 Q-DAC DNL

Figure 8.3 I-DAC INL Figure 8.4 Q-DAC INL

53
As can be seen DNL is within ±0.4 LSB and INL within ±0.6. Due to noise during the
measurements the measured results are slightly pessimistic. To make more accurate
measurements it would have been preferable if one could have taken the mean value
of several measurements instead of just one. Due to time constraints this was not
possible, however, a short measurement series was done by taking the mean value of
4 measurements on each level for the first 100 data values. It could be seen that the
performance was slightly better than the one presented above.

8.3 Dynamic measurements

To determine the DACs dynamic performance SFDR, THD, SNDR and ENOB were
measured. The results from these measurements can be seen below:

fsignal SFDR [dBc] @

[MHz]
40 [MSPS] 80 [MSPS] 125 [MSPS] 175 [MSPS]

0.756 78 77 77

1.7 73 73 73 73

3.3 73 72 71

5.5 67 68 69 67

7.3 65 70 68

9.7 60 69 67 63

13 57 66 65

17 54 62 65 62

22 61 61

37 55 54 58

47 57

61 52 52

86 49

Table 8.1 Measured SFDR performance at different update rates

fsignal THD [dB] @

[MHz]
40 [MSPS] 80 [MSPS] 125 [MSPS] 175 [MSPS]

0.756 -72.2 -71.4 -71.0

1.7 -67.4 -70.8 -69.2 -68.0

3.3 -68.0 -68.4 -66.9

5.5 -64.6 -63.9 -61.9

7.3 -62.7

9.7 -60.0

Table 8.2 Measured THD performance at different update rates

54
 Figure 8.5 ENOB versus signal frequency

From Table 8.1 and 8.2 it can be seen that the performance is good for all but the
highest frequencies. Figure 8.5 shows the ENOB versus signal frequency at 80 MSPS.
It can be seen that the performance is good all the way up to 22 MHz. There were
some problems during the measurements with the equipment used. Due to the fact that
the clock from the pattern generator deteriorated the performance an external clock
source was used. The external source triggered the pattern generator, which sent the
data to the DAC. It proved to be difficult getting this to work perfectly due to the
internal delay of the pattern generator. This might have caused some deterioration of
the measured performance.

55
Below some typical output spectrums are presented:

Figure 8.6 Measured output spectrum at 80 MSPS with a 9.7 Mhz input signal

Figure 8.7 Measured output spectrum at 80 MSPS with a 22 Mhz input signal

56
9 References

[1] David A. Johns and Ken Martin, ”Analog Integrated Circuit Design”, John
Wiley & Sons Inc, ISBN 0-471-14448-7.
[2] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, “CMOS Data
Converters for Communications”, Kluwer Academic Publishers, 2000, ISBN 0-
7923-7780-X.
[3] A. Van den Bosch, M. Steyaert & W. Sansen “SFDR-Bandwidth limitations for
high-speed high-resolution current-steering CMOS D/A converters”, in Proc.
IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999,
pp.1193 –1196.
[4] Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert and Willy
Sansen, ”A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A
Converter”, IEEE Journal of Solid-state Circuits Vol. 36, March 2001.
[5] Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh and
Nobuharu Yazawa, ”A 10-b 70-MS/s CMOS D/A Converter”, IEEE Journal of
Solid-state Circuits Vol. 26, April 1991.
[6] Marcel J. M. Pelgrom, AAD C. J. Duinmaijer, Anton P. G. Welbers, ”Matching
Properties of MOS Transistors”, IEEE Journal of Solid-state Circuits Vol. 24,
October 1989.
[7] K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, and J. Jacob
Wikner, “A 14-Bit Dual Current-Steering DAC”, SSoCC, 2003.
[8] H. Hassander and C. Lindholm, ”Simulering, layout och verifiering av mixed-
mode-kretsar i Cadence”, Del av rapport i IC-projekt – Electroscience LTH ,
Maj 2003.
[9] Jan M. Rabaey, “Digital Integrated Circuits a Design Perspective”, Prentice
Hall International, 1996, ISBN 0-13-394271-6.
[10] Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru
Tanzawa, Shigeru Atsumi and Koji Sakui, ”A CMOS Bandgap Reference
Circuit with Sub-1-V Operation”, IEEE Journal of Solid-state Circuits Vol. 34,
May 1999.
[11] Johan H. Huijsing, “Operational Amplifiers Theory and Design”, Kluwer
Academic Publishers, 2001, ISBN 0-7923-7248-0.

57
58
Appendix A

The following pages shows the Taylor expansion done in Maple. The first one is the
single-ended case and the other one is the differential.

Single-ended:
//The output signal as a function of gimp=1/Rl
> f:=N*Ir*(x+1)/(2*gl+gimp*N*(x+1));

//Taylor expansion to the 5th order

> tay:=mtaylor(f,x,5);

//Replace x with sin(wt) to be able to identify harmonics

> tayt:=subs(x=sin(wt),tay);

//Break out all terms containing sin or cos

> tayc:=combine(tayt,trig);

//Calculate the coefficient for cos*(2wt) which is the

//second harmonic
> HDS:=coeff(tayc,cos(2*wt));

//Calculate the coefficient for sin(wt) which is the

//signal
> A:=coeff(tayc,sin(wt));

59
//Set the demand on SFDR to at least 60 db
> Q:=simplify(HDS/A)=.001;

//Load equals 60 ohms

> gl:=1/60;

//10 bits gives N=1024

> N:=1024;

//Solve for gimp

> gimp:=fsolve(Q,gimp);

//The minimum needed output impedance becomes

> R:=1/gimp;

Differential:
//The output signal as a function of gimp=1/Rl
> f:=N*Ir*(x+1)/(2*gl+gimp*N*(x+1));

//The complementary output signal

> fc:=-subs(x=-x,f);

//Taylor expansion to the 7th order

> tay:=mtaylor(f,x,7);

//Taylor expansion to the 7th order of the complement

> tayc:=mtaylor(fc,x,7);

//Create the differential signal. Removes odd order

//harmonics
> taydiff:=tay+tayc;

60
//Replace x with sin(wt) to be able to identify harmonics
> tayt:=subs(x=sin(wt),taydiff);

//Break out all terms containing sin or cos

> taycomb:=combine(tayt,trig);

//Calculate the coefficient for sin(3wt) which is the

//third harmonic
> HDS:=-coeff(taycomb,sin(3*wt));

//Calculate the coefficient for sin(wt) which is the

//signal
> A:=coeff(taycomb,sin(wt));

//Set minimum SFDR to 60 dB

> Q:=simplify(HDS/A)=0.001;

//Set load to 60 ohms

> gl:=1/60;

//10 bits gives N=1024

> N:=1024;

//Solve for gimp

> gimp:=fsolve(Q,gimp);

//The minimum needed output impedance becomes

> R:=1/gimp;

61
62
Appendix B

Here are the MATLAB programs that were written to simulate the function and the
impact of different errors on the DAC.

function [SFDRar,nobbar,maxinl,maxdnl,Itot]=
DAC(nSample,Fsamp,Fsig,overtoner,noit,funk,sv);

%ADC

%Ramp
if (funk==1)
data = [0:1:1023];
end
%Sin
if (funk==2)
w = 2*pi*Fsig;
tid = [0:nSample-1]./Fsamp;
brus = 0.3*rand(size(tid));
data = round(1023*(1+sin(w*tid))/2+brus);
end
%OFDM
if (funk==3)
Fsig=(312.5e3:312.5e3:26*312.5e3);
w=2*pi.*Fsig;

tid=[0:nSample-1]./Fsamp;
phi=2*pi*rand(26);
sig=zeros(26,nSample);
for i=1:26
sig(i,:)=0.07807*sin(w(i)*tid+phi(i));
end
sigtot=sum(sig);
brus = 0.3*rand(size(tid));
data = round(1023*(1+sigtot)/2+brus);
end

%DAC

Rimp = 8e6;%Vid 20 MHz

Rl= 60;
N =1023;

Iref=5e-3/N;
sd=0.502/100;
gradient=4/400;
gradpolx=5/400;
gradpoly=5/400;
Lnoise=6.3e-6;
Inoise=3.03e-7;

%Konventionell symmetrisk matris

%i=1;
%for k=1:16
% for l=1:16
% imatris(k,l)=i;

63
% i =i+1;
% end
%end

%Generera hierarkiskt switchad matris

[imatris]=swmatris;

%Generera gradienter
t=[-1:2/31:1];

xpolgrad=-gradpolx*t.^2-gradpolx;
ypolgrad=-gradpoly*t.^2+gradpoly;

xgrad=[0.5-gradient:2*gradient/31:0.5+gradient]+xpolgrad;
ygrad=[0.5-gradient:2*gradient/31:0.5+gradient]+ypolgrad;

for k=1:32
for l=1:32
gradmat(k,l)=xgrad(k)+ygrad(l);
end
end

%Sortera strömmatrisen så att koordinaterna för källa 1 ligger först

i vektorn ims
for k=1:255
[a,b]=find(imatris==k);
ims(k,:)=[a,b];
end
imsp=ims;
imsn=flipud(ims);

%Starta iterationsprocessen
for j=1:noit

%Generera strömkällor
Irefs=Iref+Iref*sd*randn(32,32);
Ibin=Iref+Iref*sd*rand(1,3);
Ibinp=Ibin;
Ibinn=fliplr(Ibinp);

Itot=Irefs.*gradmat;

%Spara strömmatrisen
if (sv==1)
save strom_matris Itot
else
load strom_matris
end

%Generera brus
Noisetot=sqrt(N*Inoise^2+2*Lnoise^2)*randn(size(data));

%Räkna fram total ström genom att räkna fram varje summa av
strömkällor
Iutsump=zeros(1,1024);
Iutsumn=zeros(1,1024);
for i=1:4:1020
for k=1:3
Iutsump(i+k)=Iutsump(i+k-1)+Ibinp(k);
Iutsumn(i+k)=Iutsumn(i+k-1)+Ibinn(k);
end

64
 rowp=imsp(fix(i/4)+1,1);
colp=imsp(fix(i/4)+1,2);
rown=imsn(fix(i/4)+1,1);
coln=imsn(fix(i/4)+1,2);
%Summera källorna enligt common-centroid (varje kvadrant flippad
%så att enskilda källor får gemensamt centrum)
Iutsump(i+4)=Iutsump(i)+Itot(rowp,colp)+Itot(rowp,33-colp)+Itot(33-
rowp,33-colp)+Itot(33-rowp,colp);
Iutsumn(i+4)=Iutsumn(i)+Itot(rown,coln)+Itot(rown,33-coln)+Itot(33-
rown,33-coln)+Itot(33-rown,coln);
%Summera källorna utlagda likadant (ingen rotation av kvadranter)
%Iutsump(i+4)=Iutsump(i)+Itot(rowp,colp)+Itot(rowp,17-
colp)+Itot(17-rowp,17-colp)+Itot(17-rowp,colp);
%Iutsumn(i+4)=Iutsumn(i)+Itot(rown,coln)+Itot(rown,17-
coln)+Itot(17-rown,17-coln)+Itot(17-rown,coln);

end
for k=1022:1024
Iutsump(k)=Iutsump(k-1)+Ibinp(k-1021);
Iutsumn(k)=Iutsumn(k-1)+Ibinn(k-1021);
end

for i=1:length(data)
Ioutp(i)=Iutsump(data(i)+1);
Ioutn(i)=Iutsumn(1024-data(i));
end

%Räkna ut utspänningen
voutp= (2*Ioutp)./((2/Rl)+(1/Rimp)*2*data);
voutn= (2*Ioutn)./((2/Rl)+(1/Rimp)*(2046-2*data));

Idiff=Ioutp-Ioutn;
vdiff=voutp-voutn+Noisetot;
Vref1=max(vdiff)-min(vdiff);
Vref=600e-3;

%Utför analys av resultatet beroende på vilken test som körts

if funk==1
A=[ones(size(data))', data'];
yfnutt=vdiff';
c = A\yfnutt;

inl=(vdiff'-A*c)./(Iref*Rl);
for m=1:length(data)-1
dnl(m)=(vdiff(m+1)-vdiff(m)-2*Iref*60)/(Iref*60);
end
maxdnl(j)=max(abs(dnl));
MaxDNL=maxdnl(j)
maxinl(j)=max(abs(inl));
MaxINL=maxinl(j)
SFDRar=0;
nobbar=0;
j
end

matrX=[1:32];
matrY=[1:32];

if funk==2
fullfft;

65
 FOM
nob1=FOM(63:67);
SFDRvar=FOM(44:48)

figure(1)
SFDRvar=str2num(SFDRvar);
SFDRar(j)=SFDRvar;
nob1=str2num(nob1);
nobbar(j)=nob1;
maxinl=0;
maxdnl=0;
j
end

if funk==3
fullfft;
FOM
nobbar=0;
SFDRar=0;
maxinl=0;
maxdnl=0;
end

end

66
function m=swmatris();

m=zeros(4,8);
mtmp=zeros(8,8);

i=1;
for j=1:4
m(i,j)=256 - 4*(j-1);
end
for k=1:4
m(i,j+k)=m(i,j) + 4*(k-1)-1;
end
for i=2:4
for j=1:8
m(i,j)=m(1,j)-64*(i-1);
end
end

m2=flipud(m) - 16;
mtmp=[m;m2];
mtmp4=fliplr(flipud(mtmp));
mtmp1=fliplr(flipud(mtmp4)) - 2;
mtmp2=fliplr(mtmp1) - 30;
mtmp3=fliplr(flipud(mtmp2)) - 2;

m=[mtmp1 mtmp2 ; mtmp3 mtmp4];

67
clear;
nSample=4096;
Fsamp=80e6;
Fsig=11e6;
overtoner=9;
noit=100;
Vref=600e-3;
funk=2;%1=Ramp 2=Sinus 3=OFDM
save_yes=1;%1=Skapa och spara stromkallor

[SFDR,ENOB,maxinl,maxdnl,Itot]=DAC(nSample,Fsamp,Fsig,overtoner,noit,
funk,save_yes);

matrX=[1:32];
matrY=[1:32];

%figure(1)
%surf(matrX,matrY,Itot);

matrX=[1:noit];
matrY=[1:noit];
if funk==1
figure(2)
hist(maxinl,50);
xlabel('INL [LSB]');
ylabel('Number of DACs')
figure(3)
hist(maxdnl,50);
xlabel('DNL [LSB]');
ylabel('Number of DACs')
end

if funk==2
figure(2)
hist(SFDR,50);
xlabel('SFDR [dB]');
ylabel('Number of DACs')
figure(3)
hist(ENOB,50);
xlabel('ENOB [Number of bits]')
ylabel('Number of DACs')
end

68
Appendix C

This is the SKILL code used to generate the binary-to-thermometer decoder

schematic.

procedure(bin2term(nbr) ;_Oct 9 03 chrli 87

cvSch = geGetWindowCellView(window(44)) ;schematic window number
INV = geGetWindowCellView(window(27)) ;inverter window number
NAND = geGetWindowCellView(window(28)) ;NAND window number
NOR = geGetWindowCellView(window(29)) ;NOR window number
NA = 0.375 ;These values are the location of the
NB = 0.125 ;symbols’ pins
NYx = 1.25
NYy = 0.25
IYx = 0.75
IYy = 0.1875
IA = 0.1875
nbr = nbr – 1 ;nbr from above is the number of binary inputs
x = 0
old_x = 0
wireID = 0
for( i 1 nbr
nbrElements = expt(2 i) - 1
if( (mod(i 2) > 0) ;Checks if it is an odd
then ;or even stage
for( k 1 nbrElements
dbCreateInst(cvSch NOR nil list(x (1-k)) "R0" 1)
)

dbCreateInst(cvSch INV nil list(x -nbrElements) "R0" 1)

for( k 1 nbrElements
dbCreateInst(cvSch NAND nil list(x (-nbrElements - k))
"R0" 1)
)

else
for( k 1 nbrElements
dbCreateInst(cvSch NAND nil list(x (1-k)) "R0" 1)
)

dbCreateInst(cvSch INV nil list(x -nbrElements) "R0" 1)

dbCreateInst(cvSch INV nil list(old_x -nbrElements) "R0" 1)

for( k 1 nbrElements
dbCreateInst(cvSch NOR nil list(x (-nbrElements - k))
"R0" 1)
)
) ; ** if mod **

if( (i > 1 ) ;Check where to connect wires

then ;And them connecting them for
oldNbr = expt(2 i) – 1 ;the entire stage
for( k 0 (oldNbr - 1 )
x1 = old_x + NYx
x2 = x
y1 = -k + NYy
y2 = -k + NA

69
 if( (k == (expt(2 (i - 1)) - 1))
then
x1 = x1 - (NYx - IYx)
y1 = y1 - (NYy - IYy)
) ; ** if k **

schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)

0.0625 0.0625 0.0)

) ; ** for k **

nbrE = expt(2 (i + 1)) - 1

for( k 0 (nbrE - 1)
x1 = x
x2 = x - 0.25
y1 = -k + NB
y2 = y1
if( (k == oldNbr)
then
y1 = -k + IA
y2 = y1
) ; ** if k **

schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)

0.0625 0.0625 0.0)

) ; ** for k **

x1 = x - 0.25
x2 = x1
y1 = NB
y2 = (-nbrE + 1) + NB
schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625
0.0625 0.0)

for( k 0 (nbrElements - 1)
x1 = old_x + NYx
x2 = x
y1 = -k + NYy
y2 = -(nbrElements + 1) + NA - k
if( (k == ((nbrElements - 1) / 2))
then
x1 = old_x + IYx
y1 = -k + IYy
) ; ** if k **

schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)

0.0625 0.0625 0.0)

) ; ** for k **

x1 = x
x2 = -2
y1 = -((nbrE - 1) / 2) + IA
y2 = y1
id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)
0.0625 0.0625 0.0)
id = car(id)
sprintf(data_in "data_in<%d>" i)
xL = x2
yL = y1 + 0.0625

70
 schCreateWireLabel(cvSch id (xL:yL) data_in "lowerLeft" "R0"
"fixed" 0.1 nil)

) ; ** if i **

if( (i == nbr )
then
nbrE = expt(2 (i + 1)) - 1
x2 = x + NYx + 1
for( k 0 (nbrE - 1)
x1 = x + NYx
y1 = -k + NYy
y2 = y1
if( (k == ((nbrE - 1) / 2))
then
x1 = x + IYx
y1 = -k + IYy
y2 = y1
) ; ** if k **

id = schCreateWire(cvSch "route" "full" list(x1:y1

x2:y2) 0.0625 0.0625 0.0)
id = car(id)
sprintf(data_out "data_out<%d>" k)
xL = x2 - 0.75
yL = y1 + 0.0625
schCreateWireLabel(cvSch id (xL:yL) data_out "lowerLeft"
"R0" "fixed" 0.1 nil)

) ; ** for k **

) ; ** if i **

if( (i == 1)
then
x1 = 0
x2 = -0.25
for( k 0 2
y1 = -k + NB
y2 = y1
if( (k == 1)
then
y1 = -k + IA
y2 = y1
) ; ** if k **
schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)
0.0625 0.0625 0.0)

) ; ** for k **

x1 = x2
y1 = NB
y2 = NB - 2
schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625
0.0625 0.0)
x1 = 0
x2 = -2
y1 = NA
y2 = y1

71
 id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)
0.0625 0.0625 0.0)
id = car(id)
xL = x2
yL = y1 + 0.125
schCreateWireLabel(cvSch id (xL:yL) "data_in<0>" "lowerLeft"
"R0" "fixed" 0.1 nil)
y1 = IA - 1
y2 = y1
yL = y1 + 0.125
id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2)
0.0625 0.0625 0.0)
id = car(id)
schCreateWireLabel(cvSch id (xL:yL) "data_in<1>" "lowerLeft"
"R0" "fixed" 0.1 nil)

x1 = -0.5
x2 = 0
y1 = NA
y2 = NA - 2
schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625
0.0625 0.0)

) ; ** if i **

old_x = x
x = expt(i 3) + 4

) ; ** for i **

msb = expt(2 (nbr + 1)) - 2

x = old_x
x1 = x + 5
x2 = x1 + 2
y1 = -(msb / 2) + IA
y2 = y1
id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625
0.0625 0.0625)
id = car(id)
sprintf(data_out "data_out<%d:0>" msb)
xL = x1
yL = y1 + 0.125 ;The next rows puts bus-labels
;on the right place
schCreateWireLabel(cvSch id (xL:yL) data_out "lowerLeft" "R0"
"fixed" 0.15 nil)

x1 = -4
x2 = x1 - 2
id = schCreateWire(cvSch "route" "full" list(x1:y1 x2:y2) 0.0625
0.0625 0.0625)
id = car(id)
msb = nbr
sprintf(data_in "data_in<%d:0>" msb)
xL = x2
yL = y1 + 0.125
schCreateWireLabel(cvSch id (xL:yL) data_in "lowerLeft" "R0"
"fixed" 0.15 nil)

) ; ** procedure bin2term **

72
 Linköping Studies in Science and Technology
Thesis No. 976

STUDIES ON PERFORMANCE
LIMITATIONS IN CMOS DACS
K Ola Andersson

LiU-Tek-Lic-2002:49

Department of Electrical Engineering

Linköpings universitet, SE-581 83 Linköping, Sweden

Linköping, November 2002

Studies on Performance Limitations in CMOS DACs

Copyright © 2002 K Ola Andersson

Department of Electrical Engineering

Linköpings universitet
SE-581 83 Linköping
Sweden

ISBN 91-7373-452-7 ISSN 0280-7971

Printed in Sweden by UniTryck, Linköping, 2002

 Abstract
The digital-to-analog converter (DAC) is a bottle neck in broadband communica-
tion systems. High update rates are required in combination with high accuracy.
In this work, we study factors that limit the performance of current-steering
DACs, focusing on the linearity properties of DACs for telecommunication appli-
cations like digital subscriber lines (DSL).
There are many different sources of nonlinear behavior in current-steering DACs.
Static errors dominate the low-frequency behavior, whereas the high-frequency
behavior is dominated by dynamic errors. The static errors are mainly caused by
mismatch between components and finite output resistance in the current sources.
The dynamic nonlinearity caused by parasitic capacitance in transistors and wires
is of special interest in this work. Two closely related types of models of this
dynamic nonlinearity were developed.
The linearity requirements on the converters for high-speed telecommunication
applications can be hard to meet using a straightforward approach. Various meth-
ods for improving the linearity of DACs are studied in this work. Some of the
methods, like dynamic element matching (DEM) and a novel differential DAC
architecture, rely on redundant coding to improve the linearity. Two methods uti-
lizing models of the dynamic nonlinearity caused by the parasitic capacitance in
the current sources were also developed. One of the methods utilizes a feedback
similar to delta-sigma modulation to spectrally shape the distortion. The other
method is a type of predistortion where the input is modified in order to yield an
improved output that is closer to the desired output, compared with using the
original input.
CMOS technology is popular for implementation of integrated circuits. Two
main advantages of CMOS, compared with, e.g., bipolar technology, is low cost
and the possibility of designing circuits with relatively low power consumption.

i
CMOS is also the preferred technology for implementing large systems on a sin-
gle chip with both analog and digital blocks. Three different current-steering
CMOS DACs were developed in this work, and are presented in the thesis. Mea-
surement results show close resemblance with the simulation results obtained
from the developed models.

ii
 Acknowledgments
Many people deserve my gratitude for helping me during the years. First of all I
thank my supervisor, Prof. Mark Vesterbacka, for his guidance.
Dr. J Jacob Wikner, has taught me a lot about data conversion, mixed signal
design, IT tools, and other things that have simplified my work. All help from
him, M.Sc. Niklas U Andersson, and Dr. Mikael Karlsson Rudberg, all from Infi-
neon Technologies Wireless Solutions Sweden (former Ericsson Microelectron-
ics), is greatly appreciated.
I also thank Dr. Gunnar Björklund and M.Sc. Magnus Hägglund for supporting
my work during the years I spent doing research at Ericsson Microelectronics.
I appreciate the help and inspiration from all my colleagues at Ericsson Micro-
electronics and Electronics Systems, Linköping University.
Finally, I thank my family, especially my wife Helena, for their support.
The work was financially supported by the Microelectronics Research Center
(MERC) at Ericsson Microelectronics and the Center for Industrial Information
Technology (CENIIT) at Linköping University.

iii
iv
 Table of Contents
Chapter 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 The analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Scientific contribution of the author . . . . . . . . . . . . . . . . . . . . . 3
1.4 Publications related to the author . . . . . . . . . . . . . . . . . . . . . . . 3
1.4.1 Conference publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4.2 Journal publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.3 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.4 Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 2
DACs in Telecommunication . . . . . . . . . . . . . . . . . . . . 7
2.1 The DSL Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Signals and modulation in ADSL . . . . . . . . . . . . . . . . . . . . 9
Distorted signals 10
2.1.2 DAC requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 The ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Representation of digital signals . . . . . . . . . . . . . . . . . . . 12
2.2.2 Digital-to-analog conversion . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Nyquist rate DACs vs. oversampled DACs . . . . . . . . . . . 14

v
 2.3 DAC performance measures . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Performance measures in the code domain . . . . . . . . . . . 16
Differential nonlinearity, DNL 16
Integral nonlinearity, INL 17
2.3.2 Measures in the frequency domain . . . . . . . . . . . . . . . . . . 17
Signal-to-noise ratio, SNR 19
Signal-to-noise-and-distortion ratio, SNDR 19
Effective number of bits, ENOB 19
Spurious-free dynamic range, SFDR 20
Total harmonic distortion, THD 20
Multi-tone power ratio, MTPR 20

Chapter 3
Modeling of Current-Steering DACs . . . . . . . . . . . . . 23
3.1 Classification of systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 The ideal current-steering DAC . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Modeling of static errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1 Component mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Influence of graded element matching errors 28
Modeling of random matching errors 34
3.3.2 Finite output resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Modeling of dynamic errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.1 State-space model of a current-steering DAC . . . . . . . . . 35
Modeling of nonideal DAC components 35
Circuit-level model of the DAC 38
Simulations 42
3.4.2 A low-complexity model . . . . . . . . . . . . . . . . . . . . . . . . . 44
A simple DAC model 45
Model structure 46
Simulation of the low-complexity model 48
3.5 Combined models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Chapter 4
Compensation and Correction of Errors . . . . . . . . . . 51
4.1 Compensation and correction of static errors . . . . . . . . . . . . 51
4.1.1 Calibration of the MSBs . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Basic idea 52

vi
 Proposed implementation 54
Qualitative comparison with other calibration techniques 55
4.1.2 Distributed biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.1.3 Dynamic element matching . . . . . . . . . . . . . . . . . . . . . . . 56
Generalized DEM 57
DEM utilizing switching trees 58
Partial randomization DEM 59
Mismatch shaping DEM 60
4.2 Compensation and correction of dynamic errors . . . . . . . . . . 61
4.2.1 Differential DACs with variable common mode . . . . . . . 62
Proposed redundant architecture 62
Dithering of the common-mode level 64
DC level minimization 64
Common-mode level reduction with boundary conditions 66
4.2.2 Modulation of expected errors . . . . . . . . . . . . . . . . . . . . . 67
Delta-sigma modulator basics 68
Spectral shaping of nonlinearities 70
Simulations 71
Measurements 72
4.2.3 Predistortion of dynamic errors . . . . . . . . . . . . . . . . . . . . 72
Predistortion block 73
Simulation results 74
4.2.4 Implementation issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 5
Current-Steering DAC Implementations . . . . . . . . . . 77
5.1 CMOS processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.1 Large signal models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
NMOS transistors 78
PMOS transistors 79
Notes on large signal models 80
5.1.2 Small signal models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2 Analog DAC building blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2.1 CMOS current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Single transistor current source 81
Cascode current source 82
5.2.2 CMOS switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3 Digital DAC building blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.1 Binary-to-thermometer encoding . . . . . . . . . . . . . . . . . . . 84

vii
 Thermometer coded and segmented structures in general 84
Implementation of binary-to-thermometer encoders 87
5.3.2 Switch signal generators . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.4 DAC design strategies and measurement setup . . . . . . . . . . . 91
5.4.1 Overall layout structure . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.4.2 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4.3 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.5 A 14-bit DAC in 0.35 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . 94
5.5.1 Chip description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.5.2 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.6 A 14-bit PRDEM DAC in 0.35 µm CMOS . . . . . . . . . . . . . . . 97
5.6.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.6.2 Simulations and comparison with measurements . . . . . . 100
Simulation setup and results 100
Measurement results 101
Comparison of SFDR performance 101
5.7 A dual 14-bit DAC in 0.25 µm CMOS . . . . . . . . . . . . . . . . . . 102
5.7.1 Architecture and implementation . . . . . . . . . . . . . . . . . . 103
5.7.2 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.8 Summary of implemented DACs . . . . . . . . . . . . . . . . . . . . . . 105

Chapter 6
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

viii
 1 Introduction
Strict requirements are imposed on the transmitting and receiving circuits for
broadband communication. A bottle neck in these communication systems is the
data converters, i.e., digital-to-analog converters (DACs) and analog-to-digital
converters (ADCs). In this work we study performance limitations in DACs for
high-speed applications. This chapter is an overview of the work and an introduc-
tion to the thesis. In Sec. 1.1 we give a brief introduction to the analog front end
(AFE) in which the DAC is an important building block. The different parts of
the thesis are outlined in Sec. 1.2. The author’s scientific contribution to the area
is outlined in Sec. 1.3, and the publications related to this thesis are listed in
Sec. 1.4. This chapter ends in Sec. 1.5 with a list of abbreviations used through-
out the thesis.

1.1 The analog front end

Among the technologies that have emerged in recent years for broadband tele-
communication are the different digital subscriber line (DSL) technologies. A
simplified view of a typical AFE used in digital subscriber line (DSL) applica-
tions is shown in Fig. 1.1. There are a number of blocks with different functions.
The multi-tone input signal to the DAC is constructed with an inverse fast Fourier
transform (IFFT) circuit, which is one of the digital signal processing (DSP)
blocks. The DAC converts this signal to an analog signal which is the input to the
following analog transmitting circuits, consisting of lowpass (LP) filters and a
line driver. The line driver is an amplifier with good driving capability used to
feed the signal into a twisted-pair copper wire. In the receive path there is a
receive amplifier, whose output is connected via an LP filter to an ADC convert-

1
Introduction

ing the analog data to digital. The digital data is processed by a fast Fourier trans-
form (FFT) circuit to determine the correct points in the different constellations,
as will be discussed in Sec. 2.1.1.

AFE line driver

DAC LP A
DSP blocks channel
ADC LP A

receive amplifier

Figure 1.1 AFE for DSL applications.

1.2 Outline of the thesis

Below follows a brief outline of the different parts of the thesis.
Chapter 2 is an introduction to DACs in general and to their application in tele-
communication. The requirements imposed on the DACs are presented and moti-
vated. The performance measures that will be used throughout the thesis are
presented, as well as some terminology.
Chapter 3 deals with behavioral-level modeling of errors occurring when fabri-
cating current-steering DACs in complementary metal oxide semiconductor
(CMOS) technology. The errors that are studied are, e.g., caused by component
mismatch and parasitic components.
In Chapter 4 we use the models developed in Chapter 3 to develop and analyze
methods aiming for improving the linearity of DACs. The methods include cali-
bration and biasing techniques, as well as predistortion and techniques based on
redundant coding.
Three different current-steering CMOS DACs were developed in this work. The
implementations are presented in Chapter 5 together with measurement results
and discussions on the implementation of various building blocks. The work is
concluded in Chapter 6.

2
 Scientific contribution of the author

1.3 Scientific contribution of the author

The text on DACs in telecommunication applications in Chapter 2 is intended as
a background and introduction to the topic. The modeling of nonideal compo-
nents discussed in Chapter 3 is a compilation of known models and models
developed by the author. The modeling of the influence of graded matching
errors presented in Sec. 3.3.1 is original work of the author, along with all of the
work presented in Sec. 3.4 regarding dynamic errors.
The discussions on error correction and compensation in Chapter 4 is also a com-
pilation of known methods and methods developed by the author. The calibration
scheme presented in Sec. 4.1.1 is original work of the author. The remaining part
of Sec. 4.1 discusses distributed biasing and dynamic element matching, which
are priorly known methods that have been implemented in two of the DACs pre-
sented in Chapter 5. The techniques for reducing the impact of dynamic errors
presented in Sec. 4.2 were developed by the author.
The implementations of DACs presented in Chapter 5 were all designed in coop-
eration with Niklas U Andersson and Dr. J Jacob Wikner. The DAC presented in
Sec. 5.5 was designed mainly by the author, the DAC in Sec. 5.6 mainly by
Niklas U Andersson, and for the DAC in Sec. 5.7 the work was evenly distributed
between the author and Niklas U Andersson. Dr. J Jacob Wikner has supervised
the design work and provided some sub circuits and scripts useful for design
automation.

1.4 Publications related to the author

Publications, patents, and a tutorial, authored or coauthored by the author, related
to the work presented in this thesis are listed below in chronological order for
each category.

1.4.1 Conference publications

[1] K.O. Andersson and J.J. Wikner, “Modeling of the influence of graded
element matching errors in CMOS current-steering DACs,” Proc.
NORCHIP Conference, pp. 399-404, Oslo, Norway, Nov. 8-9, 1999.
[2] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS current-
steering DAC using state-space models,” Proc. 43rd Midwest Symposium
on Circuits and Systems (MWSCAS’00), pp. 668-671, Lansing, MI, USA,
Aug. 8-11, 2000.

3
Introduction

[3] K.O. Andersson, N.U. Andersson, and J.J. Wikner, “Spectral shaping of
DAC nonlinearity errors through modulation of expected errors,” Proc.
IEEE International Symposium on Circuits and Systems (ISCAS’01),
vol. 3, pp. 417-420, Sydney, Australia, May 6-9, 2001.
[4] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,
“Models and implementation of a dynamic element matching DAC,” Proc.
NORCHIP Conference, pp. 155-160, Kista, Sweden, Nov. 12-13, 2001.
[5] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, “A
differential DAC architecture with variable common-mode level,” Proc.
IEEE International Symposium on Circuits and Systems (ISCAS’02),
vol. 1, pp. 113-116,Scottsdale, AZ, USA, May 26-29, 2002.
[6] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner,
“Combining DACs for improved performance,” Proc. 4th IEE
International Conference on Advanced A/D and D/A Conversion
Techniques and their Applications, Prague, Czech Republic, June 26-28,
2002.
[7] M. Vesterbacka, K.O. Andersson, N.U. Andersson, and J.J. Wikner,
“Using different weights in DACs,” Proc. 4th IEE International
Conference on Advanced A/D and D/A Conversion Techniques and their
Applications, Prague, Czech Republic, June 26-28, 2002.

1.4.2 Journal publication

[8] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,
“Models and implementation of a dynamic element matching DAC,” to
appear in Kluwer International Journal of Analog Integrated Circuits and
Signal Processing, Special Issue: Selected Papers from the NORCHIP
2001 Conference.

1.4.3 Patents
[9] K.O. Andersson, “Improved current-steering D/A conversion,” Swedish
patent 0000731-0, 2000.
[10] K.O. Andersson, “Current Steering DAC”, pending Swedish patent, 2001.
[11] K.O. Andersson and J.J. Wikner, “Digital-to-analog converter having error
correction,” pending Swedish patent, 2002.

4
 Abbreviations

1.4.4 Tutorial
[12] J.J. Wikner, N.U. Andersson, K.O. Andersson, and M. Vesterbacka,
Compilation of error prevention and correction techniques for DACs,
Tutorial IEEE 7th Int. Conf. on Electronics, Circuits, and System
(ICECS’01), Malta, Sep. 2, 2001.

1.5 Abbreviations
Below is a list of the abbreviations used in the thesis.
ADC Analog-to-digital converter
ADSL Asymmetric digital subscriber line
AFE Analog front-end
CMOS Complementary metal oxide semiconductor
CO Central office
CPE Customer premises equipment
DAC Digital-to-analog converter
DCVS Differential cascode voltage switch
DEM Dynamic element matching
DMT Discrete multi-tone
DNL Differential nonlinearity
DSL Digital subscriber line
DSP Digital signal processing
ECH Echo canceled hybrid
ENOB Effective number of bits
FDM Frequency division multiplexing
FFT Fast Fourier transform
FIR Finite impulse response
FRDEM Full randomization dynamic element matching
GPIB General purpose interface bus
IFFT Inverse fast Fourier transform
INL Integral nonlinearity
LP Lowpass

5
Introduction

LSB Least significant bit

LTI Linear, time invariant
LVDS Low voltage differential signalling
MSB Most significant bit
MTPR Multi-tone power ratio
OSR Oversampling ratio
PC Personal computer
PCB Printed circuit board
POTS Plain old telephone service
PRDEM Partial randomization dynamic element matching
PSD Power spectral density
QAM Quadrature amplitude modulation
RF Radio frequency
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
THD Total harmonic distortion
VDSL Very high speed digital subscriber line
WLAN Wireless local area network

6
 2 DACs in
Telecommunication
The main emphasis in this thesis is on the linearity of current-steering DACs. The
work is focused on converters for telecommunication applications, and this chap-
ter is an introduction to DACs in general, and their application to telecommunica-
tion. We start by outlining the set of signals the DACs are intended for, and
illustrate the importance of high linearity in the intended applications. As appli-
cation examples we use digital subscriber line (DSL) environments. The ideal
DAC is presented on a behavioral level, along with some important performance
measures used to describe the degree of deviation from the ideal DAC.

2.1 The DSL Environment

Among the technologies that have emerged in recent years for broadband tele-
communication are the different DSL technologies, e.g., asymmetric DSL
(ADSL) and very high speed DSL (VDSL) [1, 2, 3, 4]. Common to these tech-
nologies is their use of existing twisted-pair copper wires, originally intended for
the plain old telephone service (POTS), as a medium for transmission. One rea-
son for this is that because the wires already exist, the cost for establishing the
infrastructure is considerably lower compared with, e.g., communication over
optical fibers where new lines have to be routed.
A typical DSL system is outlined in Fig. 2.1. The terminal on the user side, or
customer premises equipment (CPE) side, is connected to the central office (CO)
side with twisted-pair copper wires. The backbone network of the telecommuni-
cation operator connecting the different CO stations is typically a high-speed
optical fiber link. DSL cannot be made available in every existing POTS node,

7
DACs in Telecommunication

since the attenuation of signals in copper wires is rather high for the frequency
bands used. The maximum physical distance between the CPE and the CO side
for ADSL is approximately 5.5 km. Over this limit the possible data rate is dra-
matically reduced. This is due to the common use of so called loading coils on
such long lines to improve the voice band properties of the line. As a side effect
these loading coils increase the attenuation for frequencies above the voice band
[1].

Backbone
CPE CPE

CO CO
CPE

CPE
CPE

Figure 2.1 Overview of DSL system.

In Fig. 2.2 we show the frequency bands used in ADSL, which is a standard that
has been well established and is widespread today. The range of frequencies
below 4 kHz is reserved for POTS. The frequency range between 30 and 138 kHz
is used for upstream communication, i.e., data sent from the CPE side to the CO
side. Data is sent in the reverse direction, downstream, in the frequency range
between 138 kHz and 1.104 MHz. A guard band is present between the POTS
band and the ADSL downstream band. The information in ADSL is transmitted
using a discrete multi-tone (DMT) signal. The ADSL version described here is
known as frequency division multiplexing (FDM) ADSL [1, 2, 3, 4], where the
upstream and downstream bands are separated. There is also a version called
echo-canceled hybrid (ECH) ADSL, where the upstream and downstream bands
overlap. ECH ADSL requires echo cancellation to separate transmitted data from
received data [1, 2, 3, 4].
The downstream capacity (up to 9 Mb/s) is larger than the upstream capacity (up
to 1 Mb/s) since the desired rate for downloading data in some applications, e.g.,
video-on-demand, is larger than the corresponding uploading rate [4], hence the
term asymmetric. In VDSL on the other hand, the communication is symmetric,
i.e., the same data rate is available in both directions.

8
 The DSL Environment

The maximum signal bandwidth in ADSL is about 1 MHz. In other types of tele-
communication and data communication, e.g., VDSL and wireless local area net-
work (WLAN), the corresponding bandwidths lie around 10 MHz, and in future
communication standards the bandwidths may be even higher.

Frequency bands in FDM ADSL

ADSL downstream
ADSL upstream
guard band
POTS

0 4 30 138 1104
Frequency [kHz]

Figure 2.2 Frequency bands used in FDM ADSL.

2.1.1 Signals and modulation in ADSL

As mentioned earlier, ADSL uses a DMT signal for data transmission. For exam-
ple, in the downstream band the data is sent on 224 carriers between 138 kHz and
1.104 MHz. Generally, a DMT signal, Y (t) , can be expressed (in the time-
domain) as
K
Y (t) = ∑ ai sin ( i ⋅ ω0 ⋅ t ) + bi cos ( i ⋅ ω0 ⋅ t ) =
i=1
K
= ∑ r i sin ( i ⋅ ω0 ⋅ t + φi ) . (2.1)
i=1

It should be noted that, with the notation used in (2.1), some of the tones must
have zero amplitude in ADSL, since their frequencies are in the POTS band or
the guard band (or in the wrong ADSL band for FDM ADSL).
To each carrier there is an associated quadrature amplitude modulation (QAM)
constellation [3] given by the values of a i and b i . The bits that are to be transmit-
ted are divided into different constellations. The number of bits modulated on

9
DACs in Telecommunication

each carrier is not fixed, but is determined during training sequences and depends
on the quality of the transmission link for the corresponding frequency band. In
Fig. 2.3(a) a 16-QAM constellation is shown, and the point of the constellation to
be transmitted determines the actual values of a i and b i .

Distorted signals
When the signal is sent from the transmitter to the receiver it will be distorted.
Sources of signal distortion are, e.g., attenuation in the twisted-pair wire and non-
linearities in the transmitting circuits. Here we examine the impact on the QAM
constellation for different types of distortion using simulations in Matlab. The
simulations are performed using discrete time signals. Seven tones with angular
frequencies Ω n = n ⋅ π ⁄ 8 for n = 1, 2, …, 7 have been used, and to each of
these tones there is a 16-QAM constellation as illustrated in Fig. 2.3(a). As an
example we investigate how the constellation for the tone with n = 3 is affected
by distortion. For the remaining tones we choose random values of a i and b i
with rectangular distribution, and for each such random combination we consider
all possible combinations of a 3 and b 3 . The constellations plotted in Fig. 2.3 are
the results of 100 stochastic outcomes.
First we examine how the constellations are affected by a linear distortion. Linear
distortion affects each carrier by a signal independent phase shift and a signal
independent attenuation (or possibly amplification). Hence, the constellation of
the linearly distorted carrier is a rotated and scaled copy of the original constella-
tion, as illustrated in Fig. 2.3(b). The linear distorter is a simple finite impulse
response (FIR) filter given by y(n) = 0.5 ⋅ x(n) + 0.1 ⋅ x(n – 1) . Since there is a
one-to-one mapping from the original constellation to the distorted constellation,
the original constellation can be restored once the attenuation and the phase shift
is known.
The constellations for signals that are distorted by a simple nonlinearity,
y(n) = x(n) + 0.2 ⋅ x 3(n) , are shown in Fig. 2.3(c). It can be seen that there is no
longer a one-to-one mapping between the original constellation and the distorted
constellation. The location of the received point is depending on the amplitudes
and phases of the other tones as well. When the nonlinearity becomes more
severe, the clouds of points start to overlap and errors occur in determining the
original location of the transmitted point.
With these simple examples we have illustrated the importance of high linearity
in all parts of the transmission link. Noise added to the signal will have similar
effects on the constellations as a nonlinearity, so there are also requirements on
the noise margins.

10
 The DSL Environment

Original constellation

1.5

0.5

b
−0.5

−1.5

−1.5 −0.5 0.5 1.5

a

(a)
Linearly distorted constellation Nonlinearly distorted constellation

1.5 1.5

0.5 0.5
b

−0.5 −0.5

−1.5 −1.5

−1.5 −0.5 0.5 1.5 −1.5 −0.5 0.5 1.5

a a

(b) (c)
Figure 2.3 (a) 16-QAM constellation, (b) linearly distorted constellation, and (c) nonlin-
early distorted constellation.

2.1.2 DAC requirements

Since the copper wires used in DSL were initially intended for POTS, which is a
narrowband communication technology, strict requirements are imposed on the
transmitting and receiving circuits in order to achieve broadband communication
over these lines. General requirements on a DAC for DSL applications, which we
will use as a guideline throughout this thesis, can be found in Table 2.1.

General
Property
requirement
Signal bandwidth 1-10 MHz
Effective number of bits 12-14
Table 2.1 General DAC requirements for DSL and similar applications.

11
DACs in Telecommunication

A comment on the requirements is that 12-bit DACs are commonly used in FDM
ADSL, whereas ECH ADSL often requires 14 bits of accuracy [1]. For some
emerging communication standards the bandwidths are much higher than in
Table 2.1 [5].

2.2 The ideal DAC

In this section we introduce the ideal DAC and the notation for digital signals
used throughout the thesis.

2.2.1 Representation of digital signals

The input to the DAC is a digital signal, that we denote X (n) . The parameter n
denotes the sample (or update) instant. We will use the notation X (n) for both the
vector form representation

X (n) = [ b N – 1(n), b N – 2(n), …, b 0(n) ] (2.2)

and for the integer value

N–1
X (n) = ∑ bk(n) ⋅ wk , (2.3)
k=0

since they easily can be distinguished by the context. The binary valued signals
b k(n) are the individual bits of the digital word X (n) , and w k is the weight asso-
ciated with bit k . The weights depend on what coding scheme is used. For exam-
ple, in the binary-coded case we have that w k = 2 k , whereas w k = 1 for all k in
the thermometer-coded case. These two types of codes are common in data con-
version, and are more thoroughly described in Sec. 5.3.1. We use the notation b
for the inverse of b , and X denotes X with all individual bits inverted.
Throughout this thesis we represent the weights, w k , as positive numbers. That
is, we treat digital numbers and signals as positive. In the DSP blocks, digital sig-
nals are generally expressed as signed numbers, using, e.g., two’s complement
representation [6]. However, all designs of DACs in this thesis operate by sum-
ming positive analog weights, so from a DAC designer’s point of view it is more
convenient to use positive weights also in the digital domain.

12
 The ideal DAC

2.2.2 Digital-to-analog conversion

The purpose of a DAC is to perform a mapping of the digital input to an analog.
The analog signal can be represented by, e.g., an electrical current or voltage. If
an analog signal, A(t) , that has a limited frequency bandwidth, f 0 , is uniformly
sampled with a sample frequency f s > 2 ⋅ f 0 to a discrete-time signal, D(n) , it
can be perfectly reconstructed by the function
∞
Ã(t) = ∑ D(n) ⋅ sinc( f s ⋅ ( t – nT )) , (2.4)
n = –∞

where sinc(x) = sin(π ⋅ x) ⁄ ( π ⋅ x ) for x ∈ [ – ∞, ∞ ] , T = 1 ⁄ f s , and Ã(t) is the

reconstructed signal. The ideal DAC could be defined as a device performing the
mapping from the digital signal, X (n) , to the analog signal, A(t) , given by
∞
A(t) = K ⋅ ∑ X (n) ⋅ sinc( f u ⋅ ( t – nT )) , (2.5)
n = –∞

where K is the gain of the DAC, T is the update period, and f u = f s = 1 ⁄ T .

For practical reasons, e.g., the noncausal properties of the sinc function, we
instead define the ideal DAC according to
∞
A(t) = K ⋅ ∑ X (n) ⋅ P(t – nT ) , (2.6)
n = –∞

where P(t) is a unit square pulse with duration T , i.e.,

 1 for 0 ≤ t < T
P(t) =  . (2.7)
 0 otherwise

In other words, A(t) , is a piecewise constant signal with

N–1
A(t) = K ⋅ X (n) = K ⋅ ∑ bi(n) ⋅ wi for nT ≤ t < ( n + 1 )T . (2.8)
i=0

When designing a DAC, the goal is to come as close as possible to the operation
described in (2.6) and (2.8). It is, however, not possible to achieve exactly the
operation of an ideal DAC, since A(t) given by (2.6) is discontinuous (unless
X (n) is constant). The sinc pulse and the unit square pulse are plotted together in
Fig. 2.4.

13
DACs in Telecommunication

sinc(t/T) and P(t/T) plotted together

1
Amplitude level

−5 −4 −3 −2 −1 0 1 2 3 4 5
Normalized time, t/T

Figure 2.4 The sinc pulse (dashed) and the unit square pulse (solid) plotted together.

In the applications considered here, there is no information in the DC level of the

signal. In the general case, we add a constant to the right hand sides of (2.6) and
(2.8).

2.2.3 Nyquist rate DACs vs. oversampled DACs

Assume that we want to output a signal with bandwidth f 0 Hz. By the sampling
theorem, the minimum required update frequency is [7]

fu = 2 ⋅ f0 (2.9)

as touched upon in the previous section. A DAC using this update frequency is
referred to as a Nyquist rate DAC.
In an ideal data converter, the only errors are those caused by the quantization
process, referred to as quantization noise. It is sometimes argued that there is no
quantization noise in a DAC, since the input signal is already quantized [8]. How-
ever, since the input is already quantized it contains quantization noise. We can
therefore talk about quantization noise in the output signal from a DAC, even if
the quantization is a process in the circuits preceding the DAC.
For an N -bit DAC with N relatively large and with a varying input signal, the
quantization noise, q(n) , can often be adequately described as a white noise sig-
nal with rectangular distribution between 0 and 1 (assuming that the size of the
quantization step is unity). The total power of the quantization noise is then [7, 9]

14
 The ideal DAC

1
P q = Var(q(n)) = ------ . (2.10)
12
This power is evenly distributed over frequencies in the interval ( 0, f u ⁄ 2 ) (since
the noise is treated as white). If we use an update frequency larger than the
required 2 ⋅ f 0 , some of the noise will appear outside of the signal band, at fre-
quencies in the interval ( f 0, f u ⁄ 2 ) . This part of the noise can be filtered out,
since the signal does not have any spectral content for these frequencies, and the
overall signal-to-noise-and-distortion ratio (SNDR) (see Sec. 2.3.2) is improved.
A DAC with f u > 2 ⋅ f 0 is known as an oversampled DAC, and the oversampling
ratio (OSR) is defined as

fu
OSR = ------------
-. (2.11)
2 ⋅ f0

Compared with a Nyquist rate DAC, the signal-to-noise ratio (SNR) due to quan-
tization noise is increased with 10 ⋅ log 10(OSR) dB [8]. To further decrease the
power of the quantization noise within the signal band, delta-sigma modulation
techniques are often used. These techniques utilize feedback loops to spectrally
shape the quantization noise to frequencies outside of the signal band, and are
briefly outlined in Sec. 4.2.2.
Another reason for using oversampling is that using square pulses instead of sinc
pulses for reconstruction affects the spectral properties of the output signal. Let
A sinc(ω) denote the power spectrum of the signal reconstructed with sinc pulses,
and let A square(ω) denote the corresponding spectrum for the signal reconstructed
using square pulses. Then, the following equality holds [7, 8]

ω
A square(ω) = A sinc(ω) ⋅ sinc(------------) , (2.12)
2π f u

i.e., the signal is attenuated for frequencies close to f u . For the Nyquist fre-
quency, f u ⁄ 2 , this attenuation is ( sinc(1 ⁄ 2) ) –1 = π ⁄ 2 ≈ 3.9 dB . For a Nyquist
rate DAC this attenuation may need to be compensated for with so called anti-
sinc filters, depending on the requirements of the application. For oversampled
DACs there is no spectral content of the signal close to the Nyquist frequency, if
high enough OSR is used. Therefore, the attenuation becomes neglectable.
Moreover, the images of the signal appearing around multiples of the update fre-
quency need to be filtered out with image rejection filters before the signal enters
the communication channel to minimize the interference with other types of
communication utilizing other frequency bands. In an oversampled DAC the

15
DACs in Telecommunication

images are better separated from the signal, compared with Nyquist rate DACs,
and the requirements on the transition band widths of the image rejection filters
are reduced.

2.3 DAC performance measures

Some performance measures are needed to describe the quality of a DAC. In this
section we define the performance measures that are commonly used for charac-
terizing communication DACs [10, 11], used throughout this thesis.

2.3.1 Performance measures in the code domain

The static transfer characteristics, A(X ) , of a nonideal 4-bit DAC is shown in
Fig. 2.5. We also plot the line Y (X ) = K ⋅ X + Y offset , i.e., the transfer character-
istics for the corresponding ideal DAC, for comparison. K and Y offset are chosen
to yield a best-fit straight line (least mean square) with respect to the data points
for the nonideal DAC. If the DAC would be linear, all data points would be on the
straight line. In the following we define two common linearity measures in the
code domain.

Static transfer characteristics for a nonideal DAC

15
14
13
12
11
10
Output level

9
8
7
6
5
4
3
2
1
0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code

Figure 2.5 Static transfer characteristics of a nonideal 4-bit DAC.

Differential nonlinearity, DNL

The differential nonlinearity (DNL) for a code X , DNL(X ) , describes the devia-
tion from an ideal step in the transition from X – 1 to X [9]. DNL(X ) is defined
as

16
 DAC performance measures

A(X ) – A(X – 1) – K
DNL(X ) = ------------------------------------------------- (2.13)
K
The DNL for the DAC with the transfer characteristics in Fig. 2.5 is plotted in
Fig. 2.6.

DNL for a nonideal DAC

1
DNL

−1

−2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code

Figure 2.6 DNL of a nonideal 4-bit DAC.

Integral nonlinearity, INL

The integral nonlinearity (INL) describes the deviation from the line Y (X ) [10],
i.e.,

A(X ) – Y (X )
INL(X ) = ----------------------------- . (2.14)
K
Combining (2.13) and (2.14) yields that

DNL(X ) = INL(X ) – INL(X – 1) . (2.15)

Hence, DNL is a redundant measure (if the INL is known). The INL for the DAC
with the transfer characteristics in Fig. 2.5 is plotted in Fig. 2.7.

2.3.2 Measures in the frequency domain

For communication DACs we are often more interested in the frequency domain
behavior than in the corresponding code-domain behavior [10]. In Fig. 2.8 we
show a typical power spectral density (PSD) plot of an output signal for a DAC
with a single-tone (sinusoidal) input signal. Nonlinearities in the DAC cause har-

17
DACs in Telecommunication

INL for a nonideal DAC

INL 1

−1

−2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code

Figure 2.7 INL of a nonideal 4-bit DAC.

monic distortion in the output signal. The second and third harmonics are indi-
cated in Fig. 2.8. Hence, the different measures of distortion presented in this
section is also measures of the DAC linearity.

PSD for distorted single−tone signal

fundamental

2:nd harmonic

SFDR 3:rd harmonic

PSD

Frequency

Figure 2.8 PSD plot of the output signal from a nonideal DAC with a single-tone input sig-
nal.

The signal impurities can be divided into noise and distortion. Noise is typically
signal independent, due to, e.g., thermal activity in circuit elements, having a
smooth spectral appearance. Distortion, on the other hand, is generally character-

18
 DAC performance measures

ized by clearly visible peaks in the output spectrum and is often signal dependent,
e.g., due to circuit nonlinearities. Gray zones are present in the analysis, e.g.,
quantization errors are clearly signal dependent, but are often treated as sources
of noise. The total output power is

P out = P signal + P noise + P dist , (2.16)

where P signal is the power of the wanted output signal, P noise is the noise power,
and P dist is the total power due to distortion.

Signal-to-noise ratio, SNR

As a measure of how well the signal can be distinguished from the noise, we have
the signal-to-noise ratio (SNR)

P signal
-.
SNR = -------------- (2.17)
P noise

Signal-to-noise-and-distortion ratio, SNDR

The signal-to-noise-and-distortion ratio (SNDR, in some literature abbreviated
SINAD) is

P signal
SNDR = ------------------------------
-. (2.18)
P noise + P dist

This is a more adequate measure of signal quality than SNR if a large amount of
distortion is present. The SNDR due to quantization noise of the ideal N -bit
(Nyquist rate) DAC with a full-scale sinusoidal input signal can be expressed as
[7, 8]

SNDR ≈ 6.02N + 1.76 dB. (2.19)

Effective number of bits, ENOB

For a nonideal DAC we rearrange (2.19) to define the effective number of bits
(ENOB) as

SNDR – 1.76
ENOB = -------------------------------- , (2.20)
6.02
which is only a different way of expressing the SNDR. It is a useful measure to,
e.g., find a lower bound on the number of bits, N , to achieve a given SNDR.

19
DACs in Telecommunication

Spurious-free dynamic range, SFDR

The spurious-free dynamic range (SFDR) is defined as

P signal
-,
SFDR = -------------- (2.21)
P ls

where P ls is the power of the largest spurious (unwanted) tone. SFDR is indi-
cated in Fig. 2.8. It should be mentioned that this definition of SFDR, which is
often used for data converters, is different from the one most often used for
amplifiers, in which case SFDR is defined as the SNR for the maximum output
power without having any spurious tones [8].

Total harmonic distortion, THD

The second and third harmonic tone is indicated in Fig. 2.8. If the power of the
n :th harmonic tone is denoted P n , the total harmonic distortion (THD) is
∞

∑ Pn
n=2
THD = ---------------
-, (2.22)
P signal

i.e., THD is the power of all harmonics, normalized with respect to the signal
power.

Multi-tone power ratio, MTPR

Nonlinear systems, as opposed to linear systems, cannot be completely described
by single-tone properties [12]. In multi-carrier applications, e.g., ADSL, the
multi-tone properties of the transmitting system are more adequate for describing
the performance. One multi-tone linearity measure often used is the multi-tone
power ratio. A number of tones with equal amplitude and frequency spacing are
applied to the input. One tone is left out, and the multi-tone power ratio (MTPR)
is defined as the ratio between the rms amplitude of a carrier and the peak spuri-
ous tone in the region of the left out tone [10], as indicated in Fig. 2.9. MTPR is a
measure on how much the other tones affect the amplitude of a specific tone,
compare, e.g., with the nonlinearly distorted constellation discussed in Sec. 2.1.1.

20
 DAC performance measures

PSD for distorted multi−tone signal

MTPR
PSD

Frequency

Figure 2.9 PSD plot of a multi-tone signal with one tone left out.

21
DACs in Telecommunication

22
 3 Modeling of Current-
Steering DACs
In this chapter we discuss modeling of current-steering DACs. Both static errors,
such as component mismatch, and dynamic errors, e.g., due to parasitic capaci-
tance are discussed. The study is focused on the dynamic errors.
Modeling of nonlinear behavior in analog circuits is often made using polyno-
mial models, such as Taylor or Volterra series expansions [12, 13]. Some initial
attempts of characterizing DACs using Volterra models were made in this work.
These were, however, unsuccessful in capturing the nonlinear behavior of the
current-steering DAC, except for in very limited frequency bands. Hence, the
polynomial type models have been discarded in this work.

3.1 Classification of systems

Consider an arbitrary system (i.e., mapping from an input signal to an output sig-
nal) with input X (n) and output Y (n) . Some useful definitions for classification
of such a system are presented here.

• Suppose that we have two arbitrary input signals X 1(n) and X 2(n) , yielding
the output signals Y 1(n) and Y 2(n) , respectively. Then the system is called
linear if the input signal X (n) = aX 1(n) + bX 2(n) yields the output signal
Y (n) = aY 1(n) + bY 2(n) , where a and b are arbitrary constants. Otherwise,
the system is nonlinear.

23
Modeling of Current-Steering DACs

• Consider the special case for the signals above when X 2(n) = X 1(n – k) ,
where k is an arbitrary integer. The system is time-invariant if
Y 2(n) = Y 1(n – k) , otherwise the system is time-variant.

• The system is called causal if the value of the output signal, Y (n 1) , at instant
n 1 only is a function of the input signal X (n) for n = n 1, n 1 – 1, n 1 – 2, …
(i.e., future values of X (n) have no influence on the output).

• The system is called static if the value of the output signal, Y (n 1) , at instant
n 1 only is a function of the input signal X (n) for n = n 1 . Otherwise, the sys-
tem is called dynamic.

Some comments can be made regarding the application of the definitions to

DACs. When implementing the DAC it is desired to come as close as possible (in
some sense) to a linear, time-invariant (LTI) system. However, the linearity prop-
erty is, as for most other physical systems, limited by the fact that the DAC has a
limited input (and output) range determined by the number of bits in the input
signal. Thus, the constants a and b in the definition of linearity cannot be arbi-
trary, since overflow in the input signal causes a large amount of nonlinear distor-
tion. Moreover, the time-invariance property does not hold because of aging of
the chips and temperature variations. We do, however, regard the DAC as a time-
invariant system over a limited range of time. In ADSL each DMT signal has a
duration of less than 1 ms, and we consider the DAC to be a time-invariant sys-
tem for this short period of time.

3.2 The ideal current-steering DAC

The ideal current-steering DAC is composed of a number of ideal current
sources, I 0, …, I M – 1 , and a number of ideal switches, S 0, …, S M – 1 , as shown in
Figure 3.1. To each current source, I i , we associate a weight, w i , such that

I i = w i ⋅ I unit , (3.1)

where I unit is called the unit current. The DAC shown in Fig. 3.1 utilizes a differ-
ential architecture. The switches are controlled by the digital input such that the
current from source I i is directed to the analog output terminal A + when the dig-
ital input bit b i = 1 , otherwise the current is directed to terminal A – . The total
positive output current is
M–1 M–1
I+ = ∑ bi ⋅ I i = I unit ⋅ ∑ bi ⋅ wi = I unit ⋅ X . (3.2)
i=0 i=0

24
 The ideal current-steering DAC

I0 Ij IN–1

b0 bj bN–1

I+ I–
A+ A–

RL RL

Figure 3.1 The ideal current-steering DAC.

Similarly for the negative output current

M–1
I – = I unit ⋅ ∑ bi ⋅ wi = I unit ⋅ X . (3.3)
i=0

If we let the weights, w i , be the same as for the digital bits, b i , and compare
expression (3.2) with expression (2.8) in Chapter 2, we find that the output cur-
rent I + can be regarded as the output from an ideal DAC. Similarly, the output
current I – can be regarded as the output from an ideal DAC with input
X = [ b N – 1, …, b 0 ] .
Differential architectures are often used to reject noise and distortion [8]. The dif-
ferential output current, I diff , is defined as
M–1
I diff = I + – I – = 2 ⋅ I unit ⋅ ∑ bi ⋅ wi – I unit ⋅ ∑ wi =
i=0
= ( 2 ⋅ I unit ⋅ X – I unit ⋅ X max ) , (3.4)

where X max is the value of X when all bits b i = 1 . From (3.4) we see that the
differential output current can be regarded as the output from an ideal DAC. We
also refer to the outputs in terms of voltages, i.e.,

V + = R L ⋅ I + = R L ⋅ I unit ⋅ X , (3.5)

V – = R L ⋅ I – = R L ⋅ I unit ⋅ X , (3.6)

and

25
Modeling of Current-Steering DACs

V diff = V + – V – = R L ⋅ I diff = 2 ⋅ I unit ⋅ R L ⋅ X – I unit ⋅ R L ⋅ X max , (3.7)

where R L is the load resistance.

We have now shown that the desired operation of an ideal DAC can be achieved
by directing the currents from ideal current sources using ideal switches con-
trolled by the digital input. When implementing current-steering DACs in, e.g.,
CMOS technology, building blocks like the current sources and switches are non-
ideal. In the rest of this chapter, behavioral-level modeling is used to discuss the
impact of nonideal components on the performance characteristics of the current-
steering DAC.

3.3 Modeling of static errors

Static errors are defined as errors that are only depending on the present input
code. This definition is similar to the definition of a static system given in
Sec. 3.1. In this section we discuss two different sources of static errors; compo-
nent mismatch and finite output resistance of current sources.

3.3.1 Component mismatch

Assuming a long channel device and neglecting channel length modulation, the
drain current in an NMOS transistor in the saturation region can be approximated
by

µ ⋅ C ox W 2
I D = ---------------- ⋅ ----- ⋅ ( V gs – V T ) . (3.8)
2 L
The parameter µ is the charge carrier (electron) mobility which is dependent on,
e.g., doping concentration and temperature [14]. C ox is the oxide capacitance per
unit area, and depends on, e.g., the oxide thickness. W and L are the width and
the length of the transistor channel, V gs is the gate-source voltage, and V T is the
threshold voltage, which is dependent on, e.g., the bulk-source voltage of the
transistor. A closer description of MOS transistors is given in Sec. 5.1.
If these transistors are to be used as current sources in a current-steering DAC it
is important that the transistors are well matched to obtain the correct bit weights
(within tolerable margins). Hence, it is desirable to manufacture transistors with
the same value of the parameters µ , C ox , V T , etc. However, when manufacturing
chips, variations in these parameters over the chip area occur, something we refer
to as component mismatch.

26
 Modeling of static errors

On a higher level of abstraction mismatch leads to deviations from the desired

output currents in the current sources implemented with MOS transistors. The
current from current source I i can be expressed as

I i = w i ⋅ I unit + ∆ i , (3.9)

where the first term, w i ⋅ I unit , is the desired current, and the second term, ∆ i , is
the deviation due to mismatch. This is equivalent to the model shown in Fig. 3.2,
where an error current source, ∆ i , is connected in parallel with the desired cur-
rent source, w i ⋅ I unit .

Ii wi Iunit Di

Figure 3.2 Model of current source with matching error.

For good matching it is important to have equivalent geometrical boundary con-

ditions for the devices to be matched [8]. For this purpose it is a common design
strategy to divide the components, e.g., transistors and capacitors, into unit ele-
ments which are connected in parallel. Following this strategy, a current source
with weight w k is constructed connecting w k unit current sources in parallel. We
let { I unit, j } be a set of unit current sources. To each unit current source, I unit, j ,
there is a corresponding matching error, δ j . Further we let J i be a set of w i indi-
ces such that the current

Ii = ∑
j∈J
I unit, j , (3.10)
i

i.e., the current source I i is a parallel connection of the unit current sources
I unit, j with indices j belonging to the set J i . We can rewrite (3.10) yielding

Ii = ∑
j∈J
I unit, j = w i ⋅ I unit + ∑ δ j .
j∈J
(3.11)
i i

The last term in (3.11) is identified as the matching error of I i , i.e.,

∆i = ∑
j∈J
δj. (3.12)
i

If we consider two MOS transistors, M 1 and M 2 , on the same die, biased with
the same voltages and having (nominally) the same geometry, and compare the
corresponding drain currents I 1 and I 2 it has been shown that [15]

27
Modeling of Current-Steering DACs

A I2
Var(I 1 – I 2) = ------------- + S I2 ⋅ D 2 , (3.13)
W⋅L
where D is the distance between the centers of the transistors, and A I and S I are
process dependent constants. We see that for good matching properties (i.e.,
small variance) we should use transistors with large area ( W ⋅ L ) and keep them
as close as possible (small D ). Different yield estimation methods based on
(3.13) have been proposed in the literature [16, 17]. The use of a current-steering
DAC for efficient estimation of the parameters in (3.13) was presented in [18].
Another useful guideline for good matching properties, which is not captured in
(3.13), is to avoid covering the transistors with metal, since metal coverage
increases the variance [19].

Influence of graded element matching errors

In this section we analyze the influence of the second term in (3.13), which is
often referred to as graded matching errors. This analysis was originally pre-
sented in [20].
On a larger scale, graded matching errors are caused by parameters with circular
distribution over the wafer [15], i.e., the value of a parameter is roughly deter-
mined by the distance from the center of the wafer. As a first order approximation
over a small area (e.g., a chip), we can make a Taylor expansion of the parameter
with respect to the geometrical coordinates, which is illustrated in Fig. 3.3.

Figure 3.3 Illustration of a parameter (e.g., oxide thickness) with circular distribution over
the wafer. Over a small area (e.g., a chip) the parameter value can be approxi-
mated with the first order Taylor expansion.

The current from a current source can thus be approximately expressed as

I unit, j = I unit + k x ⋅ x + k y ⋅ y , (3.14)

28
 Modeling of static errors

where k x and k y are constants and x and y are the geometrical coordinates of the
current source with respect to a cartesian coordinate system. The matching error
δ j is given by

δ j( x , y ) = k x ⋅ x + k y ⋅ y . (3.15)

When implementing current-steering DACs, the unit current sources are often
placed in an array, as indicated in Fig. 3.4(a), where each square represents a unit
current source. A straightforward assignment of unit current sources to the differ-
ent current sources I i of a 6-bit binary weighted DAC is shown in Fig. 3.4(b),
where the upper half of the array is dedicated to the most significant bit (MSB),
the upper half of the remaining part of the array to MSB-1, etc., until the remain-
ing bits can be placed in the last row of the array.

y (b) y
5 5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

x 5 5 5 5 5 5 5 5 x

4 4 4 4 4 4 4 4

4 4 4 4 4 4 4 4

3 3 3 3 3 3 3 3

2 2 2 2 1 1 0

(a) (b)
Figure 3.4 (a) Array of unit current sources and (b) unit current source assignment for a 6-
bit binary weighted DAC.

The way of assigning unit current sources indicated in Fig. 3.4(b) is known to
have poor properties in terms of suppressing graded matching errors. Different
layout techniques for suppressing the influence of graded matching errors have
been proposed in the literature [21, 22, 23]. However, we use this approach to
show how matching errors can affect the DAC performance. First of all, we gen-
eralize the concept illustrated in Fig. 3.4(b) for an N -bit binary weighted DAC
with the M least significant bits (LSBs) contained within the bottom row. For
comparison, the DAC in Fig. 3.4(b) has N = 6 and M = 3 . The array will then
have 2 M elements in the x -direction and 2 N – M elements in the y -direction.
Computing the values of the different ∆ i yields

29
Modeling of Current-Steering DACs

∆i = ∑
j∈J
δ j = ∑ kx ⋅ x j + ky ⋅ y j =
j∈J
i i

 x y
= wi ⋅  k x ⋅

∑ -----j + k y ⋅ ∑ -----j  = w i ⋅ ( k x ⋅ x i + k y ⋅ y i ) ,
w
j∈J i j ∈ J i
w
(3.16)
i i

where x j and y j are the coordinates of unit current source I unit, j , and x i and y i
are the average coordinates for the unit current sources assigned to bit i . We nor-
malize the coordinate axis such that the distance between adjacent unit current
sources are unity in both the x - and the y -direction, and we also normalize the
currents so that I unit = 1 . We have that

3
x i = 2 M – 1 + --- ⋅ 2 i for i = 0, …, M – 1 , (3.17)
2

x i = 0 for i = M , …, N – 1 , (3.18)

y i = – 2 N – M – 1 + 2 –1 for i = 0, …, M – 1 , (3.19)

and

3
y i = – 2 N – M – 1 + --- ⋅ 2 i – M for i = M , …, N – 1 . (3.20)
2
The parameter k x only affects the errors for the M LSBs. These errors are typi-
cally much less than the errors for the more significant bits (assuming that k x is
not very large compared with k y ) due to the factor w i in (3.16). With this as an
argument we set k x = 0 to simplify the calculations. This results in

∆ i = w i ⋅ k y ⋅ ( 2 –1 – 2 N – M – 1 ) =
= ( k y ⋅ ( 2 i – 1 – 2 i + N – M – 1 ) ) for i = 0, …, M – 1 (3.21)

and

∆ i = w i ⋅ k y ⋅  --- ⋅ 2 i – M – 2 N – M – 1 =
3
2 

= k y ⋅  --- ⋅ 2 2 ⋅ i – M – 2 i + N – M – 1 for i = M , …, N – 1 .
3
(3.22)
2 

We define the error signal, e(n) , as

30
 Modeling of static errors

N–1 N–1
e(n) = ∑ bi(n) ⋅ I i – ∑ bi(n) ⋅ wi ⋅ I unit , (3.23)
i=0 i=0

i.e., the actual output signal minus the wanted output signal. Clearly,
N–1 N–1
e(n) = ∑ bi(n) ⋅ ∆i = ∑ ei(n) , (3.24)
i=0 i=0

where e i(n) = b i(n) ⋅ ∆ i . The power of this error signal, P e , can be expressed as
N–1
P e = Var(e(n)) = ∑ Var(ei(n)) + i∑≠ j Cov(ei(n), e j(n)) . (3.25)
i=0

If we assume that the probability that b i(n) = 1 and b i(n) = 0 are equal, i.e.,

1
P(b i(n) = 1) = P(b i(n) = 0) = --- (3.26)
2
we obtain

1 1 2
Var(b i(n)) = E(b i2(n)) – E 2(b i(n)) = --- –  --- = --- ,
1
(3.27)
2  2 4

which yields

∆ i2
Var(e i(n)) = Var(∆ i ⋅ b i(n)) = ∆ i2 ⋅ Var(b i(n)) = ------ . (3.28)
4
The covariance terms in (3.25) are signal dependent, since

Cov(e i(n), e j(n)) = ∆ i ⋅ ∆ j ⋅ Cov(b i, b j) (3.29)

and can therefore not be expressed explicitly for an arbitrary signal. We shall in
the following assume that the covariance sum in (3.25) is zero (or small), which
is true if, e.g., the bits are mutually uncorrelated. With this assumption, P e
becomes
N–1
Pe = ∑ Var(ei(n)) . (3.30)
i=0

Combining (3.21), (3.22), (3.28), and (3.30) yields

31
Modeling of Current-Steering DACs

4 –( M + 2 ) ⋅ T ⋅ k y2
P e = ------------------------------------- , (3.31)
105
where T is a number calculated according to

T = 70 ⋅ 2 M + N + 20 ⋅ 2 3M + N + 2 3 + 4N – 35 ⋅ 4 M – 28 ⋅ 4 2M – 35 ⋅ 4 N .
(3.32)
If we assume that the 2 3 + 4N = 8 ⋅ 2 4N term is dominating (which is true for rea-
sonable values of N and M , e.g., N = 14 and M = 6 ), we can approximate P e
with

8 ⋅ 2 4N 2 4N
P e ≈ --------------------------------
- ⋅ k = - ⋅ k y2 .
---------------------- (3.33)
16 ⋅ 105 ⋅ 2 2M y
210 ⋅ 2 2M

For a full-scale sinusoid, a ⋅ sin ( ωt ) with a ≈ 2 N – 1 , the signal power is given by

a2 2 2N – 2 2 2N
P s = ----- = --------------- = -------- (3.34)
2 2 8
and the power of the quantization noise is [7, 9]

1
P Q = ------ . (3.35)
12
Assuming that the quantization noise is uncorrelated with e(n) yields the follow-
ing expression for the SNDR
2( N + M )
Ps 105 ⋅ 2
2
-.
SNDR = ------------------- = --------------------------------------------------- (3.36)
Pe + PQ 4 ⋅ 2 4N ⋅ k y + 70 ⋅ 2 2M

For larger k y (3.36) can be approximated with

SNDR ≈ 14 + 6M – 6N – 20 log k y dB . (3.37)

In [20] there is an analysis of SFDR due to graded matching errors utilizing a

Fourier series expansion of an approximated error signal to estimate the power of
the spurious tones. The resulting expression was given as

SFDR = 21.6 + 6 ⋅ ( M – N ) – 20 log k y dB . (3.38)

To check the validity of (3.37) and (3.38) we have performed some simulations in
Matlab. A 14-bit DAC architecture has been used in the simulation and M has
been chosen to 7. A full-scale sinusoidal input was used, and matching errors

32
 Modeling of static errors

were added to the bit weights according to (3.21) and (3.22). Simulated signal
spectra for k y = 10 –4 and k y = 10 –3 are plotted in Fig. 3.16(a) and (b), respec-
tively. In Fig. 3.16(c) we show simulated and calculated (using (3.36)) values of
SNDR vs. k y . The corresponding plots for SFDR, with the calculated values
given by (3.1), are shown in Fig. 3.5(d). In this example we conclude that simu-
lated and calculated values agree well, e.g., the simulated and calculated SNDR
has a maximum deviation of less than 2.5 dB even if rough approximations are
made. In [20] there was an extended analysis taking into account the correlation
between the input bits b N – 1 and b N – 2 , reducing the maximum deviation
between the curves to approximately 0.1 dB.
−5 −4
Output signal spectrum, k =10 Output signal spectrum, k =10
y y

0 0

−20 −20

−40 −40
PSD [dB]

PSD [dB]

−60 −60

−80 −80

−100 −100

−120 −120
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Normalized frequency Normalized frequency

(a) (b)
SNDR vs. ky SFDR vs. ky
90 120
simulated simulated
calculated calculated
110
80
100
70 90

60 80
SNDR [dB]

SFDR [dB]

70
50
60
40 50
40
30
30
20
20

10 −7 −6 −5 −4 −3 −2
10 −7 −6 −5 −4 −3 −2
10 10 10 10 10 10 10 10 10 10 10 10
ky ky

(c) (d)
Figure 3.5 Simulated signal spectra of 14-bit DAC with M = 7 for (a) k y = 10 –4 and (b)
k y = 10 –3 . The plots in (c) and (d) show simulated (dashed) and calculated
(solid) values of SNDR and SFDR vs. k y .

33
Modeling of Current-Steering DACs

Modeling of random matching errors

Special layout techniques are often used to reduce or eliminate the influence of
graded element matching errors, e.g., distributed biasing discussed in Sec. 4.1.2.
However, if this is done, random parameter variations, which can be modeled as
spatial white noise [15] and correspond to the first term in (3.13) still remain.
Unit current sources with random matching errors are often modeled as

I unit, j = I unit + δ j , (3.39)

where δ j is an observation of a stochastic variable ∆ j with zero mean and Gaus-

sian distribution [15, 24]

∆ j ∈ N (0, σ) , (3.40)

where the different ∆ j are mutually uncorrelated. This way of modeling match-
ing errors will be used in Chapter 4 to analyze some methods for error compensa-
tion.

3.3.2 Finite output resistance

The ideal current source has infinite output resistance, i.e., the output current is
independent on the voltage across the current source. When implementing cur-
rent sources in, e.g., MOS or bipolar technologies, the output resistance is finite.
We now examine what influence the finite output resistance will have on the
transfer characteristics of the DAC. The results presented here have previously
been presented by Wikner in [25], and are not original parts of this work. It is
included here because it provides a good starting point for the modeling of finite
output impedance, including capacitive parts, in Sec. 3.4.
Assume that we have unit current sources with finite output resistance, R unit . For
input code X there are X unit current sources connected in parallel to the output
node. The equivalent circuit model for the DAC is shown in Fig. 3.6.

VDD

IunitX Runit/X

Vout(X)

RL

Figure 3.6 Equivalent model of current-steering DAC with current sources having finite
output resistance.

34
 Modeling of dynamic errors

The output voltage of the circuit in Fig. 3.6 is

V DD 
V out(X ) =  I unit + ----------
X
- ⋅ ----------------------------- ⋅ R L , (3.41)
 R unit RL
1 + ----------- ⋅ X
R unit

which clearly is a nonlinear function of X . Thus, the finite output resistance in

the current sources introduces nonlinear behavior, and we can conclude that is
important to have high output resistance compared with the load resistance to get
high linearity. Equation (3.41) can be used to find design criteria for the output
resistance of the current sources [26].

3.4 Modeling of dynamic errors

Modeling of different sources of dynamic errors is discussed in this section. The
error focused on in this work is the error caused by the nonzero output capaci-
tance of current sources. Nonlinear behavior due to parasitic capacitance is a
known phenomenon [27]. The work presented in this section contributes with
two different behavioral-level models that have been developed by the author,
one of which is closer to a circuit-level model.

3.4.1 State-space model of a current-steering DAC

The finite output resistance of the current sources was mentioned as a limitation
of the DAC performance in Sec. 3.3.2. In this section we present a model of the
DAC which also includes parasitic capacitance in the current sources and the
wires. The system of differential equations describing the DAC during an update
period is expressed on a state-space form. A numerical computation program,
e.g., Matlab, can then be used to calculate the final values of the different volt-
ages in the circuit, i.e., the values of the voltages at the end of the update period.
The model presented in this section was first introduced in [28].

Modeling of nonideal DAC components

The ideal current source shown in Fig. 3.7(a) has infinite output impedance. A
single transistor and a single cascode version of a PMOS current source are
shown in Fig. 3.7(b) and (c), respectively. The cascode transistor increases the
output resistance (see Sec. 5.2.1), but the source still has finite output impedance,
as indicated in the linearized model of a current source in Fig. 3.7(d).
Results from simulations of the output impedance of a single transistor current
source and a single cascode current source [7] are shown in Fig. 3.8. The simula-
tion used PMOS transistor parameters for a 0.35 µm CMOS process.

35
Modeling of Current-Steering DACs

Vbias

Iout Iout

(a) (b)

Vbias source transistor

I
Rout Cout
cascode transistor
Vcasc Vout
Iout
Iout

(c) (d)
Figure 3.7 (a) Ideal current source, (b) single transistor PMOS implementation of a current
source, (c) single cascode PMOS implementation of a current source, and (d)
linearized model of the nonideal current source.

W ⁄ L = ( 2 µm ) ⁄ ( 10 µm ) for the source transistor and the corresponding ratio

for the cascode transistor is W ⁄ L = ( 2 µm ) ⁄ ( 1 µm ) . The current is 1.22 µA .
We can see that the output resistance (i.e., output impedance at low frequencies)
of the cascode current source is higher than for the single transistor current
source. For higher frequencies the capacitive part of the output impedance
becomes dominating, and for the frequencies where the output impedance for
both types of current sources is essentially capacitive, they both have the same
output impedance. This is true provided that all transistors are equally wide,
since the output capacitance is more or less the parallel connection of an overlap
capacitance and a junction capacitance, which are both depending on the transis-
tor widths [14]. For the cascode current source it is the parasitic capacitance in
the cascode transistor that dominate. More information on the implementation of
current sources is given in Chapter 5.
Use of differential signal paths is an efficient way of rejecting noise and distor-
tion, e.g., substrate noise or channel charge injection, provided that the two paths
are symmetrically designed [8]. Therefore, differential current switches are com-
monly used and they are implemented with two or more MOS transistors in par-
allel, as shown in Fig. 3.9(a). In this work the switch is represented by the MOS

36
 Modeling of dynamic errors

|Zout(f)| for single transistor (solid) and single cascode (dashed)

10
10

Output impedance [Ω]

9
10

8
10

7
10

6
10

2 3 4 5 6 7 8
10 10 10 10 10 10 10
Frequency [Hz]

Figure 3.8 Output impedance vs. frequency for (a) a single transistor current source, and
(b) a single cascode current source.

switch-on resistance, as shown in Fig. 3.9(b), assuming that the switch transistor
operates in the linear region. This is a simplification, because the voltage over the
switch is varying with the output voltage of the DAC, and for some configura-
tions the switch transistor may even enter the saturated region. Thus, the linear-
ized model of the switch is a coarse approximation. However, it is good enough
to illustrate the effect of finite output impedance in the current sources. There is
also parasitic capacitance in the switch, but it is lumped into the parasitics of the
current source and output wire.

Iin

Iin
Rswitch

Q+ Q–

Iout+ Iout–

Iout+ Iout–

(a) (b)
Figure 3.9 (a) Example of a differential PMOS switch and (b) linearized model of the dif-
ferential switch.

37
Modeling of Current-Steering DACs

The output wires of the DAC should have zero impedance to reduce the internal
voltage drop. In reality, the wires contain resistive as well as capacitive and
inductive parts [29]. For high accuracy, a transmission line model or an RC-lad-
der network should be used as a model for the wire. However, we want to achieve
short simulation times, so a small number of circuit nodes is desired. Therefore,
we trade accuracy for a lower degree of complexity in the model. As an approxi-
mation we use a resistor and capacitor in parallel, i.e., a simple RC-ladder, as
shown in Fig. 3.10. The impedance includes the internal wire impedance as well
as the off-chip load.

Figure 3.10 Model of the output wire load.

Circuit-level model of the DAC

The model of the complete current steering DAC is found by replacing the com-
ponents of the ideal DAC in Fig. 3.1 with their nonideal counterparts presented in
the previous section. This yields the schematic in Fig. 3.11.
To simplify further analysis, we first examine the current-voltage relationship for
the model of the current source in Fig. 3.7(d). We have

( V DD – V out(t) ) ∂
I out(t) = I + ------------------------------------- – C out ⋅ V out(t) =
R out ∂t
V out(t) ∂
- – C out ⋅ V out(t)
= Ĩ – --------------- (3.42)
R out ∂t

where

V DD
Ĩ = I + ---------- . (3.43)
R out

38
 Modeling of dynamic errors

VDD
I0 R0 C0 Ij Rj Cj IN–1 CN–1
RN–1

Rs0 Rsj RSN–1

Figure 3.11 Circuit schematic of the model of the nonideal differential current-steering
DAC.

Hence, the linearized model of a unit current source is equivalent to the circuit in
Fig. 3.12, where the current I unit is replaced with the slightly larger current Ĩ unit
and the output impedance connected to ground instead of V DD . This is the model
we will use from now on to eliminate terms including V DD from the calculations.

Ĩ unit

output impedance

Figure 3.12 Equivalent circuit of current source.

Assume that we during an update period have a value of the digital input, X , such
that K of the current sources are connected to one of the analog outputs. For sim-
ple notation we let these current sources, I j , have indices j = 1, 2, …, K . The
circuit schematic for this specific configuration shown in Fig. 3.13.
The following relations between voltages and currents hold for this circuit

39
Modeling of Current-Steering DACs

I1 IK
V1 VK

Rs1 R1 C1 RsK RK CK

Iout1 IoutK

R C

Figure 3.13 Circuit schematic of one output during an update period for a certain value of
the input X .

V j(t) ∂
I outj(t) = I j – ----------- – C j ⋅ V i(t) for j = 1, 2, …, K , (3.44)
Rj ∂t

V j(t) – V (t)
- for j = 1, 2, …, K ,
I outj(t) = -------------------------- (3.45)
R sj

V (t )
I (t) = --------- , (3.46)
R
and
K
∂
I (t) = ∑ I outj(t) – C ⋅ ∂ t V (t) . (3.47)
j=1

Combining (3.44) and (3.45) yields

∂
V i(t) = ------ ⋅ I j – V j(t) ⋅  ----- + ------- + V (t) ⋅ ------- .
1 1 1 1
(3.48)
∂t Cj  R j R sj R sj

In a similar way, combining (3.45), (3.46), and (3.47) yields

K K
∂ V j(t) 1 1
∑ ∑
1
V (t) = ---- ⋅ ----------- – V (t) ⋅  --- + ------- . (3.49)
∂t C R sj R R sj
j=1 j=1

40
 Modeling of dynamic errors

We let T denote the update period of the DAC. We are interested in finding the
values of the different nodal voltages at the end of the update period. For this pur-
pose we define the voltage vector

V (t) = [ V 1(t), V 2(t), …, V K (t), V (t) ] T . (3.50)

For simplicity we let the update period start at time t = 0 . We further define the
state vector

X(t) = V (t) – V (0 –) , (3.51)

where V (0 –) contains the initial voltages, i.e., the voltages just before the switch-
ing occurs. The state vector X should not be confused with the input X . Using
(3.48)-(3.51) we can now express the system of differential equations for the
DAC as

∂ ∂
V (t) = X(t) = A ⋅ X(t) + B ⋅ u(t) , (3.52)
∂t ∂t
where

 -----
1
- + -------- ------
1 1
0 … 0
1 1
-------- ------
 R 1 R s1 C 1 R s1 C 1

0  -----
1
- + -------- ------ …
1 1
0
1 1
-------- ------
 R 2 R s2 C 2 R s2 C 2

A = … … … … …

…  ------- + -------- -------

1 1 1 1 1
0 0 -------- -------
 R K R sK  C K R sK C K
K
1 11
∑
1 1 1 1 1 1
-------- ---- -------- ---- … -------- ---- –  --- + ------- ----
R s1 C R s2 C R sK C R R sj C
j=1

(3.53)
and

41
Modeling of Current-Steering DACs

I1 I2 IK T
B = A⋅ V (0 –) + ------, ------, …, -------, 0 . (3.54)
C1 C2 CK

u(t) is a unit step used to apply the initial conditions given in B at time t = 0 . A
simple manipulation of (3.51) yields

Y (t) = V (t) = X(t) + V (0 –) . (3.55)

Equations (3.52)-(3.55) form a state-space representation of a linear system with
input u(t) and output Y (t) [30, 31]. Hence, the nodal voltages in the DAC circuit
are given as the step response of a linear system on a state-space form. This kind
of system can easily be simulated with, e.g., Matlab or another numerical compu-
tation tool.
The following algorithm is used for simulation of the model.
1. For a given value of the input, X , find the appropriate matrix A representing
one of the output terminals.
2. Use the final voltages from the last update period as initial values to calculate
the vector B . (Reasonable initial voltages are assigned for the first update
period.)
3. Calculate/simulate the final value of V (t) , e.g., with a numerical computation
tool like Matlab.
4. Repeat steps 1 through 3 for the other output terminal.
In this way we calculate the final values of all the nodal voltages in the circuit,
which reenter as initial values for one or the other output terminal in the next
update period. The outputs from the DAC, V +(n) and V –(n) , are given as the out-
put node voltage at the end of each update period, i.e., V (nT ) . If current is pre-
ferred as output, each output voltage is divided by the corresponding load
resistance.

Simulations
In this section we present simulation results to illustrate the effect of the nonideal
components introduced in the model. We consider a 14-bit binary weighted
architecture. The parameters used in the simulations are given in Table 3.1.
Fig. 3.14(a) and (b) show simulated PSD plots for single-ended and differential
outputs, respectively. The input is a full-scale, single-tone signal with signal fre-
quency f sig = 1.104 MHz and update frequency f u = 10 MHz .
Fig. 3.15 show the simulated PSD plots when the signal frequency is reduced to
f = 110.4 kHz , i.e., one tenth of the signal frequency used in Fig. 3.14. Com-
paring the two figures we find that the harmonic distortion is largely reduced

42
 Modeling of dynamic errors

Parameter Value
Unit current 1.22 µA
Output resistance, unit current source 1 GΩ
Output capacitance, unit current source 5 fF
100 Ω , j = 0, …, 7
Switch resistance
100 ⋅ 2 7 – j Ω , j = 8, …, 13
Load resistance 70 Ω
Load capacitance 200 pF
Table 3.1 Model parameter values used in the simulations.

PSD for single−ended output signal PSD for differential output signal

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]

−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 3.14 Simulated (a) single-ended and (b) differential outputs for a full-scale single-
tone input with 10 MHz update frequency and 1.104 MHz signal frequency.

when the signal frequency is lowered. For the differential case the SFDR (deter-
mined by the third harmonic) is increased from 70 to 87 dB. We can also see that
the even order harmonics that appear in the single-ended spectra (the (b) figures)
are efficiently cancelled in the differential case.
In Fig. 3.16 we show how SFDR varies with signal frequency for a half-scale sin-
gle-tone signal with update frequency f s = 10 MHz . This behavior is typical
for current-steering DACs [10, 32, 33], compare, e.g., with the measurement
results presented in Chapter 5.

43
Modeling of Current-Steering DACs

PSD for single−ended output signal PSD for differential output signal

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]
−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 3.15 Simulated (a) single-ended and (b) differential outputs for a full-scale single-
tone input with 10 MHz update frequency and 110.4 kHz signal frequency.

SFDR vs fsig, single−ended output SFDR vs fsig, differential output

90

70
85
SFDR [dB]

SFDR [dB]

65 80

75
60

70

55
5 6 5 6
10 10 10 10
Frequency [Hz] Frequency [Hz]

(a) (b)
Figure 3.16 Simulated SFDR as a function of signal frequency for (a) single-ended output
and (b) differential output. The update frequency is 10 MHz, and the signal is a
full-scale single-tone signal.

3.4.2 A low-complexity model

In this section we present a model with much lower computational complexity
than the state-space model in the previous section. One use of a model with low
computational complexity is that it can be implemented on-chip, to a relatively
low hardware cost, and used for error estimation in error compensation tech-
niques. Examples on such techniques are presented in Chapter 4.

44
 Modeling of dynamic errors

A simple DAC model

The nonlinear behavior in the models presented in Sec. 3.3.2 and Sec. 3.4.1, is
caused by a signal dependent parasitic network connected to the internal nodes of
the DAC. Consider the simplified case when this parasitic network is reduced to a
single signal dependent capacitor connected to the output node, as illustrated in
Fig. 3.17.

IX

V(t)

R CX

Figure 3.17 DAC model with signal dependent capacitive load.

This is a single pole system with the output voltage, V (t) , given by
t – t0
 – ------------
V (t) = V (t 0) + ( I X ⋅ R – V (t 0) ) ⋅  1 – e RC X  , (3.56)
 

where I X is the output current for the input code X , nominally I unit ⋅ X , and C X
is the signal dependent parasitic load. In discrete time we are interested in the
value of the output at multiples of the update period T , i.e.,

T
 – -----------
Y (n) = V (nT ) = Y (n – 1) + ( I X ⋅ R – Y (n – 1) )  1 – e RC X , (3.57)
 

where t 0 has been chosen as ( n – 1 )T . From (3.57) it can be seen that Y (n) is
depending on Y (n – 1) , which in turn is dependent on Y (n – 2) , etc. Thus, the
nonlinearity is dynamic and has infinite memory. We can however define a static
parameter describing the error, namely the relative step error

Y (n) – Y (n – 1)
e rel(X ) = 1 – ------------------------------------ (3.58)
Y X – Y (n – 1)

where Y X is the settled output value for input code X , Y X = I X ⋅ R for the sim-
ple model in Fig. 3.17. Combining (3.57) and (3.58) yields

45
Modeling of Current-Steering DACs

T
– -----------
RC X
e rel(X ) = e (3.59)

for the simple model in Fig. 3.17. This expression can be interpreted as that the
DAC has a signal dependent settling time constant τ X = RC X .

Model structure
Based on the simple model in the previous section, we propose a low-complexity
model to be used for estimation of the output in a current-steering DAC with non-
zero output capacitance in the current sources, as discussed in Sec. 3.4.1. We start
by normalizing the output such that

YX = X , (3.60)

i.e., we let the static gain of the DAC be unity. We rewrite (3.57)-(3.59) yielding

Y (n) = Y (n – 1) + [ Y X (n) – Y (n – 1) ] ⋅ [ 1 – e rel(X (n)) ] =

= Y (n – 1) + [ X (n) – Y (n – 1) ] ⋅ [ 1 – e rel(X (n)) ] , (3.61)

which is the first approach to the low-complexity model. A block diagram of a

circuit that calculates (3.61) is shown in Fig. 3.18. The relative step error is stored
in a lookup table. If e rel(X ) can be well approximated with a piece wise constant
function, the lookup table can be addressed by a few MSBs of X (instead of all
bits), and the size of the lookup table can be reduced.

X(n) lookup erel(n) Y(n)

table

z–1
Figure 3.18 Proposed model.

The state-space model presented in Sec. 3.4.1 is used as a reference to investigate

if the model given by (3.61) is reasonable. The model parameters given in
Table 3.1 on page 43 is used in a simulation, and the input is a white noise signal
with rectangular distribution where all input codes are equally probable. The
length of the signal is 2 16 samples. In Fig. 3.19(a) we plot observations of

Y (n) – Y (n – 1)
e rel(X (n)) = 1 – ------------------------------------- (3.62)
Y X (n) – Y (n – 1)

46
 Modeling of dynamic errors

as a function of X (n) . In (3.62) we use Y X (n) instead of X (n) in the denominator,

because the finite output resistance yields a nonlinear static transfer function of
the model, and by (3.58), e rel is a measure of the deviation from this static trans-
fer curve. However, for estimation of errors at frequencies, where the dynamic
errors dominate, it is sufficient to assume that the static transfer characteristic is
linear. A large spread in e rel can be observed in Fig. 3.19(a). This is because it is
not only the value of the capacitive load that determines the step error, but also
the initial values of the voltages across the capacitances. These initial values are
roughly determined by X (n – 1) , so a natural modification of the model is to
assume that e rel is a function of X (n) and X (n – 1) . In Fig. 3.19(b) we plot the
observed values of e rel together with estimated values. The estimations have
been made using 5 MSBs of X (n) and 3 MSBs of X (n – 1) . The estimated values
have been taken as the mean value of all observations having the same value of
the 5 MSBs of X (n) and the 3 MSBs of X (n – 1) . Each of the lines in
Fig. 3.19(b) represents a specific value of X (n – 1) quantized to 3 bits. From the
plot in Fig. 3.19(b) we conclude that it is reasonable that a better estimation of
e rel is found if X (n – 1) is used together with X (n) than if X (n) is used alone.

−3 erel vs X −3 erel vs X
x 10 x 10
10 10

5 5
Relative error

Relative error

0 0

−5 −5
0 2000 4000 6000 8000 10000 12000 14000 16000 0 2000 4000 6000 8000 10000 12000 14000 16000
Input code Input code

(a) (b)
Figure 3.19 The relative step error, e rel , plotted as a function of the input code X (a) with-
out and (b) with the estimated values using the low-complexity model.

The modified approach is given by

Y (n) = Y (n – 1) + [ Y X (n) – Y (n – 1) ] ⋅ [ 1 – e rel(X (n), X (n – 1)) ] . (3.63)

A block diagram of a circuit that calculates (3.63) is shown in Fig. 3.20. Again
we have set the static gain of the DAC to unity, replacing Y X with X in (3.63).
The lookup table may be addressed by only a few MSBs of X (n) and X (n – 1) to
keep the size of the lookup table small, as discussed above.

47
Modeling of Current-Steering DACs

X(n)
z–1 lookup erel(n) Y(n)
table

z–1
Figure 3.20 Block diagram for the modified approach.

Simulation of the low-complexity model

Simulation plots from the model type in Fig. 3.20 are shown in Fig. 3.21. The
parameters in the lookup table have been extracted from the model presented in
Sec. 3.4.1 using the parameters given in Table 3.1 on page 43. 5 MSBs from
X (n) and 5 MSBs from X (n – 1) have been used for estimation of e rel . The
spectra in Fig. 3.21 correspond to the spectra in Fig. 3.14, and there is a good
agreement between the simulation results from the two different models. An
important difference is that the simulation time is reduced to approximately a
tenth using the low-complexity model. Moreover, solving the state-space equa-
tions is a complex task and is not suitable for simple on-chip estimation of errors,
whereas the solutions in Fig. 3.18 and Fig. 3.20 require relatively little hardware
provided that the lookup tables are reasonably small.
The agreement between simulation results from the state-space model and the
low-complexity model is further illustrated in Fig. 3.22. Simulated SFDR as a
function of the signal frequency for the differential output of the low-complexity
model using a 10 MHz update frequency is shown Fig. 3.22(a). The correspond-
ing plot for the state-space model is shown in Fig. 3.22(b), and a good agreement
between the two plots can be observed.

3.5 Combined models

In previous sections of this chapter we have isolated a nonideal property of a cur-
rent-steering DAC, and discussed the impact of that property on the performance
of the DAC. In reality, all these nonideal properties are present at the same time.
To get more realistic simulation results, the models should be combined and sim-
ulated together. Such combined modeling was used to simulate the behavior of a
current-steering dynamic element matching (DEM) DAC [34, 35]. The results
from this work is presented in Sec. 5.6.2. The comparisons between simulations
and measurements presented there provide a validation of the state-space model
in Sec. 3.4.1.

48
 Combined models

Single−ended PSD for low−complexity model Differential PSD for low−complexity model

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]
−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 3.21 (a) Single-ended and (b) differential outputs for a full-scale single-tone input
with 10 MHz update frequency and 110.4 kHz signal frequency simulated with
the low-complexity model.

SFDR vs fsig, differential output SFDR vs fsig, differential output

90
90

85
85
SFDR [dB]

SFDR [dB]

80
80

75
75

70 70

5 6 5 6
10 10 10 10
Frequency [Hz] Frequency [Hz]

(a) (b)
Figure 3.22 Simulated SFDR as a function of signal frequency for differential output signals
with full-scale amplitude. The plot in (a) shows the results for the low-complex-
ity model, whereas (b) shows the results for the state-space model for compari-
son.

49
Modeling of Current-Steering DACs

50
 4 Compensation and
Correction of Errors
It can be hard to meet a DAC design specification using a straightforward imple-
mentation. In this chapter we present some ideas on how to compensate for the
errors, in order to improve the linearity of the circuits. So called predistortion is a
family of techniques widely used in telecommunication circuits, mostly RF
power amplifiers, to enhance the linearity and, thereby, improve the quality of the
communication link. The idea is to use models of the nonlinearity and modify the
input signal in order to get the desired output signal. Other techniques, e.g.,
dynamic element matching (DEM), rely on randomization in order to change the
spectral properties of the nonlinearities from spurious tones to (white or shaped)
noise.
The presentation of the different techniques given in this chapter has been
divided into two main groups, compensation and correction of static errors,
which is presented in Sec. 4.1, and compensation and correction of dynamic
errors, which is presented in Sec. 4.2.

4.1 Compensation and correction of static errors

In this section we discuss compensation of static errors in DACs caused by
matching errors in the current sources. In Sec. 4.1.1 and Sec. 4.1.2 we discuss
methods aiming for reduction of the matching errors between the different cur-
rent sources using calibration and careful design styles. In the DEM methods pre-
sented in Sec. 4.1.3, special randomization techniques make it possible to alter
the spectral properties of the errors in a favorable way.

51
Compensation and Correction of Errors

4.1.1 Calibration of the MSBs

One way of reducing the distortion caused by inadequate matching is to calibrate
the current sources, in order to get output currents closer to the nominal currents
than would be the case without calibration. A method for calibrating the most
significant current sources in a binary weighted DAC is proposed in this section.

Basic idea
The idea behind the proposed calibration method is to remove the DNL error in
the transition from X = [ 0, 1, 1, …, 1 ] to X = [ 1, 0, 0, …, 0 ] . This error is
often the dominating one in binary coded DACs due to the large amount of
switches turning on and off. To achieve this, the MSB current, I N – 1 , is substi-
tuted with a current
N–2
Ĩ N – 1 = I unit + ∑ Ij, (4.1)
j=0

with the intention of using the currents from the less significant bits and one addi-
tional unit current source as reference for the calibration. The DNL and INL for a
12-bit binary coded DAC with random matching errors having a standard devia-
tion of 1% are shown in Fig. 4.1 and Fig. 4.2, respectively. Values without cali-
bration are given in the (a) figures, whereas values with calibration are given in
the (b) figures. In Fig. 4.2(a) we can observe a problem with the binary weighted
architecture in that its transfer characteristics is not always monotone. In this
case,
N–2
IN – 1 < ∑ Ij. (4.2)
j=0

It is therefore common to use thermometer coded or segmented architectures

instead, which is further discussed in Sec. 5.3.1.
PSD plots of full-scale single-tone signals without and with calibration are shown
in Fig. 4.3(a) and (b), respectively. For this particular stochastic outcome, the
SFDR is improved from 66 dB to 80 dB when calibration is applied. It can be
concluded that the proposed calibration method improves the static linearity of
the binary weighted DAC for this particular case. The proposed method can eas-
ily be extended to calibrating more bits than one [36], starting with the least sig-
nificant of the bits to be calibrated, proceeding with the next bit until the most
significant bit has been calibrated.

52
 Compensation and correction of static errors

DNL curve, uncalibrated DAC DNL curve, calibrated DAC

1 1

0.5 0.5

0 0

−0.5 −0.5

−1 −1
DNL

DNL
−1.5 −1.5

−2 −2

−2.5 −2.5

−3 −3

−3.5 −3.5

−4 −4
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
Input code Input code

(a) (b)
Figure 4.1 DNL for binary weighted DAC (a) without and (b) with calibration of the MSB.

INL curve, uncalibrated DAC INL curve, calibrated DAC

3 3

2 2

1 1
INL

INL

0 0

−1 −1

−2 −2

−3 −3
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
Input code Input code

(a) (b)
Figure 4.2 INL for binary weighted DAC (a) without and (b) with calibration of the MSB.

Output spectrum, uncalibrated DAC Output spectrum, uncalibrated DAC

0 0

−20 −20

−40 −40
PSD [dB]

PSD [dB]

−60 −60

−80 −80

−100 −100

−120 −120
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Normalized frequency Normalized frequency

(a) (b)
Figure 4.3 PSD plot for full-scale single-tone signals (a) without and (b) with calibration of
the MSBs.

53
Compensation and Correction of Errors

Proposed implementation
A proposed circuit for the calibration technique is shown in Fig. 4.4. The calibra-
tion phase is shown in Fig. 4.4(a). A current mirror is utilized to construct the dif-
ference ∆I N – 1 = I N – 1 – Ĩ N – 1 , and a current memory is set to hold the current
∆I N – 1 . During the operation phase, shown in Fig. 4.4(b), the current memory is
utilized to subtract the current ∆I N – 1 from I N – 1 , yielding the total output cur-
rent Ĩ N – 1 .

IN–1 IN–2 I0 Iunit

DIN–1

current
current memory mirror

(a)
IN–1 IN–2 I0

DIN–1

(b)
Figure 4.4 Proposed circuit solution for the calibration technique during (a) the calibration
phase and (b) the operation phase.

54
 Compensation and correction of static errors

Qualitative comparison with other calibration techniques

In other calibration techniques [32], a capacitor is used to hold the proper gate
potential for the current source. Charge leakage in that capacitor causes a
decrease in the output current over time, so periodical recalibration of the current
sources are required.
Charge leakage also causes the current in the current memory, used in the pro-
posed technique, to decrease. However, if the current sources are carefully
designed, so the matching errors are small, the current ∆ i will also be small.
Hence, even if charge leakage resets the current memory, yielding the total output
current I N – 1 instead of Ĩ N – 1 , the performance of the DAC is not as severely
deteriorated as is the case when the complete output current is stored in a current
memory. A similar idea is used in [37], where a static DC current source is set to
deliver approximately 90% of the nominal current, and a current memory is used
for fine tuning the remaining part.

4.1.2 Distributed biasing

The impact of graded element matching errors was discussed in Sec. 3.3.1. One
technique that can be used to reduce the effect of graded errors is distributed bias-
ing [21, 38]. This design technique is used in the DAC presented in Sec. 5.7 to
obtain good matching properties.
A multiple-output PMOS current mirror is shown in Fig. 4.5. If we neglect the
influence of channel-length modulation (i.e., let the output transistors have infi-
nite output resistance), we have that

W out
I out, j = ----------- ⋅ I in (4.3)
W in

provided that the output transistors are operating in the saturated region and that
the transistors are perfectly matched. The transistors have the same length. W out
denotes the width of the output transistors and W in is the width of the input tran-
sistor. In the following we discuss how current mirrors can be utilized for biasing
current sources and how the matching properties are affected.
In Fig. 4.6(a) we show an example where the current-source array is made up of
the output transistors of a single multiple-output current mirror. Graded parame-
ter variations, discussed in Sec. 3.3.1, cause the output currents from the different
current sources to vary over the array. The matching of output currents can be
improved by partitioning the array of current sources into smaller parts, letting
each such part be an individual multiple-output current mirror, as indicated in
Fig. 4.6(b). This is because the bias voltage ( V b in Fig. 4.5) is set individually for

55
Compensation and Correction of Errors

Vb

Iin Iout,1 Iout,K

Figure 4.5 Multiple output PMOS current mirror.

each current mirror. If the input transistors are located close to the output transis-
tors, the bias voltage is set to give the proper output current for the values of tran-
sistor parameters in the proximity of the input transistors, reducing the current
variations over the array due to graded parameter mismatch, compared with the
approach in Fig. 4.6(a). The biasing strategy has no effect on the influence of ran-
dom matching errors, so this problem remains.

4.1.3 Dynamic element matching

This section is an overview of dynamic element matching (DEM) techniques.
The purpose is to provide a background to DEM, in order to simplify the under-
standing of the description of the DEM DAC presented in Sec. 5.6, were mea-
surement and simulation results can be found as well.
If the error in the output level, e , is determined by the input code, X , i.e.,
e(n) = f (X (n)) , the same error will occur each time a certain input code, X , is
applied. Hence, if the input signal X (n) is periodic (which is the case for, e.g., a
sinusoidal input signal), e(n) will also be periodic with the same fundamental
frequency as the input signal. This results in harmonic distortion, unless the error
is a linear gain error, e(n) = K ⋅ X (n) where K is a constant. DEM techniques
utilize randomization to make sure that the input code X do not cause the same
error each time it is applied. Generally, one can say that e(n) = f (X (n), r(n)) ,
where r(n) is a control signal. The control signal may, e.g., be random or a deter-
ministic function of the input. In this way, the error signal is changed from yield-
ing harmonic distortion to having more noise-like properties.
Some DEM algorithms transform distortion into white noise, whereas the noise-
shaping DEM techniques moves a large amount of the noise out of the signal
band. These two types of DEM are discussed in this section. There are also DEM
techniques that minimize the number of switching events [39, 40], and hence the
glitches. These techniques will not be further discussed here. DEM is especially

56
 Compensation and correction of static errors

Ibias Ibias,1

Ibias,2

current source array current source array

Ibias,K

(a) (b)
Figure 4.6 Current-source arrays with (a) global and (b) distributed bias.

suitable in audio applications where the signal bandwidths are low (compared
with, e.g., DSL applications) and a large amount of oversampling can be
afforded.

Generalized DEM
A general DEM DAC is shown in Fig. 4.7. The input, X 1(n) , is converted into a
thermometer coded signal

X 2(n) = [ t K (n), t K – 1(n), …, t 2(n), t 1(n) ] . (4.4)

The bits of X 2(n) are scrambled yielding a third code

X 3(n) = [ u K (n), u K – 1(n), …, u 2(n), u 1(n) ] , (4.5)

such that

57
Compensation and Correction of Errors

u i(n) = t j(n) , (4.6)

and for each j there is exactly one i such that (4.6) holds. Which t j(n) is mapped
on what u j(n) is determined for each update instant n by the control signal r(n) .
Each u i(n) is an input to a one bit DAC with nominal gain w and an associated
matching error ∆ i . The outputs from all one bit DACs are summed, yielding the
total output
K K K
Y (n) = ∑ ( w + ∆i ) ⋅ ui(n) = w ⋅ ∑ ui(n) + ∑ ∆i ⋅ ui(n) =
i=1 i=1 i=1
K
= w ⋅ X 1(n) + ∑ ∆i ⋅ ui(n) , (4.7)
i=1

where the first term in is the desired output, and the second term is the error due
to mismatch. Without scrambling, the error becomes
K

∑ ∆i ⋅ t i(n) (4.8)
i=1

and harmonic distortion occurs because the resulting error is periodic. This is not
true in DEM DACs, provided that the control signal r(n) is properly chosen. The
scrambling ensures that different errors occurs for the same input code at differ-
ent update instants, a property which is used to transform harmonic distortion
into noise. The overall SNDR is improved if oversampling is used, because the
out-of-band noise can be filtered out.
A straightforward implementation of the digital circuits required in DEM may
result in high hardware complexity. There is a large amount of research on DEM
circuit techniques with reduced hardware complexity presented in the literature
[41, 42]. Some of these techniques are overviewed in the following sections. For
comparisons of different networks used for DEM realizations, see, e.g., [43, 44].

DEM utilizing switching trees

One approach to implement DEM uses a tree of switches according to Fig. 4.8.
The input to the tree, denoted X (n) in Fig. 4.8, is binary coded, so the tree per-
forms both the binary-to-thermometer encoding and the scrambling. Each switch
layer, i , is controlled by a pseudo random control signal, r i(n) ∈ { 0, 1 } . A
switch has one M -bit input and two ( M – 1 )-bit outputs, which we denote out 1
and out 2 , that are inputs to the switches in the following layer. If r i = 1 , then
the bits of the ( M – 1 )-bit output out 1 are given the values of the M – 1 LSBs of

58
 Compensation and correction of static errors

binary-to-thermometer encoder

scrambler
X1(n)

1-bit combined
X2(n)

X3(n)
r(n)

DACs output

Figure 4.7 Generalized block diagram of a DEM DAC.

the input, whereas the value of the MSB of the input is assigned to all individual
bits of out 2 . When r i = 0 the MSB of the input is instead mapped on the bits of
out 1 , and the M – 1 LSBs of the input are mapped on out 2 . The number of out-
put bits for each switch is linearly decreasing with decreasing layer index, and
the tree is terminated with the switching layer having 1-bit outputs. These 1-bit
signals constitute a scrambled, thermometer coded word that is used to control 1-
bit DACs, whose outputs are summed yielding the total output for the DEM
DAC.
An additional bit with the same weight as the LSB, and fixed value ‘0’, is added
to the binary weighted input to give the LSBs the same total weight as the MSB.
This is required because there is an even number of output bits from the switch-
ing tree, whereas a thermometer coded word has an odd number of bits. This
results in that at least one of the output bits from the tree will have the value ‘0’.

Partial randomization DEM

The tree approach described above is known as full randomization DEM
(FRDEM). For DACs with a large number of input bits, the hardware complexity
of the FRDEM switching tree becomes large, since the number of outputs from
the tree grows exponentially with the number of input bits. An approach that has
been proposed to trade the hardware complexity for a lower degree of randomiza-
tion is the partial randomization DEM (PRDEM) technique. In PRDEM, the
switching tree is terminated before 1-bit outputs are achieved, thus resulting in a
lower hardware complexity. The outputs from the switches in the last layer are
used as inputs to DAC banks consisting of one 1-bit DAC and one multi-bit DAC
(the 1-bit DAC in the DAC bank is a required because of the added LSB in the

59
Compensation and Correction of Errors

layer 1
2
switch
layer N–1 r1(n)
N
switch

to 1-bit DACs
layer N
N N+1 rN–1(n)
X(n) switch
rN(n) N
‘0’ switch
rN–1(n)
2
switch
r1(n)

Figure 4.8 DEM circuit utilizing switching tree.

input to the tree). Design, modeling, and measurements of a current-steering

PRDEM DAC is discussed in Sec. 5.6. From the simulations and measurements
presented there we find that randomization in a few layers only is enough for
making the distortion due to mismatch neglectable compared with the dynamic
errors. Hence, terminating the switching tree after a few layers is acceptable.

Mismatch shaping DEM

Using random scrambling has the effect of transforming harmonic distortion
caused by mismatch into (approximate) white noise. Hence, the power of the dis-
tortion is evenly distributed over the whole frequency range. To gain even more
in SNDR it is desirable to shape the noise, so that a larger portion of the noise
appears outside of the signal band, where it can be filtered out. This is the goal
with so called mismatch shaping DEM [24, 45, 46]. In mismatch shaping DEM,
the one bit signals u i(n) are chosen according to [45]

1
u i(n) = ---- ⋅ X 1(n) + z i(n) , (4.9)
K
where K is the number of 1-bit signals and z i(n) is a signal with very little power
within the signal band. The total output is
K K

∑ ∑ ---K- ⋅ ( w + ∆i ) ⋅ zi(n) =
1 1
Y (n) = ---- ⋅ ( w + ∆ i ) ⋅ X 1(n) +
K
i=1 i=1
K K
 
= X 1(n) ⋅ w ⋅  1 +

∑
∆ i +

∑
( w + ∆i ) ⋅ zi . (4.10)
i=1 i=1

60
 Compensation and correction of dynamic errors

The first term in (4.10) is the desired output (with a slightly different gain com-
pared with (4.7)). The second term is the error, e(n) , due to mismatch. Moreover
K K
X 1(n) = ∑ ui(n) = X 1(n) + ∑ zi(n) , (4.11)
i=1 i=1

yielding
K

∑ zi(n) = 0 . (4.12)
i=1

Combining (4.10) and (4.12) yields

K
e(n) = ∑ ∆i ⋅ zi(n) . (4.13)
i=1

Since every z i has very little power within the signal band, so does e(n) . The
construction of the different u i(n) is similar to delta-sigma modulation (which is
outlined in Sec. 4.2.2) and is nontrivial. Several circuit solutions have been pro-
posed (see, e.g., [24, 45, 47, 48]), and there are also solutions where the different
u i(n) are multi-bit words.

4.2 Compensation and correction of dynamic errors

Techniques on compensation and correction of dynamic errors are presented in
this section. For behavioral-level simulations of the different techniques we use
Matlab in combination with the state-space model presented in Sec. 3.4.1. An
architecture that utilizes redundant coding of differential signals to increase the
flexibility and hence give the possibility for improved linearity is presented in
Sec. 4.2.1. The techniques described in Sec. 4.2.2 and Sec. 4.2.3 are dependent
on models to compute the expected error and the predistorted input, respectively.
For this purpose we base our techniques on the low-complexity model described
in Sec. 3.4.2. Here we only consider improvement on the linearity of the single-
ended signals. The models need modifications to reduce distortion in the differ-
ential signals. The update frequency is 10 MHz In all simulations and measure-
ments.
Methods that have been claimed to improve the dynamic behavior, are the use of
track and hold circuits or deglitcher circuits connected to the DAC outputs
[49, 50]. These techniques are not considered in this thesis.

61
Compensation and Correction of Errors

4.2.1 Differential DACs with variable common mode

In this section we propose a redundant differential DAC architecture which
allows the common mode level to be varied. This can be used, e.g., to reduce the
overall load at the outputs or to apply a dithering signal [51, 52] to reduce the
nonlinear behavior. The ideas presented in this section were introduced in
[53, 54, 55].

Proposed redundant architecture

The proposed redundant DAC architecture is shown in Fig. 4.9. It combines two
current-steering DACs (DAC1 and DAC2), which may be single-ended or differ-
ential. In the latter case we only use output A + , and connect A – to a constant DC
voltage, V dump , which in practice is the same as having a single-ended current-
steering DAC.

A+
X1(n)
DAC1
A–

X(n) r(n)
Vdump

A+
X2(n) I2 I1
DAC2
A– RL RL

Figure 4.9 Proposed redundant DAC architecture.

The input, X 1(n) , to DAC1 is

X 1(n) = X (n) + r(n) , (4.14)

where X (n) is the input to the whole system and r(n) is a control signal. The
input, X 2(n) , to DAC2 is similarly given by

X 2(n) = X max – X (n) + r(n) , (4.15)

62
 Compensation and correction of dynamic errors

where X max is the maximum value of X for the given code, i.e., with all individ-
ual bits b i = 1 . If the input code is binary weighted, then X max – X (n) corre-
sponds to X (n) with all individual bits inverted, represented by the inverter
symbol in Fig. 4.9. The control signal must not cause any of the signals X 1 and
X 2 to overflow, since this causes distortion. Thus, the DAC inputs need to fulfill

0 ≤ X i ≤ X max , (4.16)

yielding

r ≥ – min ( X , X max – X ) . (4.17)

With ideal DACs (DAC1 and DAC2) we obtain the following expressions for the
output currents
N–1
I1 = Iu ∑ wi ⋅ bi(n) + I u ⋅ r(n) and
i=0
N–1
I2 = Iu ∑ wi ⋅ bi(n) + I u ⋅ r(n) . (4.18)
i=0

For the combined differential output current, I diff = I 1 – I 2 , we obtain

N–1 N–1
I diff = I 1 – I 2 = 2I u ∑ bi ⋅ wi – I u ∑ wi . (4.19)
i=0 i=0

Hence, ideally we have the same differential output current as for a single ideal
differential current-steering DAC, because the control signals cancel. Of course,
in reality the control signal will affect the two outputs differently due to any non-
linearity in the transfer functions of the DACs, and the cancellation will not be
perfect.
We also consider the common-mode signal
N–1
I1 + I2
I cm = ---------------
2
= Iu ∑ wi + I u ⋅ r(n) . (4.20)
i=0

Hence, the control signal is added to the common-mode signal. One factor that
limits the possibly useful control signals is, therefore, the common-mode rejec-
tion of the following circuitry. Another factor is, as mentioned earlier, how the
control signal is distorted between the two DAC outputs.

63
Compensation and Correction of Errors

In an implementation, the two DACs have to be mutually well-matched, prefera-

bly manufactured on the same die, sharing same master bias, etc. It is also impor-
tant to avoid clock skew between the two DACs, and therefore it is desirable that
they share the same clock net. Obvious penalties, compared with conventional
DACs, are increased area requirements and power consumption. A test chip that
can be used for evaluation of the ideas discussed here is presented in Sec. 5.7. At
this point, however, the DACs on this chip have only been measured one at a
time, not combined.

Dithering of the common-mode level

A first method of utilizing the redundancy is to apply dithering of the common-
mode level to reduce the nonlinear distortion caused by random matching errors
in the current sources. This technique is similar to DEM techniques presented
earlier, and is actually a technique for compensation of static errors. It appears in
this section because the other methods of utilizing the redundant architecture
aims at reducing dynamic errors. For simulation purposes, we add a random
matching error with Gaussian distribution, standard deviation of σ = 0.02 ⋅ I u
and expectation value 0 to each unit current source. The simulated DAC architec-
ture utilizes segmentation where the 6 MSBs are encoded into thermometer code.
The matching errors have not been altered between the runs, i.e., the same DACs
have been used in all simulations.
The control signal r(n) was chosen to be quantized values of

a ⋅ ψ(n) , (4.21)
where a is a scaling constant and ψ(n) is white noise with a rectangular distribu-
tion

ψ(n) ∈ Re(– 0.5, 0.5) . (4.22)

The PSD plots of I diff for a = 0 and a = 2 13 are shown in Fig. 4.10(a) and (b),
respectively. The input is a single-tone signal with half-scale amplitude. It is seen
that the added dithering signal reduces the spurious tones to a large extent. In
Fig. 4.11 the SFDR is plotted vs. log 2a . We see that the SFDR increases with
increasing a . The quantitative results are, obviously, specific for this particular
outcome of the stochastic matching errors.

DC level minimization
We propose a second method based on the proposed redundant architecture in
Fig. 4.9 that aims at reducing the parasitic load associated with an output termi-
nal. Looking at the circuit models presented in Sec. 3.4 we see that each current

64
 Compensation and correction of dynamic errors

PSD plot of DAC output, a = 0 PSD plot of DAC output, a = 8192

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]
−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [MHz] Frequency [MHz]

(a) (b)
Figure 4.10 PSD plots for simulated outputs from redundant DAC with matching errors (a)
without dither signal and (b) with dither signal having amplitude a = 2 13 .

SFDR vs. log2(a)

100

98

96

94

92
SFDR [dB]

90

88

86

84

82

80
4 6 8 10 12 14
log2(a)

Figure 4.11 SFDR as a function of log 2(a) .

source connected to a terminal provides an additional load through its output

impedance. For the best possible dynamic behavior (i.e., short settling times) it is
desired to minimize the load at the output terminal, i.e., minimize the number of
unit current sources connected to the terminal. If the input does not make use of
the whole range, e.g., a half-scale single-tone signal, this can be achieved by let-
ting r(n) = r be a (negative) constant. This is equivalent to reducing the DC
level of each single-ended output.

65
Compensation and Correction of Errors

Here we present some simulation results using the model presented in Sec. 3.4.1.
The simulated DAC is 14-bit binary-weighted, and the model parameters are the
same as in Table 3.1 on page 43. The current sources are assumed to be perfectly
matched, but matching errors can also be added in the model, as discussed in
Sec. 3.5. PSD plots of the simulated DAC outputs using half-scale sinusoidal
inputs are shown in Fig. 4.12. The PSD for a single differential DAC is shown in
Fig. 4.12(a). PSDs for the proposed redundant architecture, with the dump termi-
nal connected to a DC voltage source of 0.5 V, are shown in Fig. 4.12(b) and (c).
The PSD for r = 0 is shown in Fig. 4.12(b) and the PSD for r = – 2 12 (yielding
the lowest possible DC level without overflow) is shown in Fig. 4.12(c). A Com-
parison of Fig. 4.12(a) and (b) indicates that switching a current source between
an output node and a silent node has favorable effects on the distortion, compared
with switching between two output nodes, since the distortion is 5 dB lower in
Fig. 4.12(b). This also agrees with some single-ended measurements performed.
The spurious tones are reduced even more, resulting in an improvement in the
SFDR by approximately 7 dB when the DC level is reduced, as is the case in
Fig. 4.12(c). Further measurements have to be performed before any conclusions
can be made regarding the application to real DAC circuits.

Common-mode level reduction with boundary conditions

Using the approach with a constant r(n) is only applicable to a limited class of
signals, i.e., the ones that do not utilize the possible input range. Moreover, it is
required that the maximum and minimum value of all future samples of the input
are known. Even if the signal has finitely many samples, the number of samples
is often so large that this is not possible to obtain to a reasonable hardware cost or
acceptable delay. Instead we modify the approach and choose r(n) as the small-
est integer fulfilling the boundary conditions

r(n) ≥ – min(X (n), X max – X (n)) = r min(n) (4.23)

and

r(n) – r(n – 1) ≤ ∆r max . (4.24)

Boundary condition (4.23) ensures that overflow is avoided, and ∆r max is chosen
such that the common mode variations can be sufficiently rejected in the follow-
ing circuitry. The previous approach with a constant r corresponds to
∆r max = 0 . The boundary conditions should hold for all n , so we need to keep
track of some future samples of X , otherwise we risk choosing r(n) too small to
fulfil both (4.23) and (4.24) for some future sample. However, since we do not
need to keep track of all future samples, which is the case when using a constant
r , this approach is more suitable for implementation.

66
 Compensation and correction of dynamic errors

PSD for output from conventional DAC

−20

−40

PSD [dB/Hz]
−60

−80

−100

−120
0 1 2 3 4 5
Frequency [Hz] 6
x 10

(a)
PSD for output signal, r=0 PSD for output signal, r=−4096

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]

−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(b) (c)
Figure 4.12 PSD plots of simulated DAC outputs from (a) a conventional DAC, and the pro-
posed redundant DAC with (b) r = 0 and (c) r = – 2 12 . The input is a half-
scale sinusoid with signal frequency 2.208 MHz and update frequency 10 MHz.

In Fig. 4.13(a) and (b) we show simulated 3-tone PSD plots for a single DAC and
for the proposed redundant DAC with r(n) chosen as above, respectively. The
simulation model is a 14-bit binary weighted version of the one presented in
Sec. 3.4.1. Parameter values are given in Table 3.1 on page 43, and ∆r max = 20 .
The peak-to-peak value for this particular input is approximately 10600. The
largest distortion peak is reduced from –72 to –82 dB.

4.2.2 Modulation of expected errors

Delta-sigma modulation is a technique used in data conversion to achieve high-
resolution with quantizers having few quantization levels. This is performed
using the quantization error in a feedback loop, spectrally moving a large amount
of the quantization noise power to a frequency range above the signal band. How-

67
Compensation and Correction of Errors

PSD for simulated output signal, r=0 PSD for simulated output signal, ∆r =10
max

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]
−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 4.13 PSD for 3-tone signal (a) without and (b) with common-mode level reduction.

ever, an ideal quantizer is a poor model of a real data converter. Reference levels
will not be evenly spaced due to, e.g., component mismatch. Other dynamic and
static errors also occur, as was discussed in Chapter 3.
In this section we propose a linearization technique based on delta-sigma modu-
lation, primarily intended for DACs, which also spectrally shapes nonlinearities
arising from other sources than the quantization process. The application, how-
ever, is not limited to DACs, but can be applied to any kind of oversampled sys-
tem. The technique presented here was first proposed in [56].

Delta-sigma modulator basics

The aim for a delta-sigma modulator is to spectrally shape the quantization noise,
so that it is moved out of the signal band. This technique implies that oversamp-
ling has to be used. A general delta-sigma modulator is shown in Fig. 4.14(a).
The feedback filter is assumed to be a linear filter. The quantizer is often modeled
with an error, e(n) , added to the quantizer input, as shown in Fig. 4.14(b).

X(n) Y(n) e(n)

Q X(n) Y(n)
feedback feedback
filter filter

(a) (b)
Figure 4.14 (a) General delta-sigma modulator and (b) delta-sigma modulator with quanti-
zer modeled as an added error signal.

In the frequency domain, the output can be written as

68
 Compensation and correction of dynamic errors

Y (z) = X (z) ⋅ STF(z) + E(z) ⋅ NTF(z) (4.25)

where STF(z) is the signal transfer function, NTF(z) is the noise transfer func-
tion, and Y (z) , X (z) , and E(z) are the z-transforms of Y (n) , X (n) , and e(n) ,
respectively.
The modulator structure we use in the following is shown in Fig. 4.15. It is
referred to as an error feedback modulator [8, 57], since the quantization error is
used as an input to the filter H (z) .

X(n) Y(n)
Q

e(n)
H(z)
Figure 4.15 Error feedback modulator.

It is easily derived from Fig. 4.15 that

STF(z) = 1 (4.26)
and

NTF(z) = 1 – H (z) . (4.27)

We let NTF(z) be an FIR transfer function, making H (z) an FIR filter. We can
now specify NTF(z) , and H (z) is implicitly given by (4.27). An Lth order NTF
is chosen by placing L poles in the origin and L zeros strategically on the unit
circle. This structure is sensitive to coefficient errors [8], and may be difficult to
implement. It is, however, an easy way to design an example for simulations in
Matlab, where we can have virtually infinite precision in the coefficients.
Simulation results for a 5th order modulator of this type, using OSR = 4 , with a
single-tone input is shown in Fig. 4.16. The input and output spectra are shown in
Fig. 4.16(a) and (b), respectively. The input has 14 bits of resolution, and a 6-bit
quantizer is used. The zeros of the noise transfer function are located on the unit
circle at z = 1 , z = e ± j ( π ⁄ OSR ) , and z = e ± j ( π ⁄ ( 2 ⋅ OSR ) ) . The spectrum for the
input signal quantized to 6 bits without the feedback is plotted in Fig. 4.16(c) for
comparison. As for all types of delta-sigma modulators, stability is an important
issue. The stability of delta-sigma modulators with FIR noise transfer functions is
discussed in [58].

69
Compensation and Correction of Errors

14−bit input signal to modulator

−20

−40

PSD [dB]
−60

−80

−100

−120
0 0.1 0.2 0.3 0.4 0.5
Normalized frequency

(a)
6−bit output signal from modulator 6−bit single−tone signal

0 0

−20 −20

−40 −40
PSD [dB]

PSD [dB]

−60 −60

−80 −80

−100 −100

−120 −120
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Normalized frequency Normalized frequency

(b) (c)
Figure 4.16 Spectra for (a) 14-bit single-tone signal, (b) delta-sigma modulated signal using
5th order modulator with a 6-bit quantizer, and (c) 6-bit single-tone signal.

Spectral shaping of nonlinearities

As mentioned earlier, an ideal quantizer is a poor model of a real DAC. In this
section we propose a technique for compensating nonidealities due to physical
imperfections utilizing the basic ideas of delta-sigma modulation. The modulator
spectrally shapes the quantization noise through feedback of the quantization
error. We want to do the same thing with distortion arising from nonlinearities in
the DAC. Therefore, the quantizer in Fig. 4.15 is substituted with a quantizer cas-
caded with an accurate model of the DAC, yielding the block diagram shown in
Fig. 4.17. We refer to this circuit as the distortion shaper. The output from the
quantizer, Y (n) , is passed on as the input to the real DAC.
This structure can be modeled similarly as the delta-sigma modulator was in
Fig. 4.14(b), replacing the quantizer and the DAC model with an addition of an
error signal. However, the error signal, e(n) , might be considerably larger than
the quantization error, which is bounded within one LSB of the quantizer. There-

70
 Compensation and correction of dynamic errors

Y(n) (to DAC)

X(n) DAC
Q model

e(n)
H(z)
Figure 4.17 Block diagram of the proposed distortion shaping device.

fore, a feedback configuration which is guaranteed to be stable according to some

criterion in the delta-sigma modulator case, need not necessarily be stable in this
case. The stability issue has to be carefully considered for each special case, e.g.,
through extensive simulation of the system.
For an implementation of the distortion shaper it is important to have an accurate
model of the DAC. The best model is of course the DAC itself, meaning that we
accurately measure the error for each update instant, i.e., a fast and accurate ADC
is required in the feedback loop. This is not easily achieved, so a better solution
would be to use an adaptive model of the DAC, which is updated, e.g., during a
training period.

Simulations
A suitable candidate for the model in the feedback loop to compensate for errors
due to finite output impedance is the low-complexity model presented in
Sec. 3.4.2. Here some simulation results for linearization of the DAC model in
Sec. 3.4.1 are presented. The simulation parameters are the same as in Table 3.1
on page 43, except that the output resistance in the unit current sources has been
increased a factor 10 to reduce the static nonlinearity, which is not included in the
low-complexity model. The parameters for the low-complexity model are the
same as those used in the simulations in Sec. 3.4.2. The filter H (z) is the same as
in the delta-sigma simulation in Fig. 4.16. The method is illustrated in by the
simulation plot in Fig. 4.18 where the dominating second harmonic is suppressed
with 20 dB, to the cost of increased high frequency distortion. There is one spuri-
ous tone within the signal band that increases, so the SFDR improvement is only
11 dB.

71
Compensation and Correction of Errors

Output signal wihtout distortion shaped Output signal with distortion shaped

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]
−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 4.18 PSD plots for simulated outputs (a) without and (b) with distortion shaping.

Measurements
Measured PSD plots for single-ended outputs from the DAC presented in
Sec. 5.5 are shown in Fig. 4.19. Fig. 4.19(a) shows the spectrum using an uncom-
pensated input, whereas the input used in Fig. 4.19(b) has been processed with
the distortion shaping technique presented in this section. The model used for
estimation of the error is a simple version of the low-complexity model presented
in Sec. 3.4.2, namely

e rel(X (n)) = a ⋅ b N – 1(n) . (4.28)

Referring to the block diagram of the model shown in Fig. 3.18, the lookup table
only contains two values, a and 0, and is addressed by the MSB of the input to
the DAC. The resulting SFDR improvement is approximately 12 dB, which gives
a strong indication that the model structure presented in Sec. 3.4.2 is suitable for
its purpose, i.e., to estimate dynamic errors in order to compensate for them.

4.2.3 Predistortion of dynamic errors

The method described in Sec. 4.2.2 reduces the distortion within the signal band
to the cost of increased out-of-band distortion, which requires filtering to remove
the out-of-band distortion. The technique is particularly suited to use in a delta-
sigma DAC, where filters are required in any case to remove the shaped quantiza-
tion noise. For other cases it is better to compute an input that yields an output as
close as possible to the desired output, removing the distortion rather than spec-
trally shaping it. By doing so, we also increase the possible signal bandwidth for
a given update frequency, compared with if the distortion is shaped. Filters are
still required to remove images of the signal, but the filter requirements are not as
hard as if the filters also have to remove the shaped distortion. This technique is

72
 Compensation and correction of dynamic errors

(a) (b)
Figure 4.19 PSD plots for measured outputs from a DAC (a) with and (b) without the distor-
tion shaped.

known as predistortion [12]. Methods based on predistortion are often proposed

for improving the linearity in power amplifiers for radio frequency (RF) applica-
tions [59, 60, 61]. Very little work has been done in the field of predistortion for
DACs. In [62] a method was reported utilizing a black-box model of the DAC.
No consideration was, however, taken to the computational complexity of the
predistortion block.
In this section we present a predistortion method for DACs aimed at reducing the
nonlinear behavior caused by parasitic capacitance, as discussed in Sec. 3.4. The
method utilizes the low-complexity model presented in Sec. 3.4.2 to calculate the
predistorted input to the DAC. The method first appeared in [63].

Predistortion block
The purpose of the predistortion block is to, for a given input X (n) , find a modi-
fied input, X p(n) , such that Y (n) ≈ X (n) . To accomplish this we use the low-com-
plexity DAC model presented in Sec. 3.4.2. In accordance with Sec. 3.4.2 we use

Y (n) = Y (n – 1) + [ X (n) – Y (n – 1) ] ⋅ [ 1 – e rel(X (n), X (n – 1)) ] (4.29)

as an estimate of the output from the current-steering DAC and normalize the
output such that the static gain of the DAC is unity. To find the appropriate pre-
distorted signal we replace X with X p in (4.29), yielding

Y (n) = Y (n – 1) + [ X p(n) – Y (n – 1) ] ⋅ [ 1 – e rel(X p(n), X p(n – 1)) ] .

(4.30)
Further, we set Y (n) = X (n) and assume that Y (n – 1) = X (n – 1) , i.e., that the
predistortion for the previous sample was successful. This yields

73
Compensation and Correction of Errors

X (n) = X (n – 1) + [ X p(n) – X (n – 1) ] ⋅ [ 1 – e rel(X p(n), X p(n – 1)) ] .

(4.31)
Solving for X p(n) yields

X (n) – X (n – 1)
X p(n) = X (n – 1) + ------------------------------------------------------------ . (4.32)
1 – e rel(X p(n), X p(n – 1))

In Sec. 3.4.2 only a few MSBs of X are used to estimate e rel . Thus, if we assume
that the correction introduced by the predistortion is small, i.e., X p(n) – X (n) is
small, it is reasonable to approximate e rel(X p(n), X p(n – 1)) with
e rel(X (n), X (n – 1)) . We can then make a nonrecursive definition of X p(n)

X (n) – X (n – 1)
X p(n) = X (n – 1) + ------------------------------------------------------- =
1 – e rel(X (n), X (n – 1))
= X (n – 1) + p rel(X (n), X (n – 1)) ⋅ ( X (n) – X (n – 1) ) , (4.33)

where

1
p rel(X (n), X (n – 1)) = ------------------------------------------------------- . (4.34)
1 – e rel(X (n), X (n – 1))

Similarly to the error estimation presented in Sec. 3.4.2, p rel can be stored in a
lookup table. Further, the lookup table may be addressed with only a few MSBs
of X (n) and X (n – 1) to keep the size of the lookup table small. We propose a
predistorter circuit according to Fig. 4.20.

X(n)
z–1 lookup prel(n) Xp(n)
table
Figure 4.20 Proposed predistorter circuit.

Simulation results
In this section we present results from simulations where the predistortion tech-
nique is used to linearize the state-space model of the current-steering DAC pre-
sented in Sec. 3.4.1. The simulation parameters are given in Table 3.1 on page
43, and the parameters for the predistortion block are the same as in the simula-
tions in Sec. 3.4.2.

74
 Compensation and correction of dynamic errors

The PSD plots for outputs without and with predistorted inputs are shown in
Fig. 4.21(a) and (b), respectively. The input is a half-scale sinusoid with signal
frequency 1.104 MHz and the update frequency is 10 MHz. Full-scale inputs
cannot be used since the predistorted inputs are likely to overflow in that case. In
Fig. 4.22 we have increased the signal frequency to 2.208 MHz. For both fre-
quencies it can be concluded that the predistortion reduces the second harmonic
to a large extent and suppresses the other harmonics below the noise floor. SFDR
is plotted as a function of signal frequency in Fig. 4.23. For this example the
SFDR at low frequencies is preserved over the whole frequency range when the
predistortion technique is used.
PSD for nonpredistorted input signal PSD for predistorted input signal

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]

−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 4.21 PSD plots for outputs (a) without and (b) with predistortion. The input is a half-
scale sinusoid with signal frequency 1.104 MHz, and the update frequency is
10 MHz.

PSD for nonpredistorted input signal PSD for predistorted input signal

0 0

−20 −20

−40 −40
PSD [dB/Hz]

PSD [dB/Hz]

−60 −60

−80 −80

−100 −100

−120 −120
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10

(a) (b)
Figure 4.22 PSD plots for outputs (a) without and (b) with predistortion. The input is a half-
scale sinusoid with signal frequency 2.208 MHz, and the update frequency is
10 MHz.

75
Compensation and Correction of Errors

Simulated SFDR vs. f

sig
90
without predistortion
with predistortion
85

80

75
SFDR [dB]

70

65

60

55

50 5 6
10 10
fsig [Hz]

Figure 4.23 Simulated SFDR as a function of signal frequency with and without predistor-
tion.

4.2.4 Implementation issues

Methods for compensating dynamic errors utilizing models of the errors were
presented in Sec. 4.2.2 and Sec. 4.2.3. The hardware complexity for an imple-
mentation of the compensation blocks used in the simulations is low, a few
adders and multipliers, and a small lookup table. A problem that needs to be
solved, however, is the estimation of model parameters. In simulations this is not
a problem, since both the input and the output are accessible (without approxima-
tion), and model parameters can be estimated with high precision. To do the same
thing for an actual circuit, a fast and accurate ADC is required to measure the
error in a wide-band DAC aiming for high resolution. In [62] this problem was
approached by using a state-of-the-art commercial ADC operating at a limited
part of the signal band. This solution failed to compensate for any distortion that
appeared outside of this band.

76
 5 Current-Steering DAC
Implementations
The most common type of DAC for high-speed applications, e.g., broadband
communication, is the current-steering. The implementation of three different 14-
bit current-steering DACs in standard digital CMOS processes is discussed in this
chapter, together with the measurement results.

5.1 CMOS processes

Complementary metal oxide semiconductor (CMOS) processes are very popular
for implementing integrated circuits, mainly due to low cost, but also because
they provide good possibilities for designing digital low-power circuits. The
words “metal oxide semiconductor” refers to the physical structure of the transis-
tors, whereas the word “complementary” means that the designer have access to
both NMOS and PMOS transistors. All DACs presented in this chapter have been
implemented in standard digital CMOS processes. In this section we give an
overview of the CMOS transistor.

5.1.1 Large signal models

The large signal behavior of the CMOS transistor in different operation regions is
briefly discussed in this section. Well known equations for the current-voltage
relationships, assuming long channel devices, are also presented.

77
Current-Steering DAC Implementations

NMOS transistors
A commonly used symbol for an NMOS transistor is shown in Fig. 5.1(a). The
labels G, S, D, and B denote the gate, source, drain, and bulk terminal, respec-
tively. We have also indicated the gate-source voltage, V GS , the drain-source
voltage, V DS , and the bulk-source voltage, V BS . The drain current, I D is also
indicated in the figure. In most processes, the bulk terminals of all NMOS tran-
sistors are connected to ground, and the simplified symbol in Fig. 5.1(b), without
the bulk terminal explicitly shown, can be used instead.

ID
D
G B VDS
VBS
VGS S
(a) (b)
Figure 5.1 (a) Symbol for an NMOS transistor, and (b) simplified symbol for an NMOS
transistor with the bulk terminal connected to ground.

Equations (5.1), (5.2), and (5.3) model the relationships between the drain cur-
rent and the different voltages for a long channel NMOS transistor in the cut-off,
linear, and saturated region, respectively.

V GS < V T , n ⇒
ID = 0 , (5.1)

V GS ≥ V T , n , V DS < V GS – V T , n = V eff ⇒
V DS 2
= µ 0, n C ox ----- V eff V DS – ---------- ,
W
ID (5.2)
L 2 

and

V GS ≥ V T , n , V DS ≥ V GS – V T , n = V eff ⇒
µ 0, n C ox W 2
I D = ------------------- ----- V eff ( 1 + λ ( V DS – V eff ) ) . (5.3)
2 L

78
 CMOS processes

V T , n is the threshold voltage, µ 0, n is the electron mobility, C ox is the gate oxide

capacitance per unit area, and W and L is the width and the length of the transis-
tor, respectively. λ is a parameter known as the output impedance constant,
which is roughly proportional to 1 ⁄ L [8]. A phenomenon known as the body
effect makes the threshold voltage dependent on the bulk-source voltage accord-
ing to

V T , n = V T , n, 0 + γ ( 2Φ F – V BS – 2Φ F ) , (5.4)

where V T , n, 0 is the threshold voltage at zero V BS . The built-in Fermi potential

Φ F and the body effect constant γ are process dependent parameters [8].

PMOS transistors
Symbols for PMOS transistors are shown in Fig. 5.2. In Fig. 5.2(a) the four ter-
minal symbol is shown, and the corresponding simplified symbol where it is
implied that the bulk terminal is connected to the power supply voltage ( V DD ) is
shown in Fig. 5.2(b).

VSG S
VSB
G VSD
B

ID D

(a) (b)
Figure 5.2 (a) PMOS transistor symbol and (b) simplified PMOS transistor symbol.

Equations (5.5), (5.6), and (5.7) model a long channel PMOS transistor in the
cut-off region, linear region, and saturated region, respectively

V SG < V T , p ⇒
ID = 0 , (5.5)

V SG ≥ V T , p , V SD < V SG – V T , p = V eff ⇒
V SD 2
I D = µ 0, p C ox -----  V eff V SD – ---------
- ,
W
(5.6)
L 2 

and

79
Current-Steering DAC Implementations

V SG ≥ V T , p , V SD ≥ V SG – V T , p = V eff ⇒
µ 0, p C ox W 2
I D = ------------------- ----- V eff ( 1 + λ ( V SD – V eff ) ) . (5.7)
2 L
The threshold voltage for PMOS transistors is negative. Due to the body effect
we get

V T , p = V T , p, 0 – γ ( 2Φ F – V SB – 2Φ F ) . (5.8)

Notes on large signal models

The large signal equations presented above are only suitable for long channel
devices. Circuit simulators utilize more elaborate models, including many higher
order effects, to get more accurate results. Higher order effects become more and
more important as device dimensions become smaller and smaller.

5.1.2 Small signal models

As can be seen from the equations in Sec. 5.1.1, MOS transistors are nonlinear
devices. In order to find the effect of small variations in currents and voltages we
use linearized models, so called small signal models.
In Fig. 5.3(a) below we show a so called g -parameter model of an NMOS tran-
sistor. The parameters in the saturated region are given by

∂I D W
gm = ≈ 2µ 0, n C ox ----- I D , (5.9)
∂ V GS L

∂I D
g ds = ≈ λI D , (5.10)
∂ V DS

and

∂I D γ gm
g mbs = ≈ ------------------------------------ . (5.11)
∂ V BS 2 2Φ – V
F BS

The corresponding small signal equivalent model for PMOS transistors is shown
in Fig. 5.3(b). The parameters are given by

∂I D W
gm = ≈ 2µ 0, p C ox ----- I D , (5.12)
∂ V SG L

80
 Analog DAC building blocks

G D S
id
vgs vds vsg vds
S G id D
gmvgs gmbsvbs gds gmvsg gmsbvsb gds

(a) (b)
Figure 5.3 Small signal equivalent model of (a) an NMOS transistor and (b) a PMOS tran-
sistor.

∂I D
g ds = ≈ λI D , (5.13)
∂ V SD

and

∂I D γ gm
g msb = ≈ ------------------------------------ . (5.14)
∂ V SB 2 2Φ – V
F SB

5.2 Analog DAC building blocks

Different aspects of the design of analog building blocks are discussed in this
section. An overview of implementation a current source is given in Sec. 5.2.1,
and implementation of switches is discussed in Sec. 5.2.2.

5.2.1 CMOS current sources

Current sources are essential building blocks in current-steering DACs, and in the
previous section we have established transistor models that are adequate to dis-
cuss the implementation of current sources in CMOS technology. We know from
Chapter 3 that the output impedance of the current source, and the matching
between the current sources, are critical parameters for the linearity of the DACs.

Single transistor current source

A single transistor PMOS current source is shown in Fig. 5.4(a). The bias voltage
is set by a bias circuit, as discussed in Sec. 4.1.2. The ideal current source has
infinite output impedance, i.e., the output current is independent on the voltage
across the current source. This is desired in current steering DACs since we want
the output current (from each current source) to be independent on the output
voltage. In reality the output resistance of the current source is

81
Current-Steering DAC Implementations

1
R out = ---------------------- < ∞ , (5.15)
g ds, source

due to the channel length modulation. Moreover, parasitic capacitance in the

devices, indicated in Fig. 5.4(a), contributes to a capacitive part of the output
impedance. The total output impedance is

1
Z out = ----------------------------------------- , (5.16)
g ds, source + sC out

where the output capacitance C out = C p, 1 and g ds, source is the g ds for the tran-
sistor.

Cp,1
Vbias source
transistor
Vbias Cp,1
Cp,2
Vcasc cascode
transistor
Iout

Iout

(a) (b)
Figure 5.4 PMOS current sources (a) without and (b) with cascode transistor.

Cascode current source

If the output resistance is not large enough to meet the required linearity, we can
use a cascode current source as shown in Fig. 5.4(b). The output resistance for
this current source is approximately

g m, casc 1
R out ≈ ----------------- ⋅ ---------------------- , (5.17)
g ds, casc g ds, source

where g m, casc and g ds, casc are small signal parameters for the cascode transistor
and g ds, source is the g ds for the source transistor. The output resistance is
increased, since g m, casc » g ds, casc . The cascode transistor reduces the voltage
variations over the parasitic capacitance C p, 1 , compared with the single transis-

82
 Analog DAC building blocks

tor case. Hence, the influence of C p, 1 on the bandwidth of the current source is
reduced. There are, however, also parasitic capacitance in the output node of the
cascode transistor. The output impedance is approximately

1
Z out ≈ ------------------------------------------------------------ , (5.18)
g ds, casc
g ds, source ----------------- + sC out
g m, casc

where in this case C out ≈ C p, 2 . For higher frequencies where the capacitive part
dominates, then Z out ≈ 1 ⁄ ( sC out ) for both type of current sources. C out is
roughly a parallel connection between the gate-drain and the drain-bulk capaci-
tance for the transistor connected to the output node. The value of the parasitic
capacitance is mainly determined by the width of the transistor. If the width is of
the same order in both the cascoded and the single transistor case, yielding
C p, 1 ≈ C p, 2 , we have not gained very much in the range of frequencies where
the capacitive part is dominating. A part of the output capacitance is also contrib-
uted to by the metal wires connected to the current sources. This part of the
capacitance is unaffected by the choice of current source. In the next section we
show that the cascoding effect can also be achieved with the switch. The conclu-
sions are that for higher frequencies we do not gain very much by introducing
cascode transistors but we loose in possible output swing since we need to keep
all transistors in saturation (the output resistance is severely deteriorated if the
transistors enter the linear region). Therefore, the cascode transistors have been
omitted in the later DAC implementations.

5.2.2 CMOS switches

The switches are also critical building blocks in current-steering DACs. In this
section we will assume that the current sources are of PMOS type. In the case of
NMOS current sources the discussion is similar. Differential PMOS and NMOS
switches are shown in Fig. 5.5(a) and (b), respectively.

Iin Iin

Q+ Q– Q+ Q–

I+ I– I+ I–

(a) (b)
Figure 5.5 CMOS implementations of (a) a differential PMOS switch and (b) a differential
NMOS switch.

83
Current-Steering DAC Implementations

It is important that the signals controlling the switches are such that the two tran-
sistors in the switch are not simultaneously completely turned off, in which case
charge will be assembled at the output node of the current source and give rise to
large transients once one of the transistors is turned back on.
Assume that the PMOS type differential switch is used. In steady-state, when one
of the transistors is conducting and the other turned off, the conducting switch
transistor acts as a cascode transistor (compare with Fig. 5.4(b)). In order to have
short switching times and low channel charge injection from the switches it is
desired to use transistors with small area in the switches. A large g m ⁄ g ds is
required to get a good cascoding effect. Since g m ⁄ g ds is proportional to W ,
there is a trade-off between switch area and cascoding effect. Moreover, when the
output voltage exceeds the absolute value of the threshold voltage, the switch
transistor enters the linear region of operation and the g m ⁄ g ds ratio is deterio-
rated. Even if the cascoding effect of the switch is limited, it is better to use
PMOS switches than NMOS switches. Similarly, NMOS switches are preferred
when NMOS current sources are used.

5.3 Digital DAC building blocks

Some digital building blocks are required when implementing DACs. In this sec-
tion we discuss the implementation of binary-to-thermometer encoders and
switch signal generators, i.e., the circuits used to generate proper signals to con-
trol the switches. The latter is an interface circuit between the digital and the ana-
log circuits, and is placed in the group of digital circuits since all circuits
implemented during this work are designed with classical digital circuit tech-
niques. All digital gates have been implemented using the complementary static
CMOS logic style [64, 65, 66].

5.3.1 Binary-to-thermometer encoding

Thermometer coded and segmented DAC architectures are discussed in this sec-
tion, and it is motivated why they are preferred to binary coded DACs. We also
present the binary-to-thermometer encoder architecture that has been used in the
DAC implementations presented in the following.

Thermometer coded and segmented structures in general

First consider a binary weighted architecture, i.e., where the weights w i = 2 i – 1 .
In a transition between, e.g., the codes X = [ 0, 1, 1, …, 1, 1 ] and
X = [ 1, 0, 0, …, 0, 0 ] , we may during a short moment have some erroneous
code, e.g., [ 1, 1, 1, …, 1, 1 ] controlling the switches due to different rise and fall
times of the digital circuits. This will cause a so called glitch in the transient

84
 Digital DAC building blocks

response of the DAC, as shown in Fig. 5.6. This can occur because in the transi-
tion there are individual bits making transitions from 0 to 1 , at the same time as
there are other bits making transitions from 1 to 0 .

Glitch in 4−bit binary weighted DAC

15
14
13
12
11
10
output level

9
8
7
6
5
4
3
2
1

n
update instant

Figure 5.6 Large glitch due to poor internal timing in a 4-bit binary weighted DAC. The
desired transition is from 7 to 8.

Next consider a thermometer coded architecture. The corresponding thermome-

ter codes for 2-bit, 3-bit, and 4-bit binary codes are given in Fig. 5.7(a), (b), and
(c), respectively. The weight for each bit t ik is w i = 1 , and the superscript k
indicates the corresponding number of bits in the binary code. The thermometer
code is monotone, i.e., in each transition between codes there only exist transi-
tions from 1 to 0 or from 0 to 1 in the individual bits, not both. Therefore,
glitches as in Fig. 5.6 cannot occur, indicating an advantage for the thermometer
code compared with the binary code. Moreover, even if matching errors will
cause the weights to deviate from 1, a thermometer coded DAC is guaranteed to
be monotone, i.e., the output Y (X 1) > Y (X 2) if and only if X 1 > X 2 . This is
because
X1 X2 X1 X1

Y (X 1) = ∑ wi = ∑ wi + ∑ w i = Y (X 2) + ∑ wi (5.19)
i=1 i=1 i = X2 + 1 i = X2 + 1

and all w i > 0 . As discussed in Sec. 4.1.1, a binary coded converter is not neces-
sarily monotone.

85
Current-Steering DAC Implementations

b2 b1 b0 t37 t36 t35 t34 t33 t32 t31

b1 b0 t23 t22 t21

0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

0 1 0 0 1 0 1 1 0 0 0 0 1 1 1
1 0 0 0 0 0 1 1 1 1
1 0 0 1 1
1 0 1 0 0 1 1 1 1 1
1 1 1 1 1
1 1 0 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1

(a) (b)

b3 b2 b1 b0 t415 t414 t413 t412 t411 t410 t49 t48 t47 t46 t45 t44 t43 t42 t41

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1

1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

(c)
Figure 5.7 Truth tables for (a) 2-3 encoder and (b) 3-7 encoder, and (c) 4-15 encoder.

Other types of codes that falls somewhere between the binary code and the ther-
mometer code have also been proposed, e.g., linear and polynomial codes
[67, 68], but these are not covered in this thesis. One code, that also falls between
the binary and the thermometer code, and is commonly used in DAC design is the
N
segmented code. An N -bit binary code corresponds to a ( 2 – 1 ) -bit thermome-
ter code. Hence, the hardware complexity in the encoding circuitry increases
exponentially with N , and becomes excessively large for large N . An often used

86
 Digital DAC building blocks

compromise is to use thermometer code for a few of the MSBs, say K of the
MSBs, and let the remaining N – K LSBs be binary weighted. This is referred to
as a segmented code. Assume a binary weighted input code

X b = [ b N – 1, b N – 2, …, b 0 ] , (5.20)

which is encoded into segmented code

X s = [ s 2 K + N – K – 2, …, s N – K , s N – K – 1, …, s 0 ] , (5.21)

where

[ s N – K – 1, …, s 0 ] = [ b N – K – 1, …, b 0 ] , (5.22)

and [ s 2 K + N – K – 2, …, s N – K ] is thermometer encoded from [ b N – 1, …, b N – K ] .

This is illustrated in Fig. 5.8(a), where a block diagram of a segmented DAC is
shown. The corresponding weights for the segmented codes, w s, i , are

 i for i ∈ [ 0, N – K – 1 ]
w s, i =  2 . (5.23)
 2 N – K for i ∈ [ 2 + N – K – 2, N – 1 ]
K

There are also multi-segmented architectures, as indicated in Fig. 5.8(b), where

more segments of the binary coded input are converted into thermometer code.
One example is the doubly segmented DAC presented in Sec. 5.7.

Implementation of binary-to-thermometer encoders

Analyzing the truth tables in Fig. 5.7 we will come up with a regular circuit solu-
tion utilizing a tree structure of NAND gates, NOR gates, and inverters, previ-
ously reported by Wikner in [69]. This type of encoder has been used in all
implementations described in this chapter. A similar (or possibly identical) solu-
tion has been faintly outlined by others [70].
First we consider the 2-3 encoder. It is easily verified from the truth table in
Fig. 5.7(a) that

t 12(b 1, b 0) = b 1 + b 0 ,
2
t 2(b 1, b 0) = b 1 , and
t 32(b 1, b 0) = b 1 ⋅ b 0 . (5.24)

87
Current-Steering DAC Implementations

binary-to-thermometer
encoder
latches,
binary code

switches,
and
MSBs current sources
delay

LSBs

(a)

latches,
encoders

switches,
and
current sources
delay

(b)
Figure 5.8 (a) Segmented and (b) multi-segmented current-steering DAC architecture.

88
 Digital DAC building blocks

In Fig. 5.7(b) it is indicated that the truth table of the 2-3 encoder, with inputs b 0
and b 1 , appears twice in the truth table for the 3-7 encoder. The logic expression
describing the 3-7 encoder is

t 3j (b 2, b 1, b 0) = b 2 + t 2j (b 1, b 0) = b 2 ⋅ t 2j (b 1, b 0) ,

t 43(b 2, b 1, b 0) = b 2 = b 2 , and

t j + 4(b 2, b 1, b 0) = b 2 ⋅ t 2j (b 1, b 0) = b 2 + t 2j (b 1, b 0) , (5.25)

where j ∈ { 1, 2, 3 } .
In Fig. 5.7(c) it is indicated that the logic expressions for a 4-bit encoder can be
obtained in a similar fashion if a 3-bit encoder is available. For the general N -bit
encoder we have

t Nj (b N – 1, …, b 0) = b N – 1 ⋅ t Nj – 1(b N – 2, …, b 0) ,

t 2 N – 1(b N – 1, …, b 0) = b N – 1 , and

t Nj + 2 N – 1 (b N – 1, …, b 0) = b N – 1 + t Nj – 1(b N – 2, …, b 0) , (5.26)

where j ∈ { 1, …, 2 N – 1 – 1 } . Rewriting (5.26) yields

t Nj (b N – 1, …, b 0) = b N – 1 + t Nj – 1(b N – 2, …, b 0) ,
t 2 N – 1(b N – 1, …, b 0) = b N – 1 , and

t Nj + 2 N – 1 (b N – 1, …, b 0) = b N – 1 ⋅ t Nj – 1(b N – 2, …, b 0) . (5.27)

Since differential signals are used to control the switches, it is unimportant

whether the outputs from the encoder are the thermometer coded bits or their
inverses, since both types are required. Therefore, if we allow that the outputs
from even order encoders (i.e., the encoders for which N is an even integer) are
the inverted thermometer coded bits, any N -bit encoder can be implemented with
a tree of NAND gates, NOR gates and inverters. A 2-bit encoder, a general even
order encoder, and a general odd order encoder are shown in Fig. 5.9(a), (b) and
(c), respectively.
The binary-to-thermometer encoder can be physically implemented in various
ways. One way is to describe the block in a hardware description language, e.g.,
VHDL or Verilog [71], and utilize a synthesis flow on this description to auto-
matically generate the circuit. In the implementations presented in this chapter
we have used the full-custom approach.

89
Current-Steering DAC Implementations

b
0 t2
1

2
b t2
1

2
t3

(a)

b0 tN−1 tN b0 tN−1 tN
1 1
1 1

tN−1
N−1
bN−2 N−1
tN bN−2 t2N−1−1 tN
2 −1 N−1 N−1
2 −1 2 −1

bN−1 tNN−1 bN−1 tNN−1

2 2

tNN−1
2 +1
tNN−1
2 +1

tNN tNN
2 −1 2 −1

(b) (c)
Figure 5.9 (a) 2-bit encoder, (b) even order N-bit encoder, and (c) odd order N-bit encoder.
The boxes in (b) and (c) represents (N-1)-bit encoders.

5.3.2 Switch signal generators

In the following we assume that the switches are PMOS switches, as in
Sec. 5.2.2. To avoid that both transistors are simultaneously turned off, the
switching signals Q + and Q – should not simultaneously be high [72], but rather
have nonoverlapping waveforms similar to those in Fig. 5.10. Two different cir-
cuits for creating nonoverlapping switching signals are presented in this section.
Both have been used in the implementations presented in the following. For
NMOS switches it is instead required that the switching signals are overlapping.
These signals can be generated in a similar way as nonoverlapping signals.
The first circuit, which uses digital logic gates, is shown in Fig. 5.11. It is
assumed that the inputs are synchronized with flip-flops or similar. In steady
state, Q + = D and Q – = D . When there is a transition in the inputs, an output
cannot go high until the other output has reached a low level.

90
 DAC design strategies and measurement setup

Nonoverlapping switch signals

1
Logic level

n n+1 n+2
Update instant

Figure 5.10 Nonoverlapping switch signals for controlling differential PMOS switches.

D Q+

Q−
D

Figure 5.11 Implementation of switch signal generator utilizing cross coupled NOR gates.

The second solution utilizes clocked differential cascode voltage switch (DCVS)
[73] latches, and is shown in Fig. 5.12. It is required that the inputs only change
their values while the clock signal, Φ , is high, i.e., when the clocked transistors
are turned off. This can be ensured by adding a latch at the input which is trans-
parent only during the high clock phase. By proper sizing of the transistors, the
crossover point between Q + and Q – can be chosen to avoid having both switch
transistors simultaneously shut off [21].

5.4 DAC design strategies and measurement setup

Some overall design strategies are shared between the current-steering DAC
implementations presented in this chapter. To avoid repeating these design strate-
gies for each DAC separately, we have compiled them in this section. We also
present the measurement setup that has been used.

91
Current-Steering DAC Implementations

D D

F F

Q– Q+

Figure 5.12 Clocked DCVS latch implementation of a switch signal generator.

5.4.1 Overall layout structure

An overview of a DAC floor plan is shown in Fig. 5.13. Starting from the left we
have the digital inputs entering the digital encoder consisting of binary-to-ther-
mometer encoders and delay elements. Once the decoding is performed, the sig-
nals are applied to the switch signal generators (denoted latches in Fig. 5.13),
whose outputs are used to control the switches. The current sources are placed in
the block in the right part of Fig. 5.13, and the output current wires are placed
between the array and the switches.
latches & switches
encoding & delay

current source array

digital input output currents

Figure 5.13 Layout strategy used in the DAC implementations.

92
 DAC design strategies and measurement setup

In other design strategies, using so called row-column decoding for thermometer

encoding, the switches and some digital logic are placed within the arrays [7].
This may cause interference between digital and analog parts, leading to a noisy
output signal. With the layout strategy used in the implementations presented in
this chapter, the analog and digital parts are separated. Guard rings are used
around digital as well as analog parts to reduce the substrate noise in the analog
parts due to switching in the digital parts. Separate supply voltages are used for
digital and analog circuitry, to reduce the amount of simultaneous switching
noise [74] in the analog signals.

5.4.2 Clocking strategy

Uncertainties in the timing of the switching signals, known as jitter, cause distor-
tion and noise in the DAC output. It is therefore important that the DAC is
updated at well-defined instants in time. In order to achieve that, it is required
that the clock net driving the switch signal generators is carefully designed. A
schematic of a clock net with a tree structure that has been used in the implemen-
tations is shown in Fig. 5.14. Special care has been given to equalizing the
lengths of the wires connected to the output of the inverting buffers in each level
of the tree in the layout. This is in order to have the same capacitive load in each
branch to avoid skew of the clock signal between the branches.

Figure 5.14 Tree clock network for driving the switch signal generators.

5.4.3 Measurement setup

The DAC measurements presented in the following sections have been performed
using a measurement system outlined in Fig. 5.15(a). The measurement system is
controlled by a personal computer (PC) running Matlab. Input data to the DAC is

93
Current-Steering DAC Implementations

delivered from a measurement board with a low voltage differential signalling

(LVDS) interface to the DAC. This measurement board is also capable of collect-
ing digital data for, e.g., ADC measurements. This feature is not used during the
DAC measurements, and is therefore omitted in Fig. 5.15. The peripheral instru-
ments, such as power supply, clock generator, oscilloscope, and spectrum ana-
lyzer, are connected to the PC via a general purpose interface bus (GPIB). The
instruments are controlled by a GPIB controller, which in turn is controlled from
Matlab. Measurement data can be collected from the measurement instruments
over the GPIB, and further analyzed in Matlab.
A printed circuit board (PCB) for DAC measurement is outlined in Fig. 5.15(b).
The output currents from the DAC is directed into off-chip resistors. An RF-
transformer is used to convert the differential signal to a single-ended signal that
can be handled by the different measurement instruments. In order to measure the
individual single-ended outputs, the transformer must be removed.

5.5 A 14-bit DAC in 0.35 µm CMOS

In this section we present the first DAC chip manufactured during this work. A
brief overview of the chip is given in Sec. 5.5.1. Measurement results are pre-
sented in Sec. 5.5.2.

5.5.1 Chip description

A photo of the chip is shown in Fig. 5.16. The chip was fabricated in a 0.35 µm
CMOS process with three metal layers. The total chip area is 7.3 mm2, whereas
the core area is 2 mm2. The DAC is segmented, where the 5 MSBs are encoded
into thermometer code and the remaining 9 LSBs are binary weighted. The cur-
rent sources are of PMOS type utilizing a single cascode transistor, and the
switches are of NMOS type. As was mentioned in Sec. 5.2.2, it would have been
a better choice to use PMOS switches. This mistake was corrected in the later
implementations. The strategy used for placement of unit current sources in the
array was aimed at reducing the influence of linearly graded parameter varia-
tions. The switch signal generators are of the type shown in Fig. 5.11. A thorough
description of the design is given in [75].

5.5.2 Measurement results

Output spectra from differential full-scale single-tone measurements are shown
in Fig. 5.17. For the (a) and (b) figures the update frequency is 5 MHz, and the
signal frequencies are approximately 0.6 MHz and 1.6 MHz, respectively. The
update frequency in the (c) and (d) figures is 20 MHz, and the signal frequencies

94
 A 14-bit DAC in 0.35 µm CMOS

power clock
supply generator

oscilloscope
measurement DAC
board
spectrum
GPIB analyzer
PC
controller

(a)

clock single-ended RF
outputs transformer
digital input

DAC

load
resistors combined
output
digital supply analog supply

(b)
Figure 5.15 Setup for DAC measurements. The block diagram in (a) shows the PC con-
trolled measurement system, and a PCB used for DAC measurement is outlined
in (b).

are approximately 2.5 MHz and 6.5 MHz, respectively. A common property for
all spectra in Fig. 5.17 is that the dominating spurious tone is the third harmonic,
and we observe that the SFDR decreases with increasing signal frequency.

95
Current-Steering DAC Implementations

Figure 5.16 Chip photo of the 14-bit current-steering DAC implemented in a 0.35 µm
CMOS process.

Output spectra for half-scale single-tone measurements are shown Fig. 5.18
below. The signal and update frequency for each sub figure is the same as in the
corresponding sub figure in Fig. 5.17. Once again we find that the dominating
spurious tone is the third harmonic, and that the SFDR decreases with increasing
signal frequency.
The measurements were carried out for several signal frequencies, and the SFDR
was extracted from the spectra. SFDR is plotted as a function of signal frequency
in Fig. 5.19. Fig. 5.19(a) shows SFDR for the full-scale inputs, whereas
Fig. 5.19(b) shows SFDR for the half scale inputs.
These measurement results correspond well with the simulation results presented
in Sec. 3.4. This indicates that the models of nonlinear behavior due to parasitic
capacitance that was presented provide good descriptions of the behavior of cur-

96
 A 14-bit PRDEM DAC in 0.35 µm CMOS

Output Spectrum, f = 5 MHz. Output Spectrum, f = 5 MHz.

u u
0 0

−10 −10

−20 −20

−30 −30
PSD [dBm/Hz]

PSD [dBm/Hz]
−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
Frequency [Hz] 6
x 10 Frequency [Hz] 6
x 10

(a) (b)
Output Spectrum, f = 20 MHz. Output Spectrum, f = 20 MHz.
u u
0 0

−10 −10

−20 −20

−30 −30
PSD [dBm/Hz]

PSD [dBm/Hz]

−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [Hz] x 10
6 Frequency [Hz] x 10
6

(c) (d)
Figure 5.17 Single-tone full-scale measurements on 14-bit DAC in 0.35 µm CMOS. For (a)
and (b) the update frequency is 5 MHz, and the signal frequencies are approxi-
mately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d) the update fre-
quency is 20 MHz, and the signal frequencies are approximately 2.55 MHz and
6.55 MHz, respectively.

rent-steering DACs at higher frequencies. In the later implementations, presented

in Sec. 5.6 and Sec. 5.7, the dynamic properties were improved (compared with
this implementation) by reducing the amount of parasitic capacitance.

5.6 A 14-bit PRDEM DAC in 0.35 µm CMOS

DEM techniques that use randomization to reduce the harmonic distortion caused
by component mismatch were presented in Sec. 4.1.3. In the PRDEM technique
the degree of randomization is lower than in fully randomized DEM techniques,
e.g., FRDEM, but the hardware cost is considerably lower. The design, simula-
tion and measurement of a 14-bit PRDEM DAC is discussed in this section.

97
Current-Steering DAC Implementations

Output Spectrum, f = 5 MHz. Output Spectrum, f = 5 MHz.

u u
0 0

−10 −10

−20 −20

−30 −30
PSD [dBm/Hz]

PSD [dBm/Hz]
−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
Frequency [Hz] 6
x 10 Frequency [Hz] 6
x 10

(a) (b)
Output Spectrum, f = 20 MHz. Output Spectrum, f = 20 MHz.
u u
0 0

−10 −10

−20 −20

−30 −30
PSD [dBm/Hz]

PSD [dBm/Hz]

−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [Hz] x 10
6 Frequency [Hz] x 10
6

(c) (d)
Figure 5.18 Single-tone, half-scale measurements on a 14-bit DAC in 0.35 µm CMOS. For
(a) and (b) the update frequency is 5 MHz, and the signal frequencies are
approximately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d) the update
frequency is 20 MHz, and the signal frequencies are approximately 2.55 MHz
and 6.55 MHz, respectively.

Comparisons between measurements and simulations using models of mismatch

and dynamic errors discussed in Chapter 3 are presented, showing a good agree-
ment between simulations and measurements.

5.6.1 Implementation
The PRDEM chip is constructed with four layers of switching. The control sig-
nals for the switches are generated off-chip to allow flexibility. The switching
tree is terminated with DAC banks consisting of one 1-bit DAC and one 10-bit
DAC, as was discussed in Sec. 4.1.3. The current sources and the current
switches are both of PMOS type, and no cascodes have been used in the current

98
 A 14-bit PRDEM DAC in 0.35 µm CMOS

SFDR vs. Signal Frequency SFDR vs. Signal Frequency

70 70
f = 5 MHz f = 5 MHz
u u
f = 20 MHz f = 20 MHz
u u
65 65

60 60
SFDR [dB]

SFDR [dB]
55 55

50 50

45 45

40 5 6 7
40 5 6 7
10 10 10 10 10 10
Signal frequency [Hz] Signal frequency [Hz]

(a) (b)
Figure 5.19 SFDR vs. signal frequency for (a) full-scale signals and (b) half-scale signals.
The upper curve in both figures correspond to the update frequency 5 MHz,
whereas the lower curves correspond to the update frequency 20 MHz.

sources. A description of the design strategy used is given in [76]. A chip photo
of the PRDEM DAC is shown in Fig. 5.16. The core area of the chip is approxi-
mately 6.3 mm2.

DAC bank

Figure 5.20 Chip photo of current-steering PRDEM DAC.

99
Current-Steering DAC Implementations

5.6.2 Simulations and comparison with measurements

Comparisons between measurements and simulations of the PRDEM DAC are
presented in [34] and [35]. This section is a summary of these papers.

Simulation setup and results

In the simulations a Gaussian distributed error current with a standard deviation
of approximately 10% has been added to each unit current source. This is a rather
large value but it includes all static errors in the DAC, e.g., mismatch between
current sources, mismatch in biasing, gain errors between the DAC banks etc.
The input is a full scale sinusoid with frequency f sig ≈ 1.25 MHz and update fre-
quency of f u = 10 MHz . The single-ended output, terminated over 50 Ω, is
examined. The parameters used for the state-space model are given in
Table 5.1.The output without randomization is shown in Fig. 5.21(a). The SFDR
(60.2 dB) is limited by the third harmonic. When introducing switching in the
first layer (Fig. 5.21(b)) the SFDR is increased to 67.7 dB, an improvement of
7.5 dB corresponding to approximately one effective bit, to the cost of a some-
what higher noise floor. The SFDR is now limited by the second harmonic. When
introducing switching in all four layers (Fig. 5.21(c)) we can see some smaller
differences compared with Fig. 5.21(b) but the SFDR remains the same, hence
we do not gain any SFDR performance by having more than one switching layer.
This can be explained by observing the second harmonic in Fig. 5.21(a), (b) and
(c). The second harmonic is almost unaffected by the randomization, because it
arises from dynamic errors in the DAC and as soon as the third harmonic, arising
from mismatch, is suppressed below the second harmonic we do not gain in
SFDR performance by using DEM [69].

DAC model parameter Value

Unit current (nominal) 1.22 µA
Output resistance (unit current source) 1 GΩ
Output capacitance (unit current source) 10 fF
Switch resistance 200 Ω
Load resistance 50 Ω
Load capacitance 100 pF
Table 5.1 DAC model parameters used in the simulations.

100
 A 14-bit PRDEM DAC in 0.35 µm CMOS

Simulated Spectrum Without DEM

−10
SFDR = 59.6 dB
−20

−30

PSD [dB/Hz]
−40

−50

−60

−70

−80

−90

−100
0 1 2 3 4 5
Frequency [MHz]

(a)
Simulated With 1 Layer DEM Simulated With 4 Layer DEM

0 0

−10 −10
SFDR = 67.8 dB SFDR = 68.1 dB
−20 −20

−30 −30
PSD [dB/Hz]

PSD [dB/Hz]

−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90

−100 −100
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [MHz] Frequency [MHz]

(b) (c)
Figure 5.21 Simulated spectra using 10MHz update frequency, (a) without randomization,
with (b) one switching layer and (c) four layer switching.

Measurement results
To verify the simulated results, the implemented DAC is measured with the same
update frequency, f u = 10 MHz . In Fig. 5.22(a) and Fig. 5.22(b) we compare
the gain in performance between using no randomization and using one switch-
ing layer. We find that the SFDR is increased from 60.7 to 67.7 dB, an improve-
ment of 7.5 dB which could be predicted from the simulation results. When
switching all four layers (Fig. 5.22(c)) we do not gain much in SFDR perfor-
mance compared with the results in Fig. 5.22(b).

Comparison of SFDR performance

To see how well the model works for different update frequencies, the simulated
results were compared with measurement results from the real PRDEM DAC.
The update frequency is swept while the ratio between signal frequency and
update frequency, f sig ⁄ f u ≈ 1 ⁄ 8 , is held constant. The simulated and measured

101
Current-Steering DAC Implementations

Measured Spectrum Without DEM

0

−10
SFDR = 60.7 dB
−20

−30

PSD [dB/Hz]
−40

−50

−60

−70

−80

−90

−100
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency [MHz]

(a)
Measured With 1 Layer DEM Measured With 4 Layer DEM
0 0

−10 −10
SFDR = 67.3 dB SFDR = 68 dB
−20 −20

−30 −30
PSD [dB/Hz]

PSD [dB/Hz]

−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90

−100 −100
0.5 1 1.5 2 2.5 3 3.5 4 4.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency [MHz] Frequency [MHz]

(b) (c)
Figure 5.22 Measured spectra, 10MHz update frequency, (a) without randomization, with
(b) one switching layer and (c) four layer switching.

SFDR without randomization are compared in Fig. 5.23(a). The same compari-
son with randomization is shown in Fig. 5.23(b). We find from Fig. 5.23(a) and
Fig. 5.23(b) that the simulated and measured results behaves similarly, which is a
good validation of the models used in the simulations.

5.7 A dual 14-bit DAC in 0.25 µm CMOS

Design and measurement results of a 14-bit dual DAC implemented in a 0.25 µm
CMOS process is presented in this section. The term dual indicates that two
DACs are implemented on the same chip. The chip can, e.g., be used for evalua-
tion of the techniques presented in Sec. 4.2.1, or to realize a single switching
layer PRDEM DAC.

102
 A dual 14-bit DAC in 0.25 µm CMOS

Simulated and measured SFDR without DEM Simulated and measured SFDR with DEM
65
Measured 74 Measured 12
Simulated Simulated

71
62 10
68 11

Number of bits

Number of bits
SFDR [dB]

SFDR [dB]
65
59

62 10

56 9 59

56 9

53
53
1 5 10 30 1 5 10 30
Sampling Frequency [MHz] Sampling Frequency [MHz]

(a) (b)
Figure 5.23 Simulated and measured SFDR performance for different update frequencies
with (a) no randomization, and (b) switching in all layers.

5.7.1 Architecture and implementation

The DAC has a doubly segmented architecture where both the seven LSBs and
the seven MSBs are converted into thermometer code controlling the current
switches. A single PMOS transistor current source and PMOS current switches
are used. The circuit in Fig. 5.12 is used for generation of the switching signals.
Distributed biasing (see Sec. 4.1.2) is used to achieve good matching properties.
The current source arrays are divided into eight sub arrays having individual
local bias circuits. The bias currents for the local bias circuits are generated with
a global bias circuit consisting of a multiple output cascoded NMOS current mir-
ror, which is shared between the two DACs to obtain good mutual matching. A
plot of the DAC chip is shown in Fig. 5.24.
Current source arrays and the binary-to-thermometer encoder described in
Sec. 5.3.1 are examples of regular circuit structures. The regularity has been uti-
lized in this implementation for automated design. Some sub cells, like a current
source, a switch and logic gates, have been designed by hand, whereas practically
all other parts of the design have been based on scripts. This has greatly reduced
the time required for the design. Similar approaches are used by others [77].
There is a trend of increased use of design automation for analog and mixed sig-
nal circuits [78], which will likely continue in the future.

5.7.2 Measurement results

One reason for implementing two converters on the same chip is, as mentioned,
to have a test chip for the techniques presented in Sec. 4.2.1. At this point, how-
ever, the DACs have only been measured one at a time, mainly due to the lack of
proper test equipment. SFDR for full-scale signals is plotted as a function of sig-

103
Current-Steering DAC Implementations

Figure 5.24 Chip plot of the dual current-steering DAC.

nal frequency in Fig. 5.25. For the cases when the update frequency is 5 and
10 MHz, SFDR is higher than 73 dB for a range of signal frequencies up to
3 MHz. This can be regarded as a good result, even if an SFDR of at least 86 dB
is required for 14 effective bits. The linearity is deteriorated when the update fre-
quency is increased to 25 MHz. This phenomenon is not yet explained, and
requires more study.
A more adequate measure for DMT applications is the MTPR, which is defined
in Sec. 2.3.2. For this purpose we use an ADSL-like input, which is quantized
values of
255
j⋅∆
X ( n ) = X DC + K ⋅ ∑ a j ⋅ sin  2πn ------------
fu
-f + φ j ,

(5.28)
j=1

104
 Summary of implemented DACs

SFDR vs. Signal Frequency

80
fu = 5 MHz
fu = 10 MHz
75 fu = 25 MHz

70
SFDR [dB]

65

60

55

50 6 7
10 10
Signal frequency [Hz]

Figure 5.25 Measured SFDR as a function of signal frequency.

where a j = 0 for j = 142 and a j = 1 otherwise. The frequency spacing

∆ f = 4.3125 kHz and the update frequency f u = 10 MHz . The phases φ j are
random and the scaling factor K and the dc level X DC are chosen such that the
whole input range of the DAC ( [ 0, 2 14 – 1 ] ) is used. The measured signal spec-
trum is shown in Fig. 5.26. The MTPR, limited by the noise floor, is approxi-
mately 71 dB. This is a good result, even compared with commercial DACs for
DSL applications, e.g., AD9764 [33] from Analog Devices, Inc.

5.8 Summary of implemented DACs

The DAC implementations presented in this chapter are summarized in Table 5.2.
The DAC with the highest performance is clearly the dual DAC presented in
Sec. 5.7. The modeling of nonideal behavior presented in Chapter 3 has provided
an insight in what parameters are most important and allowed an improvement
from one circuit implementation to the next.

105
Current-Steering DAC Implementations

missing tone

Figure 5.26 MTPR measurement result.

0.35 µm DAC 0.35 µm PRDEM DAC 0.25 µm dual DAC

Number of bits 14 14 14
4 mm2 (totally for
Core area 2 mm2 6.3 mm2
both DACs)
Supply voltage 3.3 V 3.3 V 2.7 V
Unit current 1.22 µA 1.22 µA 1.22 µA
5+5 bits in each DAC 7+7 bits in each
Segmentation 5 bits
bank DAC
62 dB without DEM
Peak SFDR 64 dB 78 dB
72 dB with DEM
SFDR @ 1 60 dB without DEM 77 dB,
58 dB
MHz signal 67 dB with DEM f u = 5 MHz
Table 5.2 Summary of implemented DACs.

106
 6 Conclusions
The thesis covered selected topics in the areas modeling, error correction tech-
niques and implementation of CMOS DACs. The main focus was on the linearity
properties of current-steering DACs for telecommunication applications.
The application of DACs in DSL environments was outlined. The requirements
on high linearity in the DAC was illustrated by examining the influence of non-
linear distortion on QAM constellations. The ideal DAC was presented, as well
as some performance measures commonly used for characterizing communica-
tion DACs.
Different sources of nonlinear behavior in current-steering DACs were discussed.
The static errors dominate the low-frequency behavior, whereas the high-fre-
quency behavior is dominated by dynamic errors. Mismatch between circuit ele-
ments is one of the main sources of static nonlinear behavior. An analysis of the
influence of linearly graded matching errors on the performance of current-steer-
ing DACs with a certain layout strategy was made. This layout strategy is known
to have poor properties when it comes to suppressing matching errors, but was
useful in the example. The source of nonlinear behavior that was focused on in
this work was the parasitic capacitance in the transistors and the wires. The phe-
nomenon was first modeled with a state-space model in Matlab. Results from
simulations using this model were presented to illustrate the effect of the noni-
deal components included in the model. A model with relatively low computa-
tional complexity was developed. This model is suitable for on-chip
implementation for use in error correction/compensation techniques.
Various methods for improving the linearity of DACs were discussed. Some of
the methods, like DEM and the differential DAC architecture, rely on redundant
coding to improve the linearity. In DEM the distortion caused by mismatch is, in
some sense, transformed into noise. To gain in the overall SNDR, oversampling

107
Conclusions

and filtering of out-of-band noise are required. Other methods, like distributed
biasing and a proposed calibration technique, aim at reducing the mismatch
between the output currents from the current sources. Two ideas utilizing models
of the dynamic nonlinearity caused by nonzero output capacitance in the current
sources were proposed. Both ideas aimed for enhanced linearity at higher signal
frequencies. The first method utilized a feedback loop similar to delta-sigma
modulation, and was denoted distortion shaping. The second method was a type
of predistortion. The simulations showed promising results, and an initial mea-
surement of the distortion shaping method indicates that the models used are
good enough to be practically useful. More measurements, and possibly model
modifications, are, however, required to draw any further conclusions.
Three different implementations of current-steering DACs in CMOS were pre-
sented. The required building blocks were discussed separately, and overall
design considerations were presented. The first two DACs were fabricated in a
0.35 µm CMOS process. One of these DACs utilizes the PRDEM technique for
enhanced static linearity. The third converter was fabricated in a 0.25 µm CMOS
process. Distributed biasing of current sources was used in this implementation
to reduce the matching errors between the current sources. Knowledge from the
behavioral level modeling was utilized to improve the performance from one cir-
cuit implementation to the next. Measurement results show close resemblance
with the simulation results using the behavioral level models presented in this
thesis. The simulations and measurements on the PRDEM DAC are especially
interesting, since they illustrate the limited efficiency of DEM when dynamic
errors dominate, besides validating the behavioral level modeling.

108
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 Systematic Design of a 14-bit 150-MS/s
CMOS Current-Steering D/A Converter
G. Van der Plas, J. Vandenbussche, W. Daems, A. Van den Bosch,
*
G. Gielen , M. Steyaert, W. Sansen
Department of Electrical Engineering, Katholieke Universiteit Leuven, ESAT-MICAS
Kardinaal Mercierlaan 94, 3001 Heverlee, Belgium
E-mail : georges.gielen@esat.kuleuven.ac.be
Abstract II Current-steering D/A Converter Architecture
This paper presents a D/A converter with a 14-bit in- For high-speed, high-accuracy D/A converters, a segmented cur-
trinsic linearity in 0.5µm CMOS technology, which has rent-steering topology is usually chosen as it is intrinsically faster
been designed using a systematic design methodology and more linear than competing architectures [2]. The principle of
this type of D/A converter is depicted in Fig. 1: the l least signifi-
for current-steering D/A converters. A flexible architec- cant bits are binary implemented, the m most significant bits steer
ture is proposed for which the design parameters are a unary current source array.
calculated using a performance-driven top-down design VDD

methodology. The layout of the regular structures typi-

cal for D/A converters is automatically generated. t0 t1 t2 t3
t0
T
Measurement results are reported. Due to the system- H t1 IMSB IMSB IMSB IMSB
E t2
atic design methodology, the design was realized in less R
t3
M
than one month total accumulated person effort. b0 b1 b2 b6
b7
O
M
t4 t4 t5 t6 t7

t5
ILSB 2ILSB 4ILSB E IMSB IMSB IMSB IMSB
b8 t6
T
I Introduction b9 E t7
b10 R t8 t251
b3 b4 b5
In this paper the design methodology and the design of a complete b11
D
8ILSB 16ILSB 32ILSB b12 IMSB ... ... IMSB
current-steering D/A converter implemented in a standard 0.5µm b13
E
C t251
CMOS technology, is presented. This is the first publicly reported O
D
t252
t252 t253 t254
CMOS D/A converter with 14-bit intrinsic linearity, achieved binary weighted E
R
t253
t254 IMSB IMSB IMSB
without trimming or tuning [1]. The D/A converter has been de- current cells
signed according to a systematic design methodology which al-
unary current cells
lows to generate new designs for given specifications, or to easily
port designs to new processes. The design methodology covers Fig. 1: Simplified block diagram of a 14-bit segmented current-steering
the complete design flow and is supported by both commercial D/A converter. The l (=6) least significant bits steer the binary
and in-house developed academic software tools to speed up the weighted current sources directly. The m (=8) most significant bits
task significantly. Design times of less than one month total ac- are fed into the thermometer decoder, which steers the unary current
source array
cumulated person effort are obtained. The inputs are the specifica-
tions of the D/A converter and the technology and the result is a Specification Unit Value
verified layout. Static Number of bits (n) - 14
This paper is organized as follows. In section II the architecture of INL LSB 0.5
the D/A converter and its design parameters are described. Sec- DNL LSB 0.5
tion III explains the proposed systematic design methodology. Parametric Yield % 99.9
The sizing synthesis is explained to its full extent in section IV. Dynamic Sample frequency MHz 100
Section V describes the layout generation process. Section VI SFDR@500kHz dB 80
presents the experimental results and measurements of the im- Settling time ns 10
plemented design. Conclusions are given in section VII. Environmental Output range (Vswing) V 0.5
Permission to make digital/hardcopy of all or part of this work for personal or RLoad Ω 25
classroom use is granted without fee provided that copies are not made or
Digital levels - CMOS
distributed for profit or commercial advantage, the copyright notice, the title of the
publication and its date appear, and notice is given that copying is by permission of Power Supply V 2.7
ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to Technology - 0.5µ 1P3M
lists, requires prior specific permission and/or a fee.
DAC 2000, Los Angeles, California
Optimization Power Consumption mW Minimize (300)
(c) 2000 ACM 1 -58113-188-7/00/0006..$5.00 Area mm2 Minimize (10)
Table 1: General specification list for a current-steering D/A converter with
typical values.

*
research associate of the National Fund of Scientific Research (Belgium)
The general specification list for a current-steering D/A converter The last important architectural design parameter of a current-
is given in Table 1. The specifications can be divided into four steering D/A converter is the switching scheme. The switching
categories: static, dynamic, environmental and optimization scheme has two components. A unary current source can be split
specifications. In the case of a D/A converter the static parameters in one or more units, as shown in Fig. 3. By splitting the unary
include static accuracy (i.e. number of bits), integral non- current source the spatial errors are averaged out, which is neces-
linearity (INL), differential non-linearity (DNL) and yield. The sary for high-accuracy applications [3,4]. The second parameter of
dynamic parameters include sample frequency, spurious free dy- the switching scheme is the switching sequence. In [5] it is shown
namic range (SFDR) and settling time. The environmental pa- that the remaining spatial errors are not accumulating when the
rameters include the power supply, the digital levels, the output current sources are switched on in an optimal order when the
load and the input/output range. The power consumption and area input code increases. The here proposed architecture differs from
need to be minimized for the specified technology. This specifica- previously used architectures in that the switching is fully flexible
tion list serves as input for the design process as will be explained and can be programmed when generating the layout to optimally
in the following sections. compensate for systematic errors which would otherwise deterio-
rate the targeted linearity.
In the next paragraphs the proposed D/A converter architecture
and its design parameters will be presented in detail. The designable parameters of the presented D/A converter are
summarized in Table 2. They have been classified in architecture
b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b1 b0
... level parameters and circuit level parameters
Clock Thermometer decoder Latency
driver equaliser Design parameters of the converter
VDDcur_src Full Decoder Architecture level l (number of LSBs)
un 1...255 bin 1...6
m (number of MSBs)
Iout Number of units (1/4/16 units) for unary current
Iout Iout Binary latch
Unary latches & switches source
& switches
Iout
switching sequence
2b M2a Swatch Array Circuit level WM1, LM1, (Vgs-Vt)M1
255 6
WM2, LM2
M1 Binary
Unary current source current src Latch transistor sizes
array array Clock driver sizes
VSScur_src
Current Source Array Table 2: The designable parameters of the presented D/A converter.
Fig. 2: The block diagram and floorplan of the proposed architecture.
III Systematic Design Methodology
The simplified block diagram of Fig. 1 has been implemented by
The performance-driven top-down design methodology has been
the proposed segmented architecture shown in Fig. 2. The current
accepted as the de facto standard for systematically designing
generated by the current sources (M1) are switched to one of the
analog building blocks in academia [6,7]. In [8] the design of
two differential output nodes of switch transistors M2a and M2b.
current-steering D/A converters has been automated following
These are driven by a latch. The full decoder comprises the ther-
this methodology for a specific architecture which is however
mometer decoder, which generates the steering signals for the
only feasible for 8 or 10-bit D/A converters.
unary latches, and a latency equalizer block. This latency equal-
izer block ensures correct timing for the steering signals of the
binary latches. One of the important architectural design parame- Analog Digital
ters is how many bits are implemented with binary weighted cur- Sizing
Synthesis
rent sources and how many with unary weighted current sources. Architectural level

The floorplan of the presented architecture is also shown in Fig. 2. Verification Verification
The switches and latches are implemented as one unit cell, and
placed in an array, referred to as the “swatch” array. The current
Sizing
source transistors are also placed in an array, the current source Device level
array. The three large modules (full decoder, swatch array and
current source array) are connected by signal busses. A clock Verification
driver completes the D/A converter.

Floorplanning

Layout Standard cell

Module & Device level Place & route

Verification Verification

(a) (b) (c)

Layout Assembly & Verification
Fig. 3: Three different switching schemes:
(a) unary current source implemented as 1 unit
(b) unary current source implemented as 4 units in parallel Fig. 4: Presented systematic design flow for a current-steering D/A con-
(c) unary current source implemented as 16 units in parallel verter
The design flow, shown in Fig. 4, presents the design methodol- INL of 0.2 LSB instead of 2.1 LSB. The search algorithm has
ogy that we applied to the design of a high-accuracy D/A con- been implemented in a C program.
verter. It is a mixed-signal design. The analog design flow is
grouped on the left, the corresponding digital flow is grouped on
the right. The analog flow starts with a sizing at two levels: the
architectural-level and the device level. The digital logic synthesis
completes the sizing of the mixed-signal design. These topics will
be explained in detail in section IV. The design steps are verified
using classical approaches: numerical verification with a simula-
tor, at the behavioral, device respectively gate level. The floor-
planning is done jointly for analog and digital blocks, after which
the analog layout is generated, and standard cell place & route is
used to create the digital layout. Both layouts are separately veri-
fied. The blocks are assembled at the chip-level and again a chip- Fig. 5: Prediction of the INL obtained with two different switching se-
level verification is done with industry standard tools. quences. On the left a manually derived (sub-optimal) switching
sequence, on the right the optimized switching sequence (random
The remainder of the paper focuses on the sizing synthesis and walk). The same error profile (extracted from a test chip) has been
layout generation steps in the systematic design flow. Measure- applied.
ment results of a fabricated design will be presented afterwards.
Dynamic performance
IV Sizing Synthesis The dynamic behavior of a D/A converter is usually specified in
A. Architectural-level synthesis terms of spurious free dynamic range (SFDR). This specification
The architectural-level parameters are determined during architec- is mainly determined by (1) the number of bits implemented
tural-level sizing synthesis. These have to be optimized such that unary/binary [9] and (2) the way the current sources are synchro-
the two important performance criteria, as listed in Table 1 (static nized when switched on/off. This implies that the decision on the
and dynamic performance) are met while minimizing chip area number of bits l to be implemented binary and the number of bits
and power consumption. m to be implemented unary determines the SFDR: more segmen-
tation (higher m) results in a better SFDR performance [9]. The
Static performance synchronization of the switching signals is achieved by using a
clocked latch to derive the steering signals for the switches.
The static behavior of a D/A converter is specified in terms of
INL and DNL. A distinction has to be made between random
errors and systematic errors. The random errors are determined
solely by mismatch. The systematic errors are caused by process,
temperature and electrical gradients. In optimally designed D/A
converters the INL and DNL are determined by random errors
(i.e. mismatch) only which are related to the device sizes. A small
safety margin (10 % of INL) is reserved to allow for systematic
contributions. The systematic errors are dependent on the layout
and are minimized, among others, by optimizing the switching
scheme. This also generates constraints for the layout process (as
explained in section V).
Any gradient on chip (be it caused by process, thermal or electri-
cal effects) creates a systematic deviation over the current sources
Fig. 6: Estimated area of the D/A converter in function of number of unary
in the large current source array. In order to compensate this,
bits (m).
every current source can be split in a parallel connection of
smaller transistors spread over the array (see Fig. 3). In this way The highest possible SFDR is obtained when a full unary imple-
the average currents for all current sources are closer to each mentation is chosen [9]. This would however result in a large area
other. This splitting of the unary current source is required for 12 increase. The total chip area is estimated by:
or 14-bit intrinsic linearity and beyond [3,4]. At least a value of 4
for number of units (Table 2) is required for 12-bit linearity and a
areatotal _est = areacur _ src + area swatch
(1)
value 16 units for 14-bit in the used technology. + areadecoder ( l , m) + arearouting (l , m)
But even with this splitting there are remaining current differ- The area of the current source array is fixed (see below) as is the
ences. The switching sequence is therefore optimized to reduce area of the swatch array by the required linearity constraints.
the accumulation of remaining systematic errors. A branch and However, the area of the decoder increases (2m), as does the size
bound search algorithm has been used to determine the switching of the routing busses connecting the three modules, if the number
order of the allocated current sources so that the errors do not of unary bits is increased. Fig. 6 shows that in current technolo-
accumulate but are “randomized” (i.e. compensate each other as gies an optimal number of unary implemented bits is 8, otherwise
much as possible). The result is shown in Fig. 5. On the left a the area becomes unacceptable. This choice will ultimately limit
traditionally used manually derived switching sequence has been the dynamic performance of the D/A converter.
simulated. With the same spatial error profiles but an optimal
(smallest INL) computer generated switching scheme the remain- In this way all architectural-level parameters of the converter have
ing systematic errors don’t accumulate anymore, resulting in an been determined (see Table 3) for the specifications of Table 1.
B. Circuit level synthesis where frouting is the routing overhead factor. The static perform-
The circuit level synthesis determines the circuit level design pa- ance places a strict constraint on the minimal area of the current
rameters, these are the sizing and biasing of the current source, source array.
and the sizing of the latch and switches. Again the two perform- The upper limit for the biasing voltage is determined by the output
ance constraints (static and dynamic) are taken into account. swing (switching transistors M2 need to be in saturation region)
and the power supply. From equation (2) and (3), W1 and L1 can
Static Performance be calculated for a choice of Vgs-Vt.
The active area of the unit current source array is calculated from These calculations resulting in the sizing of the current source
mismatch constraints. transistors (M1) have been automated in a Matlab script. For a 14-
100
bit converter this gives a W/L=1.1µm/104.5µm in a standard
0.5µm CMOS technology.
90

80 Dynamic performance
70
In order not to deteriorate the dynamic performance, the following
60
factors are taken into account in the circuit level synthesis [12]:
Yield [%]

50 (1) synchronize the control signals of the switching transistors, (2)

40
reduce voltage fluctuations in the drains of the current sources, (3)
carefully switch the current source transistor on/off. The synchro-
30
nization of the control signals is achieved by adding a latch im-
20
mediately in front of the switching transistors M2. The voltage
10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
fluctuation at the drain changes the current from the current
σ (I)/I [%] source because of the finite output impedance of the current
Fig. 7: Yield as a function of unit current cell variance for a 14-bit D/A source transistor M1. The problem can be solved by using a large
converter (INL < 0.5LSB). channel length for the current source transistor, and tuning the
crossing point of the switching control signals such that both
The acceptable random current error can be calculated from yield switches are never switched off simultaneously [4].
simulations. The tolerable relative standard deviation of current
matching (σ(I)/I) can thus be calculated [10]. Fig. 7 depicts the Using a simulator (Hspice) in an optimization loop, the latch and
yield simulation for a 14-bit D/A converter: to achieve a targeted the switches have been sized, taking the crossing point and speed
yield of 99% (INL < 0.5LSB), the relative standard deviation of as constraints in the optimization process.
current matching for the unit current cell (1 LSB) has to be
smaller than 0.1%. The plot shown in Fig. 7 has been calculated C. Decoder Synthesis
using a Matlab program. Since the architectural design parameters (l, m) and the latch tran-
sistor sizes are known, the thermometer decoder can then be syn-
From the required full swing (Vswing), the number of bits (n) and
thesized. The remaining l LSBs are delayed by the equalizer
the load resistance (Rload) the current of one LSB (ILSB) is calcu-
block. The digital decoder has been synthesized using logic syn-
lated:
thesis from a VHDL description.
Vswing
I LSB = (2) D. Clock Driver Synthesis
RLoad 2 n
The clock driver generates the clocking signals for the decoder
An estimate can then be calculated for the active area of the cur- and swatch array. Both these blocks have been sized and thus the
rent source transistor according to the used mismatch model [11] load is known. An invertor chain has been designed to drive this
and the derived current matching: load.

1  2 2
4 AVT 
W∗ L =  βA + 2 (3) Design parameters of the architecture
2σ 2 ( I )  (VGS − VT )  Architecture level 6 (number of LSBs)
I2 8 (number of MSBs)
16, Quad Quadrant [1] (number of units)
where σ(I)/I is the derived unit current source standard deviation
Random Walk [1] (INL optimized
and Aβ , AVT are technology constants [11]. For minimal area the switching sequence)
Vgs-Vt is maximized.
Circuit level WM1=1.1µ, LM1=104.5µ, (Vgs-Vt)Mcur_src=1Volt
The lower bound for the area is given by: WMsw=0.8µ, LMsw=1µ
sized latch transistor sizes
1
(W ∗ L) est ≈ Aβ2 (4) sized clock driver
2σ 2 ( I )
Table 3: The sized values of the designable parameters of the proposed D/A
I2 converter architecture.
The total current source array area is then estimated to be at least:
E. Sizing Result
areacur _ src ≈ 2 n (W ∗ L) est f routing (5) In Table 3 the final sizing results are summarized for the specifi-
cations of Table 1.
V Layout Generation
Current-steering D/A converters are a typical example of layout-
driven analog design. The sized schematic alone does not consti-
tute an operational converter. An important part of the perform-
ance is determined by the handling of layout-induced parasitics
and error components (i.e. systematic errors). All classical coun-
termeasures for digital to analog coupling (guard rings, shielding,
separate supplies, …), and matching guidelines (equal orientation,
dummies, …) have been applied and will not be further discussed.
A. Floorplanning
The floorplan proposed in Fig. 2 is now refined. The relative
placement of the modules (full decoder, swatch array, current
source array) was already fixed and the actual sizes (area) of the
modules are readily available. However the aspect ratio is still to
be determined. First of all the global aspect ratio influences the
aspect ratio of the modules. In general a square or near square
chip layout is preferred. Secondly, at the chip-level the connec-
tions between the modules are extremely important: a fixed pitch
for the three modules must be chosen to route the busses between
the different modules to avoid wiring area loss. Furthermore, the
choice of the chip-level pitch also ensures that the modules will
have the same width, resulting in an elegant chip assembly as can
be seen in Fig. 9.
B. Circuit and Module Layout Generation
The current source cell array, swatch cell array and full decoder
are generated next.
Current Source Layout Generation
The sizes of the unit current source have been determined. From
this the sizes of all other weighted current sources and the unary
current source are derived. To have optimal matching properties
the current source must be built up from identical basic units. This
basic unit is manually laid out. Also the floorplan of the current
source array is determined (number of units, switching sequence).
contact
area
Y
X-Y
Fig. 8: Symbolic view of cells and routing channels: vertical (Y) routing
across cells, horizontal (X) routing in between cells. Vertical wires
connect to the contact areas in the cell, horizontal wires connect to
the vertical wires.
The placement of the basic units is thus determined. The current
source array is then generated automatically with the Mondriaan
tool [13]. The Mondriaan tool is targeted to the automated layout
generation of highly regular array-type analog modules. Fig. 8
shows a symbolic view of the layout structures that Mondriaan
generates. The basic cell of the array is tiled, optionally flipped
horizontally or vertically. The connectivity inside the array and to
the outside world is realized through abutment (for power distri-
bution, biasing, clock distribution, …) and by X/Y bus routing.
The Y bus routing connects wires to the contact areas defined
inside the basic cell’s boundary, the X routing connects the Y
wires. The connection pattern has to be entered in a C-like format,
and the tool automatically generates the actual physical layout.
The current source unit is the basic cell in our case. It is placed in
a regular array and the parallel units are connected with the de-
scribed bus routing. In total over 4000 units are placed and con-
nected with more than 1000 wires. Doing this task manually is
impossible. The CPU time of Mondriaan on a standard SUN Ul-
tra I-166 workstation is less than 2 minutes (including the transfer
to a commercial EDA framework). The result is a layout and a pin
list, which serves as input to the swatch array layout generation.
Swatch Array Layout Generation
One swatch cell has been manually laid out. The placement and
routing of the swatch array is then done automatically with the
Mondriaan tool [13]. Inputs to the tool are the pin list of the cur-
rent source array, the netlist and the swatch cell layout. From this
the placement of the cells is derived and the routing created. The
output is the layout and a pin list of the bus for the steering signals
coming from the decoder.
Decoder Standard Cell Place and Route
The layout of the digital decoder is generated using a standard cell
place and route tool, i.e. the tools from Avant!. The pin list ob-
tained from the swatch array layout is input to the floorplan for
the layout generation.
C. Layout Assembly
The modules are placed stacked on top of each other. The bus
generators of the Mondriaan tool [13] are used to generate the
actual connections between the three modules (full decoder,
swatch and current source array). Trees are used to collect the
output signals and distribute the clocking signal from the clock
driver to the swatch array to have equal delay.
Fig. 9: Layout of the 14-bit segmented current-steering D/A converter.
The bonding pads are placed and manually connected to all the
external pins of the D/A converter.
With this approach the 14-bit D/A converter has been laid out.
This layout is shown on the microphotograph in Fig. 9. DRC and
LVS checking was done to verify the generated layout. Parasitics
were extracted and the sizing was verified using Hspice.
Fig. 10: Measurement setup of the 14-bit D/A converter. Fig. 12: Output spectrum measurement. The applied signal frequency is
approximately 500 kHz at full scale.
VI Experimental Results
A 14-bit D/A converter was implemented in 0.5µm CMOS tech-
nology and measured [1]. The measurement setup is shown in
Fig. 10. The update rate of this converter is 150MSamples/s. The
chip has an INL of 0.3LSB and a DNL of 0.2LSB (see Fig. 11).
Its settling time is 0.9ns. It has an SFDR of 84dB @ 500kHz full
scale input signal, the measured spectrum is shown in Fig. 12. In
Fig. 13 the spectrum at the output is shown for a 5MHz full-scale
input signal. An SFDR of 61dB is obtained. The power consump-
tion of the design is 300mW. The measurement results for this
design are summarized in Table 4.
Specification Obtained value
Number of bits 14 Fig. 13: Output spectrum measurement. The applied signal frequency is
approximately 5 MHz at full scale.
INL [LSB] 0.3
DNL [LSB] 0.2 References
Settling time (10-90%) [ns] 0.9 [1] J. Vandenbussche, et al., “A 14-bit, 150 MSamples/s Update Rate, Q2
Sample frequency [Mhz] 150 Random Walk CMOS DAC”, Proc. IEEE 1999 ISSCC, pp. 146-147,
Output range [V] 0.5 February 1999.
Rload [Ω] 25 [2] B. Razavi, “Principles of Data Conversion System Design", IEEE
Digital levels CMOS Press, ISBN 0-7803-1093-4, pp. 62-63, 1995.
Power supply [V] 2.7 [3] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-bit
Power consumption [mW] 300 Intrinisic Accuracy High-Speed CMOS DAC, IEEE JSSC, vol SC-33,
Area [mm2] 3.2 x 4.1 no. 12, pp. 1959-1969, December 1998.
Technology 1P3M 0.5µ [4] A. Van den Bosch, et al., “A 12 bit 200 MHz Low Glitch CMOS D/A
SFDR @ 500kHz [dB] 84 Converter”, Proc. IEEE 1998 CICC, pp. 249-252, May 1998.
[5] T. Miki et. Al., “An 80 Mhz 8 bit CMOS D/A Converter”, IEEE JSSC,
Table 4: Measured performance of the designed D/A converter. Vol. SC-21, no. 6, pp. 983-988, Dec. 1986.
[6] Carley R., Gielen G., Rutenbar C., Sansen W., “Synthesis tools for
mixed-signal ICs: progress on front-end and back-end strategies”, Proc.
DAC, pp.298-303 (1996).
[7] Chang H., “A Top-Down, Constraint-Driven Design Methodology for
Analog Integrated Circuits”, Phd dissertation Electronics Research
Laboratory, College of Engineering, UCB, CA 94720.
[8] R. Neff, “Automatic Synthesis of CMOS Digital/Analog Converters”,
PhD. Dissertation Electronics Research Laboratory, College of Engi-
neering, Berkeley University, 1995 (available on the WWW).
[9] C-H. Lin and K. Bult, “A 10b 500 MSamples/s CMOS DAC in
0.6mm2”, IEEE JSSC, vol SC-33, no. 12, pp. 1948-1958, December
Fig. 11: INL and DNL measurement results. 1998.
[10] J. Bastos, M. Steyaert, and W. Sansen, “A High Yield 12-bit 250-MS/s
VII Conclusions CMOS D/A Converter”, Proc. IEEE 1996 CICC, pp. 431-434, May
A 14-bit 150-Ms/s CMOS D/A converter has been designed using 1996.
a systematic design methodology, which implements the well [11] M.J.M. Pelgrom, et. Al., “Matching Properties of MOS Transistors”,
established performance-driven top-down design methodology. IEEE JSSC, Vol. SC-24, pp. 1433-1439, Oct. 1989.
Both commercially available and newly developed software tools [12] T. Wu et. al., “A Low Glitch 10-bit 75-Mhz CMOS video D/A Con-
support the methodology. The total design effort was reduced to verter”, IEEE JSSC, Vol. 30, no. 1, pp. 68-72, Jan. 1995.
less than one person-month accumulated effort. The correctness [13] G. Van der Plas, et al., “Mondriaan : a Tool for Automated Layout
of the approach has been proven by the fabrication and measure- Synthesis of Array-type Analog Blocks”, Proc. IEEE 1998 CICC, pp.
ment of the 14-bit D/A converter. 485-488, May 1998.
268 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007

The Analysis and Improvement of a Current-Steering

DAC’s Dynamic SFDR—II: The Output-Dependent
Delay Differences
Tao Chen, Student Member, IEEE, and Georges Gielen, Fellow, IEEE

Abstract—For a current-steering digital-to-analog converter

(DAC) without an extra output stage, the variation of the output
voltage will result in the variation of the output delay. These
output-dependent delay differences will deteriorate the spu-
rious-free dynamic range (SFDR) of a high-speed high-accuracy
DAC, especially when glitches exist. In this paper, a convenient
mathematical model is presented to analyze during design the im-
pact of this kind of delay differences on the SFDR. The results are
verified by comparison to the results of more detailed simulations.
Also the impact of glitches on this effect is demonstrated. Possible
solutions to reduce this impact are discussed and summarized.
Index Terms—Current-steering digital-to-analog converters
(DACs), glitch, output-dependent delay difference (ODDD),
output variation, spurious-free dynamic range (SFDR).

I. INTRODUCTION

H IGH-SPEED high-accuracy digital-to-analog converters

(DACs) are demanded by many communication and
signal processing applications. The spurious-free dynamic
Fig. 1. Schematic of a current-source cell.

range (SFDR) is one of the most important properties for these The variation of the output voltage of the DAC will result in
DACs. Very high linearity is required in order to achieve sat- the variation of the moment when the switches steering the cur-
isfying SFDR. For this purpose, the nonlinearities which may rent from the current sources to either of the two outputs change
impact the SFDR have to be analyzed and kept under control their status. We call this variation the ODDD in this paper. The
by the designers. physical reason of the ODDDs is as follows. Fig. 1 shows the
The current-steering DAC architecture is almost exclusively basic schematic of a current-source cell used in current-steering
used for high-speed high-accuracy DACs [1]. Two kinds of non- DACs. Normally the switch transistors work in saturation re-
linearities have been distinguished for this kind of DACs [2]. gion (when on) or cutoff region (when off). The voltage of the
One is the limited output impedance of the current sources, internal node X depends on the drain voltage of the on transistor.
which has been well analyzed and solved by taking the dif- Thus, the variation of the output voltage will cause a small vari-
ferential output [3]. The other kind is the delay-related nonlin- ation of , which will result in a change of the next switching
earities. According to the different causes of the delay differ- time.
ences, the cell-dependent delay differences (CDDDs) and the For example, assume that in the current sampling period,
output-dependent delay differences (ODDDs) are distinguished is high and is low, so the left transistor is on.
in our previous paper [2]. A mathematical method is presented Different values of will result in different values of .
in [2] to analyze the impact of the CDDDs on the SFDR of a cur- When the next sampling period comes, is getting lower
rent-steering DAC. Formulas with clear physical meaning were to turn off the left switch. The switch will not be turned off
derived, and were verified by comparing them to simulation re- until reaches the value of , where is
sults and published measurement results [4]. In this paper, the the threshold voltage of the switch transistors. On the other
method proposed in [2] is further extended to the case of the side, the right switch will not be turned on until reaches
ODDD. As in [2], formulas with clear physical meaning will be . Thus, the delay of the next sampling period will
obtained and verified by simulations, and then solutions to im- depend on the value of hence . This dependence
prove the SFDR will be discussed based on these formulas. will cause harmonic distortion on the output of the DAC and
therefore deteriorate the SFDR.
Manuscript received March 20, 2006; revised August 4, 2006. This paper was When in Fig. 1 is high, circuit analysis gives
recommended by Associate Editor T. N. Tarim.
The authors are with ESAT-MICAS, Katholieke Universiteit Leuven, Heverll
3001, Belgium (e-mail: tao.chen@ieee.org).
Digital Object Identifier 10.1109/TCSI.2006.887598
(1)

1057-7122/$25.00 © 2007 IEEE

CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II
where is the transconductance and output resistance
of the switch transistor respectively, and is the output
impedance of the cascoded current source (see Fig. 1). The
value of is normally in the order of 10 or lower for very
deep-submicrometer technologies. Assume for example the
variation of the output voltage is 0.5 V, and is 10,
then the variation of will be up to 0.05 V. If the rising
speed of the control signal is 1.25 V/ns, the 0.05 V
variation of will result in a delay difference of up to
40 ps. This is already a very large value for a 14-bit DAC with
sampling frequency higher than 100 MHz. The impact on the
dynamic properties will be investigated in detail in this paper.
In Section II, a mathematical analysis is presented to analyze
the impact of the ODDDs on the SFDR of both the single-ended
and differential outputs of a full-unary DAC. Then the behav-
ioral-level simulations (with and without glitches) are discussed
in Section III. Both the results of calculations and simulations
are compared in this section. In Section IV, the design require-
ments imposed by this nonlinearity are given, and possible solu-
tions are summarized, some of which have already been applied
in publications from different authors. Finally, Section V draws
conclusions.
II. MATHEMATICAL ANALYSIS
In the following analysis, we assume an ideal full-unary cur-
rent-steering DAC, whose only nonlinearity is the ODDDs.1 We
compare this to other effects in the conclusions.
Consider one of the current sources . Assume it is switched
on in the sampling cycle with delay . Then its output
current is
(2)
where is the sampling period, is the time constant at the
output node determined by the DAC’s load. The amplitude is
set to be one. This is a simplified expression, the internal poles
of the current cell have been omitted, but it’s sufficient to get
meaningful results.
The distortion of this current source due to the delay is thus
(3)
1For a full-binary or segmented DAC, the dynamic property should be
worse than a full-unary DAC due to the extra nonlinearity caused by the
binary-weighted current sources.
269
where Taylor series expansion has been applied. Higher order
terms are omitted, since it should always be true for a good
design that . This condition also means that, if a term
in (3) with low order contributes to harmonic distortion at some
frequency, the impact of the higher order terms in (3) on that
harmonic distortion will be very small and negligible.
A. SFDR of the DAC’s Single-Ended Output
As will be seen later, the first term of (3) will result in the
second-order distortion, the second term in (3), which only
slightly impacts the amplitude of the second-order distortion,
can be omitted
(4)
Assume the DAC’s input is a sinusoidal signal
(5)
where is the DAC’s number of bits. For convenience, the am-
plitude is set so that the amplitude of every unit current source
is 1. This will not impact the results since the SFDR is a ratio.
For a high-resolution DAC, ignoring the quantization errors,
the ideal output current (which is an integer due to the assump-
tion of (5)) of the DAC in the period from to
can be expressed as
(6)
(7)
Correspondingly, for the complementary output the current is
(8)
(9)
During this period the full-unary DAC’s total second-order
distortion in the single-ended output currents is contained in the
equation below
(10)
where (4) has been used and
when
(11)
else
is a square function.
270 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007

The results [shown in Fig. 4(d), later] show that only slightly
impacts the SFDR of a DAC without glitches.2

(12)

For the transition from the period to the period

, the output of the DAC is expressed in (6)–(7). There
are two possibilities as follows.
a) When is changing from low to high, and
is changing from high to low, the value of depends
on (note that the (6)–(7) describe the current), the de-
lays of the two switches can be expressed as

(13)

(14)
b) When , the value of depends on , the
delays of the two switches can be expressed as

(15)

(16)
For the case (a), applying (13) into (10) gives

Fig. 2. Output-dependent switching delays. (a) Different on/off delays,

(b) D= 20 a .

(17)
Fig. 2(a) shows the waveform of the control signals and
during the transition. The moment when the switches change For the case (b), applying (15) into (10) gives
their status depends on their common-source voltage, i.e., in
Fig. 1. The value of is determined by the voltage of the output
end whose switch is on. In the case of Fig. 2(a), is determined
by since is high before the transition and therefore the
corresponding switch is on. and are the minimum (18)
and maximum values of , corresponding to the minimum and
maximum values of respectively. If we select the moment With the condition of (12), (18) can be simplified into (17).
when the off switch is turned on at the maximum (that is The second term in (17) only slightly impacts the amplitude at
) to be time 0 as a reference, then, according to (1), when the signal frequency and can be omitted. Thus, the distortion can
, this delay can be expressed as where is a be expressed as
proportionality factor. For the other switch, which is turning off,
the delay is between and , where is the delay
difference between the two transitions (on to off and off to on).
can be adjusted (by the designer) by changing the crossing
point of the two control signals and . If is adjusted to
the value , there will be no delay difference between the
two transitions. This is used by some designs [5], [4] to avoid the
situation that both the switches are on or both are off, thus the
current of the current sources can be kept stable. For simplicity, (19)
we adopt this condition in our analysis as shown in (12) and
2In an actual current-source cell, the different delays between the on-to-off
Fig. 2(b), meaning that by design the switches are on/off at the
same moment and the current is constant. The impact of on
and off-to-on transitions (D 6 0d
= ) will result in the variation of the total
current, which will result in glitches and deteriorate the dynamic properties of
the SFDR will be investigated by simulations in Section III-A. the DAC.
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 271

where This is a sequence of Dirac functions at the frequencies

. What we are interested in is the component at the frequency
. Its amplitude is
(20)

The second term in the bracket of (19) only affects the dc level
and can be omitted. So (27)

where is the absolute value of the maximum delay

(21) difference.
The signal amplitude at the frequency for the single-ended
The total distortion can be obtained by summing the distor- output is calculated in [6]
tions in all the sampling periods
(28)

Combining (27) and (28), the SFDR can be obtained

(29)

where is the signal’s radial frequency, is the time constant

of the output node, and is the maximum ODDDs. Interest-
ingly, (29) shows that the SFDR due to ODDD has nothing to
do with the clock frequency.
(22) It is normally true for a current-steering DAC that
. Under this condition, (29) can be simplified into
where is the convolution operator.
Applying the Fourier transform (30)

Approximately, the SFDR will decrease with increasing signal

frequency or increasing maximum delay difference at
a slope of about dB/dec.
(23)
B. SFDR of the DAC’s Differential Output
The distortion generated by the i’th current source in the
n’th sampling cycle is expressed in (3). For the complementary
output, the delays may be different (see (13)–(16)), and the
corresponding distortion is
(24)

(31)
The impact on the differential-output SFDR of the two terms in
(3) and (31) will be analyzed separately, assuming the condition
(25) of (12).
1) Impact of the First Terms: We will firstly analyze the first
where is the clock frequency. terms of (3) and (31). They are shown below
The Fourier transform of (22) is given by

(32)

(33)
where the subscription “ ” is used to clarify that this distortion
(26)
comes from the first terms of (3) and (31).
272 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007

With the output current expressed in (6)–(9), the total distor- Adding up the distortions in all the sampling cycles, the total
tion generated by (32) and (33) during this sampling cycle is distortion caused by the first terms can be obtained as

(34)
(39)
Applying the Fourier transform to (39) gives

(35)
where is defined in (11).
The total distortion in the th sampling cycle of the differen-
(40)
tial output is then
It is clearly shown in (40) that no harmonic can be gener-
ated from the first terms of (3) and (31). That means that we
have to take the higher order harmonics (the second terms) into
consideration.
2) Impact of the Second Terms: The second terms of (3) and
(31) are

(41)

(42)
(36)
where the subscription “ ” is used to clarify that this distortion
comes from the second terms of (3) and (31).
For the case (a) defined in (13) and (14)
The current output of the DAC is expressed in (6)–(9). During
the n’th sampling cycle the DAC’s distortion generated by (41)
and (42) in both the two output currents is

(37) (43)
where the condition of (12) has been applied, and is de-
fined in (20).
With (6)–(9), (37) can be simplified into

(38)
(44)
For the case (b) defined in (15) and (16), similar calculations
give the same result as (38). So this equation describes the dis- where (41), (42) and (11) have been used.
tortion (during the n’th sampling cycle) caused by the first terms Similar to the previous analysis, there are also two cases here:
of (3) and (31) in the DAC’s differential output. (a) ; (b) .
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 273

For the case (a), applying (43), (44), and (13)–(16), the third- From (50), the distortion for all cycles can be obtained
order distortion of the differential output is

(45)

where has been defined in (20).

With further calculations, (45) can be transformed into

(51)

where is the convolution operator.

(46) Applying the Fourier transform

For the case (b), with similar calculations, the third-order dis-
tortion is

(52)

With the results of (23), (25), and (52), the Fourier transform
of (51) can be obtained
(47)
Applying (12) into (46) and (47), the same result is obtained

(48) (53)

Similar analysis as in Section II-B1) shows that the second This is a sequence of Dirac functions at the frequencies
term in the braces of (48) does not generate any harmonic dis- . What we are interested in is the component at the frequency
tortion. Only the first term needs to be considered . Its amplitude is

(54)

where is the absolute value of the maximum delay

difference.
For the differential output, the signal amplitude at the fre-
quency is twice the amplitude for the single-ended output
case [see (28)]
(49)
(55)
Again, the second term in the bracket of (49) is at the signal
frequency and can be omitted. So
With (54) and (55), the SFDR can be obtained

(50) (56)
274 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007

where is the signal’s radial frequency, is the time constant

of the output node, and is the maximum ODDDs. Equation
(56) shows that the SFDR has nothing to do with the sampling
frequency.
When the condition holds, (56) can be simpli-
fied into

(57)

To first order, the SFDR decreases with increasing signal fre-

quency at a slope of about dB/dec. The SFDR also de-
creases with increasing at a slope of about dB/dec. It
will increase with increasing time constant at a rate of about
dB/dec.
The results of (29) and (56) are shown in Fig. 4 later on.

III. SIMULATION RESULTS

A. Simple Single-Pole-Model Simulations

We will now compare the above calculation results with be-
havioral simulation results.
If we only take the dominant pole in the output node into
consideration, the output of the DAC can be simplified into a
simple single-pole model

(58)

where and are the code levels between which

the converter switches. is the delay of the transition. For the
th sampling cycle, is or respectively
for the two outputs, where is the sampling period, and
are defined in (13)–(16) which can be verified by SPICE
simulations. Thus, the ODDDs are included in the simulations.
The output waveform can be obtained by applying (58) to each
sampling cycle. Then the output is sampled to apply the FFT.
The spectra of the output signals are shown in Fig. 3. It can
clearly be seen from this figure that the second-order distor-
tion dominates for the case of the single-ended output, and the
(small) third-order distortion dominates for the case of the dif-
ferential output. This fits well with the calculation results in
Section II. Although the SFDR can be greatly improved by the
differential output, it may still be deteriorated by the ODDDs.
Fig. 4 compares the calculation results and the simulation re-
sults of the impact of the ODDDs on the SFDR for both the
single-ended output and the differential output as a function of
the parameters involved. A sampling frequency of 153 MHz
is used in our simulations. All the simulations are done under
the condition of (12), which means that there
is no delay difference between the turning on and turning off
transitions.
Fig. 4(a) is the SFDR- curves with fixed and ;
Fig. 4(b) is the SFDR- curves with fixed and ; and
Fig. 4(c) shows the SFDR- curves with fixed and . For
all the three variables and in (29) and (56), we see
that the calculation results fit pretty well with the simulation
results. Fig. 4(d) is the SFDR- curve with fixed
Fig. 3. Spectra for a DAC with ODDDs: f = 21:5 MHz, d = 20 ps,
0
D = 20 ps,  = 0:25 ns. (a) Spectrum of the single-ended output: second-
order harmonic distortion dominates. (b) Spectrum of the differential output:
third-order harmonic distortion dominates.
and . The result shows that the SFDR changes only slightly
with the variation of , which also fits the calculation results.
The results in Fig. 4 show that for the single-ended output,
ODDD can deteriorate the SFDR seriously. For the differential
output, the SFDR is also deteriorated by ODDD, although this
deterioration is rather small for a 14-bit DAC with signal fre-
quency lower than 75 MHz and maximum delay difference less
than 40 ps. However, our calculations and simulations above are
based on the simplified first-order model. No glitches are in-
cluded. Our further simulations in Section III-B will show that
ODDD make the dynamic property of DACs more sensitive to
glitches.
B. Simulations of a Model Including Glitches
In [7] the glitches of a full-binary DAC were analyzed and
shown to have a serious impact on the SFDR. For full-unary
DACs the amplitude of the glitches is proportional to the varia-
tion of the output current. As a result, glitches become a kind
of linear distortion and will not impact the SFDR. However,
glitches can impact the way that the ODDDs impact the dis-
tortion, even for a full-unary DAC. It is therefore necessary to
analyze the dynamic properties of DACs with both ODDD and
glitches. We will do the analysis by simulations in this section.
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II 275

Fig. 4. Single-pole-model simulations: the deterioration of the SFDR caused by ODDDs as a function of the different parameters. (a) SFDR versus signal fre-
quency: d 0 0
= 40 ps, D = d ;  = 0:25 ns. (b) SFDR versus maximum delay difference: f = 21:5 MHz, D = d ;  = 0:25 ns, (c) SFDR versus
output time constant: f = 21:5 MHz, d 0
= 40 ps, D = d . (d) SFDR versus on-to-off and off-to-on delay difference: f = 21:5 MHz, d = 40 ps,
 = 0:25 ns.

A behavioral model of DACs was presented in [8], where the way that ODDD impact the SFDR since the DAC’s output
the glitches are included as an exponentially damped sine and a during transition is changed by the glitches. In the model of
shifted hyperbolic tangent (59), the glitch period describes the time needed for the DAC
to transit from one output value to another; it can be extracted
from the results of SPICE simulations.
In our simulations the time-domain output of each transition
(59) is obtained by (59), after which it is sampled to do the FFT. The
sampling points are carefully selected so that one of the samples
in which is the output current, and is the amplitude is located in the middle of the transition. This is to achieve the
and period of the glitch, respectively. and are the highest accuracy, since the value in the middle of the transition
code levels between which the converter switches. is the delay is very sensitive to the delay of the transition.
of the transition. Repeating this process for each cycle, we can get the whole
Our simulations are based on this model. In our simulations, time-domain output of the DAC. A Hanning window is used be-
is set as described in Section III-A to include the ODDDs. fore the FFT analysis to reduce the time length needed while
For full-unary DACs can be set to be proportional to the maintaining enough accuracy. From the power spectrum ob-
variation of the codes, i.e., to . We define the tained, the SFDR at that signal frequency can be obtained.
proportionality factor pAgl as below The impact of the glitches is shown in Fig. 5. Fig. 5(a) shows
the impact of the glitches on the SFDR of a full-unary DAC
without ODDDs . As we expect, the glitches do
pAgl (60) not impact the SFDR for both the single-ended and differential
output.
So the glitches themselves are a kind of linear distortion and In Fig. 5(b), the curve with star markers is the case of the
will not impact the SFDR. However, the glitch will change single-ended output. The glitch has little impact on its SFDR
276 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
Fig. 5. The SFDR versus normalized glitch amplitude on a full-unary DAC:
f = 21:5 MHz, D = d 0 ; T = 0:35 ns. (a) Without ODDD: d
(both curves coincide). (b) With ODDDs: d = 40 ps.
since the ODDD itself has already deteriorated the SFDR
greatly (see Fig. 4). The curve with circle markers shows the
impact of the glitches on the SFDR of the differential output of
DACs with ODDD. The SFDR reduces quickly with increasing
amplitude (energy) of the glitches, hence illustrating the impact
of glitches.
The SFDR- and SFDR- curves with different values of
pAgl are shown in Fig. 6. In these simulations was chosen
to be 0.41 ns so that the simulated SFDR when pAgl (that
means no glitches exist in the output) is the same as the SFDR
calculated when ns. In this way the simulation re-
sults in this section can be easily compared with the results
in Sections II and III-A, where the analysis was based on the
first-order model. The latter calculation results are also drawn
in Fig. 6 for comparison reasons.
Fig. 6(a) shows the SFDR- curves with different pAgl
values. The SFDR decreases with increasing signal frequency
at a slope of about dB/dec, which is the same as the results
of the mathematical model based on the first-order model.
For the differential output, the SFDR is seriously reduced
when the amplitude of the glitches increases. The SFDR-
curves with different pAgl values are shown in Fig. 6(b). For
the single-ended output, the SFDR decreases with increasing
maximum delay differences at a slope of about dB/dec,
Fig. 6. Impact of the glitches on a full-unary DAC with ODDDs:
=0 T = 0:41 ns, D = d 0 ;  = 0:25 ns (for calculations). (a) SFDR
versus signal frequency: d = 40 ps. (b) SFDR versus maximum delay
difference: f = 75 MHz.
while for the differential output this slope is about dB/dec.
These slopes are consistent with our mathematical results ((30)
and (57)), although the mathematical calculations are based on
the simplified first-order model.
Two conclusions can be drawn from these results as follows.
• Even for DACs with glitches, the impact of ODDD on
SFDR still obeys similar rules as predicted by our math-
ematical model ((29) and (56)), i.e., the slope of the falloff
remains the same (but the magnitude is different).
• The glitches can deteriorate the impact of ODDD on the
SFDR seriously, especially in the case of the differential
output.
All these simulations in Figs. 5 and 6 are for full-unary DACs.
For segmented DACs with binary LSBs, the glitches themselves
become a kind of nonlinear distortion and the SFDR can be
expected to be even worse.
IV. APPLICATION OF THE RESULTS
In order to get some quantitative idea about the maximum
permitted , we will present some calculations with actual
values. For example, assume we want to design a 14-bit DAC
with signal frequency up to 75 MHz and SFDR higher than
dB. Assume the time constant at the
output node is ns, then with (56) the maximum
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II
Fig. 7. Transition of the control signal.
permitted is 30 ps. This is normally achievable in designs
using today’s CMOS technologies. However, if the glitches are
being taken into consideration, this requirement may become
critical. By curve-fitting the behavioral model (59) to the
SPICE-simulation results, we can get the values of and
pAgl for the behavioral model of the designed circuit. Assume
the parameters that we obtain are ns and pAgl , where
then from Fig. 6(b) we can obtain that the maximum permitted
is only 8 ps. Special design and layout measures must be
taken to ensure such small ODDDs.
Fig. 7 shows the waveform of the control signal . is
the peak-to-peak value of the control signal, is the transi-
tion time of the control signal. is the peak-to-peak value
of the internal node’s voltage (see Fig. 1). According to (1)
(61)
where is the peak-to-peak value of the output voltage.
The maximum ODDD therefore is
(62)
This points us to some solutions to improve the SFDR lim-
ited by ODDD. In (62) the factor is the switching
speed, so the first solution is to accelerate the switching speed.
The intrinsic idea of this method is to reduce in (62). This
solution is for instance used in [9] by applying a David-Goliath
latch.
The second possible solution is using a return-to-zero (RZ)
output stage as presented in [10]. With the RZ output stage,
the glitches are greatly reduced. Furthermore, folding current
sources with gain-boosting are applied in this output stage to
reduce the variation of the output voltages at the drain nodes
of the switch transistors. So in (62) is reduced. This RZ
output stage improves the dynamic property greatly, as shown
in [10] and [11]. The price is a lot of extra power consumption
by the folded current sources and a significant reduction of the
signal power due to the RZ operation.
277
The term in (62) is the gain of the switch transistors.
So another method to reduce the impact of ODDD is to increase
the gain of the switch transistors. Using cascoded switches as in
[5] helps but it will consume extra voltage and is seldom used in
today’s designs.3 Optimizing the size of the switch transistors
to increase is a better choice. For current-steering DACs,
the switches are driven by latches. Normally the slew rate of the
latches determines the transition time . As a first-order ap-
proximation, the latch can be simplified to a current source with
drive current . If the gate capacitance of the switch transistor
is , then the transition time can be expressed as
(63)
Since the switch transistors may work in both the cutoff re-
gion and the saturation region, their gate capacitance is highly
nonlinear. With a rough approximation, we assume that the ca-
pacitance is constant, and can be expressed as
(64)
and are coefficients, and are the width and
length of the switch transistor, respectively.
Expressing the small-signal parameters and with tech-
nological parameters[12]
(65)
where (the Early voltage per unit-channel length) and
are technological parameters [12]. is the drain current of the
switch transistor and it is determined by the design specifica-
tions (output swing and load resistor) and is thus unadjustable.
Applying (63) –(65) into (62) gives
(66)
According to (66), we can reduce the maximum ODDDs by
reducing the sizes of the switch transistor and increasing its gate
overdrive voltage (to reduce the value of ). For today’s de-
signs, the latter is difficult to achieve since the available voltage
is very limited. But the smallest sizes should be used for the
switches (to reduce ).
Equation (56) also shows that increasing the output time con-
stant (by increasing the load capacitance) can also reduce the
harmonic distortion caused by the ODDDs. But this reduces the
overall bandwidth.
Finally, enough attention should be paid to the control of
the glitch energy, even for DACs with their most MSBs imple-
mented in a unary way. This has been done in many published
designs. In [5] and [4], delay-controllable latches are used to re-
duce the glitches. The crossover adjustment circuit presented in
3In [5] the cascoded switches are actually used for reducing the glitches in-
stead of increasing the gain of the switches.
278 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
Fig. 8. Impact of technology scaling on DACs’ SFDR deterioration caused by
CDDD and ODDD.
[13] does the same thing automatically. The current-switching
cell used in [13] further reduces the glitches by compensating
the clock feedthrough. Low-swing buffers are used in [14] to
reduce the glitches.
V. CONCLUSION
In this paper, an important nonlinear distortion due to the
ODDDs in high-speed, high-accuracy DACs has been analyzed
and simulated. Formulas for the SFDR due to this effect have
been derived and verified with simulations for full-unary DACs
without glitches. Both the calculations and the simulations fit
very well. Our simulations also show that even for DACs in-
cluding glitches, the ODDD will impact the SFDR in a similar
way as described in our mathematical models. The formulas de-
scribe the impact on the SFDR of the output-dependent delay
variations due to the limited gain of the switch transistors, and
can be turned into a condition that has to be satisfied during the
design of high-speed, high-accuracy DACs. Some possible so-
lutions to reduce this impact have been summarized.
A mathematical method to analyse SFDR based on signal
analysis has been developed in [2] and in this paper. The steps
for the analysis are as follows.
1) Calculate the distortion in one sampling cycle.
2) With Taylor expansion, simplify the expressions for the
distortion in one sampling cycle.
3) Sum the distortion in all the sampling cycles and get the
full distortion.
4) Apply Fourier analysis to the distortion and obtain the am-
plitude of the harmonic distortions.
5) Calculate the amplitude at the signal frequency.
6) Calculate the SFDR.
Two kinds of delay-related nonlinearities, due to ODDDs and
due to CDDDs, for current-steering DACs have been discussed
with simple but accurate mathematical models and simulations
in this paper and in our previous paper [2]. The results show
that both these nonlinearities may seriously deteriorate the
dynamic SFDR of high-speed high-accuracy current-steering
DACs, even for differential outputs.
Depending on the design, either of these two delay-related
nonlinearities can be dominating. Generally, when the min-
imum width of the technology shrinks, the CDDDs reduce due
to the shrinking of the layout area, while the ODDDs increase
due to the decrease of of the switch transistors [see
(62)]. The arrows in Fig. 8 show the direction of ODDD’s and
CDDD’s change with the shrinking of technology.4 Therefore,
even though today the CDDD effect on the SFDR might still
dominate above the ODDD effect, this might change in future
technologies.
This paper, together with [2] has paved the way for the design
of DACs with higher and higher dynamic accuracy and speed.
REFERENCES
[1] Y. Cong and R. Geiger, “A 1.5-V 14-bit 100-MS/s self-calibrated
DAC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051–2060,
Dec. 2003.
[2] T. Chen and G. G. E. Gielen, “The analysis and improvement of a cur-
rent-steering DACs dynamic SFDR—I: The cell-dependent delay dif-
ferences,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp.
3–15, Jan. 2006.
[3] S. Luschas and H. S. Lee, “Output impedance requirements for DACs,”
in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’03), May 2003, pp.
I-861–I-864.
[4] G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G.
Gielen, “A 14-bit intrinsic accuracy Q random walk CMOS DAC,”
IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708–1718, Dec. 1999.
[5] J. Bastos, A. Marques, M. Steyaert, and W. Sansen, “A 12-bit intrinsic
accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol.
33, no. 12, pp. 1959–1969, 1998.
[6] T. Chen and G. Gielen, “Analysis of the dynamic SFDR property of
high-accuracy current-steering D/A converters,” in Proc. IEEE Int.
Symp. Circuits Syst. (ISCAS’03), May 2003, pp. I-973–I-976.
[7] J. Bastos, “Characterization of MOS transistor mismatch for analog
design,” Ph.D. dissertation, ESAT-MICAS, Katholieke Univ. Leuven,
Leuven, Belgium, 1998.
[8] J. Vandenbussche, G. Van Der Plas, G. Gielen, and W. Sansen, “Be-
havioral model of reusable D/A converters,” IEEE Trans. Circuits Syst.
II, Analog Digit. Signal Process., vol. 46, no. 10, pp. 1323–1326, Oct.
1999.
[9] J. Deveugele and M. Steyaert, “A 10 b 250 MS/s binary-weighted cur-
rent-steering DAC,” in Dig. Tech. Papers IEEE Inst. Solid-State Cir-
cuits Conf. (ISSCC’04), Feb. 2004, pp. 362–363.
[10] A. R. Bugeja and B. Song, “A self-trimming 14-b 100-MS/s CMOS
DAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841–1852,
2000.
[11] Q. Huang, P. A. Francese, C. Martelli, and J. Nielsen, “A 200 MS/s 14 b
97 mW DAC in 0.18/spl mu/m CMOS,” in Dig. Tech. Papers IEEE Inst.
Solid-State Circuits Conf. (ISSCC’04), Feb. 2004, no. 2, pp. 364–532.
[12] K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits
and Systems. New York: McGraw-Hill , 1994.
[13] B. Schafferer and R. Adams, “A 3 V CMOS 400 mW 14 b 1.4 GS/s
DAC for multi-carrier applications,” in Dig. Tech. Papers IEEE Inst.
Solid-State Circuits Conf. (ISSCC’04), Feb. 2004, no. 2, pp. 360–532.
[14] K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. van Roermund,
“A 12 b 500 MS/s DAC with >70 dB SFDR up to 120 MHz in 0.18-
m CMOS,” in Dig. Tech. Papers IEEE Inst. Solid-State Circuits Conf.
(ISSCC’05), 2005, vol. 1, pp. 116–588.
4The data come from designs with 0.5- and 0.13-m technologies, respec-
tively. The actual values heavily depend on the design (circuits and layout).
CHEN AND GIELEN: ANALYSIS AND IMPROVEMENT OF CURRENT-STEERING DAC’S DYNAMIC SFDR—II
Tao Chen (S’02–M’07) was born in Zhangping City,
Fujian Province, China, in 1974. He received the
B.Sc. degree in electronic engineering from Zhejiang
University, Hangzhou, China, the M.Sc. degree in
electronic engineering from Tsinghua University,
Beijing, China, and the Ph.D. degree in electronic
engineering from Katholieke University Leuven,
Belgium, in 1996, 1999, and 2006, respectively.
From 1999 to 2000, he was an ASIC Engineer at
Huawei High-Tech Incorporated, Beijing, and then a
Chip Design Engineer at Capella Microsystem Inco-
poration, Beijing. Currently, he is with Mindspeed Technologies, Inc, Newport
Beach, CA. His research interests are in the area of analog/mixed-signal inte-
grated circuits design and computer-aided design tools.
279
Georges G. E. Gielen (S’87–M’92–SM’99–F’02)
received the M.Sc. and Ph.D. degrees in electrical en-
gineering from the Katholieke Universiteit Leuven,
Leuven, Belgium, in 1986 and 1990, respectively.
In 1990, he was appointed as a Postdoctoral Re-
search Assistant and Visiting Lecturer in the Depart-
ment of Electrical Engineering and Computer Sci-
ence, University of California, Berkeley. From 1991
to 1993, he was a Postdoctoral Research Assistant
of the Belgian National Fund of Scientific Research,
ESAT Laboratory, Katholieke Universiteit Leuven. In
1993, he was appointed as a tenure Research Associate of the Belgian National
Fund of Scientific Research and also an Assistant Professor at the Katholieke
Universiteit Leuven. In 1995, he was promoted to Associate Professor at the
same university, where he is now a full-time Professor. His research interests
are in the design of analog and mixed-signal integrated circuits, and especially
in analog and mixed-signal computer-aided design tools and design automation
(modeling, simulation and symbolic analysis, analog synthesis, analog layout
generation, analog and mixed-signal testing). He is coordinator or partner of
several (industrial) research projects in this area. He has authored or coauthored
one book and more than 250 papers in edited books, international journals, and
conference proceedings.
Dr. Gielen served as the 2005 President of the IEEE Circuits and Systems
(CAS) Society. He was an Associate Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, and
later of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: ANALOG AND
DIGITAL SIGNAL PROCESSING. He is also a member of the Program Commit-
tees of international conferences (ICCAD, DATE, ISCAS). He received the Best
Paper Award of the Wiley International Journal on Circuit Theory and Appli-
cations in 1995. He was the 1997 Laureate of the Belgian National Academy of
Sciences, Literature and Arts. He received the 2000 Alcatel Award of the Na-
tional Fund of Scientific Research for innovations in telecom research, and the
2004 Best Paper Award at the DATE conference.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006 3

The Analysis and Improvement of a Current-Steering

DACs Dynamic SFDR—I: The Cell-Dependent
Delay Differences
Tao Chen, Student Member, IEEE, and Georges G. E. Gielen, Fellow, IEEE

Abstract—For a high-accuracy current-steering digital-to-

analog converters (DACs), the delay differences between the cur-
rent sources is one of the major reasons that cause bad dynamic
performance. In this paper, a mathematical model describing the
impact of the delay differences on the DACs SFDR property is pre-
sented. The results are verified by comparison to behavioral-level
simulations and to actual measurement data from published
papers. Based on this analysis, the delay differences cancellation
(DDC) technique to reduce the impact of the delay differences on
the SFDR property is proposed and verified by simulation results.
Index Terms—Current-steering digital-to-analog converters
(DACs), delay differences cancellation (DDC), delay differ-
ence, delay distribution, spurious-free dynamic range (SFDR),
switch-and-latch cell, switching sequence.
Fig. 1. Schematic of a current cell and the floorplan of the layout.

I. INTRODUCTION When the accuracy of a current-steering DAC increases, the

F OR TODAY’S digital-to-analog converters (DACs), higher
and higher accuracy and speed are required. Such DACs
are typically implemented as current-steering DACs. For a DAC
with an accuracy higher than 12 bits, its spurious-free dynamic
range (SFDR) property has become one of the major limiting
factors for its performance [1]–[5]. There are quite a lot of non-
ideal factors which will impact the DACs SFDR property. Some
work has been done to explore the physical reasons of the dete-
rioration of the SFDR. In [6] and [7], the impact of the current
sources’ limited output impedance for current-steering DACs is
analyzed. As a conclusion, this limited output impedance will
deteriorate the SFDR for high-accuracy high-speed DACs, es-
pecially when the single-ended output is used [7]. This conclu-
sion can be verified by the model provided in [8].
The delay-related nonlinearities are another kind of main con-
tributors to the bad dynamic property. Our previous paper [9]
proposes a method for analyzing this kind of nonlinearities. The
results of the analysis show that the delay-related nonlinearities
can indeed limit the dynamic performance of a high-accuracy
high-speed DAC if one does not apply any special techniques to
solve this problem.
Based on their different causes, two kinds of delay differences
in a high-accuracy current-steering DAC can be distinguished.
One is the cell-dependent delay differences, and the other is the
output-dependent delay differences.
Manuscript received December 14, 2004; revised April 18, 2005. This paper
was recommended by Associate Editor J. Silva-Martinez.
The authors are with ESAT-MICAS, Katholieke Universiteit Leuven, Hev-
erlee 3001, Belgium (e-mail: tao.chen@esat.kuleuven.be)
Digital Object Identifier 10.1109/TCSI.2005.854409
number of current cells1 increases, and it will be more and more
difficult to let all these current sources have the same delay from
the clock pad or to the output pad under the condition of keeping
a reasonable layout aspect ratio. Fig. 1 shows the floorplan of the
DAC and the schematic of a current cell. All the switch-and-
latch cells are connected to the same output pad and the same
clock pad. The delays from the clock pad to the switch-and-latch
cells, or the delays from the switch-and-latch cells to the output
pad, are determined by the length of the connection wire, as
shown in the two circles in Fig. 1, and has nothing to do with
the output value. We call this kind of delays the cell-dependent
delays. Due to the different positions of the switch-and-latch
cells (not the current-source cells) on the layout, the delays are
different from cell to cell. For a DAC with a number of bits
higher than 14, the delay differences may be as high as dozens of
picoseconds in today’s mainstream CMOS technologies. This is
the physical reason for the cell-dependent delay differences.
Besides the cell-dependent delays, another kind of the delay
differences is the output-dependent delay differences, whose
delay values will depend on the output value, instead of the
physical position of the current cells. The basic schematic of
a current source used in the current-steering DACs is shown in
Fig. 2(a). (Note that the current source or the switch transistor
could also be cascoded.) Normally the switch transistors work
in saturation region (when on) or cutoff region (when off). The
voltage of the internal node X will change when changing the
drain voltage of the on transistor because of the limited output
1From now on, the phrase “current cell” means the whole unit cell of the
DAC, i.e., the current source together with the switches and latches. The phrase
“current-source cell” only means the current source transistor, and “switch-and-
latch cell” means the switches and latches. See Fig. 1.

1057-7122/$20.00 © 2006 IEEE

4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
Fig. 2. Voltage variation of the internal node. (a) Schematics. (b) Small-signal
equivalent circuit.
impedance of the switch transistor. Thus, the variation of the
output voltage will cause a small variation of , which will
result in a change of the next switching time. Fig. 2(b) shows
the small-signal equivalent circuit. The transistor which is off is
omitted. When the output impedance of the (cascoded) current
source is very large, with KCL the equation below can be
obtained
(1)
where and are the transconductance and the output
impedance of the switch transistor respectively. This is the
physical reason of the output-dependent delay differences.
As the first part (part I) of our study, this paper will only
focus on the analysis and improvement of the cell-dependent
delay differences. However, our calculations show that the same
method can also be applied to the analysis of the output-depen-
dent delay differences to get meaningful results. The analysis
and improvement of the output-dependent delay differences will
be proposed in the part II of this paper.
This paper is organized as follows. In Section II, the method
used in [9] is explained in full detail to analyze the impact of
the delay differences in the clock net on the SFDR of the DAC.
Formulas with clear physical meaning are derived, and are com-
pared to the measurement results from a published paper [1].
Next, this method is extended in Section III to analyze the delay
differences in the output net. The impact of the return-to-zero
(RZ) output stage on the cell-dependent delay differences will
then be analyzed in Section IV. The intrinsic advantage of the
RZ stage in reducing the impact of the delay differences on the
SFDR can be observed from the results of the analysis. In Sec-
tion V behavioral-level simulations are presented and the results
are compared to the results of the mathematical model. Sec-
tion VI proposes the delay-difference-cancellation (DDC) tech-
nique to overcome the cell-dependent delay differences. Our
simulations show that the cell-dependent delay differences will
not impact the SFDR any more with this technique. The DDC
technique paves the way to the design of current-steering DACs
with high dynamic accuracy ( bits). Finally, Section VII
summarizes the paper and draws conclusions.
II. DELAY DIFFERENCES ON THE CLOCK NET AND ITS
MATHEMATICAL ANALYSIS
For the cell-dependent delays, the delay values are deter-
mined by the position of the current cell on the layout, while
the delays in both the two differential output ends are the same.
This means that taking the differential output will not reduce
the nonlinearity caused by this kind of delay differences, and
the second-order harmonic distortion is the dominant distortion
which will determine the SFDR deterioration. In this section,
the second-order distortion of a DACs single-ended output will
first be calculated. Then we will calculate the amplitude of
the signal frequency. From these results, the expression of the
SFDR can be obtained.
A. Second-Order Distortion Caused by the Delay Differences
on the Clock Net
For a current-steering DAC without RZ output stage,2 the
output of the current sources are added directly to the output
current of the DAC; the delay differences among these current
sources will reflect on the output current directly.
Consider one of the current sources with clock delay .
Assume it is switched on in the th sampling cycle. Then its
output current is
(2)
where is the sampling period, is the time constant decided
by the DACs load. The amplitude is set to be one. This is a
simplified expression, the internal poles of the current cell have
been omitted. But this is sufficient to get meaningful results.
The distortion of this current source is thus
(3)
Assume the DACs input is a sinusoidal signal
(4)
where is the DACs number of bits. The amplitude is set so
that the amplitude of every unit current source is 1.
2Current-steering DACs with RZ output stage will be analyzed later in Sec-
tion IV.
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 5

Fig. 3. DACs output signal without RZ output stage.

For a high-resolution DAC, ignoring the discrete nature of the cells are switched on in the same order as their delay increases
output signal, the ideal output of the DAC in the period from (referred to as linear switching sequence or LSS assumption).
to can be expressed as The LDDV assumption does not exist in a real DAC, but as will
be seen in Section V, it has little impact on the result, so it is
(5) justifiable to adopt this assumption to simplify the derivation.
(6) What will impact the SFDR is actually the distribution of
the delay values rather than the values themselves. The delay
During this period the DACs total distortion is distribution is determined by the switching sequence of the
switch-and-latch cells3 when the input code step by step changes
from the minimum value to the maximum value. Here, the LSS
assumption is one of the possible cases in a real DAC and it
leads to an interpretable analytic result. For the cell-dependent
(7) delays, when the positions of the switch-and-latch cells in the
switch-and-latch block are decided, the delay values for the
corresponding current cells are fixed, but the designer can still
where (3) has been used, and
decide the delay distribution freely by arranging the actual
when switching sequence of the switch-and-latch cells. We will see
(8)
else later from the simulation results in Section VI that the LSS
case is one of the worst delay distributions.4 However, through
is a square function.
the analysis of this worst case, we will obtain the optimized
In order to simplify the calculations, only linearly-distributed
delay distribution and the corresponding optimized switching
delays are considered for now. That is
sequence of the switch-and-latch cells.
(9)
3Note that the switching sequence of the switch-and-latch cells can be

where is a constant. Two assumptions are contained in this
approximation. First, the delay values are integer times of .
(We will refer to this condition as linearly distributed delay
values or simply LDDV assumption later.) Second, the current
different from the switching sequence of the current source cells.
4Actually, what we simulated and optimized in Sections V and VI is
the distribution of the delays in the output net. But we will see later that
the delay differences in both the clock net and the output net impact the
SFDR in a similar way [see (23) and (46)].
6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

Using (9) into (7), with a little calculation we can get the result For the high-accuracy DACs of nowadays, it normally holds that
for the DACs total distortion in the th time window

(19)

(10) It meas that, the output settles well at the end of each sampling
cycle.
Define the function as Thus, (18) can be simplified into

(11) (20)

As will be seen later, determines the amplitudes of the With (16), (17), and (20), the Fourier transform of can
distortion components at different frequencies. Then (10) can be obtained
be simplified to

(12)

With (5) and (6), we can get

(21)

This is a sequence of Dirac functions at the frequencies

. What we are interested in is the component at frequency
(13) , its amplitude is
Thus the DACs overall distortion is
(22)

Using (20), we get

(23)

(14) where is the maximum delay difference of the cur-

rent cells. We see from this result that the second-order distor-
tion is proportional to both the maximum delay difference
where “ ” is the convolution operator. and the sampling frequency , and that there is a peak when
Since the distortion is very small compared to the signal am- the signal frequency is near . is the time constant of
plitude for high-resolution converters, the distortion at the signal the output node. We see from (23) that a bigger results in a
frequency can be neglected. Thus, only the second-order distor- smaller second-order distortion.
tion must be considered5:
B. Signal Amplitude and the SFDR of a DAC Without RZ
Output Stage
In order to get the SFDR, the signal amplitude at has to
(15) be calculated. For a DAC without RZ output stage, its output
signal is shown in Fig. 3, where is the sampling cycle, and
Applying the Fourier transform are the DACs output values at time and ,
respectively, as defined in (5) and (6). is the DACs output
signal. It can easily be decomposed into two parts: (the
(16)
right bottom curve) and (the left bottom curve) , that is

(24)
(17)
Then we can get by calculating and , respec-
tively.
Define the function as
(18)
5Results later on confirm that the second-order distortion is the dominating
(25)
contribution if the signal frequency is not too high.
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I 7

where the square function is defined in (8). Then Observing (27) and (30), the relation holds
can be expressed as (ignoring the discrete nature of the output
signal) (34)

Using this equation into (33) gives

(26)

Under the condition of (19), we get the Fourier transform of (35)

as
With some calculations, (35) can be simplified into

(36)
(27)
Thus, we have obtained the amplitude of the signal frequency.
With (16), and (27), s Fourier transform is obtained Combining (23) and (36), the SFDR of a current-steering
DAC without RZ output stage due to cell-dependent delay dif-
ferences caused by the clock net of the latches can be obtained
as (assuming that the second-order distortion is dominant)

(37)
(28)

Now we calculate the Fourier transform of . It can be where is the maximum delay difference of the
expressed as current cells. We see from this expression that the SFDR will
increase with decreasing delay differences ( ) of the current
cells. This is consistent with our intuition. The most interesting
thing about this result is the dependency of the SFDR on the
signal frequency and the sampling frequency. Fig. 4(a) shows
(29) the SFDR- curve, where the signal frequency
has been normalized to the sampling frequency .
Applying the Fourier transform When the signal frequency increases from zero up to , the
SFDR will first decrease and then increase. When ,
the SFDR reaches its lowest value. This result will be verified
with more detailed simulation results later in Section V.
(30) The SFDR- curve is shown in Fig. 4(b), where the sam-
With the above equations, together with (16), we get the Fourier pling frequency has been normalized to the signal frequency
transform of as . We conclude from this figure that, when the signal fre-
quency is a constant, we can improve the SFDR by decreasing
the sampling frequency. This is reasonable because, when the
sampling frequency increases, the distortion in every sampling
cycle appears with a higher frequency, thus deteriorating the
DACs SFDR property. When the sampling frequency becomes
(31)
even higher, the amplitude of the distortion in every sampling
cycle is reduced, the total distortion will not increase much,
From (24), (28), and (31), the Fourier transform of can
thus, the SFDR will approach a constant value, as shown in the
be obtained
figure.
(32) When the signal frequency is so low that , (37) can
be simplified into
The amplitude of the component at the signal frequency
is (38)

This result shows that the SFDR will decrease with increasing
signal frequency at a rate of about dB when the signal
(33) frequency is low. This is consistent with [1]’s measurement (see
8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

delay values extracted from the layout obtain a result very close
to this number. The reason will be analyzed in that section. Ob-
viously, the cell-dependent delay difference may indeed deteri-
orate the DACs SFDR property seriously.

III. DELAY DIFFERENCES ON THE OUTPUT NET AND ITS

MATHEMATICAL ANALYSIS
Now consider the second source of possible delay differences
in a current-steering DAC, i.e., when the delays from the output
of the switches to the DACs output pad are different (see Fig. 1).
This difference can be described as a different time constant in
(2). The distortion of the th current source in the th sampling
cycle is

(40)
where is the variation of the time constant , and is much
less than itself, say, . With this condition, (40) can be
simplified into

(41)
Since

we have
Fig. 4. Equation (37): the dependence of the SFDR on the signal frequency
and the sampling frequency due to the delay differences on the clock net for a
NRZ DAC. (a) SFDR-f curve. (b) SFDR-f curve.
So, (41) can be further simplified into
[1, Fig. 16]). Another conclusion which can be drawn from (38)
is that, when the signal frequency is low enough, the DACs
SFDR property will have nothing to do with the sampling fre- (42)
quency. In [1, Fig. 18], we can see that the DACs SFDR property
is nearly constant provided that the sampling frequency is lower As in Section II-A, the total distortion in the th sampling
than 150 MHz. (If the sampling frequency becomes higher, the cycle is
DAC will not be able to achieve 14 bits accuracy, thus the SFDR
will decrease.) This result also verifies our analytic result.
With (38) we can estimate the maximum signal frequency a
DAC can achieve under a given maximum delay difference. For
an N-bit DAC, the SFDR it should achieve is at least (43)
dB [10]. So the relation below should be satisfied
where and are defined in (5) and (6), and the function
is defined in (8).
Again, we assume the variation of the time constant, , to be
(39)
linearly distributed
For example, for a 14-bit DAC, when ps (extracted
from the layout of a real DAC [1]), the maximum frequency it (44)
can achieve is only 1.39 MHz, even when all other nonlinearities
are omitted. Of course, this result is based on the simplification where is a constant. The LDDV and LSS assumptions are in-
of (9). However, our simulations in Section V with the actual cluded in this equation just as in (9). Their impact on the results
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I
Fig. 5. Equation (46): the dependence of the SFDR on the signal frequency
and the sampling frequency due to the delay differences on the output net for a
NRZ DAC. (a) SFDR-f curve. (b) SFDR-f curve.
is also similar to the case of the delay differences in the clock
net, which has been discussed when we introduce (9).
With similar calculations as in Section II-A, we can get the
amplitude of the second-order distortion as
(45)
Combining (36) and (45), the SFDR of a DAC without output
stage due to output time constant differences is obtained as
(46)
where is the maximum time constant variation. This re-
sult is shown in Fig. 5. It is very similar to (37)’s result (see
Fig. 4), i.e., the impact of the output time constant variation on
the SFDR is similar to that of the clock delay difference. That
means that the output time constant variation will impact the
SFDR in the same way as the clock delay difference does. Thus,
9
Fig. 6. RZ DACs output signal. (a) The simplified output signal f (t). (b)
The actual output signal f (t).
when designing the layout of the switch-and-latch block, it is
possible to let both delay differences cancel each other and thus
reduce the whole delay variation.
IV. IMPACT OF RZ OUTPUT STAGE ON DELAY DIFFERENCES
In [2] and [3], an RZ output stage was used to enhance the
SFDR property by setting the output to a fixed value (ac ground)
at the start of any transition. With this architecture, the output
signal is divided into two phases in every clock cycle: the track
phase and the attenuate phase. The output tracks the DAC output
only during the track phase, and it is attenuated to a very low
fixed value during the attenuate phase [2]. When the signal fre-
quency increases, the SFDR property of such a DAC will de-
crease with a much slower rate compared to DACs without RZ
output stage. In this section, a simplified ideal RZ output stage
with attenuation time assumed to approach zero as shown in
Fig. 6(a) will be analyzed as a worst-case situation to a real RZ
DAC. The impact of the cell-dependent delay differences on the
SFDR of such a DAC will be obtained. Since the delay differ-
ences on the clock net and the output net impact the SFDR in a
similar way, only the delay differences on the clock net are an-
alyzed in this section.
Fig. 6(a) shows the simplified output signal of an RZ DAC. In
this figure, the curve is the output of the RZ DAC. For com-
parison, a normal (without RZ output stage) DACs output signal
is also shown. Both the signal amplitude at frequency
10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

and the amplitude of the second-order distortion have to be re-

calculated in order to get the SFDR. The curve in Fig. 6(b)
shows the output of an actual RZ DAC with nonzero attenuation
time. We will discuss the impact of the attenuation time on the
SFDR later.
Using the function defined in (25), we can express
as

(47)
With calculations similar to Section II-B, the amplitude of the
component at frequency can be obtained as

(48)

where

(49)
The second-order distortion of such a DAC has to be recalcu-
lated too. Instead of (7), the total distortion of the th cycle is
now

(50)

where is defined in (11).

With calculations similar to Section II-A, we can get the am-
plitude of the second-order distortion as
(51)
As we now have the signal amplitude [(48)] and the amplitude
of the second-order distortion [(51)], the DACs SFDR can be
obtained as
(52)
where is the maximum delay difference. Again,
the SFDR property of such a DAC will increase with decreasing
delay differences of the current cells. But the frequency
dependence is different from that of a DAC without RZ output
stage. The SFDR- curve is shown in Fig. 7(a). We see that
the SFDR will decrease with increasing signal frequency with
a small slope. This is consistent with the measurement results
in [2], [3], and [5]. Fig. 7(b) shows the SFDR- curve re-
sulting from (52). We see from this figure that the SFDR also
decreases with increasing sampling frequency, but the reduction
happens slower than in the case without the RZ output stage [see
Fig. 4(b)].
For the RZ output stages with nonzero attenuation time [see
the curve in Fig. 6(b)], if ignoring the settling error at the
Fig. 7. Equation (52): the dependence of the SFDR on the signal frequency
and the sampling frequency due to the delay differences on the clock net for a
RZ DAC. (a) SFDR-f curve. (b) SFDR-f curve.
end of the last track phase, the DACs output during the attenu-
ation phase will not be impacted by the delay differences. The
nonlinear distortion only exist in the track phase. According to
(3), the nonlinear distortion decreases exponentially when re-
ducing the time of the track phase. Meanwhile, the signal energy
reduces linearly when reducing the time of the track phase. As
a result, for an actual RZ output stage whose attenuation time is
larger than zero, if the only nonlinearity that is taken into consid-
eration is the cell-dependent delay differences, the SFDR should
even be better than what we have obtained in (52).
When the signal frequency is so low that , (52) can
be further simplified into
(53)
This result shows that when the signal frequency is low, the RZ
DACs SFDR property will depend on the sampling frequency,
instead of the signal frequency. This property is different from
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I
Fig. 8. Layout of the switch-and-latch block from [1].
that of a DAC without output stage [see (38)], the SFDR of
which depends on the signal frequency instead of the sampling
frequency.
V. SIMULATION VERIFICATION OF MATHEMATICAL MODEL
According to the previous analysis, the delay differences on
both the clock net and the output net will impact the SFDR in a
similar way. Therefore, in our simulations we only consider the
delay differences on the output net.
Fig. 8 shows the layout of the switch-and-latch block as ex-
tracted from a real DAC [1], which is used as illustrative ex-
ample here. The clock net is not shown for simplification. We
will simulate the behavior of every current cell, and then get the
behavior of the whole DAC by adding up the current of all the
current cells. In this figure, unit 183 is taken as an example. The
resistances and the capacitors are the extracted parasitic resis-
tances and capacitors of the actual wires on the layout. For the
switch-and-latch cells in different positions, these parameters
have different values, and will result in the delay differences on
the output net.
The corresponding extracted circuits are shown in Fig. 9. As
shown in Fig. 8, , are the parasitic parameters of the main
wire on the left side of unit 183. and are on the right side.
, are the parasitic parameters of all the branch wires on
the left side of the branch wire where unit 183 is located, and
, are those on the right side. The parasitic parameters on
the branch wire where unit 183 is located are divided into two
parts. , are on the bottom side, and , are on the top
side. Replacing unit 183 with a current source, we obtain the
equivalent circuit of Fig. 9. In order to simplify the simulation,
the , subcircuit and the , subcircuit are placed in
the middle of the , subcircuit and the , subcircuit
respectively. and are the load of the DAC. The point A
is where the switch-and-latch cell is connected to the output net.
The current source describes the switching behavior of the
current source. Ignoring the internal poles, can be thought
as an ideal step function when the current cell is switched on.
The values of the resistances and the capacitances can be ex-
tracted from the layout. With this circuit model, we can calcu-
late the output current caused by every current cell. When the
clock transition happens, the output current of the DAC can be
11
Fig. 9. Extracted circuit for calculating the delays.
Fig. 10. Flowchart of the SFDR simulation method.
obtained by adding up the output currents of all the current cells
which are turned on. Applying the same calculations to each
sampling cycle, the total output signal can be obtained. Then
the FFT analysis is applied to obtain the SFDR. The flowchart
of the simulation method is shown in Fig. 10.
Fig. 11 shows the results of the simulations. For compar-
ison, the calculation results of (46) are also shown as the thick
curve without markers. The curve with the circle markers shows
the simulation results. We see that both curves agree with each
other well when the signal frequency is not so high. But when
the signal frequency is higher than 72 MHz in the example of
Fig. 11, the results of the calculation and simulation are be-
coming different: the simulated SFDR curve even flattens off.
This is because at those frequencies the higher-order distortion
dominates and makes the SFDR lower than the case when only
the second-order distortion is considered, while in our mathe-
matical model only the second-order distortion is taken into con-
sideration. If we only consider the second-order distortion in the
simulation, we will get the curve with triangle markers. It fits the
calculation results much better at higher frequencies, and it also
matches the total SFDR curve at lower frequencies, indicating
that at lower frequencies indeed the second-order component
dominates.
Our mathematical model is based on the very simplified as-
sumptions [see (9) and (44)] and these assumptions do not exist
12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
Fig. 11. Comparison of SFDR calculation and simulation results for a DAC
without output stage [1].
in real DACs. The reason why the simulation results fit the cal-
culation result is that, in the chip [1] we used, the current cells
are switched on nearly in the same order as their delays decrease
[Fig. 13(a)], i.e., it approximately fits the LSS assumption de-
fined in Section II-A. In such a case, the peak of the nonlinear
distortion caused by the different delays appears twice in one
sinusoidal cycle, and results in big second-order distortion, thus
deteriorating the SFDR.
We will show in Section VI by simulations that the delay dis-
tribution (physically the switching sequence of the switch-and-
latch cells) greatly affects the DACs SFDR property assuming
that the delay difference values are fixed. Since it is hard for
a high-accuracy DAC to reduce the delay differences of all the
current cells through proper design and layout, finding a best
delay distribution becomes a promising way to solve the SFDR
problem.
VI. DDC TECHNIQUE
As aforementioned, we can reduce the delay differences by
making the delay differences on the clock net and those on the
output net cancel with each other, as shown in Fig. 12(a). But
the length differences in the clock net and in the output net will
not result in exactly the same delay differences, therefore this
method cannot solve the problem completely. Another possible
solution is to use a tree-like connection for both the clock net
and the output net as shown in Fig. 12(b). This method will
inevitably increase the area and slow down the sampling fre-
quency, and for high-accuracy DACs, the tree-like buses will
make it difficult to get a reasonable aspect ratio.
The methods mentioned above work by reducing the values
of the delay differences. In this section, we will present another
method which will not change the delay difference values of the
current cells. Instead, we will reduce the impact of the cell-de-
pendent delay differences on the SFDR directly by properly
choosing the switching sequence of the switch-and-latch cells.
In this way, what is changed is the delay distribution instead of
the values of the delay differences. It is to some degree similar
Fig. 12. Reduction of the cell-dependent delay differences. (a) Delay
cancellation between the clock net and the output net. (b) Tree-like clock net
and output net.
to what has been done to the current source cells in order to
achieve good INL static property in [1] and [11]. Fig. 1 shows
the floorplan of a typical high-accuracy current-steering DAC.
The connections between the thermodecoder block and the
switch-and-latch block (connections 1 in the figure), together
with the connections between the switch-and-latch block and
the current source block (connections 2), provide enough
freedom to the designers for realizing in the same chip both
the optimum switching sequence in the current-source block
for good static INL performance and the optimum switching
sequence in the switch-and-latch block for good dynamic
SFDR performance.
If we only take the distortion caused by the delay differences
into consideration, two conclusions are justifiable based on the
above analysis and simulations. First, to first-order approxima-
tion, the total distortion is the sum of all the distortions in every
sampling cycle; in each cycle, the distortion is the sum of the
distortions of every current cell that is switched on; and the dis-
tortion of a current cell in a sampling cycle is linearly propor-
tional to the delay difference value of the current cell [see (3)
and (42)]. Second, the second-order distortion dominates when
the signal frequency is not too high. Correspondingly, there are
two solutions to improve the SFDR property: to reduce the am-
plitude of the distortion in each sampling cycle, or to reduce the
energy of the second-order distortion. Thus, we get two rules
(we call them “the DDC rules”) for arranging the switching se-
quence of the switch-and-latch cells
1) The amplitude of the distortion in every sampling cycle
should be reduced to as low as possible. That means that
the current cells with big delay values should neighbor
the current cells with small delay values in the switching
sequence.
CHEN AND GIELEN: CURRENT-STEERING DACs DYNAMIC SFDR I
TABLE I
POSITIONS OF SWITCH-AND-LATCH CELLS IN BLOCK
2) The distortion should appear with high frequency. That
means that the current cells with big delay variations
should be distributed as uniformly as possible. Thus, the
energy of the lower-order distortion can be reduced.
Below we will illustrate these rules by an example.
The layout of the switch-and-latch block extracted from a real
DAC [1] is shown in Fig. 8. The clock network in this chip is a
tree-like net, the delay differences are very small compared to
those caused by the output net, so it is not shown for reasons
of simplification. The positions of the switch-and-latch cells
in the matrix decide the actual delay values and are shown in
Table I, where the numbers designate the switching sequence of
the cells as used in [1]. (We will refer to it as “cell number” in
this paper.) When the DAC is working, the unary current cells
will turn on according to the order of the “cell number.” The
position of a number in the table designates its position in the
switch-and-latch block. The number “0” means that the position
is vacant. The delay values of each current cell can be calculated
by the model presented in Section V. The normalized delay dis-
tribution is shown in Fig. 13(a). Obviously, they don not satisfy
the assumptions of (9) and (44).
We see from Fig. 13(a) that in this chip the current cells
with smaller cell numbers have greater delays. As a result, for
a full-scale sinusoidal input signal, the distortion will have two
peaks in every signal cycle, i.e., , the DAC will have a very big
second-order distortion, and such a second-order distortion will
determine the DACs SFDR property when the signal frequency
is not too high (see Fig. 11). This conclusion is consistent with
the previous analysis.
We can change the switching sequence by rearranging the po-
sitions of the switch-and-latch cells. Table II shows one possible
rearrangement. The cells with consecutive cell numbers are put
13
Fig. 13. Normalized delay distributions of the switch-and-latch cells from [1].
(a) Original distribution. (b) After the sequence rearrangement.
in the opposite place vertically to satisfy DDC rule 1. According
to DDC rule 2, the cell numbers are uniformly distributed in the
whole table. The corresponding delay distribution is shown in
Fig. 13(b). The current cells with big delay deviation have been
uniformly distributed among all the cell numbers, and every big
delay cell is always neighbored by two cells with small delay
values. So the DDC rules are satisfied by this arrangement.
Performing behavioral-level simulations as before on the
“new” DAC, the SFDR results obtained are shown in Fig. 14,
where the curve with circle markers is the case with the opti-
mized switching sequence while still having the same delay
values from the original layout [1]; the curve with right-pointing
triangle markers shows the ideal case when there is no delay
difference; the curve with upward-pointing triangle markers
is the original case [1] before optimization; and the curves
with asterisk markers are cases when uniformly distributed
random switching sequences are applied. We see from these
results that the rearrangement of the delay values can improve
the DACs SFDR property significantly to a level that is very
14 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006
TABLE II
OPTIMIZED POSITIONS OF SWITCH-AND-LATCH CELLS IN BLOCK
near to the ideal case without delay differences. Even the
SFDR at high signal frequencies where the dominant harmonic
distortion is higher than the second order is improved. This
is because at these high signal frequencies the dominant har-
monic distortion, though higher than the second order, is still
a relatively low-order distortion (for example, the third-order),
which is also reduced by the DDC technique together with the
second-order distortion6.
Under the condition of satisfying the DDC rules, i.e., a delay
distribution similar to what is shown in Fig. 13(b), there may
be lots of switching sequences of the switch-and-cell cells. Our
simulations show that SFDR values very close to the ideal case
with no delay differences can be obtained for all these switching
sequences that satisfy the DDC rules. These results mean that
with a DDC switching sequence the delay differences will have
very little impact on the DACs SFDR property.
VII. CONCLUSION
Driven by signal processing and telecommunication applica-
tions, DACs with higher and higher accuracy and speed are re-
quired. As the accuracy and speed increase, some high-order
distortions become important and impose additional constraints
upon the designers. The impact of the current sources’ limited
output impedance on the SFDR has been well analyzed and can
be solved for state-of-the-art DACs by using a differential output
[6], [7]. Since most of the DACs nowadays are using differential
output to achieve large output swing, no extra solution is needed
6Actuallythe switching sequence (of the switch-and-latch cells) which can
reduce the second-order distortion normally can also reduce the distortions that
are slightly higher than the second-order. This can be observed from the results
of the uniformly distributed random switching sequences in Fig. 14.
Fig. 14. Result of optimizing the switching sequence for a real design case
(f = 150 MHz).
to overcome the impact of the limited output impedance. How-
ever, even for DACs with differential output, our studies show
that the delay-related nonlinearities still deteriorate the SFDR
seriously.
The impact of the cell-dependent delay differences on the
SFDR of thermometercode-based current-steering DACs has
been analyzed in this paper. Formulas with clear physical
meaning have been derived and verified by both behav-
ioral-level simulations and results described in published
papers. The results are also justifiable for a segmented archi-
tecture, because in this architecture the thermometric part has
a much more significant weight compared to the binary part
and its delay differences will be the main contribution to the
SFDR deterioration. According to our results, delay differences
deteriorate the DACs SFDR property already at very low signal
frequencies, and are thus one of the main reasons that may
cause a bad SFDR property.
With the method proposed, the intrinsic advantage of the Re-
turn-to-Zero output stage in improving the SFDR property of a
DAC has been analyzed and explained.
The DDC technique has been presented to reduce the impact
of the cell-dependent delay differences on the SFDR. This tech-
nique makes use of the freedom in choosing the switching se-
quence of the switch-and-latch cells, and can improve the SFDR
greatly with very low penalty on the layout area and complexity.
The simulation results show that with the DDC technique, the
DACs SFDR performance is very close to that of an ideal DAC
which has no delay differences.
ACKNOWLEDGMENT
The authors would like to thank Dr. G. Van der Plas for his
valuable discussions and suggestions.
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[7] S. Luschas and H. S. Lee, “Output impedance requirements for DAC’s,”
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Tao Chen (S’02) was born in Zhangping City, Fujian
Province, P.R. China, in 1974. He received the B.S.
degree in electronic engineering in 1996 from Zhe-
jiang University, and in 1999, he received the M.S.
degree, also in electronic engineering, from Tsinghua
University, China.
From 1999 to 2000, he was an ASIC engineer at
Huawei High-Tech Incoporation, Beijing, and then a
chip design engineer with Capella Microsystem In-
coporation, Beijing. Currently, he is a research as-
sistant with the MICAS Laboratories, K.U. Leuven,
Belgium. He is working toward the Ph.D. degree on the design of analog/mixed-
signal integrated circuits.
15
Georges G. E. Gielen (S’87–M’92–SM’99–F’02)
received the M.Sc. and Ph.D. degrees in electrical en-
gineering from the Katholieke Universiteit Leuven,
Leuven, Belgium, in 1986 and 1990, respectively.
From 1986 to 1990, he was appointed as a Re-
search Assistant by the Belgian National Fund of
Scientific Research. In 1990, he was appointed a
Postdoctoral Research Assistant and Visiting Lec-
turer with the Department of Electrical Engineering
and Computer Science, University of California,
Berkeley. From 1991 to 1993, he was a Postdoctoral
Research Assistant with the Belgian National Fund of Scientific Research,
ESAT Laboratory, Katholieke Universiteit Leuven. In 1993, he was appointed
as a tenure Research Associate of the Belgian National Fund of Scientific
Research and also an Assistant Professor at the Katholieke Universiteit Leuven.
In 1995, he was promoted to Associate Professor at the same university, where
he is now a full-time Professor. His research interests are in the design of analog
and mixed-signal integrated circuits, and especially in analog and mixed-signal
CAD tools and design automation (modeling, simulation and symbolic analysis,
analog synthesis, analog layout generation, analog and mixed-signal testing).
He is coordinator or partner of several (industrial) research projects in this area.
He has authored or coauthored one book and more than 250 papers in edited
books, international journals, and conference proceedings.
Dr. Gielen was the 2004 President-Elect of the IEEE Circuits and Systems
(CAS) Society. He has been an Associate Editor of the IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS,
and recently also of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS––II:
ANALOG AND DIGITAL SIGNAL PROCESSING. He is also a member of the Pro-
gram Committees of international conferences (ICCAD, DATE, ISCAS). He
received the Best Paper Award of the Wiley International Journal on Circuit
Theory and Applications in 1995. He was the 1997 Laureate of the Belgian Na-
tional Academy of Sciences, Literature, and Arts, and is a member of the Edi-
torial Board of the Kluwer International Journal on Analog Integrated Circuits
and Signal Processing.