27

CHNG 3
GII THIU S LT V VI IU KHIN DSPIC30F4011
3.1 c im:
C kin trc Harvard
Vi b cu trc lnh trong C v ch a ch linh hot
C 84 lnh c bn
Cu lnh c di 24 bit, v ng dn d liu 16 bit
C 48Kbytes khng gian b nh chng trnh
2 Kbytes RAM d liu
512 Bytes SRAM
1 Kbytes EEPROM d liu khng mt khi mt ngun
Hot ng ln n 30MIPS:
- DC n 40 MHz ng vo xung clock ngoi
- 4 MHz-10MHz vi ng vo l b to dao ng, c th hot ng ch
4x, 8x, 16x
C 30 ngt:
- 3 ngt ngoi
- 8 ngt do ngi s dng chn la mc cho mi ln ngt
- 4 ngt cho b x l
16 thanh ghi lm vic 16 bit
Cc c tnh ngoi vi
Mc dng cho cc chn I/O l 25mA
Module Timer vi prescaler bng chng trnh:
- 5 timers/counters 16 bit; ch bt cp 2 timers 16 bit ta c 2
module timer 32 bit
Hm ng vo capture 16 bit
Hm ng ra so sanh hay PWM 16 bit
Module 3 dy SPI
TM
(h tr ch 4 Frame)
Module I
2
C h tr nhiu Master/Slave v 7-bit/10-bit a ch
2 module UART vi b m FIFO
1 module CAN
Module PWM iu khin ng c:
28
6 knh ng ra PWM
- Ch ng ra b hoc c lp
- Ch dng theo cnh v tm
3 b pht chu k cng sut
Ng ra phn cc bng chng trnh
iu khin thi gian cht cho ch b
iu khin tay ng ra
Trigger cho chuyn i A/D
Module giao tip Encoder:
C ng vo l pha A, B v Index Pulse
B m v tr 16 bit up/down
Thit lp hng m
Ch o lng v tr (x2 hoc x4)
C kh nng lc tp nhiu ng vo
Ch chuyn i 16 bit timer/counter
Thit lp ngt cho b m v tr rollover/underflow
Analog:
10 bit cho b chuyn i A/D vi 4 ng vo S/HL
- Tc chuyn i 500 Ksps
- 9 knh ng vo
- C th chuyn i trong lc sleep v idle
C th thit lp d tm Brown-out v Reset b pht
CMOS Technology:
in p thp, tc truy cp flash cao
Phm vi ca in p hot ng cao (2.5V n 5.5V)
Phm vi nhit cng nghip v m rng
Tiu th in nng t xem
29
3.2 S chn:
Hnh 3.1 S chn kiu PDIP v TQFP ca DsPIC30F4011
30
3.3 Khi qut:
Hnh 3.2 S khi ca dsPIC30F4011
Bng m t cc chn I/O ca dspic 30f4011
31
Bng 3.1 Chc nng cc chn ca vi iu khin
Pin Name Pin
Type
Buffer Type Description
AN0-AN8 I Analog Cc knh ng vo Analog.
AN0 v AN1 cng s dng cho d liu chng trnh
ca thit b v ng vo clock, tch bit.
AV
DD
P P Ngun dng cho module Analog.
AV
SS
P P Chn ground cho module Analog.
CLKI
CLKO
I
O
ST/CMOS
__
Ng vo cho ngun xung clock ngoi. Lun lun kt
ni vi chn OSC1.
Ng ra ca b dao ng thch anh. Kt ni n thch
anh hoc cng hng ch b pht thch anh.
Chn la chc nng nh CLKO ch RC v EC.
Lun lun kt ni vi chn OSC2.
CN0-CN7
CN17-
CN18
I ST Cc ng vo thay i theo khai bo.
C th dng phn mm thit lp in tr ko ln
cho tt c cc chn ny.
C1RX
C1TX
I
O
ST
ST
Chn nhn d liu trong giao tip chun CAN1.
Chn xut d liu trong giao tip chun CAN1.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Chn input/output d liu knh truyn thng s cp
ICD.
Chn input/output xung clock knh truyn thng s
cp ICD.
Chn input/output d liu knh truyn thng cp 2
ICD.
Chn input/output xung clock knh truyn thng cp 2
ICD.
Chn input/output d liu knh truyn thng cp 2
ICD.
Chn input/output xung clock knh truyn thng cp 2
ICD.
Chn input/output d liu knh truyn thng cp 3
ICD.
Chn input/output xung clock knh truyn thn cp 3
ICD.
IC1, IC2,
IC7, IC8
I ST Ng vo Capture 1, 2, 7 v 8.
INDX
QEA
QEB
I
I
I
ST
ST
ST
Ng vo chn Index Pulse ca b m v tr.
Ng vo pha A ca b m v tr ch QEI.
Ng vo Clock/Gate bn ngoi ca Timer ph.
Ng vo pha B ca b m v tr ch QEI.
Ng vo Clock/Gate bn ngoi ca Timer ph.
INT0
INT1
INT2
I
I
I
ST
ST
ST
Ngt ngoi 0.
Ngt ngoi 1.
Ngt ngoi 2.
32
FLTA
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
I
O
O
O
O
O
O
ST
__
__
__
__
__
__
Ng vo ca PWM li A.
Ng ra ca PWM 1 Low
Ng ra ca PWM 1 High
Ng ra ca PWM 2 Low
Ng ra ca PWM 2 High
Ng ra ca PWM 3 Low
Ng ra ca PWM 3 High
MCLR I/P ST Ng vo Master Clear (Reset) hoc ng vo in p
chng trnh. Chn ny khi cp mt in p mc thp
s Reset thit b
OCFA
OC1-OC4
I
O
ST
__
Ng vo li A so snh (cho cc knh so snh t 1 n
4)
Ng ra so snh t 1 n 4
OSC1
OSC2
I
I/O
ST/CMOS
__
Ng vo ca b dao ng thch anh. B m ST khi
thit b ch RC; ch CMOS
Ng ra ca b dao ng thch anh. Kt ni n thch
anh hoc cng hng ch b dao ng thch anh.
Hm ty nh CLKO ti ch RC v EC
PGD
PGC
I/O
I
ST
ST
Chn dng np d liu cho vi iu khin.
Chn ng vo xung clock cho qua trinh np.
RB0-RB8 I/O ST PORTB l port 2 chiu I/O.
8RC13-
RC15
8I/O 8ST PORTC l port 2 chiu I/O.
RD0-RD3 I/O ST PORTD l port 2 chiu I/O.
RE0-RE5,
RE8
I/O ST PORTE l port 2 chiu I/O.
RF0-RF6 I/O ST PORTF l port 2 chiu I/O.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
__
ST
Ng I/O xung clock ni tip ng b cho SPI
TM
1.
Ng vo d liu SPI1.
Ng ra d liu SPI1.
ng b Slave SPI1.
SCL
SDA
I/O
I/O
ST
ST
Ng I/O xung clock ni tip ng b cho chun I
2
C.
Ng I/O d liu ni tip ng b cho chun I
2
C.
SOSCO
SOSCI
O
I
__
ST/CMOS
Ng ra ca b dao ng thch anh tng s thp 32kHz.
Ng vo ca b dao ng thch anh tng s thp
32kHz.
T1CK
T2CK
I
I
ST
ST
Ng vo xung clock ngoi cho Timer1.
Ng vo xung clock ngoi cho Timer2.
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
__
ST
__
ST
__
Chn nhn d liu UART1.
Chn xut d liu UART1.
Chn nhn d liu xen k UART1.
Chn xut d liu xen k UART1.
Chn nhn d liu UART2.
Chn xut d liu UART2.
V
DD
P __ Ngun dng cho logic v cc chn I/O.
V
SS
P __ Tham chiu m cho logic v cc chn I/O.
V
REF+
I Analog Ng vo tham chiu in p tng t.(High)
V
REF-
I Analog Ng vo tham thiu in p tng t.(Low)
33
3.4 Core Overview
Li c cu trc 24-bit. Program counter (PC) 23-bit vi bit Least Significant
lun lun c clear, v bit Most Significant c b qua trong sut qu trnh thc thi
bnh thng, ngoi tr cc trng hp lnh c bit. Th nn b PC c th a ch ln
n 4M cho khng gian chng trnh ca ngi s dng.
Thanh ghi lm vic c sp xp bao gm 16 thanh ghi 16-bit , mi thanh ghi
c th hot ng nh thanh ghi d liu, a ch, trng. Mt thanh ghi lm vic (W15)
hot ng nh mt con tr ngn xp chng trnh cho ngt v call.
Khng gian d liu 64Kbytes (32K words) v chia ra 2 khi, c quy thnh
b nh d liu X v Y. Mi khi c Agu c lp, chng cung cp s xut hin ca
khng gian d liu thng nht n. Trng Multiply-Accumulate ca ngun DSP kp
thc thi hot ng trong c 2 khi AGU X v Y, chia khng gian a ch d liu thanh
2 phn. ng bin khng gian d liu X v Y th khng th thay i bi ngi s
dng. Mi d liu word bao gm 2 bytes, v tt c cc lnh c th d liu a ch hoc
l word hoc bytes.
C 2 phng php thc thi ct d liu trong b nh chng trnh:
Trn 32Kbytes ca b nh khng gian d liu c th nh x n na
thp ca khng gian chng trnh ti bt k ng bin word chng
trnh 16K, c nh ngha bi 8-bit thanh ghi PSVPAG. Thm na ch
c thp hn 16bit cho mi word lnh cso th c thc thi s dng
phng php ny.
SWW tuyn tnh gin tip truy cp ca trang word 32K trong khng
gian chng trnh th cng c kh nng s dng thanh ghi lm vic, qua
c bng v vit lnh. c bng v vit lnh c th s dng truy cp
tt c 24bit ca lnh word.
Nhng b m Overhead-free circular th h tr cho c khng gian a ch X v
Y. iu ny l m rng c bn g b vng lp u cho thut ton DSP.
3.5 DSP ENGINE
B DSP bao gm li x l s hc v cng sut cao. N c trng tc 17 bit
bi 17bit s nhn, 1 ALU 40 bit, 2 b tch tr bo ha 40 bit v 1 ng dch chuyn
2 chiu 40 bit. D liu trong b lu tr hoc thanh ghi lm vic c th di chuyn ln
n 16 bit phi v 16 bit tri trong 1 chu k n. Khi DSP thc hin lnh lin tc vi
tt c cc lnh khc v c thit k cho ti u thc thi thi gian thc.
Thit b DsPIC30F c 1 lnh n, n c th m rng hoc l lnh DSP hoc l
lnh MCU. C nhiu ti nguyn phn cng b chia s gia DSP v lnh MCU.
B DSP cng c kh nng x l k tha hot ng accumulator-to-
accumulator, iu ny i hi khng c d liu thm vo.
34
Hnh 3. 3 S khi ca cu trc DSP trong dsPIC30F4011
3.6 Cc PORT I/O
Tt c cc port chn c 3 thanh ghi trc tip lin h vi hot ng ca chn
ny. Thanh ghi d liu trc tip (TRISx) quyt nh tng chn l ng vo hay ng ra.
Nu bit hng d liu l 1, th chn l input. Lu l tt c cc chn ca port c
nh ngha l input sau khi reset. c t thanh ghi LATx, c b cht. Ghi ln b
cht, ghi ln thanh ghi LATx. c t port (PORTx), c cc chn ca port, v ghi n
chn ca port bng cch ghi ln b cht (LATx).
Tm li thanh ghi TRISx iu khin hng ca chn. Thanh ghi LATx cung
cp du liu n ng ra, v c kh nng c cng nh ghi. c t trng thanh ghi
PORTx trang thi ca cc chn ng vo trong khi ghi thanh ghi PORTx thay i ni
dung ca thanh ghi LATx.
3.7 TIMER1 MODULE
Timer 1 la loi Timer A. Module Timer1 l 1 Timer 16-bit, chng c th cung
cp nh l mt b m thi gian cho xung clock thi gian thc, hoc hot ng nh
b m khong thi gian timer/counter chay ch t do. 16-bit timer c nhng ch
hot ng sau:
35
16-bit Timer
16-bit m ng b
16-bit m khng ng b
Hn na, cc c tnh hot ng sau th c h tr l:
S hot ng cng Timer
Thit lp chn la prescaler
S hot ng ca Timer trong khi CPU ch Idle v Sleep
Thanh ghi chu k ngt 16-bit bng match hoc xung cnh xung ca
cng tnh hiu ngoi
Ch hot ng c quyt nh bi vic thit lp cc bit tng ng trong thanh ghi
T1CON 16-bit.
- Ch Timer 16-bit: ch Timer 16-bit, timer tng gi tr bin m ng
vi mi vng lnh up n gi tr match, t trc trong thanh ghi PR1, sau
reset v 0 v tip tc m. Khi CPU trng thi Idle, timer s dng m, tr
khi TSIDL bit =0. Nu TSIDL =1, module logic timer s vn tip tc m kt
qu ln n gi tr hy b ch CPU Idle.
- Ch m 16-bit ng b: trong ch ny tim m da vo xung cnh
ln ca xung clock tn hiu bn ngoi, iu ny c ng b ha vi pha
clock ni. Timer m ln n gi tr match t trc PR1, sau reset v 0
v tip tc. Khi CPU ch Idle tng t vi ch trn.
- Ch m 16-bit bt ng b: ch m ny timer s tng gi tr bin
m ng vi mi xung cnh ln ca xung clock bn ngoi. Timer m ln n
gi tr match t trc PR1, sau b reset v 0 v tip tc. ch m bt
ng b v CPU ch Idle, timer s dng m nu TSIDL=1.
Hnh 3. 4 S khi ca module TIMER1 16-bit
36
3.7.1 S hot ng cng timer
Timer 16-bit c th c t ch Gated Time Accumulation. Ch ny
cho php xung clock ni tng gi tr bin m timer tng ng khi tn hiu ng vo
cng ( chn T1CK) c gi mc cao. iu khi bit TGATE phi c set enable
ch ny. Timer phi c enable (TON=1) v ngun xung clock phi c set
ch xung ni (TCS=0).
Khi CPU trng thi Idle, timer s dng m, tr khi TSIDL bit =0. Nu
TSIDL =1, module logic timer s vn tip tc m kt qu ln n gi tr hy b ch
CPU Idle.
3.7.2 Timer Prescaler
Xung ng vo (F
OSC
/4 hoc xung clock ngoi) n timer 16-bit, c th la chn
prescale 1:1, 1:8, 1:64, v 1:256 c la chn iu khin bi cc bit TCKPS<1:0>
(T1CON<5:4>). B prescaler th c xa khi c bt k trng hp no sau xy ra:
Mt lnh ghi gi tr ln thanh ghi TMR1
Xa bit TON
Thit b reset nh POR v BOR
TMR1 th khng b xa khi T1CON th c ghi. N s b xa bi vic ghi ln
thanh ghi TMR1
3.7.3 S hot ng ca timer trong sut ch Sleep
Trong sut ch Sleep ca CPU, timer s hot ng nu:
Module timer th c enable (TON=1) v
Ngun xung clock ca timer th c chn l ngoi (TCS=1) v
Bit TSYNC c xc nhn mc logic 0, chng s nh ngha ngun
xung clock ngoi nh l bt ng b.
Khi tt c 3 iu kin trn tr thnh s tht, timer s tip tc m ln n thanh
ghi PR1 v reset v 0.
Khi 1 match gia timer v thanh ghi PR xut hin, 1 ngt c th c pht ra,
nu tng ng vi bt cho php ngt timer c bt ln.
3.7.4 Timer Interrupt
Timer 16-bit c th pht ra mt ngt trong chu k match. Khi timer m v
match vi thanh ghi PR, bit T1IF c xc nhn v 1 ngt c pht, nu c bt.
Bit T1IF phi c xa bng phn mm. C ngt T1IF th c t thanh ghi iu
khin IFS0 thanh ghi iu khin ngt.
Khi ch Gated Time Accumulation c bt, 1 ngt cng s c pht trn
xung cnh ln ca tin hiu cng.
Vic cho php ngt c thit lp bng bit T1IE. Bit cho php ngt timer th
c t thanh ghi iu khin IEC0 trong thanh ghi iu khin.
37
3.7.5 Real-Time Clock
Timer 1, khi hot ng ch Real-Time Clock (RTC), cung cp thi gian
ca ngy v cc s kin c th xy ra. c tnh hot ng ca RTC l:
Hot ng t b pht xung 32kHz
8-bit prescaler
Ngun thp
Ngt RTC
3.8 Module timer 2/3
Timer 2 l timer loi B v Timer3 l timer loi C.
Module Timer 2/3 l timer 32-bit, chng c th thit lp thnh 2 timer 16-bit,
vi s chn la ch hot ng. Timer ny c th c dng bi thit b ngoi vi
khc nh l :
Input Capture
Output Compare/Simple PWM
Timer 32-bit c cc ch sau :
timer 16-bit c lp (Timer2 v Timer3) vi tt c cc ch ca 1
timer 16-bit(ngoi tr ch m khng ng b)
Hot ng nh 1 timer n 32-bit
B m ng b n 32-bit
Ngoi ra c tnh hot ng ca n c h tr :
ADC Event Trigger
Timer gate Operation
Thit lp ch prescaler
S hot ng ca timer trong ch Idle v Sleep
Ngt trn thanh ghi chu ky match 32-bit
Cc ch hot ng ca ca chng c quyt nh bi vic thit lp cc bit
tng ng trn cc thanh thi 16-bit T2CON v T3CON.
- Ch 16-bit: ch ny, timer2 v timer3 c th c cu hnh
thnh 2 timer 16-bit c lp. Mi timer c th c thit lp hoc l
timer 16-bit hoc l ch m ng b 16-bit. Ch c s khc nhau
gia timer2 v timer3 l timer2 cung cp s ng b cho ng ra xung
clock prescaler. iu ny c s dng cho ng vo xung clock
ngoi tng s cao.
- Ch 32-bit timer: trong ch ny, timer tng gi tr bin m
mi chu k lnh m ln n gi tr match, t trc gi tr 32-bit
vo thanh ghi PR3/PR2, sau n reset v 0 v tip tc. Cho vic
c ng b 32-bit ca cp timer2/timer3, vic c LS word(thanh
ghi TMR2) s lm cho MS word c c v cht ti thanh ghi gi
38
16-bit(TMR3HLD). Cho vic ghi gi tr m ng b, thanh ghi gi
TMR3HLD phi c ghi u tin. Khi cho php ghi n thanh ghi
TMR2, ni dung trong thanh ghi TMR3HLD s c chuyn v cht
m MSB ca timer 32-bit.
- Ch m ng b 32-bit, trong ch ny timer tng gi tr bin
m trn mi cnh ln ca xung clock ngoi, xung ny c ng b
vi xung clock ni. Timer m n gi tr match c t trc trong
thanh ghi PR3/PR2, sau c reset n 0 v tip tc.
Hnh 3. 5 S khi ca module TIMER2/3 32-bit
3.9 Module Timer4/Timer5
Tng t vi module timer2/timer3.
3.10 Module giao tip m Encoder(QEI)
Module QEI cung cp giao tip vi loi encoder incremental cung cp d liu
v v tr. c im ca b QEI bao gm:
knh ng vo cho 2 pha tn hiu A/B v 1 cho knh Z
B m v tr 16-bit
Xc nh hng m
39
Ch o lng v tr (x2 v x4)
Lc nhiu ng vo
S thay i gia 2 ch 16-bit timer/counter
Ngt QEI
Hnh 3. 6 S khi ca module giao tip ENCODER
3.10.1 Blogic QEI
Loi encoder incremental c 3 ng ra: pha A, pha B, v index pulse(knh Z). 2
knh, pha A/B th c mi lin h vi nhau. Nu pha A trc pha B th hng ca
motor th c cho l chiu dng hoc thun. Nu pha B trc ta c trng hp
ngc li.
Knh Z, chi xut hin khi quay c 1 vng.
3.10.2 Ch m vtr 16-bit Up/Down
B m 16-bit Up/Down m ln hoc xung mi khi c xung m, v n nhn
bit s khc nhau gia 2 pha A v B xc nh hng m. Hng m c xc
nh bi bit UPDN, n c pht bi b QEI.
Bit cho php reset POSRES iu khin c hay khng reset v tr m khi
xung index th c pht hin. Bit ny ch c s dng khi QEIM<2:0>=100 hoc
40
110. Nu bit POSRES th c t gi tr 0, th b m v tr s khng reset khi xung
index c phat hin. B m v tr s vn m tip tc ln hoc xung v s b reset
bi iu kin khc. Cc bit IMV<1:0> cho php ngi s dng thit lp iu kin d
reset thanh ghi POSCNT
3.10.3 Chovtr
Nhng ch ny c thit lp bi cc bit QEIM<2:0>:
111= cho php QEI hot ng vi ch x4 vi b m v tr reset bi
match(MAXCNT)
110= cho php QEI hot ng vi ch x4 vi b m v tr reset index pulse
101= cho php QEI hot ng vi ch x2 vi b m v tr reset bi
match(MAXCNT)
100= cho php QEI hot ng vi ch x2 vi b m v tr reset index pulse
011= khng s dng
010= khng s dng
001= bt timer 16-bit
000= QEI/timer off
3.10.4 Khnnglc nhiu:
Bng cch thit lp cc bit QECK<2:0> , QEOUT c th cho tn hiu ng ra sch.
3.10.5 Bin i timer/counter 16-bit
Khi module QEI c thit lp cho ch QEI, mo dule c th c thit lp
nh 1 mu 16-bit timer/counter. Thit lp v iu khin timer ph c thc hin
bng thanh ghi QEICON SFR. QEA c s dng nh l ng vo xung clock timer.
Hm timer ny khai bo n timer1.
Khi thit b c xem nh mt timer, thanh ghi POSCNT s tr thanh thanh
ghi cha gi tr timer v MAXCNT s tr thnh thanh ghi Period. Khi mt match xut
hin c ngt QEI s c pht.
3.10.6 Module QEI hot ng trong trng thi Sleep ca CPU
QEI s vn hot ng khi CPU trng thi Sleep, nhng timer th khng v
xung clock ni khng hot ng.
3.10.7 QEI hot ng trong trng thi Idle ca CPU
Khi CPU trang thai i dl e, modul e QEI se hoat ng nu bi t QEI SI DL=0. T ng
t vi ch ti mer
3.10.8 Ngt QEI
B QEI s pht ra mt ngt khi xut hin nhng s kin sau:
Ngt trn b m v tr 16-bit khi rollover/underflow
D tm xung index hoc nu bit CNTERR c set
41
S kin matchTimer period
S kin Gate accumulation
3.11 Module iu khin PWM ng c
y l module n gin ha ca b pht nhiu ng ra iu ch rng xung.
Cc loi ngun sau v dng iu khin chuyn ng c p dng m module PWM
h tr:
ng c 3 pha AC
Motor t tr ng ngt
Motor khng chi than DC
B chng ngt ngun (UPS)
Module PWMc cc c im sau:
6 chn I/O PWM vi 3 b pht xung khc nhau
Ln n 16-bit
Thay i tng s PWM On-the-fly
Ch ng ng ra ging cnh v im gia
Ch pht xung n
H tr ngt cho Update bt i xng ch ging im gia
iu khin ghi ng ra cho hot ng ECM
S kin c bit so snh s kin ngoi vi khc
Chn FAULT chn la li mi chn ng ra PWM
Module ny cha 3 b pht xng c lp, c s t 1 n 3. Module c 6 ng ra
PWM, c nh s PWM1H/PWM1L n PWM3H/PWM3L. 6 chn I/O c nhm
thnh cc cp high/low. ch ti b, chn low PWM th lun lun b cho chn
p ng I/O high.
42
Hnh 3. 7 S khi ca module PWM
3.11.1 C sthi gian PWM
C s thi gian PWM th c cung cp bi 1 timer 15-bit vi 1 prescaler v
postscaler. Bit PTMR<15> l bit trng thi ch c, PTDIR, ch nh ny xc nh
hng m hin ti ca c s thi gian PWM. Nu bit PTDIR th b xa, PTMR s
m ln. Nu PTDIR c st, th PTMR s m xung. C s thi gian PWM c
cu hnh qua thanh ghi PTCON SFR. B time base c cho php hay khng cho
php bi vic set/clear bit PTEN trn thanh ghi PTCON SFR. PTMR th khng b xa
khi bit PTEN b xa trong phn mm.
Thanh ghi PTPER SFR thit lp chu k m cho PTMR. Ngi s dng phi
ghi gi tr 15-bit n PTPER<14:0>. Khi gi tr trong PTMR<14:0> match gi tr
43
trong PTPER<14:0>, time base s hoc reset n 0 hoc o ngc hng m chu
k xung clock xut hin k tip.
Lu : nu thanh ghi Period th c set n 0x0000, timer s dng m, v
ngt v kch pht s kin c bit s khng c pht, thm ch nu gi tr s kin c
bit cng l 0x0000. Module s khng update thanh ghi period, nu n sng sng
0x0000; v vy ngi s dng phi disable module lnh update thanh ghi period.
B c s thi gian PWM c th c cu hnh cho 4 ch hot ng khc
nhau:
Ch chy t do
Ch single shot
Ch m lin tc up/down
Ch m lin tc up/down vi ngt cho 2 ln update
4 ch ny c chn bi cc bit PTMOD<1:0> trong thanh ghi PTCON.
Ch m up/down h tr b pht PWM ging im gia. Ch single shot cho
php module PWM h tr iu khin xung ca ECMs.
Ch chy t do (Free running): ch ny, b time base PWMm
ln cho n khi gi tr trong thanh ghi PTPER c match. Thanh ghi PTMR
th reset bng cnh xung clock ng vo v time base s tip tc m ln min l
bit PTEN c set. Khi c s thi gian PWM ch Free running
(PTMOD<1:0> =00), 1 s kin ngt s c pht mi ln match vi thanh ghi
PTPERxut hin v thanh ghi PTMR th c reset n 0. Cc bit postscaler
c chn s dng trong ch ny s gim tng s s kin ngt.
Ch Single Shot: b c s thi gian PWM bt u m ln khi bit
PTEN set. Khi gi tr trong thanh ghi PTMR match thanh ghi PTPER, thanh
ghi PTMR s reset bng cnh xung clock ng vo v bit PTEN s c xa bi
phn cng n na time base. Khi c s thi gian PWM ch ny
(PTMOD<1:0>=01), mt s kin ngt c pht khi 1 match vi thanh ghi
PTPER xut hin, thanh ghi PTMR c reset bng cnh xung clock ng vo,
v bit PTEN c xa. Chon la cc bit postscaler khng nh hng n ch
ny ca timer.
Ch m lin tc Up/Down (continous up/down counting mode):
trong ch ny b c s thi gian PWM m ln cho n khi gi tr trong
thanh ghi PTPER c match. Timer s bt u m xung cnh xung clock
k tip. Bit PTDIR trong thanh ghi PTCON ch c c v ch nh hng
m. Bit PTDIR c set khi timer m xung. Trong ch m up/down
(PTMOD<1:0>=10), 1 s kin ngt c pht mi khi gi tr trong thanh ghi
PTMR tr v 0 v time base PWM m ln tr li. Vic la chn cc bit iu
khin postscaler c th c s dng trong ch ny gim tng s s kin
ngt.
Ch update kp (double update mode): trong ch ny
(PTMOD<1:0>=11), mt s kin ngt th c pht mi ln thanh ghi PTMR
=0, tng t nh mi ln chu k match xut hin. Vic chn la cc bit
postscaler khng nh hng n timer ch ny. Ch update kp cung
44
cp 2 hm cng thm cho ngi s dng. u tin, bng thng vng iu khin
thi c double bi v chu k cng sut PWM c th c cp nht, 2 ln trong
mt chu k. K tip, dng sng PWM ging theo im gia bt i xng c th
c pht, chng c s dng cho bin dng dng sng ng ra min trong
cc ng dng iu khin ng c chc chn.
Prescaler c s thi gian PWM: xung clock ng vo n PTMR
(F
OSC
/4), c cc chn la 1:1, 1:4, 1:16 hoc 1:64, vic chn la c iu
khin bi cc bit PTCKPS<1:0> trn thanh ghi PTCON. Trng thi m
prescaler c xa khi xut hin cc trng hp sau:
- Mt ln ghi ln PTMR
- Mt ln ghi ln PTCON
- Reset thit b
Postscaler c s thi gian PWM: match ng ra c th c chn la
postscaler bng 4-bit postscaler
3.11.2 Chu kPWM
Thanh ghi 15-bit PTPER v c s dng set chu k m cho c s thi
gian PWM. PTPER l mt thanh ghi m kp. Ni dung m PTPER th c ti vo
thanh ghi PTPER ti nhng trng hp sau:
Ch Free Running v Single Shot: khi thanh ghi PTMR th reset
n 0 sau khi match vi thanh ghi PTPER.
Ch Up/Down couting: Khi PTMR c reset.
Gi tr c gi b m PTPER th t ng ti vo thanh ghi PTPER khi c
s thi gian PWMth c disable.
Chu k PWMc th c quyt nh bng cch s dng cng thc sau:
T
PWM
= (3.1)
Nu c s thi gian PWM th c cu hnh cho ch m up/down, chu k
PWMs bng 2 ln cng thc trn.
3.11.3 Ging hng theo cnh
Tn hiu ging theo cnh c cung cp bi module khi c s thi gian PWM
th ch Free Running hoc Single Shot. Ng ra PWM ging theo cnh, ng ra c
chu k xc lp bi gi tr PTPER v chu k cng sut xc lp bi thanh ghi chu k
cng sut. Ng ra ca PWM th c li hot ng ti thi im bt u ca chu k
(PTMR=0) v n s dng hot ng khi gii tr trong thanh ghi chu k cng sut
match PTMR.
Nu gi tr trong thanh ghi chu k cng sut bng 0, dn n p ng ng ra
chn PWM s ngng hot ng cho nguyn chu k PWM. Thm na, ng ra ca
45
PWM s hot ng cho nguyn chu k PWM nu gii tr trong thanh ghi chu k cng
sut ln hn gi tr gi trong thanh ghi PTPER
Hnh 3. 8 Xung PWMging theo cnh
3.11.4 Ging theo im gia
Tn hiu PWM ging im gia c cung cp bi module khi c s thi gian
PWM c cu hnh ch m Up/Down.
Ng ra so snh PWM th trng thi hot ng khi gi tr trong thanh ghi chu
k cng sut match gi tr ca PTMR v b c s thi gian ang m
xung(PTDIR=1). Ng ra s sanh PWM c li n trng thi ngng hot ng khi
b c s thi gian PWMm ln v gi tr trong thanh ghi PTMR match gi tr chu k
cng sut.
Nu gii tr trong thanh ghi chu k cng sut l 0, th ng ra p ng chn
PWM s ngng hot ng trong nguyn chu k PWM. Ngoi ra, ng ra PWM s hot
ng trong nguyn chu k nu gii tr trong thanh ghi chu k cng sut tng ng
vi gi tr c gi trong thanh ghi PTPER.
Hnh 3. 9 Xung PWMging theo im gia
46
3.11.5 Nhng bso snh thi gian T-on PWM
C 3 thanh ghi lnh 16-bit (PDC1, PDC2, PDC3) c s dng thit lp chu
k cng sut cho module PWM.
Gi tr trong thanh ghi chu k cng sut s quyt nh thi gian duy tr trng
thi tich cc ng ra PWM. Thanh ghi chu k cng sut c rng 16-bit. Bit LS ca
thanh ghi chu k cng sut quyt nh c hay khng xut hin cnh PWM trng
thi bt u. Vy l phng php PWMc hiu sut gp i.
3.11.6 Hot ng b ca PWM
Trong ch hot ng b, mi cp ng ra PWM t c bi tn hiu PWM
b. Mt khong thi gian cht c th c chn vo khi chuyn mch thit b, khi m
c 2 ng ra u khng hot ng trong 1 giai on ngn.
Trong ch b, b so snh chu k cng sut th c gn cho cc ng ra
PWM nh sau:
Thanh ghi PDC1 iu khin ng ra PWM1H/PWM1L
Thanh ghi PDC2 iu khin ng ra PWM2H/PWM2L
Thanh ghi PDC3 iu khin ng ra PWM3H/PWM3L
Ch b th c chn cho mi cp chn bng vic xa bit PMODx tng ng trn
than ghi PWMCON1.
3.11.7 B pht thi gian cht
B pht thi gian cht c th c cung cp khi bt k cp chn PWMno hot
ng ch b. Ng ra PWM s dng mch li i xng. S bt lc ca thit b
ngun ng ra trong vic chuyn mch ngay lp tc, phi mt mt khong thi gian
gia vic turn off 1 ng ra PWM trong 1 cp b v turn on ca transistor khc.
Module PWM cho php lp trnh 2 khong thi gian cht. 2 khong thi gian
cht ny c th c s dng 1 trong 2 phng php m t bn di tng tnh linh
hot cho ngi s dng:
Tn hiu ng ra PWM c th c nh gi khc nhau thi gian turn
off trong transistor high side v low side trong 1 cp b ca
transistor. Thi gian cht u tin c chn vo gia s kin turn
off ca transistor thp hn ca cp b v s kin turn on ca
transistor cao hn. Thi gian cht k tip c chn vo gia s kin
turn off ca transistor cao hn v turn on ca transistor thp hn.
khong thi gian cht c th c phn chia n c 2 chn PWM.
Ch hot ng ny cho php module PWM li b transistor/load
khc vi mi cp chn b PWM.
3.11.8 Ngra PWM c lp
Ch ng ra PWM c lp i hi vic li chc chn loi ca ti. Mt cp
ng ra PWM ch c lp, khi bit PMOD tng ng trong thanh ghi PWMCON1
c set.
47
Khng iu khin thi gian cht gia cc chn PWM lin k trong khi module
PWM ang hot ng trong trng thi c lp v c hai chn I/O th c cho php
cng lc.
ch c lp, mi b pht chu k cng sut c kt ni n c hai chn
PWM trong mt cp ng ra. Bng cch s dng thanh ghi chu k cng sut cho mi
chn PWM trong ch c lp.
3.11.9 Hot ng PWM xung n
Module PWM iu ch xung n ng ra khi bit iu khin PTMOD<1:0>=10.
Ch ch ging cnh ng ra c th iu ch ch xung n. Trong ch xung
n, chn PWM th c li trng thi active khi bit PTEN c set. Khi 1 match
vi thanh ghi chu k cng sut xut hin, chn PWM th s chuyn sang trng thi
inactive. Khi mt match vi thanh ghi PTPER xut hin, thanh ghi PTMR s b xa,
tt c cc chan PWM s c li sang trng thi inactive nu bit PTEN b xa v mt
ngt c pht.
3.11.10 Tt ngra PWM
Bit ghi ng ra PWM cho php ngi s dng iu chnh li chn PWM n
trng thi logic l thuyt, c lp b so snh chu k cng sut. Tt c cc bt iu
khin lin quan n tt ng ra PWM c cha trong thanh ghi OVDCON.
3.11.11 Kch pht s kin c bit PWM
Module PWM c th kch pht s kin c bit cho php chuyn i A/D ng
b vi c s thi gian PWM. Vic ly mu v thi gian chuyn i c th c lp
trnh xut hin ti bt k im no trong chu k PWM. Kch pht s kin c bit
cho php ngi s dng minimize khong delay gia thi gian trong khi kt qu
chuyn i A/D t c v thi gian khi gi tr chu k cng sut c update.
Kch pht s kin c bit PWM co thanh ghi tn SEVTCMP, v 5 bit iu
khin hot ng ca n.
3.11.12 Hot ng ca bPWM trong trng thi Sleep ca CPU
Ng vo FAULT A cho kh nng nh thc CPU t trng thi Sleep. Module
PWMpht 1 ngt nu chn FAULT chuyn sang mc thp trong khi ang ng.
3.11.13 Hot ng ca bPWM trong trng thi Idle ca CPU
Thanh ghi PTCON cha bit iu khin PTSIDL. Bit ny quyt nh nu module
PWM s tip tc hot ng hay dng khi thit b ang trng thi Idle
48
CHNG 4
HNG DN S DNG PHN MM MPLAB IDE
4.1 MPLAB IDE overview
Phin bn ny c m rng vi cc i tng MCU PICmicro, file ngun cn
c t trong 1 project. Code c th c xy dng da trn vic la chn cc cng c
ngn ng (assemblers, compilers, linkers, ). Trong MPLAB IDE, vic qun l project
iu khin vic x l ny.
Tt c cc project s c nhng bc c bn sau:
Chn la thit b
Kh nng ca MPLAB IDE thay i tng xng vi thit b c chn la.
Vic chn la thit b nn hon thnh trc khi bt u mt project.
To Project
Cng c Project Wizard c th c s dng to Project
Chn la cng c ngn ng
Trong Project Wizard c c phn la chn cng c ngn ng. Trong tutorial ny s
dng assembler v linker. Trong cc project khc, chng ta c th chon la dng chng
trinh bin dch hoc cng c ca hng th 3.
t file trong project
2 file cn phi c t trong project, 1 file mu v 1 linker script. C 2
cng tn ti trong MPLAB IDE. Rt d chng ta ly 2 file ny.
To code
Mt s code s c add n file mu gi gi tr gia tng ra ngoi 1 port
I/O.
Cu trc Project
Project s c to v khi file ngun c t vo m my th chng ta c
th chy trn MCU PICmicro c chn.
Test code v m phng
Cui cng code s c test bng chng trnh m phng.
Project wizard s lm n gin ha cc bc trn ca chng ta.
4.2 Chn la thit b
Sau khi ci t MPLAB IDE ta m chng trnh v bt u to mt project mi.
hin th cc menu chon la trong ti liu ny, cc mc chn menu t hng trn trong
MPLAB IDE s hin th vi ci tn ging nh sau MenuName>MenuItem. chn
49
Select Device ta chn menu Configure, ta c th ghi gn li nh sau Configure>Select
Device.
Chn Configure>Select Device. Trong hp thoi Device, chn tn vi iu khin
m chng ta ang s dng vi d nh PIC 18F8722 t list nu n cha c chn.
Hnh 4.1 Hp thoi chn thit b
Nhng ch th bng mu cho thy cc thnh phn m MPLAB IDE h tr cho thit
b ny.
Ch th mu xanh cho bit c h tr y .
Ch th mu xanh cho bit h tr s b cho phn cp nht thm bi cc tool
thnh phn c bit khc ca MPLAB IDE. Cc thnh phn vi mu vng thay
th cho mu xanh th thng dng l s cp nht sau nu ai cn h tr thm
phn ny v c hiu nh l mt s hm v hot ng c th khng c kh
nng thc thi.
Ch th mu cho thy thit b nay khng c h tr chc nng .
4.3 To PROJECT
Bc k tip l to 1 project s dng cng c Project Wizard ca MPLAB IDE.
Mt Project l cch h thng ha cc file cho vic bin dch v tng hp. Chng ta s
s dng nhng khi file n cho Project ny v linker script. Chn Project>Project
Wizard.
T hp thoi Welcome, click Next> i tip.
Hp thoi k tip cho php bn chn thit b, chng ta hon thnh bc tip theo
v chc rng thit b c chn y l PIC18F8722. Nu n khng c mc nh,
chng ta phi chn t menu rt xung. Click Next>.
50
Hnh 4.2 Hp thoi chn thit b bng cng c Wizard
4.4 Thit lp cng c ngn ng
Bc 2 ca Project Wizard l thit lp cng c ngn ng m chng ta s dng cho
project ny. Chn Microchip MPASM Toolsuite trong hp list Active Toolsuite. Sau
MPASM v MPLINK ta nn hp Toolsuite Contents. Click mt ln nhn thy
ng dn. Nu MPLAB IDE c install n danh b mc nh, hp ng thc thi
MPASM s nm ng dn:
C:\Program Files\Microchip\MPASM Suite\mpasmwin.exe
File lin kt thc thi MPLINK s nm :
C:\Program Files\Microchip\MPASM Suite\mplink.exe
V file th vin thc thi MPLIB s nm :
C:\Program Files\Microchip\MPASM Suite\mplip.exe
Nu n khng hin th ng, s dng nt Browse st ng dn cho chng
trong th mc cha MPLAB IDE.
Hnh 4.3 Hp thoi la chn ngn ng lp trnh
Khi bn hon thnh, click Next>.
51
4.5 t tn Project
Bc 3 ca wizard cho php bn t tn cho Project v ni t folder. Project mu
ny s c gi l MyProject. S dng nt Browse, chn folder cha project l
Project32. Click Next>.
Hnh 4.4 Hp thoi t tn v ng dn cho project
4.6 Cng thm file vo Project
Bc 4 ca Project Wizard cho php chn file cho project. Mt file ngun nu
cha c chn chng ta s s dng file mu ca MPLAB IDE. File mu l file n gin
c th s dng bt u 1 project. Chng c th thnh phn c bn cho mt file ngun,
c chac nhng thng tin s gip cho bn vit v h thng ha code ca mnh. C 1 file
mu cho mi MCU PICmicro v thit b dsPIC DSC.
Chn tn file l 8722tmpo.asm. Nu MPLAB IDE c install vi ng dn mc
nh, ng dn y ca file s l :
C:\Program Files\Microchip\MPASM
Suite\Template\Object\8722tmpo.asm
Hnh 4.5 Hp thoi chn file mu cho project
52
Nhn Add>> di chuyn tn file n panel bn phi, v click ln checkbox ti
im bt u ca dng vi tn file c chn copy file n danh mc project.
K tip, add thm file k tip cho project ca chng ta, tp lnh lin kt. C mt
tp lnh lin kt cho mi thit b. File ny nh ngha cu hnh b nh v tn thanh ghi
cho cc phn khc nhau. S dng tn file 18F8722. ng dn y l:
C:\Program Files\Microchip\MPASM Suite\LKR\18F8722.lkr
copy tp lnh lin kt ny n project ca chng ta, click ln checkbox.
Hnh 4.6 Hp thoi chn linker script
Chc chn rng hp thoi ca bn trng ging nh trong hnh trn, vi c 2
checkbox c check, sau nhn Next> hon thnh Project Wizard.
Hnh cui cng ca Project Wizard l mt bn xc nhn thit b c chn,
toolsuite v tn ca project mi.
Hnh 4.7 Bng thng bo kt qu ca WIZARD
Sau nhn nt Finish, xem ca s Project Window trn mn hnh MPLAB IDE.
N nn ging vi hnh sau. Nu Project Window khng c m, chn View>Project.
53
Hnh 4.8 Ca s Project
4.7 Cu trc Project
T menu Project, chng ta c th h thng v lin kt cc file hin hnh. Chng
khng cha c code ca chng ta, nhng chc chn rng project ny c thit lp ng.
xy dng project, chn mt trong cc cch sau:
Project>Build All
Click phi ln tn project trong ca s project v chn Build All
Click icon Build All trn Project toolbar.
Ca s kt qu cho thy kt qu ca tin trnh build. C li bt c
bc no hay khng.
List bo co li hnh di s khng cn tr hot ng ca chng
trnh. Chng ch thng bo 1 ch th rng c s c, chng s tip tc cc
hot ng khc. tt mn hnh bo ng, ta lam theo cch sau:
Chn Project>Build Options>Project v click ln tab MPASMAssembler.
Chn Output t list rt xung Categories.
Chn Errors only t danh mc rt xung Diagnostic level
Click OK.
54
Hnh 4.9 Ca s ng ra
4.8 To code
M file mu trong project bng cch nhn double ln tn trong ca s Project,
hoc chn n vi con tr v s dng phi chut a ra ni dung menu
File c mt s ch gii phn m u, v khu vc ny c th c s dng nh l
cc ch dn thng tin chun cho phn u ca mt file. By gi bn s b qua phn ny,
nhng nu bn mun sa i thng tin theo mnh th c th thm vo.
Hnh 4.10 Ni dung file mu
Code trong phn u tin ca file dnh cho phn hm khai bo nh l thit lp
ngt v cc bit cu hnh trong 1 ng dng. Phn code mi s c t trong file ti im
sau nhng khai bo chnh c nh ngha.
Cun xung y ca file.
55
Hnh 4.11 Phn chng trnh chnh m ngi dng thm vo
Khi file ngun c m, bn t ng trong vic thay i. Chng ta c th nh
mt on code bt k phc v cho mt yu cu no o. Ch l y chng ta ang
dng ngn ng Asm.
4.9 Cu trc Project Again
Chn Project>Build All h thng v lin kt Code. Nu code c h thng m
khng c li no, ca s Output s trng ging nh hnh di.
Nu code khng c h thng v lin kt thnh cng, kim tra nhng ch bo
theo sau v cu trc li project:
Nu bo co li vic h thng trong ca s Output, nhn p chut ln li v
MPLAB IDE s m dng tng ng trong m ngun vi mi tn xanh bn tri
ng bin ca ca s m ngun.
Kim tra li chnh t v nh dng ca code c nhp vo trong ca s editor.
Phi chc rng nhng bin mi v cc thanh ghi lnh c bit, TRISC v
PORTC nm trong hp trn.
Hnh 4.12 Ca s ng ra sau khi Build
56
Kim tra li h thng ( hp ng ASM) v lin kt cho thit b MCU PICmicro
c s dng. Chn Project>Set Language Tool Locations. Click ln hp cng
m rng toolsuite MPASM v thc thi. Click MPASM Assembler
(mpasmwin.exe) v xem ng dn ca chng trn mn hnh. Nu ng dn
ng, click Cancel. Nu sai, thay i ng dn v click OK.
Vi mt cu trc thnh cng, file ng ra c pht bi tool ngn ng s c ti.
File ny cha code i tng c th lp trnh cho MCU PICmicro v thng tin sa li vy
l m ngun c th sa li v bin ngun c th c theo di thng qua ca s Watch.
Chn cng c m phng ging nh cng c thc thi g li. iu ny c thc
hin bng cch chn Debugger>Select Tool menu s xung. Sau khi chn MPLAB SIM,
chng ta s thy c nhng thay i sau:
1) Thanh trng thi y ca ca s MPLAB IDE nn thay thnh MPLAB
SIM.
2) Danh mc menu cng thm s xut hin trong menu Debugger.
3) Bng cng c cng thm xut hin trn thanh cng c Debug.
4) Mt tab MPLAB SIM c cng thm vo ca s Output.
Hnh 4.13 Thanh cng c MPLAB SIM
K tip, chn Debugger>Reset>Processor Reset v mt mi tn xanh cho thy
ni chng trnh bt u.
xem tng bc thc thin trong chng trnh, chn Debugger>Step Into. iu
ny s thc thi tng dng lnh v di chuyn mi tn n dng k tip thc thi.
y l cc menu tt thng s dng trong cng c Debug.
57
Bng 4.1 Cc thanh cng c ca menu debug
K tip, nhn chn icon Step Into hoc chn Debugger>Step Into kim tra tng
bc trong m chnh.
thy c cc bin trong chng trinh hay cc thanh ghi thay i nh th no
khi chy cc m lnh ta c th bt ca s Watch theo di bn cch chn View>Watch,
khi mt ca s trng s xut hin. C 2 thanh ko xung nm pha trn cng ca ca
s Watch. Ci bn tri c nhn Add SFR c th s dng cng thm cc thnh ghi
lnh c bit, v d nh y ta chn PORTC. theo di cc bin ta s dng thanh bn
phi c nhn l Add Symbol. V d ta chn bin COUNT. Sau khi la chn cc bin v
thanh ghi cn quan st ta c bng kt qu sau.
Hnh 4.14 Bng theo di cc gi tr khi chy m phng