Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 1

ELEC 5270/6270 Spring 2011

Low-Power Design of Electronic Circuits

Pseudo-nMOS, Dynamic CMOS
and Domino CMOS Logic
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849

vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 2
Static CMOS: Pros and Cons
Advantages: Static (robust) operation, low
power, scalable with technology.
Disadvantages:
Large size: An N input gate requires 2N transistors.
Large capacitance: Each fanout must drive two
devices.
Alternatives: Pass-transistor logic (PTL),
pseudo-nMOS, dynamic CMOS, domino CMOS.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 3
A Pseudo-nMOS Gate

PUN


PDN

VDD
CMOS Gate

PDN

VDD
Pseudo-nMOS Gate
Output
I
n
p
u
t
s

I
n
p
u
t
s

Output
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 4
Pseudo-nMOS NOR
VDD
Input 1
Output
Input 2 Input 3
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 5
Pseudo-nMOS NAND
VDD
Input 1
Output
Input 2
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 6
Pseudo-nMOS Inverter
VDD
Input
Output
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 7
Inverter Characteristics
W/L
p
= 4
W/L
p
= 2
W/L
p
= 0.25
W/L
p
= 0.5
W/L
p
= 1
0.0 0.5 1.0 1.5 2.0 2.5
Input voltage, V
O
u
t
p
u
t

v
o
l
t
a
g
e
,

V

3.0

2.5

2.0

1.5

1.0

0.5

0.0
Nominal device:

W 0.5
= = 2
L
n
0.25
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 8
Performance of Inverter
Size, W/L
p
Logic 0 voltage
Logic 0 static
power
Delay
0 1
4 0.693 V 564 W 14 ps
2 0.273 V 298 W 56 ps
1 0.133 V 160 W 123 ps
0.5 0.064 V 80 W 268 ps
0.25 0.031 V 41 W 569 ps
J. M. Rabaey, A. Chandrakasan and B. Nokoli, Digital Integrated
Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003,
page 262.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 9
Negative Aspects of Pseudo-nMOS
Output 0 state is ratioed logic.
Faster gates mean higher static power.
Low static power means slow gates.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 10
A Dynamic CMOS Gate

PDN

VDD
I
n
p
u
t
s

Output
CK
C
L
Precharge
transistor
Evaluate
transistor
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 11
Two-Phase Operation in a Vector
Period
Phase CK Inputs Output
Precharge low dont care high
Evaluation high Valid inputs Valid outputs
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 12
4-Input NAND Dynamic CMOS Gate
Output
= CK + (ABCD) CK
C
L
CK

A

B

C

D

CK
VDD
t
LH
0
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 13
Characteristics of Dynamic CMOS
Nonratioed logic sizing of pMOS transistor is not important
for output levels.
Smaller number of transistors, N+2 vs. 2N.
Larger precharge transistor reduces output fall time, but
increases precharge power. Faster switching due to smaller
capacitance.
Static power negligible.
Short-circuit power none.
Dynamic power
no glitches following precharge, signals can either make transitions
only in one direction, 10, or no transition, 11.
only logic transitions all nodes at logic 0 are charged to VDD during
precharge phase.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 14
Switching Speed and Power
Fewer transistors mean smaller node
capacitance.
No short-circuit current to slow down
discharging of capacitance.
Only dynamic power consumed, but can
be higher than CMOS.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 15
Logic Activity
Probability of 0 1 transition:
Static CMOS, p0 p1 = p0(1 p0)
Dynamic CMOS, p0 p0 p1
Example: 2-input NOR gate
Static CMOS, Pdyn = 0.1875 C
L
V
DD
2
f
CK
Dynamic CMOS, Pdyn = 0.75 C
L
V
DD
2
f
CK
p1 = 0.5
p1 = 0.5
p1 = 0.25
p0 = 0.75
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 16
Charge Leakage
Output
A
C
L
CK

A=0

CK
VDD

CK
A
Time
P
r
e
c
h
a
r
g
e

E
v
a
l
u
a
t
e

Ideal
Actual
J. M. Rabaey, A. Chandrakasan and B. Nokoli, Digital Integrated
Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 17
Bleeder Transistor
Output
C
L
CK

A

B

C

D

CK
VDD
Output
C
L
CK

A

B

C

D

CK
VDD
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 18
A Problems With Dynamic CMOS
CK

A=01

CK
VDD
CK

A

B

C
B
J. M. Rabaey, A. Chandrakasan and B. Nokoli, Digital Integrated
Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
CK



CK
VDD
C
prech. evaluate
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 19
Remedy
Set all inputs to gates to 0 during
precharge.
Since precharge raises all outputs to 1,
inserting inverters between gates will do
the trick.
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 20
Domino CMOS
CK

A=01

CK
VDD
CK

A

B

C
B
R. H. Krambeck, C. M. Lee and H.-F. S. Law, High-Speed Compact
Circuits with CMOS, IEEE J. Solid-State Circuits, vol. SC-17, no. 3,
pp. 614-619, June 1982.
CK



CK
VDD
C
prech. evaluate
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 21
Bleeder in Domino CMOS
Output
C
L
CK

A

B

C

D

CK
VDD
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 22
Logic Mapping for Noninverting Gates
A

B

C

D

E

F
G

H
ABC
G+H
AND
OR
AND/OR
X



Y
Y
ABC
D
E
F
G+H
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9 23
Selecting a Logic Style
Static CMOS: most reliable and predictable,
reasonable in power and speed, voltage scaling
and device sizing are well understood.
Pass-transistor logic: beneficial for multiplexer
and XOR dominated circuits like adders, etc.
For large fanin gates, static CMOS is inefficient;
a choice can be made between pseudo-nMOS,
dynamic CMOS and domino CMOS.