VHDL Tieng Viet

Trng i hc bch khoa H Ni
Khoa cng ngh thng tin

B mn k thut my tnh
--------------------------------------
bo co n mn hc
Thit k mch nh my tnh
ti:
Thit k mch bng VHDL

Gio vin hng dn:
th.s. nguyn ph bnh
Nhm sinh vin thc hin: L tun anh

Nghim kim phng
Nguyn quc vit
Nguyn ngc linh
Lp:
ktmt - K46
H Ni, 10/2005
Ti 4: Thit k vi mch bng VHDL

Nhm 4
Mc lc
Trang
Danh mc hnh:
Trang
Danh mc bng:
Trang
Chng 1: Gii thiu

1.1.
Gii thiu v VHDL

Nhm 4
VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt
cao, l mt loi ngn ng m t phn cng c pht trin dng cho trng
trnh VHSIC( Very High Speed Itergrated Circuit) ca b quc phng M. Mc
tiu ca vic pht trin VHDL l c c mt ngn ng m phng phn cng
tiu chun v thng nht cho php th nghim cc h thng s nhanh hn cng
nh cho php d dng a cc h thng vo ng dng trong thc t. Ngn
ng VHDL c ba cng ty Intermetics, IBM v Texas Instruments bt u
nghin cu pht trin vo thng 7 nm 1983. Phin bn u tin c cng b
vo thng 8-1985. Sau VHDL c xut t chc IEEE xem xt thnh
mt tiu chun chung. Nm 1987 a ra tiu chun v VHDL( tiu chun
IEEE-1076-1987).
VHDL c pht trin gii quyt cc kh khn trong vic pht trin,
thay i v lp ti liu cho cc h thng s. VHDL l mt ngn ng c lp
khng gn vi bt k mt phng php thit k, mt b m t hay cng ngh
phn cng no. Ngi thit k c th t do la chn cng ngh, phng php
thit k trong khi ch s dng mt ngn ng duy nht. V khi em so snh vi
cc ngn ng m phng phn cng khc ta thy VHDL c mt s u im hn
hn l:
-
Th nht l tnh cng cng:
VHDL c pht trin di s bo tr ca chnh ph M v hin nay l

mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh sn xut thit b
cng nh nhiu nh cung cp cng c thit k m phng h thng.
-
Th hai l kh nng c h tr bi nhiu cng ngh v nhiu phng

php thit k:
VHDL cho php thit k bng nhiu phng php v d phng php
thit k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng
h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh ng b
hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu
nhin.
-
Th ba l tnh c lp vi cng ngh:
VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t

h thng dng VHDL thit k mc cng c th c chuyn thnh cc bn
tng hp mch khc nhau tu thuc cng ngh ch to phn cng mi ra i n
c th c p dng ngay cho cc h thng thit k.
-
Th t l kh nng m t m rng:
VHDL cho php m t hot ng ca phn cng t mc h thng s cho

n mc cng. VHDL c kh nng m t hot ng ca h thng trn nhiu

Nhm 4
mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Nh th
ta c th m phng mt bn thit k bao gm c cc h con c m t chi tit.
-
Th nm l kh nng trao i kt qu:
V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL

c th chy trn mi b m t p ng c tiu chun VHDL. Cc kt qu m
t h thng c th c trao i gia cc nh thit k s dng cng c thit k
khc nhau nhng cng tun theo tiu chun VHDL. Cng nh mt nhm thit
k c th trao i m t mc cao ca cc h thng con trong mt h thng ln
(trong cc h con c thit k c lp).
-
Th su l kh nng h tr thit k mc ln v kh nng s dng li

cc thit k:
VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c

th c s dng thit k mt h thng ln vi s tham gia ca mt nhm
nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun
l, th nghim v chia s thit k. V n cng cho php dng li cc phn c
sn.
1.2.
Gii thiu cng ngh (v ng dng) thit k mch bng VHDL.
1.2.1 ng dng ca cng ngh thit k mch bng VHDL

Hin nay 2 ng dng chnh v trc tip ca VHDL l cc ng dng
trong cc thit b logic c th lp trnh c (Programmable Logic Devices
PLD) (bao gm cc thit b logic phc tp c th lp trnh c v cc FPGA Field Programmable Gate Arrays) v ng dng trong ASICs(Application
Specific Integrated Circuits).
Khi chng ta lp trnh cho cc thit b th chng ta ch cn vit m
VHDL mt ln, sau ta c th p dng cho cc thit b khc nhau (nh Altera,
Xilinx, Atmel,) hoc c th ch to mt con chip ASIC. Hin nay, c
nhiu thng mi phc tp (nh cc vi iu khin) c thit k theo da trn
ngn ng VHDL.
1.2.2 Quy trinh thit k mch bng VHDL.
Nh cp trn, mt trong s ln cc ng dng ca VHDL l ch to
cc mch hoc h thng trong thit b c th lp trnh c (PLD hoc FPGA)
hoc trong ASIC. Vic ch tao ra vi mch s c chia thnh 3 giai on nh
sau:
-
Giai on 1:

Nhm 4
Chng ta bt u thit k bng vit m VHDL. M VHDL ny s c
lu vo file c ui l .vhd v c tn cng vi tn thc th. M VHDL s c
m t tng chuyn i thanh ghi.
Hnh 1.1. Tm tt quy trnh thit k VHDL

-
Giai on 2: Giai on ch to:
Bc u tin trong qu trnh ch to l bin dich. Qu trnh bin dch s

chuyn m VHDL vo mt netlist tng cng.
Bc th 2 ca qu trnh ch to l ti u. Qu trnh ti u c thc
hin trn netlist tng cng v tc v phm vi.
Trong giai on ny, thit k c th c m phng kim tra pht
hin nhng li xy ra trong qu trnh ch to.
-
Giai on 3:
L giai on ghp ni ng gi phn mm. giai on ny s to ra s

sp xp vt l cho chip PLD/FPGA hoc to ra mt n cho ASIC.
1.2.3. Cng c EDA.
-
Cc cng c phc v cho qu trnh thit k vi mch s l:

Cng c Active HDL: To m VHDL v m phng

Nhm 4
Cng c EDA (Electronic Design Automation): l cng c t ng thit
k mch in t. Cng c ny c dng phc v cho vic ch to, thc thi
v m phng mch s dng VHDL.
Cng c cho ng gi: Cc cng c ny s cho php tng hp m
VHDL vo cc chip CPLD/FPGA ca Altera hoc h ISE ca Xilinx, for
Xilinxs CPLD/FPGA chips).
1.2.4. Chuyn m VHDL vo mch.
Mt b cng y c m t trong hnh di y:
Hinh 1.2.a. S tng qut v b cng y

Trong , a , b l cc bit vo cho b cng, cin l bit nh. u ra s l bit
tng, cout l bit nh ra. Hot ng ca mch c ch ra di dng bng chn
l:
Hnh 1.2.b. Bng chn l ca b cng y

Bit s v cout c tnh nh sau:
v
T cng thc tnh s v cout ta vit on m VHDL nh di y:

Nhm 4
Hnh 1.3. M thit k b cng

T m VHDL ny, mch vt l c to ra. Tuy nhin c nhiu cch
thc hin phng trnh c miu t trong ARCHITECTURE OF, v vy mch
thc t s ph thuc vo b bin dch/b ti u ang c s dng v c bit
ph thuc mc ch cng ngh. Hnh v sau y th hin mt s dng kin trc
ca mch cng:
Hnh 1.4.a. Cc v d v s mch c th c ng vi m nh hnh 1.3

Nhm 4
Trong trng hp ny, nu mc ch cng ngh ca chng ta l thit b
lgic c th lp trnh c (PLD, FPGA), th 2 kt qu cho cout tho mn l
hnh (b) v hnh (c) (
). Cn nu mc ch cng ngh l
ASIC, th chng ta c th s dng hnh (d). Hnh D s dng cng ngh CMOS
vi cc tng transistor v cc mt n ph.
Bt c mt ci mch no c tao ra t m, th nhng thao tc ca n s
lun lun c kim tra mc thit k, nh ta ch ra hnh 1. Tt nhin,
chng ta cng c th kim tra n tng vt l, nhng sau nhng thay i l
rt tai hi.
Hnh di y l m phng kt qu ca on chng trnh vit trn
cho mch b cng y hnh 1.3.
Hnh 1.4.b: Kt qu m phng b cng c thit k theo hnh 1.3

Nhm 4
Chng 2. Cu trc m
Trong chng ny, chng ta m t cc phn c bn c cha c cc on
Code nh ca VHDL: cc khai bo LIBRARY, ENTITY v ARCHITECTURE.
2.1.
Cc n v VHDL c bn.
Mt an Code chun ca VHDL gm ti thiu 3 mc sau:

Khai bo LIBRARY: cha mt danh sch ca tt c cc th vin c
s dng trong thit k. V d: ieee, std, work,
ENTITY: M t cc chn vo ra (I/O pins) ca mch
ARCHITECTURE: cha m VHDL, m t mch s hat ng nh th
no.
Mt LIBRARY l mt tp cc an Code thng c s dng. Vic c
mt th vin nh vy cho php chng c ti s dng v c chia s cho cc
ng dng khc. M thng c vit theo cc nh dng ca FUNCTIONS,
PROCEDURES, hoc COMPONENTS, c thay th bn trong PACKAGES
v sau c dch thnh th vin ch.
2.2.
Khai bo Library.
- khai bo Library, chng ta cn hai dng m sau, dng th nht cha

tn th vin, dng tip theo cha mt mnh cn s dng:
LIBRARY library_name;
USE library_name.package_name.package_parts;
Thng thng c 3 gi, t 3 th vin khc nhau thng c s dng trong
thit k:
ieee.std_logic_1164 (from the ieee library),
standard (from the std library), and
work (work library).

Nhm 4
Hnh 2.1: Cc thnh phn c bn ca mt on m VHDL
Hnh 2.2: Cc phn c bn ca mt Library

Cc khai bo nh sau:
LIBRARY ieee;
-- Du chm phy (;) ch th
USE ieee.std_logic_1164.all;-- kt ca mt cu lnh
LIBRARY std;
-- hoc mt khai bo.mt du 2 gch
USE std.standard.all;
-- (--) bt u 1 ch thch.
LIBRARY work;
USE work.all;
Cc th vin std v work thng l mc nh, v th khng cn khai bo

chng, ch c th vin ieee l cn phi c vit r ra.
Mc ch ca 3 gi/th vin c k trn l nh sau: gi
std_logic_1164 ca th vin ieee cho bit mt h logic a mc; std l mt th
vin ti nguyn (kiu d kiu, i/o text..) cho mi trng thit k VHDL v th
vin work c s dng khi chng ta lu thit k ( file .vhd, cc file c top
bi chng trnh dch v chng trnh m phng).
Thc ra, th vin ieee cha nhiu gi nh sau:
10

Nhm 4
std_logic_1164: nh r STD_LOGIC ( 8 mc) v STD_ULOGIC
( 9 mc) l cc h logic a mc
std_logic_arith: nh r cc kiu d liu SIGNED v UNSIGNED,
cc gii thut lin quan v so snh ton t. N cng cha nhiu hm
chuyn i d liu, m cho php mt kiu c chuyn i thnh
cc kiu d liu khc: conv_integer(p),conv_unsigned(p, b),
conv_signed(p, b), conv_std_logic_vector(p, b)
std_logic_signed: cha cc hm cho php lm vic vi d liu
STD_LOGIC_VECTOR c thc hin ch khi d liu l kiu
SIGNED
std_logic_signed: cha cc hm cho php lm vic vi d liu
STD_LOGIC_VECTOR c thc hin ch khi d liu l kiu
UNSIGNED.
2.3.
Entity ( thc th).
Mt ENTITY l mt danh sch m t cc chn vo/ra ( cc PORT) ca

mch in. C php nh sau:
ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
...);
END entity_name;
Ch ca tn hiu ( mode of the signal) c th l IN, OUT, INOUT

hoc BUFFER. V d trong hnh 2.3 ta c th thy r cc chn IN, OUT ch c
mt chiu (vo hoc ra) trong khi INOUT l 2 chiu v BUFFER li khc, tn
hiu ra phi c s dng t d liu bn trong.
Kiu ca tn hiu ( type of the signal) c th l BIT, STD_LOGIC,
INTEGER,
Tn ca thc th ( name of the entity) c th ly mt tn bt k, ngai
tr cc t kha ca VHDL.
V d: Xt cng NAND hnh 2.4, khai bo ENTITY nh sau:
ENTITY nand_gate IS
PORT (a, b : IN BIT;
x : OUT BIT);
END nand_gate;
Hnh 2.3. Cc ch tn hiu
Hnh 2.4. Cng NAND

11

Nhm 4
2.4.
ARCHITECTURE ( cu trc).
ARCHITECTURE l mt m t mch dng quyt mch s lm vic

nh th no ( c chc nng g).
C php nh sau:
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END architecture_name;
Nh thy trn, mt cu trc c 2 phn: phn khai bo ( chc nng),

ni cc tn hiu v cc hng c khai bo, v phn m (code - t BEGIN tr
xung).
V d: Xt tr li cng NAND ca hnh 2.4
ARCHITECTURE myarch OF nand_gate IS
BEGIN
x <= a NAND b;
END myarch;
ngha ca ARCHITECTURE trn l nh sau: mch phi thc hin

cng vic NAND 2 tn hiu vo (a,b) v gn (<=) kt qu cho chn ra x.
Mi mt khai bo thc th u phi i km vi t nht mt kin trc tng ng.
VHDL cho php to ra hn mt kin trc cho mt thc th. Phn khai bo kin
trc c th bao gm cc khai bo v cc tn hiu bn trong, cc phn t bn
trong h thng, hay cc hm v th tc m t hot ng ca h thng. Tn ca
kin trc l nhn c t tu theo ngi x dng. C hai cch m t kin trc
ca mt phn t ( hoc h thng) l m hnh hot ng (Behaviour) hay m
t theo m hnh cu trc (Structure). Tuy nhin mt h thng c th bao gm c
m t theo m hnh hot ng v m t theo m hnh cu trc.
+
M t kin trc theo m hnh hot ng:
M hnh hot ng m t cc hot ng ca h thng (h thng p ng

vi cc tn hiu vo nh th no v a ra kt qu g ra u ra) di dng cc
cu trc ngn ng lp trnh bc cao. Cu trc c th l PROCESS , WAIT,
IF, CASE, FOR-LOOP
V d:
ARCHITECTURE behavior OF nand IS
-- Khai bo cc tn hiu bn trong v cc b danh
BEGIN
c <= NOT(a AND b);
END behavior;
V d2:
ARCHITECTURE behavioral of decode2x4 is
BEGIN
12

Nhm 4
Process (A,B,ENABLE)
Variable ABAR,BBAR: bit;
Begin
ABAR := not A;
BBAR := not B;
If ENABLE = 1 then
Z(3) <= not (A and B);
Z(0) <= not (ABAR and BBAR);
Z(2) <= not (A and BBAR);
Z(1) <= not (ABAR and B);
Else
Z <= not (ABAR and B);
End if;
End process;
END arc_behavioral;
M t kin trc theo m hnh cu trc:
M hnh cu trc ca mt phn t (hoc h thng) c th bao gm nhiu

cp cu trc bt u t mt cng logic n gin n xy dng m t cho mt h
thng hon thin. Thc cht ca vic m t theo m hnh cu trc l m t cc
phn t con bn trong h thng v s kt ni ca cc phn t con .
M t c php:
architecture identifier of entity_name is
Architecture_declarative_part
begin
all_concurrent_statements
end
[architecture][architecture_simple_name];
Khai bo cc thnh phn:
Component
Tn_componemt port [ danh sch ];
End component;
Nh vi v d m t m hnh cu trc mt flip-flop RS gm hai cng

NAND c th m t cng NAND c nh ngha tng t nh v d vi cng
NOT, sau m t s mc ni cc phn t NAND to thnh trig RS
V d1:
Hnh 2.5.a. S ca trigo RS

ENTITY rsff IS
PORT( r : IN std_logic;
s : IN std_logic;
13

Nhm 4
q : OUT std_logic;
qb : OUT std_logic);
END rsff;
ARCHITECTURE kien_truc OF rsff IS
COMPONENT nand
-- nh ngha cng nand
GENERIC(delay : time);
PORT(a : IN std_logic;
b : IN std_logic;
c : OUT std_logic);
END COMPONENT;
BEGIN
u1: nand
-- ci t u1 l thnh phn nand
GENERIC MAP(5 ns) -- gi tr delay c th thay i
values
PORT MAP(s, qb, q);
-- bn I/O cho thnh phn
u2: nand
-- thit lp u2 l thnh phn nand
GENERIC MAP(5 ns)
PORT MAP(q, r, qb);
END kien_truc;
V d2:
Architecture arc_mach_cong of mach_cong is
Component Xor
Port( X,Y : in bit ; Z, T : out bit);
End component;
Component And
Port(L,M :input ;N,P : out bit );
End component;
Begin
G1 : Xor port map (A,B,Sum);
G2 : And port map (A, B, C);
End arc_mach_cong;
M t kin trc theo m hnh tng hp

l m hnh kt hp ca 2 m hnh trn.
V d:
Entity adder is
Port (A,B,Ci : bit
S, Cout : bit);
End adder;
Architecture arc_mixed of adder is
Component Xor2
Port( P1, P2 : in bit;
PZ : out bit);
End compenent;
Signal S1 :bit;
Begin
X1 : Xor2 port map(A,B,S1);
Process (A,B,Cin)
Variable T1,T2,T3 : bit;
Begin
14

Nhm 4
T1 := A and B;
T2 := B and Cin ;
T3 :=
A and Cin;
Cout := T1 or T2 or T3 ;
End process;
End arc_mixed ;
2.5.
Cc v d m u.
Trong mc ny, chng ta s trnh by 2 v d u tin v m VHDL. Mi

v d u c theo km bi cc ch thch din gii v cc kt qu m phng.
V d 2.1: DFF vi Reset khng ng b:
Hnh 2.5.b. S ca DFF khng ng b

Hnh 2.5.b cho thy s ca mt flip-flop loi D (DFF), xung c
kch theo sn ca tn hiu ng h (clk), v vi mt tn hiu u vo reset
khng ng b (rst). Khi rst = 1, u ra lun mc thp bt k clk. Ngc
li, u ra s copy u vo ( q<=d) ti thi im khi clk chuyn t 0 ln 1.
C nhiu cch thc hin DFF ca hnh 2.5, mt gii php s c
trnh by di y. S dng mt PROCESS cho an m sau y:
1
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3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
--------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
--------------------------------------ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END behavior;
15

Nhm 4
21
---------------------------------------
(Ch : VHDL khng phn bit ch hoa v ch thng.)

* Kt qu m phng:
Hnh 2.6: Kt qu m phng ca v d 2.1

Hnh 2.6 m phng kt qu t v d 2.1, th c th c gii thch d
dng. Ct u tin cho bit tn ca tn hiu, nh c inh ngha trong
ENTITY. N cng cho bit ch ( hng) ca tn hiu, lu rng cc mi tn
ng vi rst, d v clk hng vo trong, y l pha input, cn q hng ra ngoi
tng ng vi pha output. Ct th hai cha gi tr ca mi tn hiu v tr
tng ng vi ni con tr tr ti. Trong trng hp hin ti, con tr 0ns v
tn hiu nhn gi tr (1,0,0,0). Ct th 3 cho thy s m phng ca ton b qu
trnh. Cc tn hiu vo (rst, d, clk) c th c chn mt cch t do v b m
phng s xc nh tn hiu ng ra tng ng.
V d 2.2: DFF kt hp vi cng NAND
Mch in hnh 2.7 l s kt hp ca 2 hnh 2.4 v 2.5. Trong li gii
sau y, chng ta gii thiu mt cch c ch nh mt tn hiu khng cn
thit (temp), ch minh ha mt tn hiu s c khai bo nh th no.
Hnh 2.7. DFF kt hp vi cng NAND

M thit k:
--------------------------------------ENTITY example IS
PORT ( a, b, clk: IN BIT;
q: OUT BIT);
END example;
--------------------------------------ARCHITECTURE example OF example IS
SIGNAL temp : BIT;
BEGIN
temp <= a NAND b;
PROCESS (clk)
BEGIN
16

Nhm 4
IF (clk'EVENT AND clk='1') THEN q<=temp;
END IF;
END PROCESS;
END example;
---------------------------------------
Kt qu m phng t mch DFF kt hp vi NANDtrn hnh 2.8:
Hnh 2.8. Kt qu m phng ca v d 2.2
Chng 3: Kiu d liu

vit m VHDL mt cch hiu qu, tht cn thit bit rng cc kiu
d liu no c cho php, lm th no nh r v s dng chng. Trong
chng ny, tt c cc kiu d liu c bn s c m t.
3.1.
Cc kiu d liu tin nh ngha.
VHDL bao gm mt nhm cc kiu d liu tin nh ngha, c nh

r thng qua cc chun IEEE 1076 v IEEE 1164. C th hn, vic nh ngha
kiu d liu nh th c th tm thy trong cc gi/ th vin sau:
Gi standard ca th vin std: nh ngha cc kiu d liu BIT,

BOOLEAN, INTEGER v REAL.
Gi std_logic_1164 ca th vin ieee: nh ngha kiu d liu

STD_LOGIC v STD_ULOGIC.
Gi std_logic_arith ca th vin ieee: nh ngha SIGNED v

UNSIGNED, cng thm nhiu hm chuyn i d liu v d:
conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), v
conv_std_logic_vector(p, b).
Gi std_logic_signed v std_logic_unsigned ca th vin ieee: Cha

cc hm cho php hat ng vi d liu STD_LOGIC_VECTOR
c thc hin khi m kiu d liu l SIGNED hc UNSIGNED.
Tt c cc kiu d liu tin nh ngha nu trn c m t nh sau:

+
BIT v BIT_VECTOR: 2 mc logic (0, 1).

V d:
SIGNAL x: BIT;
17

Nhm 4
-- x c khai bo nh mt tn hiu s kiu BIT.
SIGNAL y: BIT_VECTOR (3 DOWNTO 0);
-- y l mt vec t 4 bit, vi bit bn tri nht c gi l MSB.
SIGNAL w: BIT_VECTOR (0 TO 7);
-- w l mt vc t8 bit, pha bn phi nht c gi l MSB
Da vo cc tn hiu trn, cc php gn sau y l hp l ( gn mt
gi tr n mt tn hiu, ton t <= c s dng):
x <= 1;
y <= 0111;
z <= 01110001;
+
STD_LOGIC ( v STD_LOGIC_VECTOR):
H logic 8 gi tr sau y c gii tiu trong chun IEEE 1164:
X khng xc nh ( bt buc)
0
mc thp ( bt buc)
1
mc cao ( bt buc)
Z tr khng cao
W khng xc nh (yu)
L
mc thp ( yu)
H mc cao ( yu)
-
khng quan tm
V d:
SIGNAL x: STD_LOGIC;
-- x c khai bo nh mt k t s ( v hng), tn hiu thuc
kiu STD_LOGIC
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";
-- y c khai bo nh mt vector 4-bit, vi bit bn tri cng l
-- MSB. Gi tr khi u ca y l "0001". Lu
-- rng ton t ":=" c s dng thit lp gi tr khi u.
Hu ht cc mc std_logic l v hng ch i vi qu trnh m phng.

Tuy nhin 0, 1 v Z l c th kt hp khng hn ch. i vi cc gi tr
weak, chng c gii quyt trong s u tin ca cc gi tr forcing trong
cc nt a chiu ( Bng 3.1). Tht vy, nu 2 tn hiu std_logic bt k c ni
n cng mt node, th cc mc logic i lp c t ng gii quyt theo
Bng 3.1
18

Nhm 4
Bng 3.1. H thng logic gii c

+
STD_ULOGIC( STD_ULOGIC_VECTOR): h thng logic 9 mc trong
chun IEEE 1164: (U, X, 0, 1, Z, W, L, H, ). Tht vy, h
STD_LOGIC m t trn l mt tp con ca STD_ULOGIC. H thng th 2
ny thm gi tr logic U.
BOOLEAN: ng/sai
INTEGER: s nguyn 32 bits ( t -2.147.483.647 n
+2.147.483.647)
NATURAL: ms nguyn khng m ( t 0 n +2.147.483.647)
REAL: s thc nm trong khong ( t -1.0E38 n +1.0E38).
Physic literals: s dng i vi cc i lng vt l, nh thi gian,
in p,Hu ch trong m phng
Character literals: k t ASCII n hoc mt chui cc k t nh th
SIGNED v UNSIGNED: cc kiu d liu c nh ngha trong gi
std_logic_arith ca th vin ieee. Chng c hnh thc ging nh
STD_LOGIC_VECTOR, nhng ngai tr cc ton t s hc, m tiu
biu l kiu d liu INTEGER
Cc v d:
x0 <= '0';
-- bit, std_logic, or std_ulogic value '0'
x1 <= "00011111"; -- bit_vector, std_logic_vector,
-- std_ulogic_vector, signed, or unsigned
x2 <= "0001_1111"; -- ng gch di cho php d hnh dung
hn
x3 <= "101111"
-- biu din nh phn ca s thp phn 47
x4 <= B"101111" -- nh trn
x5 <= O"57"
-- biu din bt phn ca s thp phn 47
x6 <= X"2F"
-- biu din s thp lc phn ca s thp
phn 47
n <= 1200;
-- s nguyn
m <= 1_200;
-- s nguyn, cho php gch di
IF ready THEN... -- Logic, thc hin nu ready=TRUE
y <= 1.2E-5;
-- real, not synthesizable
q <= d after 10 ns; -- physical, not synthesizable
19

Nhm 4
V d: Cc ton t c php v khng c php nm gia cc kiu d liu
khc nhau:
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
...
a <= b(5); -- c php (cng kiu v hng: BIT)
b(0) <= a; -- c php (cng kiu v hng: BIT)
c <= d(5); -- c php (cng kiu v hng: STD_LOGIC)
d(0) <= c; -- c php (cng kiu v hng: STD_LOGIC)
a <= c; -- khng c php (khng th kt hp kiu: BIT x
STD_LOGIC)
b <= d; -- khng c php (khng th kt hp kiu:
BIT_VECTOR x
-- STD_LOGIC_VECTOR)
e <= b; -- khng c php (khng th kt hp kiu: INTEGER x
BIT_VECTOR)
e <= d; -- khng c php (khng th kt hp kiu: INTEGER x
3.2.
Cc kiu d liu ngi dng nh ngha.
VHDL cng cho php ngi dng t nh ngha cc kiu d liu. Hai
loi kiu d liu ngi dng nh ngha c ch ra di y bao gm integer
v enumerated.
Kiu integer ngi dng nh ngha:
TYPE integer IS RANGE -2147483647 TO +2147483647;
-- Thc ra kiu ny c nh ngha trc bi kiu INTEGER.
TYPE natural IS RANGE 0 TO +2147483647;
-- Thc ra kiu ny c nh ngha trc bi kiu
NATURAL.
TYPE my_integer IS RANGE -32 TO 32;
-- Mt tp con cc s integer m ngi dng nh ngha.
TYPE student_grade IS RANGE 0 TO 100;
-- Mt tp con cc s nguyn hoc s t nhin ngi dng nh
ngha.
_ Cc kiu m ngi dng inh ngha:
TYPE bit IS ('0', '1');
-- c nh ngha trc bi kiu BIT
TYPE my_logic IS ('0', '1', 'Z');
20

Nhm 4
-- Mt tp con ca std_logic m ngi dng nh ngha
TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT;
-- c nh ngha trc bi BIT_VECTOR.
-- RANGE <> c s dng ch th rng cc mc.khng gii
hn.
-- NATURAL RANGE <>, on the other hand, indicates that the
only
-- restriction is that the range must fall within the NATURAL
-- range.
TYPE state IS (idle, forward, backward, stop);
-- Mt kiu d liu , in hnh ca cc my trng thi hu hn.
TYPE color IS (red, green, blue, white);
-- Kiu d liu lit k khc.
Vic m ha cc kiu lit k c thc hin mt cch tun t v t
ng.
V d: Cho kiu mu nh trn, m ha cn 2 bit ( c 4 trng thi),
bt u 00 c gn cho trng thi u tin ( red), 01 c gn cho trng
thi th hai (green), 10 k tip (blue) v cui cng l trng thi 11 (while).
3.3.
Cc kiu con (Subtypes).
Kiu d liu con l mt kiu d liu i km theo iu kin rng buc.

L do chnh cho vic s dng kiu d liu con sau nh ra mt kiu d
liu mi l, cc thao tc gia cc kiu d liu khc nhau khng c cho
php, chng ch c cho php trong trng hp gia mt kiu con v kiu c
s tng ng vi n.
V d: kiu d liu sau y nhn c cc kiu d liu c gii thiu
trong cc v d phn trc.
SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH;
-- NATURAL is a kiu con (tp con) of INTEGER.
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z';
-- Gi li STD_LOGIC=('X','0','1','Z','W','L','H','-').
-- Do , my_logic=('0','1','Z').
SUBTYPE my_color IS color RANGE red TO blue;
-- khi color=(red, green, blue, white), th
-- my_color=(red, green, blue).
SUBTYPE small_integer IS INTEGER RANGE -32 TO 32;
-- Mt tp con ca INTEGER.
Example: Cc php ton hp l v khng hp l gia cc kiu d liu v
cc kiu d liu con.
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';
SIGNAL a: BIT;
SIGNAL b: STD_LOGIC;
SIGNAL c: my_logic;
21

Nhm 4
...
b <= a; --khng hp l (khng th kt hp kiu: BIT vi STD_LOGIC)
b <= c; --hp l (cng kiu c s: STD_LOGIC)
3.4.
Mng (Arrays).
Mng l mt tp hp cc i tng c cng kiu. Chng c th l mt

chiu (1D), 2 chiu (2D) hc mt chiu ca mt chiu (1D x 1D) v cng c
th c nhng kch thc cao hn.
Hnh 3.1 minh ha vic xy dng mt mng d liu. Mt gi tr n ( v
hng c ch ra (a), mt vector ( mng 1D) (b) v mt mng cc vector (
mng 1Dx1D) (c) v mng ca mng 2D nh trong (d)
Tht vy, cc kiu d liu VHDL c nh ngha trc (mc 3.1)
ch bao gm cc i lng v hng-scalar ( bit n) v vector ( mng mt
chiu cc bit). Cc kiu d liu c th kt hp trong mi loi ny l nh di
y:
_ Scalars: BIT, STD_LOGIC, STD_ULOGIC, and BOOLEAN.
_
Vectors:
BIT_VECTOR,
STD_LOGIC_VECTOR,
STD_ULOGIC_VECTOR,
INTEGER, SIGNED, and UNSIGNED.
Hnh 3.1: Minh ha scalar (a), 1D (b), 1Dx1D (c), v 2D (d)

Nh c th thy, khng h c nh ngha trc mng 2D hoc 1Dx1D,
m khi cn thit, cn phi c ch nh bi ngi dng. lm nh vy, mt
kiu mi (new TYPE) cn phi c nh ngha u tin, sau l tn hiu mi
(new SIGNAL), new VARIABLE hc CONSTANT c th c khai bo s
dng kiu d liu . C php di y s c dng:
ch nh mt kiu mng mi:
TYPE type_name IS ARRAY (specification) OF data_type;
to s dng kiu mng mi:
SIGNAL signal_name: type_name [:= initial_value];
Trong c php trn, mt SIGNAL c khai bo. Tuy nhin n cng
c th l mt CONSTANT hoc mt VARIABLE. Gia tr khi to ty chn.
* V d mng 1Dx1D:
Chng ta mun xy dng mt mng cha 4 vector, mi vector c kch
thc l 8 bit, l mt mng 1Dx1D ( hnh 3.1). Ta gi mi vector l hng
(row) v mng hon chnh l ma trn (matrix). Hn na, chng ta mun bit bn
22

Nhm 4
tri cng ca mi vector tr thnh MSB ( most significant bit) ca n, v dng
trn cng tr thnh dng 0. Khi s thc hin y mng s l nh sau:
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array
TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array
SIGNAL x: matrix; -- 1Dx1D signal
* V d mng 1Dx1D khc:
Cch khc xy dng mng 1Dx1D trn cn c thc hin nh
sau:
TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7
DOWNTO 0);
* V d mng 2D:
Mng sau y thc s l hai chiu. Lu rng vic xy dng n da
trn cc vector, nhng kh hon chnh trn cc i lng v hng.
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
-- 2D array
* Khi u cho mng:
Nh thy trong c php trn, gi tr khi u ca mt SIGNAL
hoc VARIABLE l ty chn. Tuy nhin, khi vic khi u gi tr c i hi,
n c th c thc hin nh trong v d pha di y:
... :="0001";
-- for 1D array
... :=('0','0','0','1')
-- for 1D array
... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or-- 2D array
* V d: Cc php gn mng hp l v khng hp l
Php gn trong v d ny c da trn nh ngha kiu v khai bo cc
tn hiu nh sau:
TYPE row IS ARRAY (7 DOWNTO 0)OF STD_LOGIC;
-- 1D array
TYPE array1 IS ARRAY (0 TO 3) OF row;
-- 1Dx1D array
TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7
DOWNTO 0);
-- 1Dx1D
TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
-- 2D array
SIGNAL x: row;
SIGNAL y: array1;
SIGNAL v: array2;
SIGNAL w: array3;
23

Nhm 4
--------- Cc php gn v hng hp l: ---------------- Cc php gn i lng v hng (bit n) di y l hp l,
-- bi v kiu ( v hng) c bn l STD_LOGIC cho tt c cc tn hiu
-- (x,y,v,w).
x(0) <= y(1)(2); -- lu 2 cp du ngoc n
-- (y is 1Dx1D)
x(1) <= v(2)(3); -- 2 cp du ngoc n (v is 1Dx1D)
x(2) <= w(2,1); -- 1 cp du ngoc n (w is 2D)
y(1)(1) <= x(6);
y(2)(0) <= v(0)(0);
y(0)(0) <= w(3,3);
w(1,1) <= x(7);
w(3,0) <= v(0)(3);
--------- Gn vector: --------------------x <= y(0);

-- hp l (cng kiu: ROW)
x <= v(1);
-- khng hp l (khng ph hp kiu: ROW v
x <= w(2);
-- khng hp l (w phi l 2D)
x <= w(2,2 DOWNTO 0);--khng hp l (khng ph hp kiu: ROW x
-- STD_LOGIC)
v(0)<=w(2,2 DOWNTO 0);--illegal(mismatch: STD_LOGIC_VECTOR
-- x STD_LOGIC)
v(0) <= w(2);
-- illegal (w must have 2D index)
y(1) <= v(3);
-- illegal (type mismatch: ROW x
y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0); -- legal (same type,
-- same size)
v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0); -- legal (same type,
-- same size)
w(1,5 DOWNTO 1)<=v(2)(4 DOWNTO 0);-- illegal (type
mismatch)
3.5.
Mng cng ( Port Array).
Nh chng ta bit, khng c kiu d liu c nh ngha trc no

c hn mt chiu. Tuy nhin, trong cc c im ca cc chn vo hoc ra (cc
PORT) ca mt mch in ( m c xy dng thnh ENTITY), chng ta c
th phi cn nh r cc PORT nh l mng cc VECTOR
Khi cc khai bo TYPE khng c cho php trong mt ENTITY, gii
php khai bo kiu d liu ngi dng nh ngha trong mt PACKAGE, m
c th nhn bit ton b thit k. Mt v d nh sau:
------- Package: -------------------------LIBRARY ieee;
---------------------------PACKAGE my_data_types IS
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR(7 DOWNTO 0);
24

Nhm 4
END my_data_types;
-------------------------------------------------- Main code: ------------------------LIBRARY ieee;
USE work.my_data_types.all; -- user-defined package
--------------------------ENTITY mux IS
PORT (inp: IN VECTOR_ARRAY (0 TO 3);
... );
END mux;
... ;
--------------------------------------------
C th thy trong v d trn, mt kiu d liu ngi dng nh ngha

c gi l vector_array, c to ra, m n c th cha mt s khng xc
nh cc vector, mi vector cha 8 bit. Kiu d liu c lu gi trong mt
PACKAGE gi l my_data_types, v sau c s dng trong mt ENTITY
xc nh mt PORT c gi. Ch trong on m chnh bao gm thm c
mt mnh USE thc hin gi ngi dng nh ngha my_data_types c
th thy trong thit k.
Chc nng khc cho PACKAGE trn s c trnh by di y, ni
m c khai bo CONSTANT:
------Package:
------------------------------LIBRARY ieee;
---------------------------PACKAGE my_data_types IS
CONSTANT b: INTEGER := 7;
TYPE vector_array IS ARRAY (NATURAL RANGE <>)
OF
STD_LOGIC_VECTOR(b DOWNTO 0);
END my_data_types;
----------------------------------------------
3.6.
Kiu bn ghi (Records).
Bn ghi tng t nh mng, vi im khc rng chng cha cc i

tng c kiu d liu khc nhau.
V d:
TYPE birthday IS RECORD
day: INTEGER RANGE 1 TO 31;
month: month_name;
END RECORD;
3.7.
Kiu d liu c du v khng du ( Signed and Unsigned).
25

Nhm 4
Nh cp trc y, cc kiu d liu ny c nh ngha trong gi
std_logic_arith ca th vin ieee. C php ca chng c minh ha trong v
d di y:
V d:
SIGNAL x: SIGNED (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3);
Lu rng c php ca chng tng t vi STD_LOGIC_VECTOR,

khng ging nh INTEGER.
Mt gi tr UNSIGNED l mt s khng bao gi nh hn zero. V d,
0101 biu din s thp phn 5, trong khi 1101 l 13. Nhng nu kiu
SIGNED c s dng thay vo, gi tr c th l dng hoc m ( theo nh
dng b 2). Do , 0101 vn biu din s 5, trong khi 1101 s biu din s
-3
s dng kiu d liu SIGNED hoc UNSIGNED, gi
std_logic_arith ca th vin ieee, phi c khai bo. Bt chp c php ca
chng, kiu d liu SIGNED v UNSIGNED c hiu qu ch yu i vi cc
php ton s hc, ngha l, ngc vi STD_LOGIC_VECTOR, chng chp
nhn cc php ton s hc. mt kha cnh khc, cc php ton logic th
khng c php.
* V d:
Cc php ton hp l v khng hp l i vi kiu d liu
signed/unsigned:
LIBRARY ieee;
USE ieee.std_logic_arith.all;
-- gi cn thit
thm vo
...
SIGNAL a: IN SIGNED (7 DOWNTO 0);
SIGNAL b: IN SIGNED (7 DOWNTO 0);
SIGNAL x: OUT SIGNED (7 DOWNTO 0);
...
v <= a + b;
-- hp l (php ton s hc
OK)
w <= a AND b;
-- khng hp l (php ton logic
khng OK)
Cc php ton hp l v khng hp l vi std_logic_vector:

LIBRARY ieee;
USE ieee.std_logic_1164.all; -- khng thm gi i
hi
...
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
26

Nhm 4
v <= a + b;
-- khng hp l (php
ton s hc khng OK)
w <= a AND b;
-- hp l (php ton logic OK)
* V d: Cc php ton s hc vi std_logic_vector

LIBRARY ieee;
USE ieee.std_logic_unsigned.all; -- bao gm gi thm
vo
...
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v <= a + b;
-- hp l (php ton s hc
OK), khng du
w <= a AND b;
-- hp l (php ton logic OK).
3.8.
Chuyn i d liu.
VHDL khng cho php cc php ton trc tip ( s hc, logic, ) tc
ng ln cc d liu khc kiu nhau. Do , thng l rt cn thit i vi vic
chuyn i d liu t mt kiu ny sang mt kiu khc. iu ny c th c
thc hin trong hai cch c bn: hoc chng ta vit mt t code cho iu ,
hoc chng ta gi mt FUNCTION t mt gi c nh ngha trc m n
cho php thc hin cc php bin i cho ta.
Nu d liu c quan h ng ( ngha l 2 ton hng c cng kiu c
s, bt chp ang c khai bo thuc v hai kiu lp khc nhau), th
std_logic_1164 ca th vin ieee cung cp cc hm chuyn i d thc hin.
* V d: cc php ton hp l v khng hp l i vi cc tp con
TYPE long IS INTEGER RANGE -100 TO 100;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;
...
y <= 2*x + 5;
-- li, khng ph hp kiu
y <= long(2*x + 5);
-- OK, kt qu c chuyn i
thnh kiu long
Nhiu hm chuyn i d liu c th c tm trong gi std_logic_arith

ca th vin ieee:
o conv_integer(p): chuyn i mt tham s p ca kiu INTEGER,
UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr

INTEGER. Lu rng STD_LOGIC_VECTOR khng c k n.
27

Nhm 4
o conv_unsigned(p, b): chuyn i mt tham s p ca kiu INTEGER,

UNSIGNED vi kch c l b bit.
o conv_signed(p, b): chuyn i mt tham s p ca kiu INTEGER,
SIGNED vi kch c l b bits.
o conv_std_logic_vector(p, b): chuyn i mt tham s p thuc kiu
d liu INTEGER, UNSIGNED, SIGNED, hoc STD_LOGIC thnh
mt gi tr STD_LOGIC_VECTOR vi kch thc b bits.
* V d: chuyn i d liu:
LIBRARY ieee;
...
SIGNAL a: IN UNSIGNED (7 DOWNTO 0);
SIGNAL b: IN UNSIGNED (7 DOWNTO 0);
SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
-- Php ton hp l: a+b c chuyn i t UNSIGNED
thnh mt
-- gi tr 8-bit STD_LOGIC_VECTOR, sau gn cho y.
Mt cch khc c th chn c cp n trong mc trc y. N

bao gm vic s dng cc gi std_logic_signed v std_logic_unsigned t th
vin ieee. Cc gi ny cho php cc php ton vi d liu
STD_LOGIC_VECTOR c thc hin nu d liu l kiu SIGNED hoc
UNSIGNED, mt cch ln lt.
3.9. Tm tt.
Cc kiu d liu VHDL tng hp c bn c tm tt trong bng 3.2
28

Nhm 4
Bng 3.2. Tng hp cc kiu d liu.

3.10. Cc v d.
* V d 3.1: S phn chia i vi cc kiu d liu
Cc php gn hp l v khng hp l c trnh by k tip c da
trn cc nh ngha kiu v cc khai bo tn hiu sau y:
TYPE byte IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D
-- array
TYPE mem1 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D
-- array
TYPE mem2 IS ARRAY (0 TO 3) OF byte; -- 1Dx1D
-- array
TYPE mem3 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(0 TO 7); -- 1Dx1D
-- array
SIGNAL a: STD_LOGIC; -- scalar signal
SIGNAL b: BIT; -- scalar signal
SIGNAL x: byte; -- 1D signal
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); -- 1D signal
SIGNAL v: BIT_VECTOR (3 DOWNTO 0); -- 1D signal
SIGNAL z: STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); -- 1D signal
SIGNAL w1: mem1; -- 2D signal
SIGNAL w2: mem2; -- 1Dx1D signal
SIGNAL w3: mem3; -- 1Dx1D signal
-------- Legal scalar assignments: --------------------x(2) <= a; -- same types (STD_LOGIC), correct indexing
y(0) <= x(0); -- same types (STD_LOGIC), correct indexing
z(7) <= x(5); -- same types (STD_LOGIC), correct indexing
b <= v(3); -- same types (BIT), correct indexing
w1(0,0) <= x(3); -- same types (STD_LOGIC), correct indexing
Table 3.2
Synthesizable data types.
Data types Synthesizable values
BIT, BIT_VECTOR 0, 1
29

Nhm 4
STD_LOGIC, STD_LOGIC_VECTOR X, 0, 1, Z (resolved)
STD_ULOGIC, STD_ULOGIC_VECTOR X, 0, 1, Z (unresolved)
BOOLEAN True, False
NATURAL From 0 to 2, 147, 483, 647
INTEGER From _2,147,483,647 to 2,147,483,647
SIGNED From _2,147,483,647 to 2,147,483,647
UNSIGNED From 0 to 2,147,483,647
User-defined integer type Subset of INTEGER
User-defined enumerated type Collection enumerated by user
SUBTYPE Subset of any type (pre- or user-defined)
ARRAY Single-type collection of any type above
RECORD Multiple-type collection of any types above
Data Types 39
TLFeBOOK
w1(2,5) <= y(7); -- same types (STD_LOGIC), correct indexing
w2(0)(0) <= x(2); -- same types (STD_LOGIC), correct indexing
w2(2)(5) <= y(7); -- same types (STD_LOGIC), correct indexing
w1(2,5) <= w2(3)(7); -- same types (STD_LOGIC), correct indexing
------- Illegal scalar assignments: -------------------b <= a; -- type mismatch (BIT x STD_LOGIC)
w1(0)(2) <= x(2); -- index of w1 must be 2D
w2(2,0) <= a; -- index of w2 must be 1Dx1D
------- Legal vector assignments: ---------------------x <= "11111110";
y <= ('1','1','1','1','1','1','0','Z');
z <= "11111" & "000";
x <= (OTHERS => '1');
y <= (7 =>'0', 1 =>'0', OTHERS => '1');
z <= y;
y(2 DOWNTO 0) <= z(6 DOWNTO 4);
w2(0)(7 DOWNTO 0) <= "11110000";
w3(2) <= y;
z <= w3(1);
z(5 DOWNTO 0) <= w3(1)(2 TO 7);
w3(1) <= "00000000";
w3(1) <= (OTHERS => '0');
w2 <= ((OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'));
w3 <= ("11111100", ('0','0','0','0','Z','Z','Z','Z',),
(OTHERS=>'0'), (OTHERS=>'0'));
w1 <= ((OTHERS=>'Z'), "11110000" ,"11110000", (OTHERS=>'0'));
------ Illegal array assignments: ---------------------x <= y; -- type mismatch
y(5 TO 7) <= z(6 DOWNTO 0); -- wrong direction of y
w1 <= (OTHERS => '1'); -- w1 is a 2D array
w1(0, 7 DOWNTO 0) <="11111111"; -- w1 is a 2D array
w2 <= (OTHERS => 'Z'); -- w2 is a 1Dx1D array
w2(0, 7 DOWNTO 0) <= "11110000"; -- index should be 1Dx1D
-- Example of data type independent array initialization:
FOR i IN 0 TO 3 LOOP
30

Nhm 4
FOR j IN 7 DOWNTO 0 LOOP
x(j) <= '0';
y(j) <= '0'
40 Chapter 3
TLFeBOOK
z(j) <= '0';
w1(i,j) <= '0';
w2(i)(j) <= '0';
w3(i)(j) <= '0';
END LOOP;
END LOOP;
---------------------------------------------------------
* V d 3.2: Bit n v bit vector

V d ny minh ha s khc nhau gia php gn mt bit n v php
gn mt bit vector (ngha l, BIT vi BIT_VECTOR, STD_LOGIC vi
STD_LOGIC_VECTOR, hoc STD_ULOGIC vi STD_ULOGIC_VECTOR).
Hai on m VHDL c gii thiu pha di. C hai thc hin php
ton AND gia cc tn hiu vo v gn kt qu n tn hiu ra. Ch c mt s
khc bit gia chng l s lng bit cng vo v cng ra ( mt bit trong v
d u tin, 4 bits trong v d th hai). Mch in suy ra t cc on m ny
c biu din trn hnh 3.2:
-- code 1---------------------------------------------------------------------------ENTITY and2 IS
PORT (a, b: IN BIT;
x: OUT BIT);
END and2;
-------------------------------------------------------ARCHITECTURE and2 OF and2 IS
BEGIN
x <= a AND b;
END and2;
-----------------------------------------------------------code 2--------------ENTITY and2 IS
PORT (a, b: IN BIT_VECTOR (0 TO 3);
x: OUT BIT_VECTOR (0 TO 3));
END and2;
--------------------------------------------------------------ARCHITECTURE and2 OF and2 IS
BEGIN
x <= a AND b;
END and2
31

Nhm 4
Hnh 3.2. M ch c suy ra t m ca v d 3.2

Kt qu m phng trn Active HDL 6.1:
Code 1:
Hnh 3.2.a. K t qu m phng cho on m 1ca v d 3.2

Code 2:
Hnh 3.2.b. K t qu m phng cho on m 1ca v d 3.2

* V d 3.3: B cng ( Adder)
Hnh 3.3. B cng 4 bit cho v d 3.3

Hnh 3.3 cho thy gin mc nh ca mt b cng 4 bit, mch in
c 2 u vo (a,b) v mt u ra (sum). C 2 gii php c cp. Th nht,
tt c cc tn hiu c kiu d liu SIGNED, trong khi gii php th hai u ra
c kiu INTEGER. Lu trong gii php th hai c mt hm chuyn i
32

Nhm 4
(conversion function) c s dng dng 13, kiu ca (a+b) ph hp vi
kiu ca tng. Lu cn bao gm c gi std_logic_arith (dng 4 ca mi gii
php), c m t kiu d liu SIGNED. Nh li rng mt gi tr SIGNED c
m t ging nh mt vector, ngha l, tng t nh STD_LOGIC_VECTOR,
khng ging INTEGER.
Code:
---------------------------------------------------1
----- Solution 1: in/out=SIGNED ---------2
LIBRARY ieee;
3
4
5
-----------------------------------------6
ENTITY adder1 IS
7
PORT ( a, b : IN SIGNED (3 DOWNTO 0);
8
sum : OUT SIGNED (4 DOWNTO 0));
9
END adder1;
10
-----------------------------------------11
ARCHITECTURE adder1 OF adder1 IS
12
BEGIN
13
sum <= a + b;
14
END adder1;
15
----------------------------------------------------------------------------------------1
------ Solution 2: out=INTEGER ----------2
LIBRARY ieee;
3
4
5
-----------------------------------------6
ENTITY adder2 IS
7
PORT ( a, b : IN SIGNED (3 DOWNTO 0);
8
sum : OUT INTEGER RANGE -16 TO 15);
9
END adder2;
10
-----------------------------------------11
ARCHITECTURE adder2 OF adder2 IS
12
BEGIN
13
sum <= CONV_INTEGER(a + b);
14
END adder2;
15
------------------------------------------
* Kt qu m phng trn Active HDL 6.1
Hnh 3.4 Kt qu m phng cho v d 3.3
33

Nhm 4
Chng 4: Ton t v thuc tnh.

4.1.
Ton t.
VHDL cung cp mt s ton t sau:
Ton t gn.
Ton t logic.
Ton t ton hc.
Ton t so snh.
Ton t dch.
Sau y chng ta s xem xt c th tng ton t mt.
4.1.1Ton t gn.
VHDL nh ngha ba loi ton t gn sau:
<=: Dng gn gi tr cho SIGNAL.
:= : Dng gn gi tr cho VARIABLE, CONSTANT,GENERIC.
=>: Dng gn gi tr cho thnh phn cc vector v cc loi gi tr
khc.
V d:
SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
x <= '1';
y := "0000
w <= "10000000";
w <= (0 =>'1', OTHERS =>'0');
4.1.2Ton t Logic.
VHDL nh ngha cc ton t logic sau:
NOT, AND, OR, NAND, NOR, XOR, XNOR
D liu cho cc ton t ny phi l kiu: BIT, STD_LOGIC,
STD_ULIGIC, BIT_VECTOR, STD_LOGIC_VECTOR,
STD_ULOGIC_VECTOR.
V d:
y <= NOT a AND b;
y <= NOT (a AND b);
y <= a NAND b;
4.1.3Ton t ton hc.

Cc ton t ny dng cho cc kiu d liu s nh l:INTEGER,
SIGNED, UNSIGNED, REAL. Cc ton t bao gm:
+
Ton t cng.
34

Nhm 4
Ton t tr.
*
Ton t nhn.
/
Ton t chia.
**
Ton t ly m.
MOD Php chia ly phn nguyn.
REM Php chia ly phn d.
ABS Php ly gi tr tuyt i.
-
4.1.4Ton t so snh.
C cc ton t so snh sau:
=
So snh bng
/=
So snh khng bng.
<
So snh nh hn.
>
So snh ln hn.
<=
So snh nh hn hoc bng.
>=
So snh ln hn hoc bng.
4.1.5Ton t dch.
C php s dng ton t dch l:
<left operand> <shift operation> <right operand>
Trong <left operand> c kiu l BIT_VECTOR, cn <right operand>
c kiu l INTEGER. C hai ton t dch:
Sll
Ton t dch tri. in 0 vo pha phi.
Rll
Ton t dch phi. in 0 vo pha tri.
4.2.
Thuc tnh.
4.1.1.Thuc tnh d liu.

VHDL cung cp cc thuc tnh sau.
dLOW
Tr v gi tr nh nht ca ch s mng.
dHIGH
Tr v ch s ln nht ca mng.
dLEFT
Tr v ch s bn tri nht ca mng.
dRIGHT
Tr v ch s bn phi nht ca mng.
dLENGTH
Tr v kch thc ca mng.
dRANGE
Tr v mng cha ch s.
dREVERSE_RANGE Tr v mng cha ch s c o ngc.
V d: Nu d l mt vector c khai bo nh sau:
SIGNAL d : STD_LOGIC_VECTOR(0 TO 7)
Ta s c:
d'LOW = 0, d'HIGH = 7, d'LEFT = 7, d'RIGHT = 0, d'LENGTH = 8,
d'RANGE = (7 downto 0), d'REVERSE_RANGE = (0 to 7).
Cc thuc tnh ny c th dng trong cc vng lp:
FOR i IN RANGE (0 TO 7) LOOP ...

FOR i IN x'RANGE LOOP ...
35

Nhm 4
FOR i IN RANGE (x'LOW TO x'HIGH) LOOP ...
FOR i IN RANGE (0 TO x'LENGTH-1) LOOP ...
Nu tn hiu c kiu lit k th:

dVAL(pos)
Tr v gi tr ti pos.
dPOS(val)
Tr v v tr c gi tr l val.
dLEFTOF(value)
Tr v gi tr v tr bn tri ca value.
dVAL(row,colum)
Tr v gi tr mt v tr c bit.
4.1.2.Thuc tnh tn hiu.
Cc thuc tnh loi ny ch c p dng i vi d liu SIGNAL. Nu
s l mt SIGNAL th ta c :
sEVENT :
Tr v true khi mt s kin xy ra i vi s.
sSTABLE:
Tr v true nu khng c s kin no xy ra i
vi s.
sACTIVE:
Tr v true khi s = 1.
sQUIET<time>: Tr v true khi trong khong thi gian time khong
c s kin no xy ra.
sLAST_EVENT: Tr v thi gian tri qua k t s kin cui cng
sLAST_ACTIVE: Tr v thi gian k t ln cui cng s = 1
sLAST_VALUE: Tr v gi tr ca s trc s kin trc .
Trong cc thuc tnh trn th thuc tnh sEVENT l hay c dng
nht.
Vi d: y l v d vi tn hiu ng h.
IF (clk'EVENT AND clk='1')...

IF (NOT clk'STABLE AND clk='1')...
WAIT UNTIL (clk'EVENT AND clk='1');
IF RISING_EDGE(clk)...
4.3.
Thuc tnh c nh ngha bi ngi dng.
VHDL, ngoi vic cung cp cc thuc tnh c sn n cn cho php

ngi dng t nh ngha cc thuc tnh. Cc thuc tnh ny mun s dng cn
phi khai bo v m t r rng theo cu trc sau:
ATTRIBUTE <attribute_name>:< attribute_type>;
ATTRIBUTE <attribute_name> OF< target_name>: <class>
IS
<value>;
Trong
+
attribute_type l kiu d liu.
+
Class : SIGNAL, TYPE, FUNCTION.
V d :
ATTRIBUTE number_of_inputs: INTEGER;

ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3;
36

Nhm 4
4.4.
Chng ton t.
Cng ging nh cc thuc tnh c nh ngha bi ngi dng. Trong

VHDL ta cng c th xy dng chng cc ton t ton hc. xy dng chng
cc ton t ny ta cn phi ch r loi d liu tham gia. V d nh ton t +
trn ch p dng cho cc loi d liu cng kiu s.By gi ta xy dng ton t
+ dng cng mt s INTEGER vi mt BIT.
FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS
BEGIN
IF (b='1') THEN RETURN a+1;
ELSE RETURN a;
END IF;
END "+";
4.5.
GENERIC.
GENERIC l mt cch to cc tham s dng chung (ging nh cc bin

static trong cc ngn ng lp trnh). Mc ch l cho cc on code mm
do v d s dng li hn.
Mt on GENERIC khi c s dng cn phi c m t trong
ENTITY. Cc tham s phi c ch r. Cu trc nh sau:
GENERIC (parameter_name : parameter_type := parameter_value);
V d: V d sau s nh ngha bin n c kiu INTEGER v l
GENERIC n c gi tr mc nh l 8. Khi khi n c gi bt k u,
trong mt ENTITY hay mt ARCHITECTURE theo sau gi tr ca n lun
l 8.
ENTITY my_entity IS
GENERIC (n : INTEGER := 8);
PORT (...);
END my_entity;
ARCHITECTURE my_architecture OF my_entity IS
...
END my_architecture;
C th c nhiu hn 1 tham s GENERIC c m t trong mt ENTITY. V

d:
GENERIC (n: INTEGER := 8; vector: BIT_VECTOR := "00001111");
4.6. V d.
lm r hn cc vn ni trn chng ta s xem xt mt vi v
d sau:
V d 1: Generic Decoder.
37

Nhm 4
Hnh v sau y m phng mt b gii m c hai u vo. Mt tn hiu
vo d liu sel gm m bt v mt tn hiu l ena. N c mt u ra d liu gm
n bt. C m = log2(n).
Hnh 4.1. B m ho cho v d 4.1

Khi tn hiu ena = 0 th tt c cc bt u ra x = 1. u ra c chn
theo u vo sel. Chng trnh sau y m t v i tng ny vi 3 u vo
sel v pha u ra c 8 ng x.
LIBRARY ieee;
ENTITY decoder IS
PORT ( ena : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO
0);
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END decoder;
ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR
(x'HIGH
DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO
x'HIGH;
BEGIN
temp1 := (OTHERS => '1');
temp2 := 0;
IF (ena='1') THEN
FOR i IN sel'RANGE LOOP
IF (sel(i)='1') THEN
temp2:=2*temp2+1;
ELSE
temp2 := 2*temp2;
END IF;
END LOOP;
temp1(temp2):='0';
END IF;
x <= temp1;
END PROCESS;
38

Nhm 4
END generic_decoder;
Hnh sau y m t kt qu hot ng ca b gii m trn.
Hnh 4.2 M phng kt qu ca b m ho

Nh chng ta thy khi ena =0 th tt c cc bt pha u ra u bng 1.
Khi ena = 1 th ch mt bt pha u ra c chn tc l bng 0. V d nh khi
sel=000 th u ra x = 11111110, sel = 001 x = 11111101.
Trong v d trn ta s dng cc ton t +, * , cc ton t gn v thuc
tnh RANGE.
V d 2 : Generic parity detector.
V d sau y m phng mt mch pht hin tnh parity. N bao gm
mt u vo n bt v mt u ra. u ra s c gi tr bng 0 khi s u vo c
gi tr l mt l mt s chn v bng 1 trong cc trng hp cn li.
Hnh 4.3. B pht hin bt chn l

Sau y l m ngun m t mch trn.
ENTITY parity_det IS
PORT ( input: IN BIT_VECTOR (n DOWNTO 0);
output: OUT BIT);
END parity_det;
ARCHITECTURE parity OF parity_det IS
BEGIN
PROCESS (input)
VARIABLE temp: BIT;
BEGIN
temp := '0';
FOR i IN input'RANGE LOOP
39

Nhm 4
temp := temp XOR
input(i);
END LOOP;
output <= temp;
END PROCESS;
END parity;
Trong on m trn chng ta s dng mt mnh GENERIC nh

ngha n =7. Khi tt c cc ln n xut hin n u c gi tr l 7.
Kt qu ca mch c biu din bi hnh sau. Khi u vo input =00000000
th u ra output =0. Khi input =00000001 th u ra output = 1 v s u
vo l 1 l mt s l.
Hnh 4.4. M phng kt qu ca hnh 4.2

V d 3: Parity Generator
Mch sau s thm mt bt parity vo tn hiu input. Bt ny l 0 khi s
u vo =1 ca input l mt s chn v bng 0 trong trng hp ngc li. Nh
vy mch s gm n-1 u vo d liu v n u ra, trong n-1 u ra bn phi
ging nh n-1 u vo, u ra cn li l gi tr kim tra parity.
Hnh 4.5. B pht bit chn l ca v d 4.3

ENTITY parity_gen IS
PORT ( input: IN BIT_VECTOR (n-1 DOWNTO 0);
output: OUT BIT_VECTOR (n DOWNTO 0));
END parity_gen;
ARCHITECTURE parity OF parity_gen IS
BEGIN
PROCESS (input)
VARIABLE temp1: BIT;
VARIABLE temp2: BIT_VECTOR
(output'RANGE);
BEGIN
temp1 := '0';
FOR i IN input'RANGE LOOP
temp1 := temp1 XOR input(i);
temp2(i) := input(i);
40

Nhm 4
END LOOP;
temp2(output'HIGH) := temp1;
output <= temp2;
END PROCESS;
END parity;
Kt qu:
50
100
150
200
250
300
350
400
450
500
input
00
01
02
03
04
05
output
00
81
82
03
84
05
ns
Hnh 4.6. M phng kt qu ca v d 4.3

Nh ta thy khi u vo input =0000000 th u ra output = 00000000. Khi
u vo input =0000001 th u ra output = 10000001.
41

Nhm 4
Chng 5: M song song

5.1.
Song song v tun t.
u tin chng ta s xem xt s khc bit gia mch t hp v mch

dy sau s xem st s khc bit gia m ngun tun t v m song song.
5.1.1.Mch t hp v mch dy.
Mch t hp l mch m u ra ca mch ch ph thuc vo u vo ca
h ti thi im hin ti. T ta thy, h ny khng cn yu cu b nh v
chng c to thnh ch t cc cng logic c bn.
Mch dy l mch m u ra ca mch cn ph thuc vo c u vo
trong qu kh ca mch. T ta thy i vi h ny cn phi c b nh v
mt vng phn hi tn hiu. Hnh sau y m t hai loi mch ny.
Hnh 5.1. Mch t hp v mch dy

5.1.2.M song song v m tun t.
M ngun VHDL l song song. Ch cc on m trong mt PROCESS,
FUNCTION, PROCEDURE l tun t. Cc khi ny c thc hin mt
cch tun t. M song song c gi l m lung d liu ( dataflow code).
V d. Mt on m gm ba khi lnh song song ( stat1, stat 2, stat3).
Khi cc on sau s thc hin cng mt lc trong mch vt l.
42

Nhm 4
Cc on m song song khng th s dng cc thnh phn ca mch
ng b ( hot ng ch xy ra khi c s ng b ca xung ng h.). Mt cch
khc chng ta ch c th xy dng da trn cc mch t hp. Trong mc ny
chng ta tm hiu v cc on m song song. Chng ta ch tm hiu cc on
m c s dng bn ngoi PROCESS, FUNCTION, PROCEDURES. Chng
l cc khi ln WHEN v GENERATE. Bn cnh , cc php gn dng cc
ton t c s dng to cc mch t hp. Cui cng mt loi khi ln c
bit c gi l BLOCK s c s dng.
5.2.
S dng cc ton t.
y l cch c bn nht dng to cc on m song song. Cc ton t

(AND, OR, ..) c tm hiu trn s c lit k bng di y. Cc ton
t c th c s dng nh l mt thnh phn ca mch t hp. Tuy nhin
r rng. Cc mch hon chnh s s dng cch vit tun t mc d cc mch
khng cha cc phn t tun t. Cc v d sau y c thit k ch s dng
cc thnh phn logic c bn.
Bng 5.1. Cc ton t

V d : B dn knh 4 -1.
Hnh 5.2. B dn knh

B dn knh 4-1 c 4 u vo d liu, hai u vo iu khin v mt
u ra. Tn hiu u ra s l tn hiu ca mt trong 4 u vo tu theo gi tr
ca hai u vo iu khin s0,s1. Sau y l chng trnh m phng.
43

Nhm 4
LIBRARY ieee;
--------------------------------------------ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN
STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
--------------------------------------------ARCHITECTURE pure_logic OF mux IS
BEGIN
y <= (a AND NOT s1 AND NOT s0) OR
(b AND NOT s1 AND s0) OR
(c AND s1 AND NOT s0) OR
(d AND s1 AND s0);
END pure_logic;
Kt qa m phng.
50
100
150
200
250
300
350
400
450
500
ns
a
b
c
d
s0
s1
y
Hnh 5.3. M phng kt qu ca v d 5.1

5.3.
Mnh WHEN.
WHEN l mt thnh phn ca cc khi ln song song. N xut hin

trong hai trng hp. WHEN / ELSE v WITH / SELECT / WHEN. C php
c trnh by nh sau.
V d:
44

Nhm 4
-----With
WHEN/ELSE
------------------------outp <= "000" WHEN (inp='0' OR reset='1') ELSE
"001" WHEN ctl='1' ELSE
"010";
---With
WITH/SELECT/WHEN
-------------------WITH control SELECT
output <= "000" WHEN reset,
"111" WHEN set,
UNAFFECTED WHEN OTHERS;
Sau y ta s xem xt cc v d dng mnh WHEN.

V d 1: B dn knh 4 -1.
Nguyn tc hot ng ca mch ny ta ni trn. y chng ta s
dng mnh WHEN thay cho c ton t. Chng ta c th dng theo c hai
cch. d hiu chng ta s xem xt c hai cch s dng mnh WHEN.
Hnh 5.4. B dn knh cho v d 2

------- S dng WHEN/ELSE --------
LIBRARY ieee;
------------------------------------------ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END mux;
------------------------------------------ARCHITECTURE mux1 OF mux IS
BEGIN
y <= a WHEN sel="00" ELSE
b WHEN sel="01" ELSE
c WHEN sel="10" ELSE
d;
END mux1;
-------------------------------------------
--- S dng WITH/SELECT/WHEN ----LIBRARY ieee;
45

Nhm 4
------------------------------------------ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
------------------------------------------ARCHITECTURE mux2 OF mux IS
BEGIN
WITH sel SELECT
y <= a WHEN "00",
b WHEN "01",
c WHEN "10",
d WHEN OTHERS;
END mux2;
--------------------------------------------
V d 2: B m 3 trng thi.
Hnh 5.5. B m 3 trng thi

Mch b m 3 trng thi cho u ra output = input khi ena = 0 v tr
khng cao khi ena = 1.
LIBRARY ieee;
---------------------------------------------ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
output: OUT STD_LOGIC_VECTOR (7 DOWNTO
0));
END tri_state;
---------------------------------------------ARCHITECTURE tri_state OF tri_state IS
BEGIN
output <= input WHEN (ena='0') ELSE
(OTHERS => 'Z');
END tri_state;
----------------------------------------------
Kt qu m phng
46

Nhm 4
50
100
150
200
250
300
350
400
450
500
ns
ena
input
01
00
output
01
00
ZZ
01
00
01
ZZ
Hnh 5.6. Kt qu m phng cho v d 5.3
V d 3: Encoder.
Hnh 5.7. B m ho cho v d 5.4

Mt b ENCODER c n u vo, m u ra vi m = log2 (n). Ti mt
thi im ch c mt bt u vo bng 1. Sau y l chng trnh m phng s
dng WHEN theo c hai cch dng WHEN / ELSE,v WITH / SELECT /
WHEN.
---- s dng WHEN/ELSE ------------LIBRARY ieee;
--------------------------------------------ENTITY encoder IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
END encoder;
--------------------------------------------ARCHITECTURE encoder1 OF encoder IS
BEGIN
y <=
"000" WHEN x="00000001" ELSE
"001" WHEN x="00000010" ELSE
"010" WHEN x="00000100" ELSE
"011" WHEN x="00001000" ELSE
"100" WHEN x="00010000" ELSE
"101" WHEN x="00100000" ELSE
"110" WHEN x="01000000" ELSE
"111" WHEN x="10000000" ELSE
"ZZZ";
END encoder1;
---------------------------------------------
---- S dng WITH/SELECT/WHEN -----LIBRARY ieee;
47

Nhm 4
--------------------------------------------ENTITY encoder IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
END encoder;
--------------------------------------------ARCHITECTURE encoder2 OF encoder IS
BEGIN
WITH x SELECT
y <= "000" WHEN "00000001",
"001" WHEN "00000010",
"010" WHEN "00000100",
"011" WHEN "00001000",
"100" WHEN "00010000",
"101" WHEN "00100000",
"110" WHEN "01000000",
"111" WHEN "10000000",
"ZZZ" WHEN OTHERS;
END encoder2;
---------------------------------------------
Kt qu m phng:
100
200
300
400
500
00
01
02
03
04
05
600
06
700
07
800
900
08
09
1000
0A
ns
0B

V d 4: ALU.
Hnh 5.9. ALU

Mch ALU thc hin cc php ton logic v ton hc i vi hai u
vo a v b. Chng c iu khin bi 4 bt sel(3:0). Tu thuc vo gi tr ca
sel m khi s thc hin thao tc no vi d liu. Bng di y m t cc thao
tc ca ALU.
48

Nhm 4
Hnh 5.9.b. Hot ng chinh ca cc phn t ALU
M ngun thc hin m phng:
---------------------------------------------LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
---------------------------------------------ENTITY ALU IS
PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cin: IN STD_LOGIC;
END ALU;
---------------------------------------------ARCHITECTURE dataflow OF ALU IS
SIGNAL arith, logic: STD_LOGIC_VECTOR (7
DOWNTO 0);
BEGIN
----- Arithmetic unit: -----WITH sel(2 DOWNTO 0) SELECT
arith <= a WHEN "000",
a+1 WHEN "001",
a-1 WHEN "010",
b WHEN "011",
b+1 WHEN "100",
b-1 WHEN "101",
a+b WHEN "110",
a+b+cin WHEN OTHERS;
----- Logic unit: ----------WITH sel(2 DOWNTO 0) SELECT
logic <= NOT a WHEN "000",
NOT b WHEN "001",
a AND b WHEN "010",
a OR b WHEN "011",
a NAND b WHEN "100",
a NOR b WHEN "101",
49

Nhm 4
a XOR b WHEN "110",
NOT (a XOR b) WHEN OTHERS;
-------- Mux: --------------WITH sel(3) SELECT
y <= arith WHEN '0',
logic WHEN OTHERS;
END dataflow;
----------------------------------------------
Kt qu m phng.
50
100
150
200
250
300
350
400
450
500
00
01
02
03
04
05
arith
00
02
02
04
03
05
00
01
02
03
04
05
logic
FF
FE
FD
FC
04
05
sel
00
02
02
04
03
05
ns
cin
5.4.

GENERATE.
GENERATE l mt khi lnh song song khc. N tng ng vi khi

lnh tun t LOOP trong vic cho php cc on lnh c thc hin lp li
mt s ln no . Mu dng ca n l FOR / GENERATE.
label: FOR identifier IN range GENERATE
(concurrent assignments)
END GENERATE;
Mt cch khc s dng GENERATE l dng IF. y mnh ELSE

khng c s dng. Mt cch hay c s dng l dng IF trong
FOR/GENERATE.
Mu s dng nh sau.
label1: FOR identifier IN range GENERATE
...
label2: IF condition GENERATE
(concurrent assignments)
END GENERATE;
...
END GENERATE;
V d:
SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
...
G1: FOR i IN x'RANGE GENERATE
z(i) <= x(i) AND y(i+8);
END GENERATE;
Mt iu cn phi ch l gii hn ca dy phi c khai bo l static

nu khng s khng hp l. Trong v d sau choice khng c khai bo l
static nn khng hp l:
NotOK: FOR i IN 0 TO choice GENERATE
(concurrent statements)
50

Nhm 4
END GENERATE;
hiu r hn v khi lnh GENERATE chng ta s xt v d sau:

V d: Vector shifter.
V d sau minh ho cho vic s dng GENERATE. Trong u vo s
c dch i mt bt v to thnh u ra. V d u vo c 4 ng v gi tr
ban u l 1111 th u ra s c m t nh sau:
row(0): 0 0 0 0 1 1 1 1
row(1): 0 0 0 1 1 1 1 0
row(2): 0 0 1 1 1 1 0 0
row(3): 0 1 1 1 1 0 0 0
row(4): 1 1 1 1 0 0 0 0
Chng trnh m phng.
-----------------------------------------------LIBRARY ieee;
-----------------------------------------------ENTITY shifter IS
PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel: IN INTEGER RANGE 0 TO 4;
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END shifter;
-----------------------------------------------ARCHITECTURE shifter OF shifter IS
SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
SIGNAL row: matrix;
BEGIN
row(0) <= "0000" & inp;
G1: FOR i IN 1 TO 4 GENERATE
row(i) <= row(i-1)(6 DOWNTO 0) & '0';
END GENERATE;
outp <= row(sel);
END shifter;
Kt qu m phng:
50
100
150
200
250
300
350
400
inp
outp
00
01
02
03
04
sel
450
500
ns

Nh hnh ta thy, nu input = 0011th u ra output =00000011 khi
sel = 0. output = 00000110 khi sel = 1. output = 00001100 nu sel = 2.
5.5.
BLOCK.
51

Nhm 4
C hai loi khi lnh BLOCK : Simple v Guarded.
5.5.1.Simple BLOCK
Khi lnh BLOCK cho php t mt khi lnh song song vo mt on,
iu gip cho cc on lnh d c v d qun l hn. Cu trc ca chng
nh sau:
label: BLOCK
[declarative part]
BEGIN
(concurrent statements)
END BLOCK label;
Cc khi lnh BLOCK t lin tip nhau nh v d sau:

-----------------------ARCHITECTURE example ...
BEGIN
...
block1: BLOCK
BEGIN
...
END BLOCK block1
...
block2: BLOCK
BEGIN
...
END BLOCK block2;
...
END example;
------------------------
V d:
b1: BLOCK
SIGNAL a: STD_
BEGIN
a <= input_sig
END BLOCK b1;
Mt on BLOCK c th c t trong mt on BLOCK khc, khi

c php nh sau:
label1: BLOCK
[declarative part of top block]
BEGIN
[concurrent statements of top block]
label2: BLOCK
[declarative part nested block]
BEGIN
(concurrent statements of nested block)
END BLOCK label2;
[more concurrent statements of top block]
END BLOCK label1;
5.5.2.Guarded BLOCK
52

Nhm 4
Mt Guarded BLOCK l mt khi BLOCK c bit. N cha mt iu
kin v BLOCK ch c thc hin khi iu kin c gi tr l TRUE.
Cu trc nh sau:
label: BLOCK (guard expression)
[declarative part]
BEGIN
(concurrent
guarded
and
statements)
END BLOCK label;
unguarded
tm hiu r hn v khi BLOCK ta i xt v d sau:

Vd 1: Cht s dng Guarded BLOCK. Trong v d ny khi no clk =
1 th khi c hot ng khi khi lnh s c thc hin.
------------------------------LIBRARY ieee;
------------------------------ENTITY latch IS
PORT (d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END latch;
------------------------------ARCHITECTURE latch OF latch IS
BEGIN
b1: BLOCK (clk='1')
BEGIN
q <= GUARDED d;
END BLOCK b1;
END latch;
-------------------------------
Kt qu m phng
100
200
300
400
500
600
700
800
900
1000
ns
clk
d
q

V d 2: DFF dng Guarded BLOCK.Trong v d ny chng ta s xem xt hot
ng ca mt TrigerT hot ng ng b sn dng.
------------------------------LIBRARY ieee;
------------------------------ENTITY dff IS
q: OUT STD_LOGIC);
END dff;
------------------------------ARCHITECTURE dff OF dff IS
53

Nhm 4
BEGIN
b1: BLOCK (clk'EVENT AND clk='1')
BEGIN
q <= GUARDED '0' WHEN rst='1'
ELSE d;
END BLOCK b1;
END dff;
------------------------------
Kt qu m phng:
100
200
300
400
500
600
700
800
900
1000
ns
clk
d
q
rst
Chng 6: M tun t
6.1.
PROCESS
PROCESS l phn tun t ca m VHDL. N c m t bi cc cu

lnh IF, WAIT, CASE, hoc LOOP, v bi danh sch nhy (ngoi tr WAIT
c s dng). PROCESS phi c ci t trong m chnh, v c thc thi
mi thi im mt tn hiu trong danh sch nhy thay i.
C php:
[label:]
PROCESS (sensitivity list)

[VARIABLE name type [range] [:=
initial_value;]]
BEGIN
(sequential code)
END PROCESS [label];
VARIABLES l tu chn. Nu s dng, chng phi c khai bo trong

phn khai bo ca PROCESS (trc t kho BEGIN). Gi tr khi to khng
th kt hp, ch ly i din khi m phng.
Nhn cng c s dng tu chn, mc ch l nng cao kh nng c
c ca m. Nhn c th l bt k t no, ngoi tr t kho.
V d 6.1a:
54

Nhm 4
Hnh 6.1a.1 DFF vi tn hiu reset khng ng b

10
20
30
40
50
60
70
80
90
ns
rst
d
clk
q
Hnh 6.1a.2 Kt qu m phng

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFF is
Port(d,clk,rst:in std_logic;
q:out std_logic);
end DFF;
architecture Behaviour of DFF is
begin
process(clk,rst)
begin
-- wait on rst,clk;
if (rst='1') then
q <= '0';
elsif (clk'Event and clk='1') then
q <= d;
end if;
end process;
end Behaviour;
6.2.
Signals v Variables.
VHDL c hai cch nh ngha cc gi tr khng tnh: bng SIGNAL

hoc bng VARIABLE. SIGNAL c th c khai bo trong PACKAGE,
ENTITY hoc ARCHITECTURE (trong phn khai bo ca n), trong khi
VARIABLE c th c m t bn trong mt phn ca m tun t (trong
PROCESS). Do , trong khi gi tr ca phn trc c th l ton cc, phn
sau lun l cc b.
Gi tr ca VARIABLE c th khng bao gi nh ngha ngoi
PROCESS mt cch trc tip, nu cn, th n phi c gn thnh SIGNAL.
55

Nhm 4
Trong cch x l khc, cp nht VARIABLE l tc th, ta c th tnh ton tc
th gi tr mi ca n trong dng lnh tip theo. iu khng phi l trng
hp ca SIGNAL (khi c s dng trong PROCESS), gi tr mi ca n ch
tng qut c bo ton c th dng c sau khi kt thc qu trnh chy
hin ti ca PROCESS.
Php ton gn cho SIGNAL l <= (sig <= 5), trong khi vi
VARIABLE l := (var := 5).
6.3.
IF.
IF, WAIT, CASE, v LOOP l cc cu lnh i vi m tun t. Do ,

chng ch c th c s dng bn trong PROCESS, FUNCTION hoc
PROCEDURE.
V nguyn tc, c mt kt qu ph nh, tng hp s ti u ho cu trc
v trnh i su vo phn cng.
C php:
IF conditions THEN assignments;
ELSIF conditions THEN assignments;
...
ELSE assignments;
END IF;
V d:
IF (x<y) THEN temp:="11111111";
ELSIF (x=y AND w='0') THEN temp:="11110000";
ELSE temp:=(OTHERS =>'0');
V d 6.3a:
Hnh 6.2a.1. B m ch s thp phn

10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
ns
clk
digit
Hnh 6.2a.2. Kt qu m phng

56

Nhm 4
LIBRARY ieee;
ENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
ARCHITECTURE counter OF counter IS
BEGIN
count: PROCESS(clk)
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
IF (clk'EVENT AND clk='1') THEN
temp := temp + 1;
IF (temp=10) THEN temp := 0;
END IF;
END IF;
digit <= temp;
END PROCESS count;
END counter;
V d 6.3b:
Hnh 6.3b.1. Thanh ghi dch 4 bit

50
100
150
200
250
300
350
400
450
clk
rst
d
internal
Hnh 6.3b.2. Kt qu m phng
LIBRARY ieee;
ENTITY shiftreg IS
57
500
550
600
650 ns

Nhm 4
GENERIC (n: INTEGER := 4); -- # of stages
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
ARCHITECTURE behavior OF shiftreg IS
SIGNAL internal: STD_LOGIC_VECTOR (n-1 DOWNTO 0);
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
internal <= (OTHERS => '0');
internal <= d & internal(internal'LEFT DOWNTO
1);
END IF;
END PROCESS;
q <= internal(0);
END behavior;
6.4.
WAIT.
Php ton WAIT i khi tng t nh IF. Tuy nhin, nhiu hn mt nh

dng c th dng c. Hn na, khi IF, CASE, hoc LOOP c s dng,
PROCESS khng th c mt danh sch nhy khi WAIT c s dng.
C php:
WAIT UNTIL signal_condition;
WAIT ON signal1 [, signal2, ... ];
WAIT FOR time;
Cu lnh WAIT UNTIL nhn ch mt tn hiu, do thch hp cho m

ng b hn l m khng ng b. Khi PROCESS khng c danh sch nhy
trong trng hp ny, WAIT phi l cu lnh u tin trong PROCESS.
PROCESS c thc hin mi thi im khi gp iu kin.
V d:
Thanh ghi 8 bit vi tn hiu reset ng b
PROCESS -- no sensitivity list
BEGIN
IF (rst='1') THEN
output <= "00000000";
output <= input;
END IF;
58

Nhm 4
END PROCESS;
WAIT ON, trong cch x l khc, nhn nhiu tn hiu. PROCESS c

t gi cho n khi bt k tn hiu no thay i. PROCESS s tip tc thc
hin bt k khi no mt thay i trong rst hoc clk xut hin.
V d:
Thanh ghi 8 bit vi tn hiu reset khng ng b
PROCESS
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
output <= "00000000";
output <= input;
END IF;
END PROCESS;
WAIT FOR ch dng m phng. V d: WAIT FOR 5ns;
V d 6.4a:
DFF vi tn hiu reset khng ng b
5
10
15
20
25
30
35
40
45
50
55
rst
d
clk
q

library IEEE;
entity DFF is
Port(d,clk,rst:in std_logic;
q:out std_logic);
end DFF;
architecture DFF of DFF is
begin
process
begin
wait on rst,clk;
59
60
65
70
75
80
ns

Nhm 4
if (rst='1') then
q <= '0';
elsif (clk'Event and clk='1') then
q <= d;
end if;
end process;
end DFF;
V d 6.4b:
B m mt ch s thp phn 0 9 0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
ns
clk
0
digit

LIBRARY ieee;
ENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
BEGIN
PROCESS -- no sensitivity list
BEGIN
temp := temp + 1;
IF (temp=10) THEN
temp := 0;
END IF;
digit <= temp;
END PROCESS;
END counter;
6.5.
CASE.
CASE l lnh duy nht cho m tun t (i km vi IF, LOOP, v WAIT).
C php:
CASE identifier IS
WHEN value => assignments;
WHEN value => assignments;
...
END CASE;
60

Nhm 4
V d:
CASE control IS
WHEN "00" => x<=a; y<=b;
WHEN "01" => x<=b; y<=c;
WHEN OTHERS => x<="0000"; y<="ZZZZ";
END CASE;
Lnh CASE (tun t) tng t vi WHEN (kt hp). Tt c s hon v

u phi c kim tra, v vy t kho OTHERS rt hu ch. T kho quan
trng khc l NULL (bn sao ca UNAFFECTED), nn c s dng khi
khng c hot ng no thay th. V d: WHEN OTHERS => NULL;. Tuy
nhin, CASE cho php nhiu php gn vi mi iu kin kim tra, trong khi
WHEN ch cho php mt.
Ging nh trong trng hp ca WHEN, y WHEN value c th
c 3 dng:
WHEN value -- single value
WHEN value1 to value2 -- range, for enumerated data types
-- only
WHEN value1 | value2 |... -- value1 or value2 or ...
WHEN
CASE
Kiu lnh
ng thi
Tun t
S dng
Ch ngoi PROCESS, Ch trong PROCESS,
FUNCTION,
hoc FUNCTION,
hoc
PROCEDURE
PROCEDURE
Tt c s hon v phi C
vi C
c kim tra
WITH/SELECT/WHEN
S php gn ln nht 1
Bt k
cho mi kim tra
T kho khng kch UNAFFECTED
NULL
hot
Bng 6.1. So snh gia WHEN v CASE
V d:
Vi WHEN:
WITH sel SELECT
x <= a WHEN "000",
b WHEN "001",
c WHEN "010",
UNAFFECTED WHEN OTHERS;
Vi CASE:
CASE sel IS
61

Nhm 4
WHEN
WHEN
WHEN
WHEN
END CASE;
"000" => x<=a;

"001" => x<=b;
"010" => x<=c;
OTHERS => NULL;
V d:
B dn knh MUX 4-1
Vi IF:
IF (sel="00") THEN x<=a;
ELSIF (sel="01") THEN x<=b;
ELSIF (sel="10") THEN x<=c;
ELSE x<=d;
Vi CASE:
CASE sel IS
WHEN "00" => x<=a;
WHEN "01" => x<=b;
WHEN "10" => x<=c;
WHEN OTHERS => x<=d;
END CASE;
V d 6.5a:
DFF vi tn hiu reset khng ng b
5
10
15
20
25
30
35
40
45
50
55
60
65
70
rst
d
clk
q

LIBRARY ieee; -- Unnecessary declaration, -- because
USE ieee.std_logic_1164.all; -- BIT was used instead of
-- STD_LOGIC
ENTITY dff IS
PORT (d, clk, rst: IN BIT;
q: OUT BIT);
END dff;
ARCHITECTURE dff3 OF dff IS
BEGIN
PROCESS (clk, rst)
BEGIN
62
75
80
ns

Nhm 4
CASE rst IS
WHEN '1' => q<='0';
WHEN '0' =>
q <= d;
END IF;
WHEN OTHERS => NULL;-- Unnecessary,rst is of
-- type BIT
END CASE;
END PROCESS;
END dff3;
V d 6.5b:
B m hai ch s thp phn 0 99 0, u ra l 2 LED 7 thanh
Hnh 6.5b.1. B m 2 ch s thp phn

20
40
60
80
100
120
140
160
180
200
220
240
260
280
ns
300
reset
clk
temp1
temp2
digit1
7E
digit2
7E
30
7E
30
7E
30
6D
79
33
7E
30

LIBRARY ieee;
ENTITY counter IS
PORT (clk, reset : IN STD_LOGIC;
digit1, digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END counter;
BEGIN
63

Nhm 4
PROCESS(clk, reset)
VARIABLE temp1: INTEGER RANGE 0 TO 10;
BEGIN
---------------------- counter: ---------------------IF (reset='1') THEN
temp1 := 0;
temp2 := 0;
temp1 := temp1 + 1;
IF (temp1=10) THEN
temp1 := 0;
temp2 := temp2 + 1;
IF (temp2=10) THEN
temp2 := 0;
END IF;
END IF;
END IF;
---- BCD to SSD conversion: -------CASE temp1 IS
WHEN 0 => digit1 <= "1111110"; --7E
WHEN 1 => digit1 <= "0110000"; --30
WHEN 2 => digit1 <= "1101101"; --6D
WHEN 3 => digit1 <= "1111001"; --79
WHEN 4 => digit1 <= "0110011"; --33
WHEN 5 => digit1 <= "1011011"; --5B
WHEN 6 => digit1 <= "1011111"; --5F
WHEN 7 => digit1 <= "1110000"; --70
WHEN 8 => digit1 <= "1111111"; --7F
WHEN 9 => digit1 <= "1111011"; --7B
WHEN OTHERS => NULL;
END CASE;
CASE temp2 IS
WHEN 0 => digit2 <= "1111110"; --7E
WHEN 1 => digit2 <= "0110000"; --30
WHEN 2 => digit2 <= "1101101"; --6D
WHEN 3 => digit2 <= "1111001"; --79
WHEN 4 => digit2 <= "0110011"; --33
WHEN 5 => digit2 <= "1011011"; --5B
WHEN 6 => digit2 <= "1011111"; --5F
WHEN 7 => digit2 <= "1110000"; --70
WHEN 8 => digit2 <= "1111111"; --7F
WHEN 9 => digit2 <= "1111011"; --7B
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END counter;
6.6.
LOOP.
LOOP hu ch khi mt phn ca m phi c th hin nhiu ln. Ging

nh IF, WAIT, v CASE, LOOP l duy nht i vi m tun t, v vy n cng
c th c s dng bn trong PROCESS, FUNCTION, hay PROCEDURE.
64

Nhm 4
C nhiu cch s dng LOOP.
C php:
FOR/LOOP: vng lp c lp li mt s ln c nh.
[label:]
FOR identifier IN range LOOP

(sequential statements)
END LOOP [label];
WHILE/LOOP: vng lp c lp cho n khi iu kin khng tho

mn.
[label:]
WHILE condition LOOP

(sequential statements)
END LOOP [label];
EXIT: s dng kt thc vng lp.

[label:]
EXIT [label] [WHEN condition];
NEXT: s dng b qua cc bc vng lp.

[label:]
NEXT [loop_label] [WHEN condition];
V d:
Vi FOR/LOOP:
x(i) <= enable AND w(i+2);
y(0, i) <= w(i);
END LOOP;
Mt c im quan trng ca FOR/LOOP (tng t to vi

GENERATE) l gii hn ti thiu phi l tnh. Do , mt khai bo kiu FOR
i IN 0 TO choice LOOP, vi choice l mt tham s u vo (khng tnh),
khng kt hp tng qut c.
V d:
Vi WHILE/LOOP
WHILE (i < 10) LOOP
WAIT UNTIL clk'EVENT AND clk='1';
(other statements)
END LOOP;
V d:
Vi EXIT
FOR i IN data'RANGE LOOP
CASE data(i) IS
WHEN '0' => count:=count+1;
65

Nhm 4
WHEN OTHERS => EXIT;
END CASE;
END LOOP;
V d:
Vi NEXT
NEXT WHEN i=skip; -- jumps to next iteration
(...)
END LOOP;
V d 6.6a:
B cng c nh 8 bit khng du.
Hnh 6.6a.1. B cng c nh 8 bit khng du

20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
cin
a
92
40
04
31
86
C6
32
24
81
09
63
0D
8D
65
B7
C2
0D
94
93
53
97
cout

Mi phn t ca s l mt b cng y .
sj = aj XOR bj XOR cj
cj1 = (aj AND bj) OR (aj AND cj) OR (bj AND cj)
Cch 1:
Dng Generic vi cc VECTOR
----- Solution 1: Generic, with VECTORS -------LIBRARY ieee;
ENTITY adder IS
GENERIC (length : INTEGER := 8);
PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cout: OUT STD_LOGIC);
66
ns

Nhm 4
END adder;
ARCHITECTURE adder OF adder IS
BEGIN
PROCESS (a, b, cin)
VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0);
BEGIN
carry(0) := cin;
FOR i IN 0 TO length-1 LOOP
s(i) <= a(i) XOR b(i) XOR carry(i);
carry(i+1) := (a(i) AND b(i)) OR (a(i) AND
carry(i)) OR (b(i) AND carry(i));
END LOOP;
cout <= carry(length);
END PROCESS;
END adder;
Cch 2:
Dng non-generic vi cc INTEGER
---- Solution 2: non-generic, with INTEGERS ---LIBRARY ieee;
ENTITY adder IS
PORT ( a, b: IN INTEGER RANGE 0 TO 255;
c0: IN STD_LOGIC;
s: OUT INTEGER RANGE 0 TO 255;
c8: OUT STD_LOGIC);
END adder;
ARCHITECTURE adder OF adder IS
BEGIN
PROCESS (a, b, c0)
BEGIN
IF (c0='1') THEN temp:=1;
ELSE temp:=0;
END IF;
temp := a + b + temp;
IF (temp > 255) THEN
c8 <= '1';
temp := temp; ---256
ELSE c8 <= '0';
END IF;
s <= temp;
END PROCESS;
END adder;
V d 6.6b:
67

Nhm 4
B dch n gin: dch vector u vo (kch thc 8) 0 hoc 1 v
pha tri. Khi dch, bit LSB phi c in 0. Nu shift = 0 th outp = inp; nu
shift = 1 th outp(0) = 0 v outp(i) = inp(i-1) vi 1 i 7.
Hnh 6.6b.1. B dich n gin

Kt qu m phng:
20
inp
00
shift
outp
00
40
60
14
80
100
120
140
28
160
3C
180
200
220
50
240
260
280
300
64
78
C8
F0
1
14
28
3C
A0

LIBRARY ieee;
ENTITY barrel IS
GENERIC (n: INTEGER := 8);
PORT ( inp: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
shift: IN INTEGER RANGE 0 TO 1;
outp: OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0));
END barrel;
ARCHITECTURE RTL OF barrel IS
BEGIN
PROCESS (inp, shift)
BEGIN
IF (shift=0) THEN
68
ns

Nhm 4
outp <= inp;
ELSE
outp(0) <= '0';

FOR i IN 1 TO inp'HIGH LOOP
outp(i) <= inp(i-1);
END LOOP;
END IF;
END PROCESS;
END RTL;
V d 6.6c:
B m s s 0 ca mt vector nh phn, bt u t bn tri
50
100
data
00
01
02
zeros
150
03
200
250
04
05
300
06
350
07
400
450
08
09
500
550
0A
0B
600
0C
ns
0D
Hnh 6.6c.1. Kt qu m phng

LIBRARY ieee;
ENTITY LeadingZeros IS
PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
zeros: OUT INTEGER RANGE 0 TO 8);
END LeadingZeros;
ARCHITECTURE behavior OF LeadingZeros IS
BEGIN
PROCESS (data)
VARIABLE count: INTEGER RANGE 0 TO 8;
BEGIN
count := 0;
FOR i IN data'RANGE LOOP
CASE data(i) IS
WHEN '0' => count := count + 1;
WHEN OTHERS => EXIT;
END CASE;
END LOOP;
zeros <= count;
END PROCESS;
END behavior;
6.7.
Bad Clocking.
Trnh bin dch ni chung khng c kh nng tng hp cc m cha cc

php gn cho tn hiu ging nhau ti c chuyn tip ca tn hiu ng h
(clock) tham chiu (ti sn dng cng ti sn m). Trong trng hp ny,
trnh bin dch c th thng bo mt thng ip signal does not hold value
after clock edge hoc tng t.
69

Nhm 4
V d:
B m phi c tng ti mi s chuyn tip ca tn hiu clock (sn
dng cng sn dng)
PROCESS (clk)
BEGIN
counter <= counter + 1;
ELSIF(clk'EVENT AND clk='0') THEN
counter <= counter + 1;
END IF;
...
END PROCESS;
Trnh bin dch c th cn thng bo rng tn hiu counter b nhn dn.

Trong trng hp ny, vic bin dch s b treo.
Kha cnh quan trng khc l thuc tnh EVENT phi c lin quan ti
iu kin kim tra. V d: lnh IF (clkEVENT and clk=1) l ng, nhng ch
s dng IF (clkEVENT) c th trnh bin dch gi s mt gi tr kim tra mc
nh (and clk=1) hoc thng bo mt thng ip clock not locally stable.
PROCESS (clk)
BEGIN
IF (clk'EVENT) THEN
counter := counter + 1;
END IF;
...
END PROCESS;
Khi PROCESS c chy mi thi im clk thay i, b m c th

c tng hai trn mi chu k clock. Tuy nhin, iu ny khng xy ra. Nu
trnh bin dch gi thit mt gi tr mc nh, mt mch li s c tng hp,
bi v ch mt sn ca clk s c quan tm; nu khng c gi tr mc nh
gi thit, th mt thng ip li v khng c s bin dch c mong mun.
Nu mt tn hiu xut hin trong danh sch nhy, nhng khng xut hin
trong bt k php gn no ca PROCESS, th xem nh trnh bin dch s b
qua. Tuy nhin, mt thng ip ignored unnecessary pin clk c th c
thng bo.
PROCESS (clk)
BEGIN
counter := counter + 1;
...
END PROCESS;
Hai on m PROCESS sau s c tng hp chnh xc bi bt k trnh

bin dch no. Tuy nhin, ch rng s dng mt tn hiu khc nhau trong mi
PROCESS.
70

Nhm 4
PROCESS (clk)
BEGIN
x <= d;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
y <= d;
END IF;
END PROCESS;
V d 6.7a:
RAM (Random Acess Memory), dung lng 16 t nh x 8 bit
Hnh 6.7a.1. RAM

50
100
150
200
250
300
350
400
450
500
550
600
ns
wr_ena
clk
addr
data_in
32
33
34
35
36
37
38
data_out
UU
UU
32
33
34
32
UU
33
UU
34

Mch c bus d liu vo (data_in), bus d liu ra (data_out), bus a ch
(addr), cng tn hiu clock (clk) v cc chn cho php ghi (wr_ena). Khi
wr_ena c xc nhn, ti sn dng tip theo ca clk, vector c mt ti
data_in phi c lu tr ti a ch c m t bi addr. u ra, data_out,
bng cch x l khc, phi hin th lin tc d liu chn bi addr.
Khi wr_ena mc thp, q c ni vi u vo ca flip-flop, v d c
m, v vy khng c d liu mi s c ghi vo b nh. Khi wr_ena tr v
mc cao, d c ni vi u vo ca thanh ghi, v vy ti sn dng tip theo
ca clk, d s ghi gi tr lin trc.
LIBRARY ieee;
71

Nhm 4
ENTITY ram IS
GENERIC ( bits: INTEGER := 8;-- # of bits per word
words: INTEGER := 16);--#of words in the mem
PORT ( wr_ena, clk: IN STD_LOGIC;
addr: IN INTEGER RANGE 0 TO words-1;
data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
ARCHITECTURE ram OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
SIGNAL memory: vector_array;
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='1') THEN
memory(addr) <= data_in;
END IF;
END IF;
END PROCESS;
data_out <= memory(addr);
END ram;
6.8.
S dng m tun t thit k cc mch t hp.
M tun t c th c s dng thc hin cc h dy hay t hp.

Trong trng hp h dy, cc thanh ghi l cn thit, v vy s c suy ra bi
trnh bin dch. Tuy nhin, iu ny s khng xy ra trong trng hp h t
hp. Hn na, nu m c dng cho h t hp, th bng tht y nn c
mt t r rng trong m.
tho mn cc tiu chun trn c cc lut c xt:
- Lut 1: m bo tt c tn hiu u vo s dng trong PROCESS xut
hin trong danh sch nhy ca n. Trnh bin dch a ra cnh bo nu
mt tn hiu u vo cho khng c cha trong danh sch nhy, v
sau x l nu tn hiu c cha.
- Lut 2: m bo tt c t hp cc tn hiu u vo/u ra c bao gm
trong m, bng tht y ca mch c th c cha (iu ny ng
vi c m tun t v m ng thi). Cc c t khng y ca cc tn
hiu u ra c th gy cho vic tng hp suy ra cc cht gi cc
gi tr lin trc.
V d 6.8a:
Thit k mch t hp sai
72

Nhm 4
Hnh 6.8a.1. Mch t hp sai v cc bng tht

50
100
150
200
250
300
350
400
450
500
550
600
ns
a
b
c
d
sel
x
y

x hot ng nh mt b dn knh, y = 0 khi sel = 00, hoc = 1 nu sel
= 01. Tuy nhin cc c t c cung cp cho y khng dy .
LIBRARY ieee;
ENTITY example IS
PORT (a, b, c, d: IN STD_LOGIC;
sel: IN INTEGER RANGE 0 TO 3;
x, y: OUT STD_LOGIC);
END example;
ARCHITECTURE example OF example IS
BEGIN
PROCESS (a, b, c, d, sel)
BEGIN
IF (sel=0) THEN
x<=a;
y<='0';
ELSIF (sel=1) THEN
x<=b;
y<='1';
ELSIF (sel=2) THEN
x<=c;
ELSE
x<=d;
END IF;
END PROCESS;
END example;
73

Nhm 4
Sau khi bin dch, cc file bo co th hin khng c flip-flop no c
suy ra. Gi tr ging nhau ca u vo (sel = 3 = 11), hai kt qu khc nhau
cho y (khi sel =3 c i trc sel = 0, kt qu y = 0, trong khi y = 1 khi sel
= 3 c i trc sel = 1).
y = (sel(0) AND sel(1)) OR (sel(0) AND y) OR (sel(1) AND y)
Do , mt cht (s dng cc cng AND/OR) c thc hin, tr v
bng tht 2. trnh s dng cht, nn s dng X l gi tr khng xc nh,
lnh y <= X; phi c cha di cc dng 22 v 24, do y = sel(0).
Chng 7: Signal v Variable

74

Nhm 4
VHDL cung cp hai i tng gii quyt cc gi tr d liu khng
tnh (non-static): SIGNAL v VARIABLE. N cn cung cp cc cch thit
lp cc gi tr mc nh (static): CONSTANT v GENERIC.
CONSTANT v GENERIC c th l ton cc v c th c s dng
trong c kiu m, ng thi hoc tun t. VARIABLE l cc b, ch c th
c s dng bn trong mt phn ca m tun t (trong PROCESS,
FUNCTION, hoc PROCEDURE).
7.1.
CONSTANT.
CONSTANT phc v cho vic thit lp cc gi tr mc nh.
C php:
CONSTANT name : type := value;
V d:
CONSTANT set_bit : BIT := '1';
CONSTANT datamemory : memory := (('0','0','0','0'),
('0','0','0','1'),
('0','0','1','1'));
CONSTANT c th c khai bo trong PACKAGE, ENTITY v

ARCHITECTURE. Khi khai bo trong gi (package), n l ton cc, gi c th
c s dng bi nhiu thc th (entity). Khi khai bo trong thc th (sau
PORT), n l ton cc vi tt c cc kin trc (architecture) theo thc th. Khi
khai bo trong kin trc (trong phn khai bo ca n), n ch ton cc vi m
ca kin trc .
7.2.
SIGNAL.
SIGNAL phc v gii quyt cc gi tr vo v ra ca mch, cng nh l

gia cc n v bn trong ca n. Tn hiu biu din cho vic kt ni mch (cc
dy). Th hin l, tt c cc PORT ca ENTITY l cc tn hiu mc nh.
C php:
SIGNAL name : type [range] [:= initial_value];
V d:
SIGNAL control: BIT := '0';
SIGNAL count: INTEGER RANGE 0 TO 100;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);
75

Nhm 4
Khai bo ca SIGNAL c th c to ra cc ch ging nhau nh l
khai bo CONSTANT.
Kha cnh quan trng ca SIGNAl, khi s dng bn trong mt phn ca
m tun t (PROCESS), s cp nht n khng tc th. Gi tr mi ca khng
nn c i c c trc khi kt thc PROCESS, FUNCTION, hoc
PROCEDURE tng ng.
Php ton gn cho SIGNAL l <= (count <= 35;). Gi tr khi to
khng th tng hp c, ch c xt khi m phng.
Kha cnh khc nh hng n kt qu khi nhiu php gn c to
cng SIGNAL. Trnh bin dch c th thng bo v thot s tng hp, hoc c
th suy ra mch sai (bng cch ch xt php gn cui cng). Do , vic xt lp
cc gi tr khi to, nn c thc hin vi VARIABLE.
V d 7.2a:
B m s s 1 trong mt vector nh phn
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
din
00
01
02
03
04
05
06
temp
ones

LIBRARY ieee;
ENTITY count_ones IS
PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
ones: OUT INTEGER RANGE 0 TO 8);
END count_ones;
ARCHITECTURE not_ok OF count_ones IS
SIGNAL temp: INTEGER RANGE 0 TO 8;
BEGIN
PROCESS (din)
BEGIN
temp <= 0;
IF (din(i)='1') THEN
temp <= temp + 1;
END IF;
END LOOP;
ones <= temp;
END PROCESS;
END not_ok;
76
ns

Nhm 4
7.3.
VARIABLE
Ngc li vi CONSTANT v SIGNAL, VARIABLE ch biu din

thng tin cc b. N ch c th c s dng bn trong PROCESS,
FUNCTION, hay PROCEDURE (trong m tun t). Vic cp nht gi tr ca
n l tc th, v vy gi tr mi c th c lp tc s dng trong dng lnh tip
theo ca m.
C php:
VARIABLE name : type [range] [:= init_value];
V d:
VARIABLE control: BIT := '0';
VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
Khi VARIABLE ch c th c s dng trong m tun t, khai bo ca

n ch c th c thc hin trong phn khai bo ca PROCESS, FUNCTION,
hay PROCEDURE.
Php ton gn ca VARIABLE l := (count:=35;). Cng ging nh
trng hp ca SIGNAl, gi tr khi to khng th tng hp c, ch c xt
khi m phng.
V d 7.3a:
B m s s 1 ca mt vector nh phn
Khi cp nht bin l tc th, gi tr khi to c thit lp chnh xc v
khng c thng bo no v nhiu php gn do trnh bin dch.
50
din
00
01
ones
100
02
150
200
250
03
04
05
300
06
350
400
450
07
08
09
500
0A
LIBRARY ieee;
ENTITY count_ones IS
PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
ones: OUT INTEGER RANGE 0 TO 8);
END count_ones;
ARCHITECTURE ok OF count_ones IS
BEGIN
PROCESS (din)
VARIABLE temp: INTEGER RANGE 0 TO 8;
77
550
600
ns
0B
0C
0D

Nhm 4
BEGIN
temp := 0;
IF (din(i)='1') THEN
temp := temp + 1;
END IF;
END LOOP;
ones <= temp;
END PROCESS;
END ok;
SIGNAL
<=
Biu din s kt ni cc
mch (cc dy)
C th l ton cc (trn
ton b m)
Php gn
Tnh nng
Phm vi
Hot ng
Cp nht khng tc th
trong m tun t (gi tr
mi ch c th dng lc
kt thc PROCESS,
FUNCTION,
hay
PROCEDURE)
Trong
PACKAGE,
ENTITY,
hay
ARCHITECTURE.
Trong ENTITY, tt c
cc PORT l cc
SIGNAL mc nh
S dng
VARIABLE
:=
Biu din thng tin cc
b
Cc b (ch trong
PROCESS,
FUNCTION,
hay
PROCEDURE tng
ng)
Cp nht tc th (gi tr
mi c th c s
dng trong dng lnh
tip theo ca m)
Ch trong m tun t,
trong
PROCESS,
FUNCTION,
hay
PROCEDURE
Bng 7.1. So snh gia SIGNAL v VARIABLE

V d 7.3b:
B dn knh 4-1
Hnh 7.3b.1. B dn knh 4-1
78

Nhm 4
Cch 1:
S dng SIGNAL (khng ng)
-- Solution 1: using a SIGNAL (not ok) -LIBRARY ieee;
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE not_ok OF mux IS
SIGNAL sel : INTEGER RANGE 0 TO 3;
BEGIN
PROCESS (a, b, c, d, s0, s1)
BEGIN
sel <= 0;
IF (s0='1') THEN sel <= sel + 1;
END IF;
IF (s1='1') THEN sel <= sel + 2;
END IF;
CASE sel IS
WHEN 0 => y<=a;
WHEN 1 => y<=b;
WHEN 2 => y<=c;
WHEN 3 => y<=d;
END CASE;
END PROCESS;
END not_ok;
Cch 2:
S dng VARIABLE (ng)
-- Solution 2: using a VARIABLE (ok) ---LIBRARY ieee;
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE ok OF mux IS
BEGIN
PROCESS (a, b, c, d, s0, s1)
VARIABLE sel : INTEGER RANGE 0 TO 3;
BEGIN
sel := 0;
IF (s0='1') THEN sel := sel + 1;
79

Nhm 4
END IF;
IF (s1='1')
END IF;
CASE sel IS
WHEN 0
WHEN 1
WHEN 2
WHEN 3
END CASE;
END PROCESS;
END ok;
THEN sel := sel + 2;

=>
=>
=>
=>
y<=a;
y<=b;
y<=c;
y<=d;
Mt li thng xuyn khi s dng SIGNAL l khng nh n c th yu

cu mt khong thi gian cp nht. Do , php gn sel <= sel + 1 (dng 16)
trong cch 1, kt qu cng thm 1 bt k gi tr va c to lin trc cho sel,
vi php gn sel <= 0 (dng 15) c th khng c thi gian to. iu ny
ng vi vi sel <= sel +2 (dng 18). y khng l vn khi s dng
VARIABLE, php gn ca n lun tc th.
Kha cnh th 2 c th l mt vn trong cch 1 l hn mt php ton
ang c to cho cng SIGNAL (sel, dng 15, 16, v 18), c th khng c
chp nhn. Tm li, ch mt php gn vi SIGNAL c php bn trong
PROCESS, v vy phn mm ch xt php gn cui cng (sel <= sel +2) hoc
n gin l a ra thng bo li v kt thc vic bin dch. y cng khng
bao gi l vn khi s dng VARIABLE.
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
ns
600
ns
s0
s1
a
b
c
d
y
50
100
150
200
250
300
350
400
450
500
s0
s1
a
b
c
d
y
Hnh 7.3b.2. Kt qu m phng cch 1 v 2

V d 7.3c:
DFF vi q v qbar
80
550

Nhm 4
Hnh 7.3c.1. DFF

Cch 1:
Khng ng
---- Solution 1: not OK --------------LIBRARY ieee;
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
ARCHITECTURE not_ok OF dff IS
BEGIN
PROCESS (clk)
BEGIN
q <= d;
qbar <= NOT q;
END IF;
END PROCESS;
END not_ok;
Cch 2:
ng
---- Solution 2: OK ------------------LIBRARY ieee;
ENTITY dff IS
END dff;
ARCHITECTURE ok OF dff IS
BEGIN
PROCESS (clk)
BEGIN
q <= d;
END IF;
END PROCESS;
81

Nhm 4
qbar <= NOT q;
END ok;
Trong cch 1, cc php gn q<=d (dng 16) v qbar<=NOT q (dng 17)

u ng b, v vy cc gi tr mi ca chng s ch c dng lc kt thc
PROCESS. y l vn i vi qbar, bi v gi tr mi ca q khng va mi
to ra. Do , qbar s nhn gi tr o gi tr c ca q. Gi tr ng ca qbar s
b tr mt chu k ng h, gy cho mch lm vic khng chnh xc.
Trong cch 2, thay qbar<=NOT q (dng 30) bn ngoi PROCESS, do
php tnh nh mt biu thc ng thi ng.
50
100
150
200
250
300
350
400
450
500
550
600
ns
50
100
150
200
250
300
350
400
450
500
550
600
ns
d
clk
q
qbar
d
clk
q
qbar
Hnh 7.3c.2. Kt qu m phng cch 1 v 2

V d 7.3d:
B chia tn, chia tn s clock bi 6.
Hnh 7.3d.1. B chia tn

Thc hin hai u ra, mt l da trn SIGNAL (count1), v mt da trn
VARIABLE (count2).
20
40
60
80
100
120
140
160
180
200
220
clk
count1
count2
out1
out2
Hnh 7.3d.2. Kt qu m phng

LIBRARY ieee;
82
240
260
280
300
ns

Nhm 4
ENTITY freq_divider IS
PORT ( clk : IN STD_LOGIC;
out1, out2 : BUFFER STD_LOGIC);
END freq_divider;
ARCHITECTURE example OF freq_divider IS
SIGNAL count1 : INTEGER RANGE 0 TO 7;
BEGIN
PROCESS (clk)
VARIABLE count2 : INTEGER RANGE 0 TO 7;
BEGIN
count1 <= count1 + 1;
count2 := count2 + 1;
IF (count1 = 7 ) THEN
out1 <= NOT out1;
count1 <= 0;
END IF;
IF (count2 = 7 ) THEN
out2 <= NOT out2;
count2 := 0;
END IF;
END IF;
END PROCESS;
END example;
7.4.
S thanh ghi.
S flip-flop c suy ra t m bi trnh bin dch. Mc ch l khng

ch hiu tip cn yu cu s thanh ghi ti thiu, m cn m bo on m thc
hin mch mong mun.
Mt SIGNAL sinh mt flip-flop bt c khi no mt php gn c to
ra ti s chuyn tip ca tn hiu khc, khi mt php gn ng b xy ra. Php
gn ng b, c th ch xy ra bn trong PROCESS, FUNCTION, hay
PROCEDURE (thng l mt khai bo kiu IF signalEVENT hoc
WAIT UNTIL ).
Mt VARIABLE s khng sinh cc flip-flop cn thit nu gi tr ca n
khng bao gi ri PROCESS (hoc FUNCTION, hoc PROCEDURE). Tuy
nhin, nu mt gi tr c gn cho mt bin ti s chuyn tip ca tn hiu
khc, v gi tr thm ch c a ti mt tn hiu (ri PROCESS), th cc flipflop s c suy ra. Mt VARIABLE cn sinh mt thanh ghi khi n c s
dng trc mt gi tr va c gn cho n.
V d:
Trong PROCESS, output1 v output2 u s c lu tr (suy ra cc
flip-flop), bi v c hai u c gn ti s chuyn tip ca tn hiu khc (clk).
PROCESS (clk)
83

Nhm 4
BEGIN
output1 <= temp; -- output1 stored
output2 <= a; -- output2 stored
END IF;
END PROCESS;
Trong PROCESS tip theo, ch output1 c lu tr (output2 s to

cch s dng cc cng logic).
PROCESS (clk)
BEGIN
output1 <= temp; -- output1 stored
END IF;
output2 <= a; -- output2 not stored
END PROCESS;
Trong PROCESS, bin temp s gy ra tn hiu x lu tr
PROCESS (clk)
VARIABLE temp: BIT;
BEGIN
temp <= a;
END IF;
x <= temp; -- temp causes x to be stored
END PROCESS;
V d 7.4a:
DFF vi q v qbar
Cch 1 c 2 php gn SIGNAL ng b (dng 16-17), v vy 2 flip-flop
s c sinh. Cch 2 c mt trong cc php gn l ng b, vic tng hp s
lun suy ra ch mt flip-flop
Hnh 7.4a.1. Cc mch suy ra t m ca cch 1 v 2
84

Nhm 4
50
100
150
200
250
300
350
400
450
500
550
600
ns
50
100
150
200
250
300
350
400
450
500
550
600
ns
d
clk
q
qbar
d
clk
q
qbar
Hnh 7.4a.2. Kt qu m phng cch 1 v 2

Cch 1:
Sinh hai DFF
---- Solution 1: Two DFFs --------------LIBRARY ieee;
ENTITY dff IS
END dff;
ARCHITECTURE two_dff OF dff IS
BEGIN
PROCESS (clk)
BEGIN
q <= d; -- generates a register
qbar <= NOT d; -- generates a register
END IF;
END PROCESS;
END two_dff;
Cch 2:
Sinh mt DFF
---- Solution 2: One DFF ---------------LIBRARY ieee;
ENTITY dff IS
END dff;
ARCHITECTURE one_dff OF dff IS
BEGIN
85

Nhm 4
PROCESS (clk)
BEGIN
q <= d; -- generates a register
END IF;
END PROCESS;
qbar <= NOT q; -- uses logic gate (no register)
END one_dff;
V d 7.4b:
B m 0 - 7
Hnh 7.4b.1. B m 0 7
Cch 1:
Mt php gn VARIABLE ng b c tao ra (dng 14-15). Mt
VARIABLE c th sinh cc thanh ghi bi v php gn ca n (dng 15) ti s
chuyn tip ca tn hiu khc (clk, dng 14) v gi tr ca n khng ri
PROCESS (dng 17).
------ Solution 1: With a VARIABLE -------ENTITY counter IS
PORT ( clk, rst: IN BIT;
count: OUT INTEGER RANGE 0 TO 7);
END counter;

BEGIN
PROCESS (clk, rst)
VARIABLE temp: INTEGER RANGE 0 TO 7;
BEGIN
IF (rst='1') THEN
temp:=0;
temp := temp+1;
END IF;
count <= temp;
86

Nhm 4
END PROCESS;
END counter;
Cch 2:
Mt php gn SIGNAL ng b xy ra (dng 13-14). Ch s dng cc
SIGNAL. Ch , khi khng c tn hiu ph c s dng, count cn c khai
bo nh kiu BUFFER (dng 14), bi v n c gn mt gi tr v cng c
c (s dng) ni ti (dng 14). Mt SIGNAL, ging nh mt VARIABLE, c
th cng c tng khi s dng trong m tun t.
------ Solution 2: With SIGNALS only ------ENTITY counter IS
PORT ( clk, rst: IN BIT;
count: BUFFER INTEGER RANGE 0 TO 7);
END counter;
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
count <= 0;
count <= count + 1;
END IF;
END PROCESS;
END counter;
T 2 cch trn, 3 flip-flop c suy ra ( gi 3 bit tn hiu u ra

count).
50
100
150
200
250
300
350
400
450
500
550
600
ns
rst
clk
count
50
100
150
200
250
300
350
400
450
500
550
600
ns
rst
clk
count
Hnh 7.4b.2. Kt qu m phng cch 1 v 2

V d 7.4c:
Thanh ghi dch 4 cp
87

Nhm 4
Hnh 7.4c.1. Thanh ghi dch 4 cp

Cch 1:
3 VARIABLE c s dng (a, b, v c, dng 10). Tuy nhin cc bin
c s dng trc cc gi tr c gn cho chng (o ngc th t, bt u
vi dout, dng 13, v kt thc vi din, dng 16). Kt qu l, cc flip-flop s
c suy ra, lu tr cc gi tr t php chy lin trc ca PROCESS.
-------- Solution 1: ----------------ENTITY shift IS
PORT ( din, clk: IN BIT;
dout: OUT BIT);
END shift;
ARCHITECTURE shift OF shift IS

BEGIN
PROCESS (clk)
VARIABLE a, b, c: BIT;
BEGIN
dout <= c;
c := b;
b := a;
a := din;
END IF;
END PROCESS;
END shift;
Cch 2:
Cc bin c thay th bi cc SIGNAL (dng 8), v cc php gn c
to ra trong th t trc tip (t din-dout, dng 13-16). Khi cc php gn tn
hiu ti s chuyn tip tn hiu khc sinh cc thanh ghi, mch ng s c suy
ra.
-------- Solution 2: -----------------
ENTITY shift IS
dout: OUT BIT);
END shift;
SIGNAL a, b, c: BIT;
BEGIN
PROCESS (clk)
88

Nhm 4
BEGIN
a <= din;
b <= a;
c <= b;
dout <= c;
END IF;
END PROCESS;
END shift;
Cch 3:
Cc bin ging nhau ca cch 1 b chim, nhng trong th t trc
tip (t din-dout, dng 13-16). Tuy nhin, mt php gn cho mt bin l tc th,
v khi cc bin ang c s dng trong th t trc tip (sau khi cc gi tr va
c gn cho chng), dng 13-15 thnh 1 dng, tng ng vi c:=din. Gi
tr ca c ri PROCESS trong dng tip theo (dng 16), khi mt php gn tn
hiu (dout <= c) xy ra ti s chuyn tip ca clk. Do , mt thanh ghi s
c suy ra t cch 3, nn khng to kt qu mch chnh xc.
-------- Solution 3: -----------------
ENTITY shift IS
dout: OUT BIT);
END shift;
BEGIN
PROCESS (clk)
VARIABLE a, b, c: BIT;
BEGIN
a := din;
b := a;
c := b;
dout <= c;
END IF;
END PROCESS;
END shift;
u ra dout l bn sn clock dng sau u vo din cch 1, nhng

ch mt sn dng sau u vo cch 2.
50
100
150
200
250
300
350
400
450
500
550
600
ns
50
100
150
200
250
300
350
400
450
500
550
600
ns
din
clk
dout
din
clk
dout
89

Nhm 4
50
100
150
200
250
300
350
400
450
500
550
600
ns
din
clk
dout
Hnh 7.4c.2. Kt qu m phng cch 1, 2, v 3

V d 7.4d:
Thanh ghi dch 4 bit
Hnh 7.4d.1. Thanh ghi dch 4 bit

Bit ra (q) phi l 4 sn clock dng sau bit vo (d). Reset phi l
khng ng b, xo tt c cc u ra flip-flop v 0 khi kch hot.
Cch 1:
S dng mt SIGNAL sinh cc flip-flop. Cc thanh ghi c to bi
v mt php gn cho mt tn hiu c to ra ti s chuyn tip ca tn hiu
khc (dng 17-18).
---- Solution 1: With an internal SIGNAL --LIBRARY ieee;
ENTITY shiftreg IS
q: OUT STD_LOGIC);
END shiftreg;
SIGNAL internal: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
internal <= (OTHERS => '0');
internal <= d & internal(3 DOWNTO 1);
END IF;
END PROCESS;
q <= internal(0);
90

Nhm 4
END behavior;
Cch 2:
S dng mt VARIABLE. Php gn ti s chuyn tip ca tn hiu khc
c to ra cho mt bin (dng 17-18), nhng khi gi tr ca n ri PROCESS
(n c chuyn n mt port trong dng 20), n cng suy ra cc thanh ghi.
-- Solution 2: With an internal VARIABLE --LIBRARY ieee;
ENTITY shiftreg IS
q: OUT STD_LOGIC);
END shiftreg;
BEGIN
PROCESS (clk, rst)
VARIABLE internal: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
IF (rst='1') THEN
internal := (OTHERS => '0');
internal := d & internal(3 DOWNTO 1);
END IF;
q <= internal(0);
END PROCESS;
END behavior;
Cc mch c tng hp l ging nhau (4 flip-flop c suy ra).

50
100
150
200
250
300
350
400
450
500
550
600
clk
rst
d
internal
Hnh 7.4d.2. Kt qu m phng
91
ns

Nhm 4
Chng 8: My trng thi

Mt thit k mch s c th c chia lm 2 thnh phn: b x l d
liu v b iu khin. Mi quan h gia b iu khin v b x l d liu trong
mch c biu din
My trng thi hu hn (FSM) l mt cng ngh m hnh ho c bit
cho cc mch logic tun t. M hnh c th rt c gip trong thit k
ca nhng loi h thng no , c bit l cc thao tc ca nhng h thng
theo khun dng tun t hon ton xc nh.
8.1.
Gii thiu.
Hnh sau y ch ra s khi ca mt my trng thi mt pha. Trong

hnh ny, phn mch dy cha cc mch dy (flip-flops), phn cao cha mch
logic t hp.
92

Nhm 4
Hnh 8.1 S my trng thi

Phn mch t hp c 2 u vo v 2 u ra:
+ u vo th nht: l u vo trng thi hin ti ca my.
+ u vo th 2: l u vo t bn ngoi.
+ u ra th nht: l u ra pha ngoi
+ u ra th 2: l trng thi tip theo ca my.
Phn mch dy c:
+ 3 u vo: clock, reset, v trng thi tip theo
+ 1 u ra: trng thi hin ti.
Tt c cc flip-flop u nm trong phn ny, cc tn hiu clock v reset
phi c kt ni vi cc flip flop thc hin vic iu khin.
Nh vy, mt my tmt hu hn l mt b 6 thng s <X, Y, S, s 0, ,
>, trong :
X - Tp hp cc tn hiu vo ca tmat:
X = { x1(t),,xn(t)}
Tp cc tn hiu ra ca tmat:
Y = {y1(t),,ym(t)}
Tp hp cc trng thi ca tmat:
S = {s1(t),,ss(t)}
Hm (s, x) hm chuyn trng thi ca tmat
Hm (s,x) hm u ra ca tmat.
Tng ng vi cc phng php tnh ton hm chuyn trng thi v

hm ra, chng ta c cc loi tmat khc nhau. Hai dng tmat hu hn
chuyn dng l: tmat Moore v tmat Mealy.
Quay li vi hnh v trn, mch cn thit k c chia lm hai on.
Vic chia on nh th ny s gip chng ta thit k tt hn. Chng ta s thit
k 2 phn theo nhng cch khc nhau. C th trong mi trng VHDL, phn
mch dy chng ta s thc hin trong PROCESS v phn mch t hp chng ta
93

Nhm 4
c th thc hin theo cu trc hoc tun t hoc kt hp c cu trc ln tun t.
Tuy nhin m tun t c th p dng cho c 2 loi logic: t hp v tun t.
Thng thng cc tn hiu clock v cc tn hiu reset trong phn mch
dy s xut hin trong PROCESS (tr khi tn hiu reset l ng b hoc khng
c s dng, tn hiu WAIT c s dng thay cho lnh IF). Khi tn hiu reset
c xc nhn, trng thi hin ti s c thit lp cho trng thi khi to ca
h thng. Mt khc, ti sn ng h thc t, cc flip-flop s lu tr trng thi
tip theo, do s chuyn n ti u ra ca phn mch dy (trng thi hin ti).
Mt iu quan trng lin quan ti phng php FSM l : v nguyn tc
chung l bt k mt mch dy no cng c th c m hnh ho thnh 1 my
trng thi, nhng iu ny khng phi lun lun thun li. V c nhiu trng
hp (c bit l cc mch thanh ghi nh: b m,) nu thit k theo phng
php FSM th m ngun c th tr nn di hn, phc tp hn, mc nhiu li
hn so vi phng php thng thng.
Nh thnh mt quy tc nh, phng php FSM th thch hp vi cc h
thng m thao tc ca n l mt dy hon ton c cu trc, v d: cc mch
iu khin s. V i vi cc h thng loi ny th tt c cc trng thi ca n
c th d dng c lit k. Khi son tho m VHDL, th cc trng thi ny s
c khai bo trong phn u ca phn ARCHITECTURE di dng kiu d
liu lit k c nh ngha bi ngi s dng.
8.2.
Thit k theo kiu 1 (thit k theo m hnh may moore).
C vi phng php c th c hnh thnh thit k mt FSM.

Chng ta s m t chi tit mt v d mu m mch hon ton c cu trc v
d dng p dng. Trong phn mch dy ca my trng thi s tch bit vi
phn mch t hpca n (hnh v trn).
Tt c cc trng thi ca my lun lun c khai bo r rng bng cch
s dng kiu d liu lit k.
Thit k phn mch dy:

Trn hnh trn, cc flip-flop nm phn mch dy. Cc u vo t bn
ngoi ca phn ny l cc tn hiu clock v reset. Cc tn hiu ny c ni vi
cc Flip-flop. Mt u vo khc (bn trong) l trng thi tip theo. u ra duy
nht ca phn ny l trang thi hin ti. xy dng cho phn mch dy ny,
ta cn s dng cu trc PROCESS. Trong cu trc ca PROCESS chng ta co
th s s dng cc cu lnh tun t nh lnh IF, WAIT, CASE, LOOP.
Khun mu thit k ca phn mch dy s nh sau:
PROCESS (reset, clock)
BEGIN
IF reset = 1 THEN
Trang_thai_hien_tai <= Trang_thai_0 ;
ELSIF (clock EVENT and clock = ) THEN
Trang_thai_hien_tai
94
Trang_thai_tiep_theo;
END IF ;
END PROCESS ;
<=

Nhm 4
M ch ra y l rt n gin. N ch cha mt tn hiu reset ng b.

Tn hiu reset ny s xc nh trng thi khi u ca h thng, sau l lu
tr ng b trng thi tip theo (ti sn dng ng h),v a ra u ra ca
phn mch dy trng thi hin ti.
Vic thit k cho phn mch dy ny th n gin v n l mt chun c
bn, v s lng cc thanh ghi l ti thiu. phn 7.5, chng ta bit rng s
lng cc flip flop s tnh da vo s bits cn thit m ho tt c cc trng
thi ca FSM. Bi vy nu mu c m ho theo cch mc nh (m ho nh
phn) th, chng ta s cn log2n Flip-flop, vi n l s trng thi.
Thit k phn mch t hp:
hnh 1, th phn mch t hp l y , v vy m ca n s khng
cn thit theo tun t. Tt nht, chng ta nn s dng m ng thi. Song trong
v d mu di y chng ta s s dng m tun t vi cu lnh CASE ng
vai tr trung tm.
PROCESS (input, pr_state)
BEGIN
CASE pr_state IS
WHEN state0 =>
IF (input = ...) THEN
output <= <value>;
nx_state <= state1;
ELSE ...
END IF;
WHEN state1 =>
output <= <value>;
nx_state <= state2;
ELSE ...
END IF;
WHEN state2 =>
output <= <value>;
nx_state <= state2;
ELSE ...
END IF;
...
END CASE;
END PROCESS;
95

Nhm 4
on m y cng rt n gin, v n s thc hin 2 cng vic chnh:
+
Gn gi tr cho u ra.
+
Thit lp trang thi tip theo.
Mu my trng thi cho kiu thit k 1:
Di y l khun mu hon chnh v kiu thit k 1:
LIBRARY ieee;
----------------------------------------------------ENTITY <entity_name> IS
PORT ( input: IN <data_type>;
reset, clock: IN STD_LOGIC;
output: OUT <data_type>);
END <entity_name>;
----------------------------------------------------ARCHITECTURE <arch_name> OF <entity_name> IS
TYPE state IS (state0, state1, state2, state3, ...);
SIGNAL pr_state, nx_state: state;
BEGIN
---------- Phn mch dy: -----------------------PROCESS (reset, clock)
BEGIN
IF (reset='1') THEN
pr_state <= state0;
ELSIF (clock'EVENT AND clock='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------Phn mch t hp: -----------------------PROCESS (input, pr_state)
BEGIN
CASE pr_state IS
WHEN state0 =>
output <= <value>;
nx_state <= state1;
ELSE ...
END IF;
WHEN state1 =>
output <= <value>;
nx_state <= state2;
ELSE ...
END IF;
WHEN state2 =>
output <= <value>;
nx_state <= state3;
ELSE ...
END IF;
...
96

Nhm 4
END CASE;
END PROCESS;
END <arch_name>;
V d 8.1: B m BCD
Mt b m l mt v d ca my Moore, u ra ch ph thuc vo kt
qu ca trng thi hin ti. Ging nh mt mch thanh ghi v mt mch dy
n gin. thit k mch ny, chng ta c th dng phng php thng
thng nh nhng phn mch mch t hp, nhng y ta s dng phng
php FSM.
Gi s ta cn thit k b m modul 10. Nh vy chng ta s cn c mt
may c 10 trang thi. Cc trng thi y c gi l zero, one,,nine.
hnh trng thi ca my c cho nh sau:
Hnh 8.2. S trng thi ca b m BCD

M VHDL cng ging nh khun mu ca thit k mu 1. Trong :
kiu d liu lit k s xut hin dng 11 12, thit k ca phn mch dy s
t dng 16 n dong 23, thit k ca phn mch t hp(mch t hp) s xut
hin t dng 25 29. Do c 10 trang thi nn s lng cac thanh ghi bng l
[log210 ]= 4.
M thit k s nh sau:
------------------------------------------------LIBRARY ieee;
------------------------------------------------ENTITY counterBCD IS
PORT ( clk, rst: IN STD_LOGIC;
count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END counterBCD;
------------------------------------------------ARCHITECTURE state_machine OF counterBCD IS
97

Nhm 4
TYPE state IS (zero, one, two, three, four,
five, six, seven, eight, nine);
BEGIN
------------- Phan mach day: ----------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= zero;
END IF;
END PROCESS;
------------- Phan mach to hop: ----------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
count <= "0000";
nx_state <= one;
WHEN one =>
count <= "0001";
nx_state <= two;
WHEN two =>
count <= "0010";
nx_state <= three;
WHEN three =>
count <= "0011";
nx_state <= four;
WHEN four =>
count <= "0100";
nx_state <= five;
WHEN five =>
count <= "0101";
nx_state <= six;
WHEN six =>
count <= "0110";
nx_state <= seven;
WHEN seven =>
count <= "0111";
nx_state <= eight;
WHEN eight =>
count <= "1000";
nx_state <= nine;
WHEN nine =>
count <= "1001";
nx_state <= zero;
END CASE;
END PROCESS;
END state_machine;
-------------------------------------------------
M phng kt qu:
98

Nhm 4
Hnh 8.3. Kt qu m phng ca b m BCD

V d 8.2: My trng thi kt thc kiu 1
Hnh 4 l s khi ca 1 FSM n gin. H thng c 2 trng thi:
trng thi A v trng thi B. My phi chuyn trng thi khi nhn c d = 1 v
u ra mong mun l x = a khi my trng thi A hoc x = b khi my trng
thi B.
Hnh 8.4. My trng thi ca v d 8.2

M thit k s nh sau:
------------------------------------------------LIBRARY ieee;
---------------------------------------------ENTITY vd_FSM IS
PORT ( a, b, d, clk, rst: IN BIT;
x: OUT BIT);
END vd_FSM;
---------------------------------------------ARCHITECTURE state_machine OF vd_FSM IS
TYPE state IS (stateA, stateB);
BEGIN
---------- Phan mach day: ---------------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= stateA;
99

Nhm 4
END IF;
END PROCESS;
---------- Phan mach to hop: ----------------PROCESS (a, b, d, pr_state)
BEGIN
CASE pr_state IS
WHEN stateA =>
x <= a;
IF (d='1') THEN nx_state <= stateB;
ELSE nx_state <= stateA;
END IF;
WHEN stateB =>
x <= b;
IF (d='1') THEN nx_state <= stateA;
ELSE nx_state <= stateB;
END IF;
END CASE;
END PROCESS;
END state_machine;
----------------------------------------------
Kt qu m phng:

8.3.
Thit k kiu 2.
Nh chng ta thy trong kiu thit k 1 th ch c trng thi hin ti

c lu tr. Tt c cc mch nh vy s c tm tt nh trong hnh 8.6.1.
Trong trng hp ny nu mch l my Mealy (u ra ca n ph thuc vo
u vo hin ti), u ra c th thay i khi u vo thay i (u ra khng
ng b).
Trong nhiu ng dng, tn hiu c yu cu l ng b, th u ra s
ch cp nht khi thay i sn clock. to ra my ng b Mealy, u ra phi
c lu tr tt, nh trong hnh 8.6.2
100

Nhm 4
Hnh 8.6.1 S mch kiu 1
Hnh 8.6.2. S mch kiu 2
Cu trc nh trong hnh 8.6.2 s l i tng ca thit k kiu 2.

thc hin cu trc mi ny, chng ta cn c vi s thay i so vi
thit k kiu 1. V d, chng ta c th s dng mt tn hiu thm (nh tn hiu
trung gian) tnh ton gi tr u ra (on trn), nhng ch chuyn cc gi tr
ca n thnh tn hiu u ra khi s kin clock thay i (phn mch dy). S
thay i ny chng ta s thy trong khun mu ch ra di y:
Khun mu my trng thi ca thit k 2
LIBRARY ieee;
------------------------------------------------------ENTITY <ent_name> IS
PORT (input: IN <data_type>;
reset, clock: IN STD_LOGIC;
output: OUT <data_type>);
END <ent_name>;
------------------------------------------------------ARCHITECTURE <arch_name> OF <ent_name> IS
TYPE states IS (state0, state1, state2, state3, ...);
SIGNAL pr_state, nx_state: states;
SIGNAL temp: <data_type>;
BEGIN
---------Phan mach to hop: ----------------------------------Phan mach day: -------------------------PROCESS
(pr_state)
PROCESS
(reset,
clock)
BEGIN
BEGIN
CASE pr_state IS
IF (reset='1') THEN
pr_state
WHEN
state0<==>state0;
ELSIF (clock'EVENT
AND clock='1') THEN
temp <= <value>;
output
temp;
IF <=
(condition)
THEN nx_state <= state1;
pr_state
<=
nx_state;
...
END IF;
END IF;
END PROCESS;
WHEN state1 =>
temp <= <value>;
IF (condition) THEN nx_state <= state2;
...
END IF;
WHEN state2 =>
temp <= <value>;
IF (condition) THEN nx_state <= state3;
...
END IF;
...
END CASE;
101
END PROCESS;
END <arch_name>;

Nhm 4
So snh khun mu ca thit k kiu 2 vi thit k kiu 1, chng ta thy

ch c mt s khc nhau duy nht, l xut hin tn hiu trung gian temp. Tn
hiu ny s c tc dng lu tr u ra ca my. Ch cho cc gi tr chuyn
thnh u ra khi khi c s thay i s kin clock.
V d 8.3:
Chng ta s nhn li thit k ca v d 8.2. Tuy nhin y chng ta
mun u ra l ng b (ch thay i khi c s kin thay i clock). V vy
trong v d ny chng ta s thit k theo kiu 2.
----------------------------------------------
library IEEE;
---------------------------------------------ENTITY VD_FSM2 IS
PORT ( a, b, d, clk, rst: IN BIT;
x: OUT BIT);
END VD_FSM2;
---------------------------------------------ARCHITECTURE VD_FSM2 OF VD_FSM2 IS
TYPE state IS (stateA, stateB);
SIGNAL temp: BIT;
BEGIN
----- Phan mach day: ---------------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= stateA;
102

Nhm 4
x <= temp;
END IF;
END PROCESS;
---------- Phan mach to hop: ----------------PROCESS (a, b, d, pr_state)
BEGIN
CASE pr_state IS
WHEN stateA =>
temp <= a;
IF (d='1') THEN nx_state <= stateB;
ELSE nx_state <= stateA;
END IF;
WHEN stateB =>
temp <= b;
IF (d='1') THEN nx_state <= stateA;
ELSE nx_state <= stateB;
END IF;
END CASE;
END PROCESS;
END VD_FSM2;
----------------------------------------------
y chng ta thy c 2 flip flop c s dng, mt ci m ho trng thi

ca my, mt ci lu tr u ra.
B m phng kt qu c ch ra trong hnh di y:
Hnh 8.7.Kt qu m phng cho v d 8.3

V d 8.4. B pht hin chui
Chng ta mun thit k mt mch m u vo l lung bit ni tip v
u ra l 1 khi u c xut hin chui 111, l 0 trong cc trng hp cn li
hnh trng thi ca my c ch ra trong hnh 8. y chng ta c
4 trng thi v chng ta quy c l trng thi zero, one, tow, three.
+
Trang thi 0 l trng thi ch 1 u tin.
+
Trang thai 1 l trang thi c 1 v ch 1 th 2
+
Trng thi 2 l trng thi c 11 v ang ch 1 th 3.
+
Trng thi 3 l trng thi thu c xu 111.
103

Nhm 4
Hnh 8.8. S trng thi ca b pht hin chui

M ca my c thit k nh sau:
---------------------------------------------library IEEE;
---------------------------------------------ENTITY Bo_doan_xau IS
PORT ( d, clk, rst: IN BIT;
q: OUT BIT);
END Bo_doan_xau;
-------------------------------------------ARCHITECTURE state_machine OF Bo_doan_xau IS
TYPE state IS (zero, one, two, three);
BEGIN
--------- Phan mach day: -------------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= zero;
END IF;
END PROCESS;
---------- Phan mach to hop: --------------PROCESS (d, pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
q <= '0';
IF (d='1') THEN nx_state <= one;
ELSE nx_state <= zero;
END IF;
WHEN one =>
q <= '0';
IF (d='1') THEN nx_state <= two;
END IF;
WHEN two =>
104

Nhm 4
q <= '0';
IF (d='1') THEN nx_state <= three;
END IF;
WHEN three =>
q <= '1';
IF (d='0') THEN nx_state <= zero;
ELSE nx_state <= three;
END IF;
END CASE;
END PROCESS;
END state_machine;
--------------------------------------------
Kt qu m phng s nh sau:
Hnh 8.9.Kt qu m phng cho b on nhn xu.

V d 8.5: B iu khin n giao thng (TLC)
Nh gii thiu phn mch mch t hp, b iu khin s l mch v
d tt c th thc hin hiu qu khi m hnh ho my trng thi. Trong v d
ny, chng ta s thit k mt TLC vi nhng c im c tm lc nh
trong hnh 8.10:
Hnh 8.10.a. S nguyn l hot ng ca TLC
105

Nhm 4
Hnh 8.10.b. hnh trng thi ca TLC

y chng ta thy c 3 ch thao tc:
+ Ch bnh thng: ch ny, mch c 4 trng thi, mi trng
thi l c lp, thi gian lp trnh .?
+ Ch kim tra: Cho php tt c thi gian c lp trnh trc c
vit ln vi 1 gi tr nh, do vy h thng c th d dng c kim tra trong
sut qu trnh ba dng.
+ Ch Standby: Nu thit lp h thng s kch hot n vng trong
khi tn hiu standby c kch hot.
ng thi 1 ng h tn s 60 HZ lun hot ng.
M thit k:
-----------------------------------------------------------library IEEE;
ENTITY Bodk_den_giao_thong IS
PORT ( clk, stby, test: IN STD_LOGIC;
r1, r2, y1, y2, g1, g2: OUT STD_LOGIC);
END Bodk_den_giao_thong;
------------------------------------------------ARCHITECTURE state_machine_be OF Bodk_den_giao_thong IS
CONSTANT timeMAX : INTEGER := 2700;
CONSTANT timeRG : INTEGER := 1800;
CONSTANT timeRY : INTEGER := 300;
CONSTANT timeGR : INTEGER := 2700;
CONSTANT timeYR : INTEGER := 300;
CONSTANT timeTEST : INTEGER := 60;
TYPE state IS (RG, RY, GR, YR, YY);
SIGNAL time : INTEGER RANGE 0 TO timeMAX;
BEGIN
-------------Phan mach day: ---PROCESS (clk, stby)
VARIABLE count : INTEGER RANGE 0 TO timeMAX;
BEGIN
IF (stby='1') THEN
pr_state <= YY;
106

Nhm 4
count := 0;
count := count + 1;
IF (count = time) THEN
count := 0;
END IF;
END IF;
END PROCESS;
----------- Phan mach to hop: ---PROCESS (pr_state, test)
BEGIN
CASE pr_state IS
WHEN RG =>
r1<='1';r2<='0';y1<='0'; y2<='0'; g1<='0'; g2<='1';
nx_state <= RY;
IF (test='0') THEN time <= timeRG;
ELSE time <= timeTEST;
END IF;
WHEN RY =>
r1<='1';r2<='0';y1<='0';y2<='1';g1<='0'; g2<='0';
nx_state <= GR;
IF (test='0') THEN time <= timeRY;
END IF;
WHEN GR =>
r1<='0';r2<='1';y1<='0';y2<='0';g1<='1'; g2<='0';
nx_state <= YR;
IF (test='0') THEN time <= timeGR;
END IF;
WHEN YR =>
r1<='0';r2<='1';y1<='1'; y2<='0'; g1<='0'; g2<='0';
nx_state <= RG;
IF (test='0') THEN time <= timeYR;
END IF;
WHEN YY =>
r1<='0';r2<='0';y1<='1'; y2<='1'; g1<='0'; g2<='0';
nx_state <= RY;
END CASE;
END PROCESS;
END state_machine_be;
----------------------------------------------------
Nh ta thy, s lng Flip-flop dng thc hin mch l 15 ci: 3

ci cho lu tr trng thi hin ti, 12 ci cn li cho b m.
c th d dng thy kt qu m phng, y ta thc hin gim thi gian
thc t i 100 ln.
Kt qu m phng c ch ra trong hnh di y:
+
ch hot ng bnh thng (stby = 0, test = 0):
107

Nhm 4
Hnh 8.11.a. Kt qu m phng TLC ch hd bnh thng

ch kim tra:
Hnh 8.11.b. Kt qu m phng TLC ch kim tra

V d 8.6: B pht tn hiu:
Chng ta mun thit k mt mch m t tn hiu clock clk a ra tn
hiu nh trong hnh di y:
Hnh 8.12.Dng tn hiu cn to.

y mch phi hot ng c 2 sn ca tn hiu clk.
108

Nhm 4
M chng trnh:
----------------------------------------ENTITY Bo_phat_tin_hieu IS
PORT ( clk: IN BIT;
outp: OUT BIT);
END Bo_phat_tin_hieu;
----------------------------------------ARCHITECTURE state_machine OF Bo_phat_tin_hieu IS
TYPE state IS (one, two, three);
SIGNAL pr_state1, nx_state1: state;
SIGNAL pr_state2, nx_state2: state;
SIGNAL out1, out2: BIT;
BEGIN
----- Phan mach day cua may 1: --PROCESS(clk)
BEGIN
pr_state1 <= nx_state1;
END IF;
END PROCESS;
----- Phan mach day cua may 2: --PROCESS(clk)
BEGIN
pr_state2 <= nx_state2;
END IF;
END PROCESS;
---- Phan mach to hop cua may 1: ----PROCESS (pr_state1)
BEGIN
CASE pr_state1 IS
WHEN one =>
out1 <= '0';
nx_state1 <= two;
WHEN two =>
out1 <= '1';
nx_state1 <= three;
WHEN three =>
out1 <= '1';
nx_state1 <= one;
END CASE;
END PROCESS;
---- Phan macpt hop cua may 2: ----PROCESS (pr_state2)
BEGIN
CASE pr_state2 IS
WHEN one =>
out2 <= '1';
nx_state2 <= two;
WHEN two =>
out2 <= '0';
nx_state2 <= three;
WHEN three =>
109

Nhm 4
out2 <= '1';
nx_state2 <= one;
END CASE;
END PROCESS;
outp <= out1 AND out2;
END state_machine;
------------------------------------------
Kt qu m phng:
Hnh 8.13.Kt qu m phng cho v d 8.6

8.4.
Kiu m ho: t nh phn sang Onehot.
m ho trng thi ca my trng thi, chng ta c th chn mt trong

vi kiu c sn. Kiu m ho mc nh l nh phn. u im ca kiu m ho
ny l n yu cu s lng flip-flop t nht. Trong trng hp ny, vi n mch
flip-flop th c th chng ta c th m ho c 2n trng thi. Nhc im ca
kiu m ho ny l n yu cu v logic nhiu hn v n chm hn so vi nhng
kiu khc.
Ci cui cng l kiu m ho onehot, vi kiu m ho ny, chng ta cn
s dng 1 flip-flop cho 1 trng thi. V vy, n i hi s lng flip-flop ln
nht. Trong trng hp ny, vi n flip-flop (n bit) ch c th m ho c n
trng thi. Nhng b li, phng php ny li yu cu tnh ton logic it nht, v
tc nhanh nht
Mt kiu nm gia 2 kiu trn l kiu m ho twohot (trong mt trng
thi ch c 2 bit 1). V vy vi n flip-flop (n bit), th chng ta c th m ho
c n(n-1)/2 trng thi.
Kiu m ho onehot c gii thiu trong cc ng dng m s lng
cc flip-flop nhiu nh trong cc chip FPGA. Nhng trong cc mch ASIC th
m nh phn li c u tin hn.
V d: Gi s chng ta c mt my trng thi c 8 trang thi nh trong bng
di y:
110

Nhm 4
Bng 8.1.M ho trng thi cho my FSM 8 trng thi
Vi 8 trng thi ca my ny th s lng flip-flop c yu cu ng
vi cc kiu m ho s bng:
+
3 (=log28), ng vi kiu m ho nh phn.
+
5 ( n(n-1)/2= 8 => n = 5 ), ng vi kiu m ho twohot
+
8, ng vi kiu m ho onehot.
111

Nhm 4
Chng 9: Thit k thm cc mch

Phn ny chng ta s trnh by cc mch sau:
+
Barrel shifter
+
B so snh khng du v c du.
+
B cng
+
B chia du chm tnh.
+
B iu khin my bn hng.
+
B nhn d liu ni tip.
+
B chuyn i song song sang ni tip.
+
SSD
+
B pht tn hiu
+
B nh
9.1.
Barrel Shifter.
S ca mch ca b dch barrel c ch ra trong hnh 9.1. u vo

l vector 8 bit. u ra l phin bn dch ca u vo, vi lng dch c nh
ngha bi 8 u vo shift (t o n 7). Mch gm c 3 b dch barrel ring
l, mi mt ci ging nh trong v d 6.9. Nhng chng ta phi chu rng,
barrel u tin c ch c 1 u 0 c kt ni vi mt b dn knh, trong khi
barrel th 2 c 2 u vo 0 v barrel cui cng c ti 4 u vo 0.
vector ln hn th chng ta phi d 2 u vo l 0. V d nu shift = 001
th ch barrel u tin gy ra dch, cn nu shift = 111 th tt cc u gy ra
dch.
112

Nhm 4
Hnh 9.1. B dch barrel

M thit k s nh sau:
--------------------------------------------LIBRARY ieee;
--------------------------------------------ENTITY barrel IS
PORT ( inp: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shift: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END barrel;
--------------------------------------------ARCHITECTURE behavior OF barrel IS
BEGIN
PROCESS (inp, shift)
VARIABLE temp1: STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE temp2: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
---- Bo dich thu nhat ----IF (shift(0)='0') THEN
temp1 := inp;
ELSE
temp1(0) := '0';
temp1(i) := inp(i-1);
END LOOP;
END IF;
---- Bo dich thu 2 -----
113

Nhm 4
IF (shift(1)='0') THEN
temp2 := temp1;
ELSE
temp2(i) := '0';
END LOOP;
temp2(i) := temp1(i-2);
END LOOP;
END IF;
---- Bo dich thu 3 ----IF (shift(2)='0') THEN
outp <= temp2;
ELSE
outp(i) <= '0';
END LOOP;
outp(i) <= temp2(i-4);
END LOOP;
END IF;
END PROCESS;
END behavior;
---------------------------------------------
Kt qu m phng:
Hnh 9.2.Kt qu m phng cho b dch barrel

9.2.
B so snh khng du v c du.
Hnh 9.3 hin ln s ca b so snh. Kch thc ca vector c so

snh l generic (n+1). 3 u ra phi c cung cp l: 1 u ra l a>b, 1 u ra
l a = b, u ra cn li l a < b. 3 gii php c gii thiu : u tin xt a v b
l cc s c du, trong khi 2 gii php cn li l cc s khng du. Kt qu m
phng s cho chng ta thy r hn.
114

Nhm 4
Hnh 9.3.M hnh ca b so snh
B so snh c du:
lm vic vi s c du hoc s khng du th chng ta u phi khai
bo gi std_logic_arith (c th chng ta s thy trong on m di y).
M thit k b so snh c du:
---- Bo so sanh co dau: ----------------
LIBRARY ieee;
USE ieee.std_logic_arith.all; -- can thiet!
---------------------------------------ENTITY Bo_so_sanh_co_dau IS
PORT (a, b: IN SIGNED (n DOWNTO 0);
x1, x2, x3: OUT STD_LOGIC);
END Bo_so_sanh_co_dau;
---------------------------------------ARCHITECTURE arc OF Bo_so_sanh_co_dau IS
BEGIN
x1 <= '1' WHEN a > b ELSE '0';
x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0';
END arc;
----------------------------------------
Kt qu m phng:
Hnh 9.4. Kt qu m phng b so snh c du

B so snh khng du 1:
Phn m VHDL sau y l bn sao ca phn m c trnh by ( b
so snh khng du).
---- Bo so sanh khong dau 1: ----------LIBRARY ieee;
USE ieee.std_logic_arith.all; --rat can thiet!
----------------------------------------
115

Nhm 4
ENTITY Bo_so_sanh_khong_dau1 IS
PORT (a, b: IN UNSIGNED (n DOWNTO 0);
END Bo_so_sanh_khong_dau1;
---------------------------------------ARCHITECTURE arc OF Bo_so_sanh_khong_dau1 IS
BEGIN
x1 <= '1' WHEN a > b ELSE '0';
x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0';
END arc;
----------------------------------------
Kt qu:
Hnh 9.5.1.Kt qu b so snh khng du 1

B so snh khng du 2:
B so snh khng du c th cng c thc hin vi
STD_LOGIC_VECTORS, trong trng hp ny khng cn thit phi khai bo
std_logic_arith.
M thit k s nh sau:
---- Bo so sanh khong dau: ----------LIBRARY ieee;
---------------------------------------ENTITY comparator IS
PORT (a, b: IN STD_LOGIC_VECTOR (n DOWNTO 0);
END comparator;
---------------------------------------ARCHITECTURE unsigned OF comparator IS
BEGIN
x1 <= '1' WHEN a > b ELSE '0';
x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0';
END unsigned;
116

Nhm 4
M phng kt qu:
Hnh 9.5.2. Kt qu ca b so snh khng du2

9.3.
B cng Carry Ripple v b cng Carry Look Ahead.
Carry ripple v carry look ahead l 2 phng php c in thit k

ccc b cng. Phng php u tin c thun li l yu cu phn cng t, trong
khi ci th hai li nhanh hn.
+ B cng carry ripple:
Hnhd 9.6 ch ra 1 b cng ripple cary 4 bit khng du:
Hnh 9.6. S b cng ripple carry

Trn s ta c th thy, vi mi bit, mt n v b cng y s
c thc hin. Bng tht ca b cng y c ch ra bn cnh s ,
trong a, b l cc bt u vo, cin l bit nh vo, s l bit tng, cout l bit nh
ra. T bng tht ta d dng tnh c:
s = a xor b xor cin
cout = (a and b) xor (a and cin) xor (b xor cin)
T cng thc trn ta xy dng chng trnh VHDL nh sau ( y
chng ta c th p dng cho bt k s lng u vo no):
LIBRARY ieee;
--------------------------------------------ENTITY Bo_cong_carry_ripple IS
PORT ( a, b: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0);
END Bo_cong_carry_ripple;
---------------------------------------------
117

Nhm 4
ARCHITECTURE arc OF Bo_cong_carry_ripple IS
SIGNAL c: STD_LOGIC_VECTOR (n DOWNTO 0);
BEGIN
c(0) <= cin;
G1: FOR i IN 0 TO n-1 GENERATE
s(i) <= a(i) XOR b(i) XOR c(i);
c(i+1) <= (a(i) AND b(i)) OR
(a(i) AND c(i)) OR
(b(i) AND c(i));
END GENERATE;
cout <= c(n);
END arc;
---------------------------------------------
Kt qu m phng:
Hnh 9.7. Kt qu m phng cho b cng ripple carry

+ B cng carry look ahead:
S b cng carry look ahead 4 bit c ch ra trong hnh 9.8.1 di
y:
Hnh 9.8.1. S b cng carry look ahead

Mch c hot ng da trn cc khi nim generate v propagate.
Chnh c im ny lm cho b cng ny thc hin vi tc nhanh hn so
vi b cng trc.
Gi s 2 u vo l 2 bit a,b th 2 tn hiu p(propagate) v g(generate)
c tnh nh sau:
g = a and b
118

Nhm 4
p = a or b
Nu chng ta xem a, b l cc vector:
a = a(n-1)a(1)a(0) ; b = b(n-1)b(1)b(0)
th g, p c tnh nh sau:
p = p(n-1)p(1)p(0); g = g(n-1)g(1)g(0)
Trong :
g(i) = a(i) and b(i)
p(i) = a(i) or b(i)
Lc ny vector nh s l: c = c(n-1)c(1)c(0), trong :
c(0) = cin
c(1) = c(0)p(0) + g(0)
c(2) = c(0)p(0)p(1) + g(0)p(1) + g(1)
c(i) = c(i-1)p(i-1) + g(i-1)
T cng thc tnh trn, chng ta vit chng trnh thit k b cng carry
look ahead 4 bit nh sau:
--------------------------------------------LIBRARY ieee;
--------------------------------------------ENTITY Bo_cong_carry_look_ahead IS
PORT ( a, b: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
END Bo_cong_carry_look_ahead;
--------------------------------------------ARCHITECTURE
Bo_cong_carry_look_ahead
Bo_cong_carry_look_ahead IS
SIGNAL c: STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL p: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL g: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
---- PGU: --------------------------------G1: FOR i IN 0 TO 3 GENERATE
p(i) <= a(i) XOR b(i);
g(i) <= a(i) AND b(i);
s(i) <= p(i) XOR c(i);
END GENERATE;
---- CLAU: -------------------------------c(0) <= cin;
c(1) <= (cin AND p(0)) OR
g(0);
c(2) <= (cin AND p(0) AND p(1)) OR
(g(0) AND p(1)) OR
g(1);
c(3) <= (cin AND p(0) AND p(1) AND p(2)) OR
(g(0) AND p(1) AND p(2)) OR
(g(1) AND p(2)) OR g(2);
c(4) <= (cin AND p(0) AND p(1) AND p(2) AND p(3)) OR
119
OF

Nhm 4
(g(0) AND p(1) AND p(2) AND p(3)) OR
(g(1) AND p(2) AND p(3)) OR
(g(2) AND p(3)) OR g(3);
cout <= c(4);
END Bo_cong_carry_look_ahead;
---------------------------------------------
Kt qu m phng:
Hnh 9.8.2. Kt qu m phng cho b cng carry look ahead
9.4.
B chia du chm tnh.

Trc khi i vo thit k, chng ta cn phi nhc li thut ton chia:
Thut ton chia:
Mc ch ca thut ton l chng ta cn tnh y = a/b trong a, b l

nhng s cng c (n+1) bit.
Thut ton c th hin trong bng 9.9, trong a = 1011 ( = (11)10)
v b = 0011 (=(3)10). Kt qu s thu c: thng y = 0011 (=(3)10) v s
d r = 0010 (=(2)10).
Ch s
3
2
1
0
u vo a
1011
1011
1011
0101
0010
So snh
<
<
>
>
u vo b
0011000
0001100
0000110
0000011
120
y
0
0
1
1
Thao tc cho ct a
Khng lm g
Khng lm g
Tr ct a cho ct b
Tr ct a cho ct b

Nhm 4
Hnh 9.9. Thut ton chia

Gii thch thut ton:
+
u tin chuyn s chia thnh s 2n+1 bit bng cch thm vo
sau n -1 bit 0 , s b chia vn gi nguyn.
+
So snh s b chia vi s chia . Nu s b chia ln hn hoc bng
s chia th gn y =1 v thay s b chia bng hiu ca s b chia vi s
chia. Ngc li th y =0
+
Qu trnh thc hin lin tc cho n khi ht n ln.
+
Thng l dy bit ca y, s d l s b chia cui cng.
thit k b chia ny th chng ta c 2 phng php: C 2 phng
php u thc hin theo m tun t: Phng php th nht ch thc hin bng
cu ln if, phng php th 2 thc hin bng c cu ln if v loop.
M thit k b chia s nh sau:
Thit k theo phng php 1:
----- Phuong phap 1: step-by-step ------------------LIBRARY ieee;
-------------------------------------------------ENTITY Bo_chia IS
y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rest: OUT INTEGER RANGE 0 TO 15;
err : OUT STD_LOGIC);
END Bo_chia;
-------------------------------------------------ARCHITECTURE arc OF Bo_chia IS
BEGIN
PROCESS (a, b)
BEGIN
----- Khoi tao va bat loi: ------temp1 := a;
temp2 := b;
IF (b=0) THEN err <= '1';
ELSE err <= '0';
END IF;
----- y(3): --------------------------IF (temp1 >= temp2 * 8) THEN
y(3) <= '1';
temp1 := temp1 - temp2*8;
ELSE y(3) <= '0';
121

Nhm 4
END IF;
y(2) <= '1';
temp1 := temp1 - temp2 * 4;
ELSE y(2) <= '0';
END IF;
y(1) <= '1';
temp1 := temp1 - temp2 * 2;
ELSE y(1) <= '0';
END IF;
----- y(0): --------------------------IF (temp1 >= temp2) THEN
y(0) <= '1';
temp1 := temp1 - temp2;
ELSE y(0) <= '0';
END IF;
----- Phan du: ---------------------rest <= temp1;
END PROCESS;
END arc;
--------------------------------------------------
Kt qu m phng:
Hnh 9.10.1. Kt qu m phng b chia

Thit k theo phng php 2:
------ Phuong phap 2:-----------------------------
LIBRARY ieee;
-------------------------------------------------ENTITY Bo_chia2 IS
GENERIC(n: INTEGER := 3);
y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rest: OUT INTEGER RANGE 0 TO 15;
err : OUT STD_LOGIC);
END Bo_chia2;
-------------------------------------------------ARCHITECTURE arc OF Bo_chia2 IS
BEGIN
122

Nhm 4
PROCESS (a, b)
BEGIN
----- Khoi tao gia tri va bat loi: ------temp1 := a;
temp2 := b;
IF (b=0) THEN err <= '1';
ELSE err <= '0';
END IF;
----- thuong: -----------------------------FOR i IN n DOWNTO 0 LOOP
IF(temp1 >= temp2 * 2**i) THEN
y(i) <= '1';
temp1 := temp1 - temp2 * 2**I;
ELSE y(i) <= '0';
END IF;
END LOOP;
----- phan du: ---------------------rest <= temp1;
END PROCESS;
END arc;
--------------------------------------------------
Kt qu m phng:
Hnh 9.10.2.Kt qu m phong b chia th 2
9.5.
B iu khin my bn hng.
Trong v d ny, chng ta s thit k b iu khin my bn hng, my

bn hng s bn cc thanh ko vi gi 25 xu. Chng ta s thit k theo m hnh
my FSM. u ra v u vo ca b iu khin c th hin trong hnh 9.11.
Tn hiu vo l nickel_in, dime_in, v quarter_in thng bo rng mt
ng tin tng ng c gi vo ti khon. Ngoi ra cn c 2 u vo iu
khin: u vo reset (rst) v u vo clock (clk). B iu khin tr li bng 3
tn hiu u ra: candy_out ( phn pht thanh ko), nickel_out v
dime_out(cp nht li thay i).
Trn hnh 9.11 cng ch ra hnh trng thi ca my FSM. Cc s bn
trong cc vng trn biu din tng ti khon ca khch hng (ch c cc nickel,
dime v quarter l c chp nhn).
123

Nhm 4
Hnh 9.11. hnh trng thi ca b iu khin my bn hng

Trng thi 0 l trng thi l trng thi khng lm g c. T nu 1 ng
nickel c gi vo ti khon, my s chuyn trng thi n trng thi 5, nu 1
ng dime c gi vo ti khon th my chuyn ti trng thi 10 hoc nu 1
ng quarter th my s chuyn n trng thi 25. Tnh hung tng t s c
lp li cho tt c cc trng thi, cho ti trng thai 20. Nu trng thi 25 c
xc nhn, th thanh ko c phn pht v khng chuyn i. Tuy nhin nu
trng thi 40 c xc nhn th a nickel c tr li, bi vy trng thi s
chuyn ti trng thi 35, l 1 trng thi m 1 dime c tr li v 1 candy
bar c phn pht. C 3 trng thi to ra chu trnh kp, l t 1 thanh ko
c phn pht v my tr li trng thi 0. Bi ton ny s c chia thnh 2
phn:
+ Trong phn u: din mo c bn lin quan n thit k b iu khin
my bn hng (nh trong hnh 9.11) .
+ Trong phn 2: Cc chc nng m rng c thm vo.
y chng ta ch nghin cu phn mt ca bi ton: Nhn vo hnh
trng thi ca my hnh 9.11, chng ta thy c 10 trng thi, nh vy cn c
4 bit m ho cc trng thi, tc l cn s dng 4 flip-flop.
M thit k s nh sau:
124

Nhm 4
-----------------------------------------------------LIBRARY ieee;
-----------------------------------------------------ENTITY Bo_dieu_khien_may_bh IS
PORT ( clk, rst: IN STD_LOGIC;
nickel_in, dime_in, quarter_in: IN BOOLEAN;
candy_out, nickel_out, dime_out: OUT STD_LOGIC);
END Bo_dieu_khien_may_bh;
-----------------------------------------------------ARCHITECTURE state_machine OF Bo_dieu_khien_may_bh IS
TYPE state IS (st0, st5, st10, st15, st20, st25,
st30, st35, st40, st45);
SIGNAL present_state, next_state: STATE;
BEGIN
---- Lower section of the FSM (Sec. 8.2): --------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
present_state <= st0;
present_state <= next_state;
END IF;
END PROCESS;
---- Upper section of the FSM (Sec. 8.2): --------PROCESS (present_state, nickel_in, dime_in, quarter_in)
BEGIN
CASE present_state IS
WHEN st0 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st5;
ELSIF (dime_in) THEN next_state <= st10;
ELSIF (quarter_in) THEN next_state <= st25;
ELSE next_state <= st0;
END IF;
WHEN st5 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
END IF;
WHEN st10 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
END IF;
WHEN st15 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
125

Nhm 4
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN

END IF;
st20 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
END IF;
st25 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
next_state <= st0;
st30 =>
candy_out <= '1';
nickel_out <= '1';
dime_out <= '0';
next_state <= st0;
st35 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '1';
next_state <= st0;
st40 =>
candy_out <= '0';
nickel_out <= '1';
dime_out <= '0';
next_state <= st35;
st45 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '1';
next_state <= st35;
END CASE;
END PROCESS;
END state_machine;
------------------------------------------------------
Kt qu m phng:
126

Nhm 4
Hnh 9.12.Kt qu m phng b iu khin my bn hng
9.6.
B nhn d liu ni tip.
S khi ca b nhn d liu ni tip c ch ra trong hnh 9.13. N

bao gm mt u vo d liu ni tip (din) v mt u ra d liu song song
(data(6:0)). Ngoi ra cn c tn hiu iu khin clk (tn hiu clock). Hai tn hiu
gim st c to ra bi mch l: tn hiu err (error) v tn hiu data_valid. u
vo x l cha 10 bt. Bit u tin l bit bt u, nu bit l 1 th mch bt u
nhn d liu. 7 bit tip theo l cc bit d liu hot ng. Bit th 9 l bit chn l:
bit ny = 0 nu s lng cc bit 1 trong d liu la chn v bng 1 trong
trng h cn li. Bit 10 l bit stop: bit ny s mang gi tr l 1 nu qu trnh
chuyn i l ng. Mt li c pht hin khi bit chn l khng c kim tra
hoc bit stop khng phi la 1. Khi qu trnh nhn kt thc m khng c li
no c pht hin th d liu c lu tr trong cc thanh ghi bn trong s
chuyn vo data(6:0) v u ra data_valid c xc nhn.
Hnh 9.13. S b nhn d liu ni tip

thit k mch ny chng ta s s dng mt vi bin lm cc bin
m, bin xc nhn s bit nhn c, bin lu tr d liu, bin tnh ton li v
bin trung gian.
M thit k b nhn d liu ni tip s nh sau:
--------------------------------------------LIBRARY ieee;
--------------------------------------------ENTITY Bo_nhan_du_lieu_nt IS
PORT ( din, clk, rst: IN BIT;
data: OUT BIT_VECTOR (6 DOWNTO 0);
err, data_valid: OUT BIT);
END Bo_nhan_du_lieu_nt;
--------------------------------------------ARCHITECTURE arc OF Bo_nhan_du_lieu_nt IS
BEGIN
PROCESS (rst, clk)
VARIABLE reg: BIT_VECTOR (10 DOWNTO 0);
VARIABLE temp : BIT;
BEGIN
IF (rst='1') THEN
count:=0;
reg := (reg'RANGE => '0');
127

Nhm 4
temp := '0';
err <= '0';
data_valid <= '0';
IF (reg(0)='0' AND din='1') THEN
reg(0) := '1';
ELSIF (reg(0)='1') THEN
count := count + 1;
IF (count < 10) THEN
reg(count) := din;
ELSIF (count = 10) THEN
temp := (reg(1) XOR reg(2) XOR reg(3) XOR
reg(4) XOR reg(5) XOR reg(6) XOR
reg(7) XOR reg(8)) OR NOT reg(9);
err <= temp;
count := 0;
reg(0) := din;
IF (temp = '0') THEN
data_valid <= '1';
data <= reg(7 DOWNTO 1);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END arc;
-------------------------------------------------
Kt qu m phng:
Hnh 9.14.Kt qu m phng b nhn d liu

9.7.
B chuyn song song thnh ni tip.
B chuyn song song thnh ni tip l mt loi ng dng ca thanh ghi

dch. B chuyn i ny s thc hin vic gi i mt khi d liu ni tip. Vic
s dng b chuyn i ny l rt cn thit v d: Trong cc con chip ASIC, khi
128

Nhm 4
khng c cc chn d cho ra ng thi tt c cc bit d liu. Khi
chng ta cn thit phi s dng b chuyn i song song thnh ni tip.
S khi ca b chuyn i song song thnh ni tip c trnh by
trong hnh 9.15.
Hnh 9.15.B chuyn song song thnh ni tip

Trong :
+
d(7:0) l vector d liu gi i
+
dout l u ra thc t.
+
clk: u vo ca xung clock
+
load: u vo xc nhn
Vector d c lu tr ng b trong thanh ghi dch reg. Khi load
trng thi cao th d liu c np vo thanh ghi dch theo th t bit MSB l
bt gn u ra nht, v u ra l d(7). Mi khi load tr li 0 th bit tip theo
c xut hin ti u ra ca mi sn dng ca xung ng h. Sau khi tt c
8 bit c gi i, u ra tr li mc thp cho n ln chuyn i tip theo.
M thit k nh sau:
LIBRARY ieee;
------------------------------------------------ENTITY Bo_chuyen_dl_ss_nt IS
PORT ( d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clk, load: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END Bo_chuyen_dl_ss_nt;
------------------------------------------------ARCHITECTURE Bo_chuyen_dl_ss_nt OF Bo_chuyen_dl_ss_nt IS
SIGNAL reg: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF (load='1') THEN reg <= d;
ELSE reg <= reg(6 DOWNTO 0) & '0';
END IF;
END IF;
END PROCESS;
dout <= reg(7);
END Bo_chuyen_dl_ss_nt;
129

Nhm 4
-------------------------------------------------
Kt qu m phng:
Hnh 9.16. Kt qu m phng cho b chuyn song song thnh ni tip

9.8.
Tr chi trn led 7 thanh.
Chng ta thit k tr chi vi SSD (seven segment display). S ca

mch c ch ra trong hnh 9.17. N bao gm 2 u vo l clk v stop, v mt
u ra l dout(6:0), u ra ny s c hin th trn SSD. Chng ta phi m
bo rng fdk = 1khz
Hnh 9.17. S ca SSD

Mch ca chng ta s to ra mt s chuyn ng lin tc theo chiu kim
ng h ca cc on SSD. ng thi n cn to ra s dch chuyn chng lp
gia cc thanh k nhau. Chng ta c th biu din quy trnh ca n nh sau:
a->ab->b->bc->c->cd->d->de->e->ef->f->fa->a.
130

Nhm 4
Hnh 9.18. hnh trng thi

Qu trnh s dng li khi c tn hiu Stop, v khi mch s tr li trng
thi a v ch cho n khi stop xung thp tr li. H thng ca chng ta s gi
li cc trng thi a, b, c, d , e, f trong khong thi gian time1 = 80ms v cc
trng thi ab, bc, cd, de, ef, fa l time2 = 30ms.
M chng trnh ca chng ta s nh sau:
-------------------------------------------------------LIBRARY ieee;
-------------------------------------------------------ENTITY Trochoiled7thanh IS
PORT ( clk, stop: IN BIT;
dout: OUT BIT_VECTOR (6 DOWNTO 0));
END Trochoiled7thanh;
-------------------------------------------------------ARCHITECTURE arc OF Trochoiled7thanh IS
CONSTANT time1: INTEGER := 4; -- Gia tri thuc te hien thi la
80
CONSTANT time2: INTEGER := 2; -- Gia tri thuc te hien thi is
30
TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);
SIGNAL present_state, next_state: STATES;
SIGNAL count: INTEGER RANGE 0 TO 5;
SIGNAL flip: BIT;
BEGIN
------- Phan mach day cua arc : -----------PROCESS (clk, stop)
BEGIN
IF (stop='1') THEN
present_state <= a;
IF ((flip='1' AND count=time1) OR
(flip='0' AND count=time2)) THEN
count <= 0;
131

Nhm 4
ELSE count <= count + 1;
END IF;
END IF;
END PROCESS;
------- Phan mach to hop: -----------PROCESS (present_state)
BEGIN
WHEN a =>
dout <= "1000000"; -- Decimal
flip<='1';
next_state <= ab;
WHEN ab =>
dout <= "1100000"; -- Decimal
flip<='0';
next_state <= b;
WHEN b =>
dout <= "0100000"; -- Decimal
flip<='1';
next_state <= bc;
WHEN bc =>
dout <= "0110000"; -- Decimal
flip<='0';
next_state <= c;
WHEN c =>
dout <= "0010000"; -- Decimal
flip<='1';
next_state <= cd;
WHEN cd =>
dout <= "0011000"; -- Decimal
flip<='0';
next_state <= d;
WHEN d =>
dout <= "0001000"; -- Decimal
flip<='1';
next_state <= de;
WHEN de =>
dout <= "0001100"; -- Decimal
flip<='0';
next_state <= e;
WHEN e =>
dout <= "0000100"; -- Decimal
flip<='1';
next_state <= ef;
WHEN ef =>
dout <= "0000110"; -- Decimal
flip<='0';
next_state <= f;
WHEN f =>
dout <= "0000010"; -- Decimal
flip<='1';
next_state <= fa;
WHEN fa =>
dout <= "1000010"; -- Decimal
flip<='0';
132
64
96
32
48
16
24
12
66

Nhm 4
next_state <= a;
END CASE;
END PROCESS;
END arc;
--------------------------------------------------------
Kt qu m phng:
Hnh 9.19. Kt qu m phng cho tr chi trn SSD

9.9.
B pht tn hiu.
T mt tn hiu clock, chng ta mong mun thu c mt tn hiu c

dang sng nh trong hnh 9.20. Vi bi ton loi ny, chng ta c th s dng
phng php FSM hoc phng php truyn thng. C 2 phng php u
c chng ta trnh by di y:
Phng php FSM:
Hnh 9.20 Hnh dng sng cn pht

Tn hiu ca hnh 9.20 c th c m hnh nh mt FSM 8 trng thi.
S dng b m t 0 n 7. Chng ta c th thit lp mt sng bng 0 khi
bin m = 0 ( xung th nht) v bng 1 khi bin m = 1 (xung th
hai),vvnh trong hnh 9.20. thc thi c b to sng ny th yu cu 4
flip-flop: trong c 3 ci lu tr s m (3 bit), mt ci lu tr sng (1
bit ). thit k b to sng ny, chng ta thit k theo kiu 2, c th s nh
sau:
----------------------------------------------------LIBRARY ieee;
----------------------------------------------------ENTITY Bo_phat_tin_hieu IS
PORT (clk: IN STD_LOGIC;
wave: OUT STD_LOGIC);
END Bo_phat_tin_hieu;
133

Nhm 4
----------------------------------------------------ARCHITECTURE arc OF Bo_phat_tin_hieu IS
TYPE states IS (zero, one, two, three, four, five,
seven);
SIGNAL present_state, next_state: STATES;
SIGNAL temp: STD_LOGIC;
BEGIN
--- Phan mach day: --PROCESS (clk)
BEGIN
wave <= temp;
END IF;
END PROCESS;
--- Phan mach to hop: --PROCESS (present_state)
BEGIN
WHEN zero => temp<='0'; next_state <= one;
WHEN one => temp<='1'; next_state <= two;
WHEN two => temp<='0'; next_state <= three;
WHEN three => temp<='1'; next_state <= four;
WHEN four => temp<='1'; next_state <= five;
WHEN five => temp<='1'; next_state <= six;
WHEN six => temp<='0'; next_state <= seven;
WHEN seven => temp<='0'; next_state <= zero;
END CASE;
END PROCESS;
END arc;
-----------------------------------------------------
six,
Kt qu m phng:
Hnh 9.2.1. Kt qu m phng to sng

Phng php truyn thng:
Chng ta thit k b pht tn hiu theo phng php truyn thng vi
cu lnh IF nh sau:
--------------------------------------LIBRARY ieee;
--------------------------------------ENTITY Bo_phat_tin_hieu2 IS
PORT (clk: IN BIT;
wave: OUT BIT);
END Bo_phat_tin_hieu2;
--------------------------------------ARCHITECTURE arc OF Bo_phat_tin_hieu2 IS
BEGIN
PROCESS
134

Nhm 4
BEGIN
CASE count IS
WHEN 0 => wave <= '0';
WHEN 1 => wave <= '1';
WHEN 2 => wave <= '0';
WHEN 3 => wave <= '1';
WHEN 4 => wave <= '1';
WHEN 5 => wave <= '1';
WHEN 6 => wave <= '0';
WHEN 7 => wave <= '0';
END CASE;
if count = 7 then
count := 0;
else
count := count + 1;
end if
;
END PROCESS;
END arc;
---------------------------------------
Kt qu m phng:
Hnh 9.22. Kt qu m phng to sng theo phng php truyn thng

9.10. Thit k b nh.
Trong on ny, chng ta s thit k cc mch b nh sau:
+
ROM
+
RAM vi bus d liu vo ra tch ri.
+
ROM vi bus d liu vo ra hai chiu
ROM (Read Only Memory): B nh ch c v ghi: S ca ROM
c ch ra trong hnh 9.23. V ROM l b nh ch c, khng c tn hiu
clock, chn cho php ghi, n ch c tn hiu vo bus a ch v tn hiu ra l bus
d liu.
Hnh 9.23.S ca ROM
135

Nhm 4
M thit k ROM nh sau:
--------------------------------------------------LIBRARY ieee;
--------------------------------------------------ENTITY rom IS
GENERIC ( bits: INTEGER := 8; -- # of bits per word
words: INTEGER := 8); -- # of words in the memory
PORT ( addr: IN INTEGER RANGE 0 TO words-1;
data: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END rom;
--------------------------------------------------ARCHITECTURE rom OF rom IS
CONSTANT memory: vector_array := ( "00000000",
"00000010",
"00000100",
"00001000",
"00010000",
"00100000",
"01000000",
"10000000");
BEGIN
data <= memory(addr);
END rom;
---------------------------------------------------
Kt qu m phng:
Hnh 9.24. Kt qu m phng thit k ROM

RAM vi ng bus vo ra ring bit: S ca RAM vi ng bus
vo ra ring bit c th hin trong hnh 9.25
Hnh 9.25. RAM vi ng d liu tch ri
136

Nhm 4
Nh chng ta thy trn hnh, RAM c cc bus d liu vo data_in, bus
d liu ra data_out, bus a ch, tn hiu clk v tn hiu cho php c/ghi. Khi
tn hiu cho php ghi/c c xc nhn l ghi th ti mi xung ln tip theo
ca clk th d liu u vo (data_in) phi c lu tr ti v tr addr, v d liu
ra phi c c t a ch addr.
M thit k RAM s nh sau:
----------------------------------------------------------------------------------------library IEEE;
--------------------------------------------------ENTITY ram IS
words: INTEGER := 16); -- # of words in the
-------- memory---------PORT ( wr_ena, clk: IN STD_LOGIC;
data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
--------------------------------------------------ARCHITECTURE ram OF ram IS
BEGIN
BEGIN
memory(addr) <= data_in;
END IF;
END IF;
END PROCESS;
data_out <= memory(addr);
END ram;
---------------------------------------------------
Kt qu m phng:
Hnh 9.26. Kt qu m phng RAM c ng d liu vo ra khc nhau.

RAM vi ng bus song song:
137

Nhm 4
S ca RAM vi ng bus song song c th hin trong hnh 9.27.
D liu c ghi vo RAM hay c c t RAM thc hin trn cng 1 ng
bus.
Hnh 9.27. RAM vi ng d liu chung

M thit k s nh sau:
------------------------------------------------LIBRARY ieee;
------------------------------------------------ENTITY ramc IS
words: INTEGER := 16); -- # of words in the
-- memory
PORT ( clk, wr_ena: IN STD_LOGIC;
bidir: INOUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ramc;
------------------------------------------------ARCHITECTURE arc OF ramc IS
BEGIN
BEGIN
bidir <= memory(addr);
ELSE
bidir <= (OTHERS => 'Z');
memory(addr) <= bidir;
END IF;
END IF;
END PROCESS;
END arc;
-------------------------------------------------
138

Nhm 4
Kt lun
Ngy ny vic ng dng VHDL trong vic thit k mch v chp ngy
cang nhiu. Cng ngh ny ang l xu hng ca thi i, n gin v n
khng ch tiu tn t v tin bc m n cn gip cho chng ta n gin trong
vic thit k phn cng.
Trn y, chng ta trnh by mt cch khi qut v phng php thit
k cc mch. Nhng mch c bn nht c chng ta thit k mt cch chi
tit, hon thin. y l c s cho nhng thit k ln hn v phn cng, thit
k cc ng dng cho cc FPGA, ASIC.
139

Nhm 4
Ti liu tham kho:

- Circuit design with VHDL , Voilnei A.Pedroni
- VHDL language.
- The vhdl cookbook , Peter J.Ashedo
- Thit k mch bng my tnh, Nguyn Linh Giang
..
Phn cng cng vic:
Nguyn Ngc Linh: Chng 2,3
Nguyn Quc Vit: Chng 4,5
140

Nhm 4
Nghim Kim Phng: Chng 6,7
L Tun Anh: Chng 8, 9, gii thiu, tng kt
141

VHDL Tieng Viet

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VHDL Tieng Viet

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Trng i hc bch khoa H Ni

Khoa cng ngh thng tin

Thit k mch bng VHDL

th.s. nguyn ph bnh

Nhm sinh vin thc hin: L tun anh

Ti 4: Thit k vi mch bng VHDL

Chng 1: Gii thiu

Gii thiu v VHDL

Ti 4: Thit k vi mch bng VHDL

Th nht l tnh cng cng:

VHDL c pht trin di s bo tr ca chnh ph M v hin nay l

Th hai l kh nng c h tr bi nhiu cng ngh v nhiu phng

Th ba l tnh c lp vi cng ngh:

VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t

VHDL cho php m t hot ng ca phn cng t mc h thng s cho

Ti 4: Thit k vi mch bng VHDL

Th nm l kh nng trao i kt qu:

V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL

Th su l kh nng h tr thit k mc ln v kh nng s dng li

VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c

Gii thiu cng ngh (v ng dng) thit k mch bng VHDL.

1.2.1 ng dng ca cng ngh thit k mch bng VHDL

Ti 4: Thit k vi mch bng VHDL

Hnh 1.1. Tm tt quy trnh thit k VHDL

Giai on 2: Giai on ch to:

Bc u tin trong qu trnh ch to l bin dich. Qu trnh bin dch s

L giai on ghp ni ng gi phn mm. giai on ny s to ra s

Cc cng c phc v cho qu trnh thit k vi mch s l:

Ti 4: Thit k vi mch bng VHDL

Hinh 1.2.a. S tng qut v b cng y

Hnh 1.2.b. Bng chn l ca b cng y

Ti 4: Thit k vi mch bng VHDL

Hnh 1.3. M thit k b cng

Hnh 1.4.a. Cc v d v s mch c th c ng vi m nh hnh 1.3

Ti 4: Thit k vi mch bng VHDL

Hnh 1.4.b: Kt qu m phng b cng c thit k theo hnh 1.3

Ti 4: Thit k vi mch bng VHDL

Mt an Code chun ca VHDL gm ti thiu 3 mc sau:

- khai bo Library, chng ta cn hai dng m sau, dng th nht cha

Ti 4: Thit k vi mch bng VHDL

Hnh 2.1: Cc thnh phn c bn ca mt on m VHDL

Hnh 2.2: Cc phn c bn ca mt Library

Cc th vin std v work thng l mc nh, v th khng cn khai bo

Ti 4: Thit k vi mch bng VHDL

Entity ( thc th).

Mt ENTITY l mt danh sch m t cc chn vo/ra ( cc PORT) ca

Ch ca tn hiu ( mode of the signal) c th l IN, OUT, INOUT

Hnh 2.3. Cc ch tn hiu

Hnh 2.4. Cng NAND

Ti 4: Thit k vi mch bng VHDL

ARCHITECTURE l mt m t mch dng quyt mch s lm vic

Nh thy trn, mt cu trc c 2 phn: phn khai bo ( chc nng),

ngha ca ARCHITECTURE trn l nh sau: mch phi thc hin

M t kin trc theo m hnh hot ng:

M hnh hot ng m t cc hot ng ca h thng (h thng p ng

Ti 4: Thit k vi mch bng VHDL

M t kin trc theo m hnh cu trc:

M hnh cu trc ca mt phn t (hoc h thng) c th bao gm nhiu

Khai bo cc thnh phn:

Nh vi v d m t m hnh cu trc mt flip-flop RS gm hai cng

Hnh 2.5.a. S ca trigo RS

Ti 4: Thit k vi mch bng VHDL

M t kin trc theo m hnh tng hp

Ti 4: Thit k vi mch bng VHDL