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bo co n mn hc
Thit k mch nh my tnh
ti:
Lp:
ktmt - K46
H Ni, 10/2005
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VHDL cho php thit k bng nhiu phng php v d phng php
thit k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng
h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh ng b
hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu
nhin.
-
Th t l kh nng m t m rng:
Giai on 1:
Giai on 3:
Chng 2. Cu trc m
Trong chng ny, chng ta m t cc phn c bn c cha c cc on
Code nh ca VHDL: cc khai bo LIBRARY, ENTITY v ARCHITECTURE.
2.1.
Cc n v VHDL c bn.
2.2.
Khai bo Library.
10
2.3.
ARCHITECTURE ( cu trc).
V d2:
ARCHITECTURE behavioral of decode2x4 is
BEGIN
12
Component
Tn_componemt port [ danh sch ];
End component;
13
V d2:
Architecture arc_mach_cong of mach_cong is
Component Xor
Port( X,Y : in bit ; Z, T : out bit);
End component;
Component And
Port(L,M :input ;N,P : out bit );
End component;
Begin
G1 : Xor port map (A,B,Sum);
G2 : And port map (A, B, C);
End arc_mach_cong;
14
2.5.
Cc v d m u.
--------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
--------------------------------------ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END behavior;
15
---------------------------------------
16
STD_LOGIC ( v STD_LOGIC_VECTOR):
H logic 8 gi tr sau y c gii tiu trong chun IEEE 1164:
X khng xc nh ( bt buc)
0
mc thp ( bt buc)
1
mc cao ( bt buc)
Z tr khng cao
W khng xc nh (yu)
L
mc thp ( yu)
H mc cao ( yu)
-
khng quan tm
V d:
SIGNAL x: STD_LOGIC;
-- x c khai bo nh mt k t s ( v hng), tn hiu thuc
kiu STD_LOGIC
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";
-- y c khai bo nh mt vector 4-bit, vi bit bn tri cng l
-- MSB. Gi tr khi u ca y l "0001". Lu
-- rng ton t ":=" c s dng thit lp gi tr khi u.
18
19
3.2.
VHDL cng cho php ngi dng t nh ngha cc kiu d liu. Hai
loi kiu d liu ngi dng nh ngha c ch ra di y bao gm integer
v enumerated.
Kiu integer ngi dng nh ngha:
TYPE integer IS RANGE -2147483647 TO +2147483647;
-- Thc ra kiu ny c nh ngha trc bi kiu INTEGER.
TYPE natural IS RANGE 0 TO +2147483647;
-- Thc ra kiu ny c nh ngha trc bi kiu
NATURAL.
TYPE my_integer IS RANGE -32 TO 32;
-- Mt tp con cc s integer m ngi dng nh ngha.
TYPE student_grade IS RANGE 0 TO 100;
-- Mt tp con cc s nguyn hoc s t nhin ngi dng nh
ngha.
_ Cc kiu m ngi dng inh ngha:
TYPE bit IS ('0', '1');
-- c nh ngha trc bi kiu BIT
TYPE my_logic IS ('0', '1', 'Z');
20
21
Mng (Arrays).
22
23
24
3.6.
3.7.
25
26
3.8.
Chuyn i d liu.
VHDL khng cho php cc php ton trc tip ( s hc, logic, ) tc
ng ln cc d liu khc kiu nhau. Do , thng l rt cn thit i vi vic
chuyn i d liu t mt kiu ny sang mt kiu khc. iu ny c th c
thc hin trong hai cch c bn: hoc chng ta vit mt t code cho iu ,
hoc chng ta gi mt FUNCTION t mt gi c nh ngha trc m n
cho php thc hin cc php bin i cho ta.
Nu d liu c quan h ng ( ngha l 2 ton hng c cng kiu c
s, bt chp ang c khai bo thuc v hai kiu lp khc nhau), th
std_logic_1164 ca th vin ieee cung cp cc hm chuyn i d thc hin.
* V d: cc php ton hp l v khng hp l i vi cc tp con
TYPE long IS INTEGER RANGE -100 TO 100;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;
...
y <= 2*x + 5;
-- li, khng ph hp kiu
y <= long(2*x + 5);
-- OK, kt qu c chuyn i
thnh kiu long
27
3.9. Tm tt.
Cc kiu d liu VHDL tng hp c bn c tm tt trong bng 3.2
28
29
30
31
32
33
Ton t.
VHDL cung cp mt s ton t sau:
Ton t gn.
Ton t logic.
Ton t ton hc.
Ton t so snh.
Ton t dch.
Sau y chng ta s xem xt c th tng ton t mt.
4.1.1Ton t gn.
VHDL nh ngha ba loi ton t gn sau:
<=: Dng gn gi tr cho SIGNAL.
:= : Dng gn gi tr cho VARIABLE, CONSTANT,GENERIC.
=>: Dng gn gi tr cho thnh phn cc vector v cc loi gi tr
khc.
V d:
SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
x <= '1';
y := "0000
w <= "10000000";
w <= (0 =>'1', OTHERS =>'0');
4.1.2Ton t Logic.
VHDL nh ngha cc ton t logic sau:
NOT, AND, OR, NAND, NOR, XOR, XNOR
D liu cho cc ton t ny phi l kiu: BIT, STD_LOGIC,
STD_ULIGIC, BIT_VECTOR, STD_LOGIC_VECTOR,
STD_ULOGIC_VECTOR.
V d:
y <= NOT a AND b;
y <= NOT (a AND b);
y <= a NAND b;
34
4.1.4Ton t so snh.
C cc ton t so snh sau:
=
So snh bng
/=
So snh khng bng.
<
So snh nh hn.
>
So snh ln hn.
<=
So snh nh hn hoc bng.
>=
So snh ln hn hoc bng.
4.1.5Ton t dch.
C php s dng ton t dch l:
<left operand> <shift operation> <right operand>
Trong <left operand> c kiu l BIT_VECTOR, cn <right operand>
c kiu l INTEGER. C hai ton t dch:
Sll
Ton t dch tri. in 0 vo pha phi.
Rll
Ton t dch phi. in 0 vo pha tri.
4.2.
Thuc tnh.
Ta s c:
d'LOW = 0, d'HIGH = 7, d'LEFT = 7, d'RIGHT = 0, d'LENGTH = 8,
d'RANGE = (7 downto 0), d'REVERSE_RANGE = (0 to 7).
35
4.3.
Trong
+
attribute_type l kiu d liu.
+
Class : SIGNAL, TYPE, FUNCTION.
V d :
36
Chng ton t.
4.5.
GENERIC.
4.6. V d.
lm r hn cc vn ni trn chng ta s xem xt mt vi v
d sau:
V d 1: Generic Decoder.
37
38
39
40
Kt qu:
50
100
150
200
250
300
350
400
450
500
input
00
01
02
03
04
05
output
00
81
82
03
84
05
ns
41
42
S dng cc ton t.
43
Kt qa m phng.
50
100
150
200
250
300
350
400
450
500
ns
a
b
c
d
s0
s1
y
Mnh WHEN.
V d:
44
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END mux;
------------------------------------------ARCHITECTURE mux1 OF mux IS
BEGIN
y <= a WHEN sel="00" ELSE
b WHEN sel="01" ELSE
c WHEN sel="10" ELSE
d;
END mux1;
-------------------------------------------
45
V d 2: B m 3 trng thi.
Kt qu m phng
46
100
150
200
250
300
350
400
450
500
ns
ena
input
01
00
output
01
00
ZZ
01
00
01
ZZ
V d 3: Encoder.
47
Kt qu m phng:
100
200
300
400
500
00
01
02
03
04
05
600
06
700
07
800
900
08
09
1000
0A
ns
0B
48
---------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
---------------------------------------------ENTITY ALU IS
PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
cin: IN STD_LOGIC;
y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END ALU;
---------------------------------------------ARCHITECTURE dataflow OF ALU IS
SIGNAL arith, logic: STD_LOGIC_VECTOR (7
DOWNTO 0);
BEGIN
----- Arithmetic unit: -----WITH sel(2 DOWNTO 0) SELECT
arith <= a WHEN "000",
a+1 WHEN "001",
a-1 WHEN "010",
b WHEN "011",
b+1 WHEN "100",
b-1 WHEN "101",
a+b WHEN "110",
a+b+cin WHEN OTHERS;
----- Logic unit: ----------WITH sel(2 DOWNTO 0) SELECT
logic <= NOT a WHEN "000",
NOT b WHEN "001",
a AND b WHEN "010",
a OR b WHEN "011",
a NAND b WHEN "100",
a NOR b WHEN "101",
49
Kt qu m phng.
50
100
150
200
250
300
350
400
450
500
00
01
02
03
04
05
arith
00
02
02
04
03
05
00
01
02
03
04
05
logic
FF
FE
FD
FC
04
05
sel
00
02
02
04
03
05
ns
cin
5.4.
V d:
SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
...
G1: FOR i IN x'RANGE GENERATE
z(i) <= x(i) AND y(i+8);
END GENERATE;
50
Kt qu m phng:
50
100
150
200
250
300
350
400
inp
outp
00
01
02
03
04
sel
450
500
ns
BLOCK.
51
V d:
b1: BLOCK
SIGNAL a: STD_
BEGIN
a <= input_sig
END BLOCK b1;
5.5.2.Guarded BLOCK
52
unguarded
Kt qu m phng
100
200
300
400
500
600
700
800
900
1000
ns
clk
d
q
53
END dff;
------------------------------
Kt qu m phng:
100
200
300
400
500
600
700
800
900
1000
ns
clk
d
q
rst
Chng 6: M tun t
6.1.
PROCESS
54
20
30
40
50
60
70
80
90
ns
rst
d
clk
q
6.2.
Signals v Variables.
55
IF.
END IF;
V d:
IF (x<y) THEN temp:="11111111";
ELSIF (x=y AND w='0') THEN temp:="11110000";
ELSE temp:=(OTHERS =>'0');
V d 6.3a:
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
ns
clk
digit
V d 6.3b:
100
150
200
250
300
350
400
450
clk
rst
d
internal
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftreg IS
57
500
550
600
650 ns
6.4.
WAIT.
58
V d 6.4a:
DFF vi tn hiu reset khng ng b
5
10
15
20
25
30
35
40
45
50
55
rst
d
clk
q
59
60
65
70
75
80
ns
V d 6.4b:
B m mt ch s thp phn 0 9 0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
ns
clk
0
digit
6.5.
CASE.
CASE l lnh duy nht cho m tun t (i km vi IF, LOOP, v WAIT).
C php:
CASE identifier IS
WHEN value => assignments;
WHEN value => assignments;
...
END CASE;
60
Vi CASE:
CASE sel IS
61
V d:
B dn knh MUX 4-1
Vi IF:
IF (sel="00") THEN x<=a;
ELSIF (sel="01") THEN x<=b;
ELSIF (sel="10") THEN x<=c;
ELSE x<=d;
Vi CASE:
CASE sel IS
WHEN "00" => x<=a;
WHEN "01" => x<=b;
WHEN "10" => x<=c;
WHEN OTHERS => x<=d;
END CASE;
V d 6.5a:
DFF vi tn hiu reset khng ng b
5
10
15
20
25
30
35
40
45
50
55
60
65
70
rst
d
clk
q
62
75
80
ns
V d 6.5b:
B m hai ch s thp phn 0 99 0, u ra l 2 LED 7 thanh
40
60
80
100
120
140
160
180
200
220
240
260
280
ns
300
reset
clk
temp1
temp2
digit1
7E
digit2
7E
30
7E
30
7E
30
6D
79
33
7E
30
63
6.6.
LOOP.
64
V d:
Vi FOR/LOOP:
FOR i IN 0 TO 5 LOOP
x(i) <= enable AND w(i+2);
y(0, i) <= w(i);
END LOOP;
V d:
Vi EXIT
FOR i IN data'RANGE LOOP
CASE data(i) IS
WHEN '0' => count:=count+1;
65
V d:
Vi NEXT
FOR i IN 0 TO 15 LOOP
NEXT WHEN i=skip; -- jumps to next iteration
(...)
END LOOP;
V d 6.6a:
B cng c nh 8 bit khng du.
40
60
80
100
120
140
160
180
200
220
240
260
280
300
cin
a
92
40
04
31
86
C6
32
24
81
09
63
0D
8D
65
B7
C2
0D
94
93
53
97
cout
Cch 1:
Dng Generic vi cc VECTOR
----- Solution 1: Generic, with VECTORS -------LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY adder IS
GENERIC (length : INTEGER := 8);
PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cout: OUT STD_LOGIC);
66
ns
Cch 2:
Dng non-generic vi cc INTEGER
---- Solution 2: non-generic, with INTEGERS ---LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY adder IS
PORT ( a, b: IN INTEGER RANGE 0 TO 255;
c0: IN STD_LOGIC;
s: OUT INTEGER RANGE 0 TO 255;
c8: OUT STD_LOGIC);
END adder;
ARCHITECTURE adder OF adder IS
BEGIN
PROCESS (a, b, c0)
VARIABLE temp : INTEGER RANGE 0 TO 511;
BEGIN
IF (c0='1') THEN temp:=1;
ELSE temp:=0;
END IF;
temp := a + b + temp;
IF (temp > 255) THEN
c8 <= '1';
temp := temp; ---256
ELSE c8 <= '0';
END IF;
s <= temp;
END PROCESS;
END adder;
V d 6.6b:
67
inp
00
shift
outp
00
40
60
14
80
100
120
140
28
160
3C
180
200
220
50
240
260
280
300
64
78
C8
F0
1
14
28
3C
A0
68
ns
V d 6.6c:
B m s s 0 ca mt vector nh phn, bt u t bn tri
50
100
data
00
01
02
zeros
150
03
200
250
04
05
300
06
350
07
400
450
08
09
500
550
0A
0B
600
0C
ns
0D
6.7.
Bad Clocking.
69
70
V d 6.7a:
RAM (Random Acess Memory), dung lng 16 t nh x 8 bit
100
150
200
250
300
350
400
450
500
550
600
ns
wr_ena
clk
addr
data_in
32
33
34
35
36
37
38
data_out
UU
UU
32
33
34
32
UU
33
UU
34
71
6.8.
72
100
150
200
250
300
350
400
450
500
550
600
ns
a
b
c
d
sel
x
y
73
CONSTANT.
CONSTANT phc v cho vic thit lp cc gi tr mc nh.
C php:
CONSTANT name : type := value;
V d:
CONSTANT set_bit : BIT := '1';
CONSTANT datamemory : memory := (('0','0','0','0'),
('0','0','0','1'),
('0','0','1','1'));
SIGNAL.
V d:
SIGNAL control: BIT := '0';
SIGNAL count: INTEGER RANGE 0 TO 100;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);
75
40
60
80
100
120
140
160
180
200
220
240
260
280
300
din
00
01
02
03
04
05
06
temp
ones
76
ns
VARIABLE
V d:
VARIABLE control: BIT := '0';
VARIABLE count: INTEGER RANGE 0 TO 100;
VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
din
00
01
ones
100
02
150
200
250
03
04
05
300
06
350
400
450
07
08
09
500
0A
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY count_ones IS
PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
ones: OUT INTEGER RANGE 0 TO 8);
END count_ones;
ARCHITECTURE ok OF count_ones IS
BEGIN
PROCESS (din)
VARIABLE temp: INTEGER RANGE 0 TO 8;
77
550
600
ns
0B
0C
0D
SIGNAL
<=
Biu din s kt ni cc
mch (cc dy)
C th l ton cc (trn
ton b m)
Php gn
Tnh nng
Phm vi
Hot ng
Cp nht khng tc th
trong m tun t (gi tr
mi ch c th dng lc
kt thc PROCESS,
FUNCTION,
hay
PROCEDURE)
Trong
PACKAGE,
ENTITY,
hay
ARCHITECTURE.
Trong ENTITY, tt c
cc PORT l cc
SIGNAL mc nh
S dng
VARIABLE
:=
Biu din thng tin cc
b
Cc b (ch trong
PROCESS,
FUNCTION,
hay
PROCEDURE tng
ng)
Cp nht tc th (gi tr
mi c th c s
dng trong dng lnh
tip theo ca m)
Ch trong m tun t,
trong
PROCESS,
FUNCTION,
hay
PROCEDURE
78
Cch 1:
S dng SIGNAL (khng ng)
-- Solution 1: using a SIGNAL (not ok) -LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE not_ok OF mux IS
SIGNAL sel : INTEGER RANGE 0 TO 3;
BEGIN
PROCESS (a, b, c, d, s0, s1)
BEGIN
sel <= 0;
IF (s0='1') THEN sel <= sel + 1;
END IF;
IF (s1='1') THEN sel <= sel + 2;
END IF;
CASE sel IS
WHEN 0 => y<=a;
WHEN 1 => y<=b;
WHEN 2 => y<=c;
WHEN 3 => y<=d;
END CASE;
END PROCESS;
END not_ok;
Cch 2:
S dng VARIABLE (ng)
-- Solution 2: using a VARIABLE (ok) ---LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE ok OF mux IS
BEGIN
PROCESS (a, b, c, d, s0, s1)
VARIABLE sel : INTEGER RANGE 0 TO 3;
BEGIN
sel := 0;
IF (s0='1') THEN sel := sel + 1;
79
y<=a;
y<=b;
y<=c;
y<=d;
40
60
80
100
120
140
160
180
200
220
240
260
280
300
ns
600
ns
s0
s1
a
b
c
d
y
50
100
150
200
250
300
350
400
450
500
s0
s1
a
b
c
d
y
80
550
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
ARCHITECTURE not_ok OF dff IS
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
q <= d;
qbar <= NOT q;
END IF;
END PROCESS;
END not_ok;
Cch 2:
ng
---- Solution 2: OK ------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
ARCHITECTURE ok OF dff IS
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
81
100
150
200
250
300
350
400
450
500
550
600
ns
50
100
150
200
250
300
350
400
450
500
550
600
ns
d
clk
q
qbar
d
clk
q
qbar
40
60
80
100
120
140
160
180
200
220
clk
count1
count2
out1
out2
82
240
260
280
300
ns
7.4.
S thanh ghi.
83
V d 7.4a:
DFF vi q v qbar
Cch 1 c 2 php gn SIGNAL ng b (dng 16-17), v vy 2 flip-flop
s c sinh. Cch 2 c mt trong cc php gn l ng b, vic tng hp s
lun suy ra ch mt flip-flop
84
100
150
200
250
300
350
400
450
500
550
600
ns
50
100
150
200
250
300
350
400
450
500
550
600
ns
d
clk
q
qbar
d
clk
q
qbar
Cch 2:
Sinh mt DFF
---- Solution 2: One DFF ---------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
qbar: OUT STD_LOGIC);
END dff;
ARCHITECTURE one_dff OF dff IS
BEGIN
85
V d 7.4b:
B m 0 - 7
Hnh 7.4b.1. B m 0 7
Cch 1:
Mt php gn VARIABLE ng b c tao ra (dng 14-15). Mt
VARIABLE c th sinh cc thanh ghi bi v php gn ca n (dng 15) ti s
chuyn tip ca tn hiu khc (clk, dng 14) v gi tr ca n khng ri
PROCESS (dng 17).
------ Solution 1: With a VARIABLE -------ENTITY counter IS
PORT ( clk, rst: IN BIT;
count: OUT INTEGER RANGE 0 TO 7);
END counter;
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Cch 2:
Mt php gn SIGNAL ng b xy ra (dng 13-14). Ch s dng cc
SIGNAL. Ch , khi khng c tn hiu ph c s dng, count cn c khai
bo nh kiu BUFFER (dng 14), bi v n c gn mt gi tr v cng c
c (s dng) ni ti (dng 14). Mt SIGNAL, ging nh mt VARIABLE, c
th cng c tng khi s dng trong m tun t.
------ Solution 2: With SIGNALS only ------ENTITY counter IS
PORT ( clk, rst: IN BIT;
count: BUFFER INTEGER RANGE 0 TO 7);
END counter;
ARCHITECTURE counter OF counter IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
count <= 0;
ELSIF (clk'EVENT AND clk='1') THEN
count <= count + 1;
END IF;
END PROCESS;
END counter;
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ns
rst
clk
count
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ns
rst
clk
count
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Cch 2:
Cc bin c thay th bi cc SIGNAL (dng 8), v cc php gn c
to ra trong th t trc tip (t din-dout, dng 13-16). Khi cc php gn tn
hiu ti s chuyn tip tn hiu khc sinh cc thanh ghi, mch ng s c suy
ra.
-------- Solution 2: -----------------
ENTITY shift IS
PORT ( din, clk: IN BIT;
dout: OUT BIT);
END shift;
ARCHITECTURE shift OF shift IS
SIGNAL a, b, c: BIT;
BEGIN
PROCESS (clk)
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Cch 3:
Cc bin ging nhau ca cch 1 b chim, nhng trong th t trc
tip (t din-dout, dng 13-16). Tuy nhin, mt php gn cho mt bin l tc th,
v khi cc bin ang c s dng trong th t trc tip (sau khi cc gi tr va
c gn cho chng), dng 13-15 thnh 1 dng, tng ng vi c:=din. Gi
tr ca c ri PROCESS trong dng tip theo (dng 16), khi mt php gn tn
hiu (dout <= c) xy ra ti s chuyn tip ca clk. Do , mt thanh ghi s
c suy ra t cch 3, nn khng to kt qu mch chnh xc.
-------- Solution 3: -----------------
ENTITY shift IS
PORT ( din, clk: IN BIT;
dout: OUT BIT);
END shift;
ARCHITECTURE shift OF shift IS
BEGIN
PROCESS (clk)
VARIABLE a, b, c: BIT;
BEGIN
IF (clk'EVENT AND clk='1') THEN
a := din;
b := a;
c := b;
dout <= c;
END IF;
END PROCESS;
END shift;
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ns
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ns
din
clk
dout
din
clk
dout
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ns
din
clk
dout
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Cch 2:
S dng mt VARIABLE. Php gn ti s chuyn tip ca tn hiu khc
c to ra cho mt bin (dng 17-18), nhng khi gi tr ca n ri PROCESS
(n c chuyn n mt port trong dng 20), n cng suy ra cc thanh ghi.
-- Solution 2: With an internal VARIABLE --LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftreg IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
ARCHITECTURE behavior OF shiftreg IS
BEGIN
PROCESS (clk, rst)
VARIABLE internal: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
IF (rst='1') THEN
internal := (OTHERS => '0');
ELSIF (clk'EVENT AND clk='1') THEN
internal := d & internal(3 DOWNTO 1);
END IF;
q <= internal(0);
END PROCESS;
END behavior;
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clk
rst
d
internal
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ns
Gii thiu.
92
X - Tp hp cc tn hiu vo ca tmat:
X = { x1(t),,xn(t)}
Tp cc tn hiu ra ca tmat:
Y = {y1(t),,ym(t)}
Tp hp cc trng thi ca tmat:
S = {s1(t),,ss(t)}
Hm (s, x) hm chuyn trng thi ca tmat
Hm (s,x) hm u ra ca tmat.
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<=
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V d 8.1: B m BCD
Mt b m l mt v d ca my Moore, u ra ch ph thuc vo kt
qu ca trng thi hin ti. Ging nh mt mch thanh ghi v mt mch dy
n gin. thit k mch ny, chng ta c th dng phng php thng
thng nh nhng phn mch mch t hp, nhng y ta s dng phng
php FSM.
Gi s ta cn thit k b m modul 10. Nh vy chng ta s cn c mt
may c 10 trang thi. Cc trng thi y c gi l zero, one,,nine.
hnh trng thi ca my c cho nh sau:
97
M phng kt qu:
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99
Kt qu m phng:
Thit k kiu 2.
100
END <arch_name>;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
---------------------------------------------ENTITY VD_FSM2 IS
PORT ( a, b, d, clk, rst: IN BIT;
x: OUT BIT);
END VD_FSM2;
---------------------------------------------ARCHITECTURE VD_FSM2 OF VD_FSM2 IS
TYPE state IS (stateA, stateB);
SIGNAL pr_state, nx_state: state;
SIGNAL temp: BIT;
BEGIN
----- Phan mach day: ---------------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= stateA;
ELSIF (clk'EVENT AND clk='1') THEN
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Kt qu m phng s nh sau:
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END CASE;
END PROCESS;
outp <= out1 AND out2;
END state_machine;
------------------------------------------
Kt qu m phng:
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111
Barrel Shifter.
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Kt qu m phng:
114
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; -- can thiet!
---------------------------------------ENTITY Bo_so_sanh_co_dau IS
GENERIC (n: INTEGER := 7);
PORT (a, b: IN SIGNED (n DOWNTO 0);
x1, x2, x3: OUT STD_LOGIC);
END Bo_so_sanh_co_dau;
---------------------------------------ARCHITECTURE arc OF Bo_so_sanh_co_dau IS
BEGIN
x1 <= '1' WHEN a > b ELSE '0';
x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0';
END arc;
----------------------------------------
Kt qu m phng:
115
Kt qu:
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117
Kt qu m phng:
119
OF
Kt qu m phng:
9.4.
u vo a
1011
1011
1011
0101
0010
So snh
<
<
>
>
u vo b
0011000
0001100
0000110
0000011
120
y
0
0
1
1
Thao tc cho ct a
Khng lm g
Khng lm g
Tr ct a cho ct b
Tr ct a cho ct b
121
Kt qu m phng:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------ENTITY Bo_chia2 IS
GENERIC(n: INTEGER := 3);
PORT ( a, b: IN INTEGER RANGE 0 TO 15;
y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rest: OUT INTEGER RANGE 0 TO 15;
err : OUT STD_LOGIC);
END Bo_chia2;
-------------------------------------------------ARCHITECTURE arc OF Bo_chia2 IS
BEGIN
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Kt qu m phng:
9.5.
B iu khin my bn hng.
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WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
END CASE;
END PROCESS;
END state_machine;
------------------------------------------------------
Kt qu m phng:
126
--------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------ENTITY Bo_nhan_du_lieu_nt IS
PORT ( din, clk, rst: IN BIT;
data: OUT BIT_VECTOR (6 DOWNTO 0);
err, data_valid: OUT BIT);
END Bo_nhan_du_lieu_nt;
--------------------------------------------ARCHITECTURE arc OF Bo_nhan_du_lieu_nt IS
BEGIN
PROCESS (rst, clk)
VARIABLE count: INTEGER RANGE 0 TO 10;
VARIABLE reg: BIT_VECTOR (10 DOWNTO 0);
VARIABLE temp : BIT;
BEGIN
IF (rst='1') THEN
count:=0;
reg := (reg'RANGE => '0');
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Kt qu m phng:
128
M thit k nh sau:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------ENTITY Bo_chuyen_dl_ss_nt IS
PORT ( d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clk, load: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END Bo_chuyen_dl_ss_nt;
------------------------------------------------ARCHITECTURE Bo_chuyen_dl_ss_nt OF Bo_chuyen_dl_ss_nt IS
SIGNAL reg: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load='1') THEN reg <= d;
ELSE reg <= reg(6 DOWNTO 0) & '0';
END IF;
END IF;
END PROCESS;
dout <= reg(7);
END Bo_chuyen_dl_ss_nt;
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Kt qu m phng:
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96
32
48
16
24
12
66
Kt qu m phng:
B pht tn hiu.
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six,
Kt qu m phng:
134
Kt qu m phng:
135
Kt qu m phng:
136
Kt qu m phng:
138
Kt lun
Ngy ny vic ng dng VHDL trong vic thit k mch v chp ngy
cang nhiu. Cng ngh ny ang l xu hng ca thi i, n gin v n
khng ch tiu tn t v tin bc m n cn gip cho chng ta n gin trong
vic thit k phn cng.
Trn y, chng ta trnh by mt cch khi qut v phng php thit
k cc mch. Nhng mch c bn nht c chng ta thit k mt cch chi
tit, hon thin. y l c s cho nhng thit k ln hn v phn cng, thit
k cc ng dng cho cc FPGA, ASIC.
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