Bai Giang Orcad

Bi ging Orcad Nguyn Thy Bnh- KTT
1
1. Khi ng Orcad Capture

Start Programs Orcad Family Release 9.2 Capture

2
Khi bt u v mt s mch (schematic), chn menu Options/Preferences t cc thuc tnh
ty chn ring cho tng ngi thit k
1.1. Tab Color/Print: Chn gam mu cho tng i tng trong trang s mch nguyn l

Tab Grid Display

3
Chn ch hin th (Visible) hoc khng hin th li trong trang v s mch (Schematic
Page) hoc trong trang chnh sa linh kin (Part and Symbol). Kiu li c th l dng chm (dots)
hoc dng ng thng (lines).
Chn ch Pointer snap to grid neo con tr vo cc im li. Trong qu trnh thit k
c th Bt/Tt ch ny bng cch kch vo biu tng
Chn xong nhp chut vo OK.
Tab Pan and Zoom

Chn t l phng to/ thu nh trang v s mch v trang chnh sa linh lin khi thc hin lnh
Zoom. y chng ta chn t l Zoom l 2.
Chn xong nhp chut vo OK.
4

Tab Select

Tab Miscellaneous

5
Gn cc thuc tnh cho cc i tng khi v cc i tng: ng thng (line), ng a nt
(polyline), hnh ch nht (rectangle), hnh ellipse (ellipse), cung trn (Arc) trong trang s mch
(Schematic Page Editor) hay trong trang chnh sa linh kin, k hiu (Part and Sybol Editor).
Ngoi ra cn c mt s chc nng quan trng:
Auto Recovery: T ng lu li Project trnh hin tng mt d liu khi xy ra s c khng
mong mun
Auto Reference: T ng hin th ch s ca linh kin khi c ly t th vin
Intertool Communication: Chc nng ny ng vai tr nh thng dch vin gia Capture v
Layout khi m ng thi c 2 chng trnh ny nhm sp xp chn ca cc linh kin theo la chn ca
ngi thit k.
Tab Text Editor

To Project mi c th lin thng vi cc phn mm khc: FileNewProject
Nu ch mun v s nguyn l , chn: FileNewDesign
Mun to th vin mi, chn: FileNewLibrary
To file np cho EPROM: FileNewVHDL
To file vn bn: FileNewText File

6

Analog or Mixed A/D: Project lin thng vi trnh Pspice
PC Board Wizard: Project lin thng vi trnh Layout Plus
Programmable Logic Wizard: Project lin thng vi trnh PLD np chng trnh vo cc IC
EPROM
Schematic: Ch v s nguyn l
Tn Project
ng dn ti th mc lu Project
7

Mun m mt Project, mt Design, mt Library, c sn thc hin lnh: FileOpenProject

2. Cc giao din chnh ca Orcad Capture
2.1. Session Log

Session Log cha cc thng tin v nhng s kin xy ra trong qu trnh thit k mch nh thng bo v
cc li, cc cnh bo v nhng d liu v cc linh kin. xa ni dung trong ca s ny ti bt k
thi im no c th thc hin lnh Clear Session Log t menu Edit hoc cng c th s dng phm
nng Ctrl+Del
8

2.2. Project Manager

Project Manager gm 2 Tab: File v Hierarchy.
Tab File lit k tt c cc file c to ra trong qu trnh thit k mch.
Tab Hierarchy: lit k tt c cc linh kin c trong s mch nguyn l (V d i vi s mch
trn gm: Diode D
1
(D1N4447); in tr R
1
(10K)

v ngun V
1
(VDC))
9
2.3. Schematic Page

Schematic Page cho php chng ta v s mch vi s h tr ca cc thanh cng c Toolbar v
Tool Palettes. ngha ca tng tiu hnh trn cc thanh cng c c lit k trn bng 1 v bng 2.
Toolbar

Bng 1
Tool Tn M t

New To trang v mi (ging lnh New trn menu File)

Open
M mt Project hoc mt th vin c sn (ging lnh Open
trn menu File)

Save
Lu li trang v hin ti, s nguyn l ca mch hoc
cc linh kin (tng ng vi lnh Save trn menu File)

Print
In cc trang c chn trong th mc Schematic, hoc
trang v hin ti hoc c th in tng linh kin (tng
ong lnh Print trn menu File)

Cut
Ct i tng c chn v ct vo Clipboard (Tng
ng vi lnh Cut trn menu Edit)

Copy
Sao chp i tng c chn v ct vo Clipboard (tng
ng vi lnh Copy trn menu Edit)
10

Paste
Dn ni dung c trong Clipboard ln trang v ti v tr
ca con tr (tng ng vi lnh Paste trn menu Edit)

Undo
B lnh va thc hin, khi phc li trng thi trc
(tng ng vi lnh Undo trn menu Edit)

Redo
Ly li lnh va thc hin (tng ng vi lnh Redo
trn menu Edit)

MRU
Cc linh kin va c s dng c lu trong vng nh
tm thi (Most Recently Used)

Zoom in
a trang v li gn (phng to), tng ng vi cch
chn Zoom v In trn menu View

Zoom out
a trang v ra xa (thu nh), tng ng vi cch chn
Zoom v Out trn menu View

Zoom Area
Ch phng to phn c chn (tng ng vi cch chn
Zoom v Area trn menu View)

Zoom All Cho php quan st ton b trang s mch.

Annotate
Ghi k hiu cc linh kin trn s mch (tng ng
vi lnh Annotate trn menu Tool)

Back
Annotate
Ghi li k hiu ca cc linh kin trn s mch (tng
ng vi lnh Back Annotate trn menu Tools)

Design Rule
Check
Kim tra li trn trang s mch nguyn l (tng ng
vi lnh Design Rules Check trn menu Tools)

Creat Netlist
To file .mnl khai bo cc c tnh ca mch sau khi
kim tra s nguyn l khng c bt k li no, thc hin
sau lnh DRC (tng ng vi lnh Creat Netlist trn
menu Tools)

Cross
Reference
To nn mt thng bo v s mch, khi to mt file
.xrf c sinh ra trong th mc Output trong ca s Project
Manager (Tng ng vi lnh Cross Reference trn
menu Tools)

Bill of
Materials
To nn mt bng k khai cc linh kin c s dng trong
s mch (to file .bom) (tng ng vi lnh Bill of
Materials)

Snap to Grid Bt hoc tt chc nng dnh trn cc im li

Project
Manager
M ca s qun l cc file lin quan n trang s mch

Help Topic Tr gip

11
Tool Palettes

Bng 2
Tool Tn M t

Select Chn i tng

Place Part
Chn linh kin trong th vin (tng ng vi lnh Part trn menu
Place )

Place Wire
Ni dy dn qua chn cc linh kin (n v gi Shift i dy khng
vung gc), (tng ng vi lnh Wire trn menu Place)

Place Net Alias
t tn cho cc ng dy ni (tng ng vi lnh Net Alias trn
menu Place)

Place Bus To Bus (tng ng vi lnh Bus trn menu Place )

Place Junction To cc giao im ca cc dy dn ct nhau

Place Bus Entry
t cc im vo ca Bus (tng ng vi lnh Bus Entry trn
menu Place)

Place Power
M ca s ly k hiu ngun (tng ng vi lnh Power trn
menu Place)

Place Ground
M ca s ly k hiu ni t (tng ng vi lnh Ground trn
menu Place)

Place Hierarchical
Block
To khi phn cp tng ng vi mt s mch (ging lnh
Hierarchical Block trn menu Place)

Place Hierarchical
Port
To cng trn s khi (tng ng vi lnh Hierarchical Port
trn menu Place)

Place Hierarchical
Pin
To chn trn s khi (tng ng vi lnh Hierarchical Pin
trn menu Place)

Place Off-page
Connector
t cc k hiu kt ni (tng ng vi lnh Off-Page Connector
trn menu Place)

Place No Connect
t k hiu khng kt ni trn cc chn c b trng (tng ng
vi lnh No Connect trn menu Place)

Place Line V ng thng (tng ng vi lnh Line trn menu Place)

Place Polyline
V ng kn c to bi nhiu on thng (tng ng vi lnh
Polyline trn menu Place)

Place Rectangle V hnh ch nht (tng ng vi lnh Rectangle trn menu Place)

Place Ellipse
V hnh trn hoc hnh Ellipse (tng ng vi lnh Ellipse trn
menu Place)

Place Arc V cc cung trn (tng ng vi lnh Arc trn menu Place)

Place Text
Vit ch trn trang s mch, to ch thch (tng ng vi lnh
Text trn menu Place)

12
2.4. Part Editor
m giao din Part Editor (trang chnh sa linh kin): Nhy chut phi vo linh kin cn chnh sa,
chn Edit Part.
13
Trong trang Part Editor cn c thm thanh cng c c dnh ring cho vic chnh sa linh kin: Part
Editor Tool Palettes.

Trong Part Editor ta c th dng con tr di chuyn
chn linh kin ti v tr mong mun. to mt linh
kin mi ta c th phc ha hnh dng ca linh kin
nhng c tnh ca cc chn linh kin cn phi c
khai bo mt cch chnh xc.
Mi chn linh kin c nhng c tnh ring:

Tool Tn M t

Select Chn i tng cn chnh sa

Place IEEE Symbol t cc k hiu ca IEEE

Place Pin V 1 chn linh kin

Place Pin Array V dy chn linh kin

Place Line V ng thng

Place Polyline V ng khp kn gm nhiu on thng

Place Rectangle V khung hnh ch nht

Place Ellipse V hnh elip hoc hnh trn

Place Arc V cung trn

Place Text Vit ch
14

Name: Tn chn
Number: S hiu chn
Shape: Hnh dng chn
Clock: Nhn tn hiu xung nhp
Dot: Chn c tnh o pha
Dot-Clock: Nhn tn hiu xung nhp v c tnh o pha
Line: Chn dng ng thng
Short: Dng chn ngn
Zero Length: Chn c chiu di bng 0(thng dng cho chn ngun V
CC
hoc chn
GND)
Type: Loi chn
3 State: Chn 3 trng thi (c trng thi tr khng cao)
Bidirectional: Chn cho php tn hiu truyn theo c 2 hng
Input: Chn nhn tn hiu vo
Open Collector: Chn ly tn hiu ra trn cc Collector h mch
Open Emitter: Chn ly tn hiu ra trn cc Emitter h mch
Output: Chn a tn hiu ra
Passive: Chn th ng (Chn in tr, t in,)
Power: Chn ngun(chn VCC hoc chn GND)
Sau khi chnh sa, nhy chut vo nt Close ng trang Part Editor, khi mt ca s con Save Part
Instance c m ra

Update Current: Ch cp nht nhng sa i vo ngay chnh linh kin
15
Update All: Cp nht i vi tt c cc linh kin cng loi
Discard: B qua tt c nhng sa i
Cancel: Quay li ca s ca Part Editor
2.5. Status Bar

Status bar c t gc phi pha di ca ca s Capture c nhim v thng bo mi hot ng
ti thi im hin ti: S lng phn t c chn, t l phng to/ thu nh v v tr ca con tr.
Trng bn tri m t cc lnh trn thanh cng c, trn menu hay trng thi hin ti ca ca s
Capture.

Trng gia hin th s lng phn t c chn trn trang v s mch hoc trang chnh sa linh
kin
Trng bn phi hin th t l phng to/ thu nh v v tr hin ti ca con tr.
3. V d v mt s mch
3.1. Ly cc linh kin trong th vin
ly linh kin t trong th vin ra
trang v s mch ta c th thc hin
bng 1 trong cc cch sau:
Thc hin lnh: PlacePart
trn thanh menu
S dng phm nng P hoc
Shift+P
Nhp chut vo tiu hnh
Khi ca s Place Part hin ra

16
Trong Library: Chn th vin cha linh kin ANL_MISC
Trong Part List: Chn tn linh kin555B
Chn xong, nhp chut vo OK.
Ta cng c th thc hin cc thao tc: Add Library (thm th vin)
Remove Library (xa b th vin)
Part Search (Tm linh kin)
C th thm th vin linh kin trong th mc Library hoc trong PSpice. Ch lin thng vi trnh
PSpice cc th vin c chn phi nm trong th mc PSpice. Nu ch thit k cc mch in in
t thng dng ch cn Add cc th vin: Capsym.olb, Connector.olb, Counter.olb, Discrete.olb,
Gate.olb, analog.olb, source.olb,
Nu mun xa mt th vin no trong khung Libraries, chn th vin v nhp chut vo Remove
Library. Nu khng bit linh kin cn tm nm trong th vin no ta c th thc hin lnh: Part
Search
17

Sau khi chn xong linh kin trong th vin, quay tr li trang v s mch, linh kin dnh vo chut,
chn v tr t linh kin, nhy chut tri. Linh kin vn dnh vo chut, nu mun s dng tip cng
linh kin , chn v tr t linh kin v tip tc nhy chut tri, ngc li, nu mun la chn linh
kin khc, c th nhy chut phi, chn End Mode hoc nhn nt Esc trn bn phm.

18

3.2. Chnh sa linh kin
Nhy chut tri chn linh kin cn chnh sa
Nhy chut phi
Chn Edit Part
Trong trang Part Editor, di chuyn chn IC sao cho ph hp,
sau nhn nt ng ca s Part Editor v chn
Update Current v quay tr li trang v s mch (ging
hnh sau).

Thao tc chn v t v tr ca cc in tr R v t in C cng c thc hin tng t.
19

Xoay linh kin theo mun thc
hin bng cch:
Nhp chut tri chn linh
kin
Nhp chut phi
Chn 1 trong cc lnh:
Mirror Horizontally (H)
Mirror Vertically (V)
Rotate (R)

20

Ta v c s mch nh sau
Lu li s mch, kt thc Orcad Capture!!!
21
4. Orcad Pspice
Pspice Toolbar in Capture

New Simulation Profile M mt trang m phng mi

Edit Simulation Settings
M ca s Simulation Setting chn cc iu kin m
phng mch

Run PSpice Chy trnh PSpice

View Simulation Results Xem kt qu m phng

Voltage/ Level Marker u d mc in p ti mi im

Voltage Differential Marker u d o chnh lch in p gia 2 im

Current Marker u d cng dng in

Power Dissipation Maker u d o cng sut tiu hao trn mi linh kin

Enable Bias Voltage Display Hin th in p phn cc ti mi nt

Enable Bias Current Display Hin th cng dng in phn cc trn mi linh kin

Enable Bias Power Display Hin th cng sut tiu hao trong iu kin phn cc

File Toolbar in PSpice
Tool Tn M t

New M mt trang m phng mi hoc mt file dng vn bn

Open M mt file

Append File M mt file d liu .DAT

Save Lu li file d liu

Print In kt qu

22
Edit Toolbar in PSpice
Tool Tn M t

Cut Ct phn chn khi trang th v lu vo Clipboard

Copy Sao chp phn chn vo Clipboard

Paste Dn ni dung trong Clipboard vo trang th

Undo Xa thao tc va thc hin, ly li trng thi trc

Redo Ly li lnh va thc hin

Simulate Toolbar in PSpice
Tool Tn M t

Current Simulation Thng bo kiu m phng ang thc hin

Run Chy trnh PSpice

Pause Tm dng qu trnh phn tch

Probe Toolbar in PSpice
Tool Tn M t

Zoom In Phng to trang th

Zoom Out Thu nh trang th

Zoom Area Phng ln vng th c chn

Zoom Fit Hin th ton b phn trn trang th

Log X Axis Thay i thang chia ca trc X

Fourier Phn tch tn hiu theo vch ph tn, dng Fourier

Performance Analysis Tt/m trang th phn tch dng tch hp

Log Y Axis Thay i thang chia ca trc Y

Add Trace V thm th

Eval Goal Function X l tn hiu theo dng hm tch hp
23

Text Label Cho php ghi Text ln trang th

Mark Data Points Tt/m im nh du trn th

Toggle Cursor Hin th hoc khng hin th con tr trn th

Cursor Toolbar in PSpice
Tool Tn M t

Cursor Peak Con tr di chuyn ngay ti im c bin ln nht

Cursor Trough Con tr di chuyn ngay ti im c bin nh nht

Cursor Slope Con tr di chuyn ngay ti im c dc ln nht

Cursor Min Con tr di chuyn ngay ti im cc tiu

Cursor Max Con tr di chuyn ngay ti im cc i

Cursor Point Con tr di chuyn ti cc im d liu trn th

Cursor Search M ca s Search Command a con tr ti im cn tm

Cursor Next Tran a con tr ti im nhy mc tip theo ca tn hiu xung/s

Cursor Previous Tran a con tr ti im nhy mc trc ca tn hiu xung/s

Mark Label t ta ti v tr ca con tr

Tool Tn M t

Always On Top

View Circuit File Xem file mch s nguyn l

View Simulation Output File Xem file kt qu u ra ca qu trnh m phng

View Simulation Results Xem kt qu m phng

Simulation Queue Hng i m phng

Edit Simulation Settings Thit lp cc la chn ca m phng

24
Bi 1
a. V s mch in nh hnh 1

To mt m phng mi

Trn Menu Bar chn PSpiceNew Simulation Profile, hoc kch vo trn PSpice Toolbar trong
Capture, mt ca s New Simulation xut hin:

R1
22k
R4
1.2k
R3
5.6k
0
V1
12Vdc
Q2
Q2SC1815
0
R5
56k
0
R2
1k
Q1
Q2SC1815
Hnh 1
25

Trong khung Name: in tn ca m
phng mi, v d l: Bias Point
Trong khung Inherit From: Chn tn
ca mt m phng m ta mun k
tha kt qu hoc c th chn None
Sau Click Creat

Ca s Simulation Setting hin ra

Trong khung Analysis Type (kiu phn tch), chn: Bias Point. Sau click OK ng ca s
Simulation Setting v quay tr li trang s mch.
Trn Menu bar chn PSpiceRun hoc c th click tiu hnh hoc c th nhn phm nng F11.
Pspice A/D m phng v tnh ton cc tham s ca im phn cc.

26

PSpice A/D s m ra mt trang th, tuy nhin trong kiu phn tch Bias Point ta s khng thy
c bt k mt th no do cc tham s ca im phn cc u l cc tham s tnh. Sau khi hon tt
qu trnh m phng, PSpice A/D s xut ra mt file kt qu (output file) ng thi c th a ra cc
cnh bo hoc cc li xut hin trong qu trnh m phng.
c file kt qu, trong trong Pspice A/D chn ViewOutput File

File kt qu c hin th trong ca s Bias point.out. Ta c th c c cc gi tr in p ti mi
nt v cng dng in qua ngun V1. PSpice A/D o cng dng in chy vo ti cc th
nht v ra ti cc th 2 ca linh kin, i vi ngun p cc th nht tng ng l cc dng v cc th
hai l cc m nn dng in c gi tr m trong file kt qu.
27

Mun hin th cc gi tr in p v cng dng ti mi im click vo tiu hnh v .

b. Thm cc linh kin c s mch nh hnh 2

R5
56k
Q1
Q2SC1815
0V
0 0
R2
1k
12.00V
Q2
Q2SC1815
V1
12Vdc
0
447.8mV
R1
22k
2.053V
1.325V
R3
5.6k
R4
1.2k
0V
1.153V
5.843V
0V
R5
56k
3.060uA
Q1
Q2SC1815
3.060uA
444.8uA
-447.8uA
0 0
R2
1k
447.8uA
Q2
Q2SC1815 7.394uA
1.099mA
-1.107mA
V1
12Vdc
1.552mA
0
R1
22k
452.1uA
R3
5.6k
1.099mA
R4
1.2k
1.104mA
R2
1k
R5
56k
0 0 0
R3
5.6k
C1
10uF
C2
10uF
R6
5k
0
Q2
Q2SC1815
V1
12Vdc
R1
22k
R4
1.2k
C3
220uF
0
V2
1Vac
0Vdc
Q1
Q2SC1815
0
Hnh 2
28
Trong Menu Bar ca Capture, chn PSpiceNew Simulation Profile
Ca s New Simulation c m ra:

Trong khung Name: t tn cho m phng mi, gi
s l AC Sweep
Trong khung Inherit From: Chn SCHEMATIC1-
Bias Point
Click Creat

Ca s
Simulation
Setting c m
ra:

Trong text box Analysis type: Chn AC Sweep/Noise (kiu phn tch)
Trong text box Option: Chn General Setting
AC Sweep Type: Chn Logarithmic (Thang Logarith)
29
Start Frequency (Tn s khi u): 10Hz (10)

End Frequency (Tn s kt thc): 1MHz (1Meg)
Point/Decade (S im d liu trong mt thang Decade): 1000, s im d liu trong mt
thang Decade cng ln th cng trn tuy nhin thi gian thc hin qu trnh m phng li
ln.
Sau khi la chn xong, click OK ng ca s Simulation Setting v quay tr li trang s
mch (Schematic Page).
Ly u o a ti im gia C2 v R6 o in p u ra.
Chy m phng bng mt trong 3 cch:
T Menu Bar, chn PSpiceRun
Nhn phm F11
Click vo tiu hnh
Trang th c m ra, biu din s ph thuc ca in p u ra vo tn s ca tn hiu vo (c
tuyn bin-tn)

Biu din c tuyn Pha-tn
Trn menu bar, chn PSpiceMarkersAdvancedPhase of Voltage

30

a u o ti u ra ca mch (im gia C2 v R6), sau chy m phng. Ta quan st c c
tuyn Pha-tn ca mch nh hnh sau:

31

Phn tch mch theo bin thi gian (Transient)

V1
12Vdc
C3
220uF
0 0 0
R1
22k
Q2
Q2SC1815
C2
10uF
R6
5k
V
0
R3
5.6k
C1
10uF
Q1
Q2SC1815
R4
1.2k
V3
FREQ =1KHz
VAMPL =10mV
VOFF =0
0
R5
56k
R2
1k
0
32
33
Bi 2

Q3
Q2SC1815
R2
10k
D3
D1N4148
R6 10k
Q1
Q2SC1815
Q2SD880
Q5
R10
1k
R5
1k
Q4
Q2SA1015
R4
150
R1
68k
R9
150
R3
5.6k
D2
D1N4148
0
R8
3.9k
D1
D1N4148
R11
560
V1
26Vdc
Q2
Q2SC1815
R7
47k
R12
560
Q2SD880
Q6
0
13.47V
14.19V
0
1.098V
Q2SD880
Q5
R1
68k
26.00V
14.63V
1.822V
0V
Q3
Q2SC1815
D3
D1N4148
Q1
Q2SC1815
R9
150
R7
47k
D1
D1N4148
Q2SD880
Q6
785.2mV
R11
560
9.324V
Q2
Q2SC1815
R3
5.6k
R5
1k
13.50V
R8
3.9k
Q4
Q2SA1015
V1
26Vdc
52.05uV
R2
10k
R6 10k
954.5mV
0
12.74V
R10
1k
R12
560
R4
150 D2
D1N4148
13.35V
0V
0
D3
D1N4148
93.72nA
Q2
Q2SC1815
66.02uA
-10.33mA
R3
5.6k
948.2uA
R6 10k
1.137mA
Q2SD880
Q5
-2.101pA
17.28pA
-15.18pA
V1
26Vdc
11.67mA
R12
560
92.94nA
R4
150
R2
10k
182.2uA
R7
47k
267.4uA
R11
560 267.4uA
R10
1k
10.27mA
D1
D1N4148
Q4
Q2SA1015
-785.0pA
93.72nA
R9
150
R5
1k
954.5uA
Q3
Q2SC1815
1.728uA 265.7uA
Q2SD880
Q6 62.37pA
30.97pA
-93.34pA
R8
3.9k
201.3uA
0
R1
68k
188.4uA
D2
D1N4148
Q1
Q2SC1815
6.251uA
948.2uA
34
Thm cc t in v ngun tn hiu c mch nh hnh v.
R1
68k
C3
10uF
R12
560
V2
1Vac
0Vdc
V
Q2
Q2SC1815
R11
560
D1
D1N4148
C1
10uF
Q4
Q2SA1015
0
R9
150
R4
150
Q1
Q2SC1815
R7
47k
C5
47uF
D2
D1N4148
R2
10k
C4
220uF
Q3
Q2SC1815
C6
1000uF
R8
3.9k
C7
100pF
R13
8
Q2SD880
Q5
D3
D1N4148
V1
26Vdc
Q2SD880
Q6
0
0
R3
5.6k
C2
220uF
R5
1k
R10
1k
R6 10k
35

R2
10k
C7
100pF
D3
D1N4148
R12
560
R10
1k
V2
FREQ =1KHz
VAMPL =10mV
VOFF =0
R3
5.6k
D1
D1N4148
R5
1k
C2
220uF
Q1
Q2SC1815
Q2SD880
Q6
C5
47uF
R4
150
C4
220uF
R6 10k
V1
26Vdc
V
R13
8
Q2SD880
Q5
0
C6
1000uF
Q4
Q2SA1015
D2
D1N4148
0
R7
47k
0
R9
150
Q3
Q2SC1815
Q2
Q2SC1815
C1
10uF
C3
10uF
R1
68k
R11
560
R8
3.9k
36

Nu tng bin u vo, tn hiu ra b mo ln.

Sa mo bng cch ghp hi tip: a mt phn tn hiu ra quay tr li u vo tuy lm gim h s
khuch i nhng ngc li ci thin mt s thng s: rng di thng, gim mo, n nh mch
khuch i.
T C8 v in tr R14 ng vai tr l ng cp tn hiu hi tip. Gi tr R14 cng nh th mc hi
tip cng mnh (cng su)
37

Bi 3. To ra mt th vin mi, trong cc k hiu ca cc linh kin c thay i ging nh di
hnh v

R2
8
+-
9V
BT2
BATTERY
F1
FUSE
U1
OPAmp
3
2
4
1 8
7
6
5
D
LED
+ -
1. 5V
BT1
BATTERY
+
C
D1
DIODE
D2
DIODE
R
R1
1k
Q1
Q2SC1815

Q1
Q2SC1815
C7
100pF
D1
D1N4148
R3
5.6k
R7
47k
R4
150
C1
10uF
Q4
Q2SA1015
R2
10k
0
R8
3.9k
R9
150
C3
10uF
R5
1k
0
R13
8
Q2SD880
Q5
C6
1000uF
C8
100uF
V1
26Vdc
R6 10k
V
D2
D1N4148
C4
220uF
Q3
Q2SC1815
R10
1k
Q2SD880
Q6
D3
D1N4148
R1
68k
Q2
Q2SC1815
R12
560
C5
47uF
C2
220uF
R11
560
R14
10k
0
V2
FREQ =1KHz
VAMPL =200mV
VOFF =0
38
0
In
Mid
0
R3
3.3k
C1
0.47uF
D1
D1N3940
R1
1k
R2
3.3k
V1
5V
R4
5.6k
Vcc
In
Vin
0V
Out
Vcc
D2
D1N3940
0
Bi 4
V s mch nh hnh v.

a. Xc nh im lm vic (Bias Point)
To mt m phng mi: PSpiceNew Simulation Profile hoc click vo tiu hnh
trn PSpice Toolbar trong Capture.
Ca s Simulation c m ra. in tn ca m phng vo text box Name. Trong
text box Inherit From chn none.
Click Creat.

Ca s Simulation Setting m ra:
Trong Analysis type chn: Bias Point
Trong Options chn: General Settings

39

Quay tr li trang v s mch v chy PSpice.
Trang PSpice A/D c m ra, c th c kt qu ca m phng bng cch m Output file bng
cch chn ViewOutput File hoc c th click vo tiu hnh
40
In
0
Mid
R2
3.3k
1.229mA
D1
D1N3940
404.1pA
D2
D1N3940
400.9pA
R3
3.3k
285.9uA
R4
5.6k
0A
V1
5V
1.229mA
Vcc
Out
Vin
0V
943.4uA
0
Vcc
C1
0.47uF
In
R1
1k
943.4uA
0
In
5.000V
0V
Mid
R2
3.3k
Vin
0V
D1
D1N3940
5.000V
943.4mV
D2
D1N3940
R3
3.3k
R4
5.6k
V1
5V
0
0
Out
0V
Vcc
C1
0.47uF
Vcc
In
R1
1k
0
Hin th cc gi tr in p v cng dng in mt chiu trn mch.

b. Phn tch p ng u ra khi cho ngun u vo thay i (DC Sweep)
To mt m phng mi v thit lp cc tham s nh hnh di.
41

V th ca cc in p V(IN), V(MID), V(OUT) khi V(IN) thay i:
Trn Menu bar ca PSpice A/D chn: TraceAdd Trace

Ca s Add Traces c m ra. Click vo V(IN), V(MID),V(OUT) trong danh sch cc th.
42

Cc th c v trong trang th (Probe Window).

Trace Legend
Probe Window
43

Hin th con tr: Trn menu ca PSpice chn TraceCursorDisplay. Khi 2 con tr xut
hin v chy trn th c v u tin c th hin trong Trace Legend: K hiu ca ng V(IN)
c bao ngoi bi mt vung nh v ca s Probe Cursor c m ra hin th ta ca 2 im
A1, A2 tng ng vi 2 con tr v dif l chnh lch ta ca 2 con tr.
Con tr th nht ng vi chut tri v con tr th hai ng vi chut phi.

44
Mi con tr c hin th l giao im ca 2 ng vung gc vi nhau khi click chut tri hoc
chut phi. Khi di chuyn chut trong ca s th ta ca cc im A1, A2 v dif s thay i.
Cng c th nh ngha 2 con tr chy trn 2 th khc nhau bng cch click vo cc k hiu ca cc
ng tng ng trong Trace Legend. V d: Click chut tri v chut phi vo cc k hiu tng ng
ca cc ng V(IN) v V(MID) (nh hnh v), khi con tr th nht chy trn ng V(IN), con
tr th hai chy trn ng V(MID).

C th chnh ta ca cc con tr bng cch di chuyn con tr hoc c th nhn phm v
i vi con tr th nht, hoc Shift+ v Shift+ chnh tinh.
c. Phn tch mch theo bin thi gian (Transient)

Ly thm cc linh kin v v s mch ging hnh di.

45

46
Trnh PSpice Stimulus Editor to cc dng ngun tn hiu
Trong th vin SOURCESTM.LIB ta c 8 ngun tn hiu c tnh chn nh vi trnh PSpice Stimulus
Editor:

Dng trnh PSpice Stimulus Editor bin son v to ra dng tn hiu mong mun.
Khai bo ngun VSTIM
Chn ngun VSTIM
Click chut phi v chn Edit PSpice Stimulus.
Ca s New Stimulus c m ra:
Name: Ghi tn ca tn hiu (SINE)
Chn dng tn hiu: (SIN)
Analog
EXP: Dng hm m
PUSLE: Dng xung
PWL: Dng tuyn tnh ha tng phn
SFFM: Dng iu ch FM n tn
SIN: Dng sng Sine
Digital
Clock: Dng xung nhp
Signal: Dng ngun tn hiu t chn
Bus: Ngun tn hiu s dng cho Bus

Ca s Attribute c m, yu cu khai bo cc tham s ca ngun tn hiu:
Offset value: Mc in p chun ca tn hiu dng sin (thnh phn DC) [V]
Amplitue: Bin [V]
Frequency: Tn s [Hz]
Time delay: Thi gian tr [s]
Damping factor: H s m [s
-1
]
Phase angle: Gc pha []
Khai bo xong, clicl Apply v OK.

S8
DSTM6
Implementation =
S
V1
Implementation =
S4
DSTM5
Implementation =
S
I1
Implementation =
S2
DSTM3
Implementation =
S32
DSTM4
Implementation =
S16
DSTM2
Implementation =
S1
DSTM1
Implementation =
47

To mt m phng mi v khai bo cc thng s ca qu trnh m phng. Quay tr li trang v
s mch v chy m phng. Hin th dng sng ca tn hiu u vo V(IN) v tn hiu u ra
V(OUT).
48

d. Phn tch mch theo bin tn s (AC Sweep)

V s mch nh hnh v
To mt m phng mi, phn tch s thay i ca V(MID) v V(OUT) theo tn s
V th Bode (V(MID) v V(OUT) c o theo n v Decibel):
PSpiceMarkersAdvanceddB Magnitude of Voltage

49

In
Vcc
Vin
1Vac
Mid
In
Vcc
R1
1k
R3
3.3k
S
V2
SINE
Out
R4
5.6k
D2
D1N3940
C1
0.47uF
0
0
R2
3.3k
D1
D1N3940
0
V1
5V
50

VDB VDB
In
Vcc
Vin
1Vac
In
0
R1
1k
Out
R3
3.3k
S
V2
SINE
0
R4
5.6k
D2
D1N3940
Mid
C1
0.47uF
0
R2
3.3k
Vcc
D1
D1N3940
V1
5V
51

Biu din c tuyn bin-tn v pha-tn trn 2 trc Y khc nhau

Click vo nhn VP(OUT) trong Trace legend chn ng
T menu Edit chn Cut hoc nhn phm Shift+Delete hoc click vo tiu hnh ,
ng VP(OUT) c lu vo Clipboard.
T menu Plot trong PSpice chn Add Y Axis. Trc Y th 2 xut hin
Chn EditPaste dn ng cong VP(OUT) vo trang th vi trc Y th 2. Hai
c tuyn bin-tn v pha-tn c biu din vi 2 trc Y vi thang chia khc nhau.

52

e. Phn tch s nh hng ca in tr u vo ti cc thng s ca mch: rng di thng, h
s khuch i,

Thay gi tr 1K ca in tr R1 bng biu thc {Rval}

Double-click vo gi tr 1K ca R1, ca s Display Properties c m ra
Trong text box Value: xa 1K v thay bi biu thc {Rval}. Pspice A/D hiu biu thc trong du
{} nh l mt tham s.
Click OK.

Thm phn t PARAM khai bo tham s Rval
Ly phn t PARAM v t ti v tr bt k trong trang s mch
53

Double-click vo phn t PARAM, ca s Property Editor c m ra, lit k cc thng s ca
phn t

Click vo New Column, ca s Add New
Column c m ra
Trong text box Name: in Rval
Trong text box Value: in 1K, l gi tr
khi to ca R1
Click OK
54
VDB
Mid
In
In
R4
5.6k
V1
5V
Vcc
D2
D1N3940
0
R2
3.3k
D1
D1N3940
Vin
1Vac
R1
{Rval}
PARAMETERS:
Rval =1K
Vcc
0
R3
3.3k
0
S
V2
SINE
Out
C1
0.47uF
Quay tr li ca s Property Editor,
chn Rval
Click Display, ca s Display
Property c m ra
Chn Name and Value
Xong, click OK.

Ta c c s mch nh hnh v

To mt m phng mi v khai bo cc tham s ca trnh m phng ging nh cc hnh di.

Gi tr Rval l mt tham s chy t gi tr 100 n gi
tr 10K theo thang Logarithm, tng ng vi 2
Decade. Mi Decade c chia thnh 10 im, do
Rval chy t 100 n 10K tng ng vi 21 gi tr.
V c tuyn bin tn ti u ra ca mch, khi
h c tuyn bao gm 21 ng

55

56

Search Command

57
V1
0Vdc
R1
10
I
D1
D1N4007
0
Bi 5. Dng Pspice phn tch mt s linh kin bn dn
a. Phn tch Diode

V c tuyn ca Diode

Phn tch s nh hng ca nhit ti c tuyn ca Diode

58

b. Phn tch Diode Zener

R1
100
D2
1N4372
1
2
0
V1
0Vdc I
59
c. Phn tch Transistor lng cc

V1
0V
0
V2
0V
0
0
R1
47k
Q1
Q2SC1815
I
60

Hin th 2 th ly theo hai trc Y c thang chia khc nhau: mA I
C
v A I
B

V c tuyn vo const U U f I
CE BE B

d. Phn tch Transistor trng MOSFET cng sut
Hin th h c tuyn vo v c tuyn ra ca MOSFET

VDS
0V
0
0 0
M1
IRF150 VGS
0V
I
61

62
Bi 6. PSpice v cc mch s
S dng trnh Pspice Stimulus Editor khai bo mt ngun tn hiu s
63

Nu chn ngun tn hiu l Signal, cn to nn cc sn (transition). Trong PSpice Stimulus
Editor ta c th thc hin cc thao tc sau:
Thm cc sn (Add a transition)
Dch chuyn sn (Move a transition)
To, chnh sa sn (Edit a transition)
Xa sn (Delete a transition)
Thm sn vo ngun tn hiu
1. Trn menu Edit trong ca s Stimulus Editor chn Add hoc click vo tiu hnh
2. Chn tn hiu s cn bin son
3. Click chut vo v tr mun to sn ti (c s thay i trng thi)
4. Nu mun to thm cc sn, lp li cc bc th 2 v th 3
5. Click chut phi khi mun kt thc qu trnh to sn

Dch chuyn sn tn hiu
1. Click vo sn mun dch chuyn
2. C th s dng Shift+click chut nu mun chn nhiu sn ng thi
3. Dch chuyn sn ti v tr mi
64
Bin son cc thng s ca sn
1. C th thc hin theo mt trong cc cch sau:
Chn sn cn bin son, EditProperties
Double-click vo sn cn bin son
2. Ca s Edit Digital Transition c m ra, in cc
thng s, sau click OK.
Xa sn tn hiu
1. Click vo sn mun xa
2. C th s dng Shift+click chut tri nu mun chn
nhiu sn ng thi
3. Chn EditDelete hoc nhn phm Delete trn bn phm

Nu ngun tn hiu c chn l Bus, ta cng phi xc nh cc sn ca Bus
to ra mt Bus cn 3 bc:
To nn mt ngun kch tn hiu s dng Bus
To nn cc sn
Thit lp h m cho Bus
To mt ngun tn hiu s dng Bus
1. T menu Stimulus ca trnh Stimulus Editor, chn New
2. Trong khung Digital, chn Bus
3. C th thay i rng ca Bus (gi tr mc nh l 8 bit)
4. Xong, click OK.
To cc sn cho Bus
C th to nn cc sn cho Bus theo 2 cch sau:
Cch 1:
1. T menu Edit trong Stimulus Editor, chn Add
2. Trong trng gi tr trn Toolbar (ngay bn phi ca tiu hnh Add), in gi tr ca Bus theo
mt trong 3 cch sau:

Nu khng nhp gi tr ca h m, trnh Stimulus Editor s da vo h m mc nh ca Bus
Thng thng <S nguyn khng du>[; h m] 12
Tng +<S nguyn khng du>[; h m] +12;H
Gim -<S nguyn khng du>[; h m] -12;H
Trng gi tr
65

3. Nhp chut vo v tr ca Bus mun to sn ti
4. Lp li cc bc 2 v bc 3 nu cn thit
5. Xong, nhp chut phi kt thc.
Cch 2:
1. T menu Edit trong Stimulus Editor, chn Add
2. Click chut (u mi bt ch) vo ti v tr mun to sn
3. Xong, nhp chut phi kt thc
4. Nhp chut tri vo v tr sn u tin, mt hnh thoi nh xut
hin ti sn
5. Chn EditAttributes (Ctr+T), ca s Edit Digital
Transition c m ra
6. Trong Transition Type, chn Set Value (gi tr xc nh),
Increment (mt gi tr tng so vi gi tr trc), hoc
Decrement (mt gi tr gim so vi gi tr trc)
7. Trong text box Value, in mt gi tr xc nh hoc c th
chn mt trong cc trng hp c mc nh (0, All bits 1(tt
c cc bit u bng 1), X (khng xc nh), hoc Z (tr khng
cao) )
8. Xong, click OK
9. Lp li cc bc t bc 4 n bc 8 i vi mi sn
Thit lp h m cho Bus
1. Chn ToolOption, ca s Stmed Options c m ra
2. Trong khung Bus Display Defaults, chn h m trong danh sch c lit k ti Radix
3. Xong, click OK
66
Thit k mch m nh phn 4 bit, hin th cc u ra v to bus {DCBA}
a. B m khng ng b
b. B m ng b

Thit k b m khng ng b c modul m M=10 (m t 0 n 9) s dng JK FF.
Hin th kt qu u ra.
U2A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
D
B C
A
U5A
7408
1
2
3
S1
DSTM3
CLR
U1A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
S1
DSTM2
Clock
CLK
U3A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
U5B
7408
4
5
6
U4A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
S1
DSTM1
IN
CLK
U1A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
C
U4A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
U2A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
S1
DSTM1
IN
S1
DSTM3
CLR
B A D
U3A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
S1
DSTM2
Clock
B
U5A
7400
1
2
3
U1A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
D
U4A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
S1
DSTM1
IN
U2A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
U3A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
C
A
S1
DSTM2
Clock
CLK
67
Thit k b m ng b c M=5. Hin th kt qu ti u ra?

Bi 7. V mch gii m EPROM

A6
U3
74AS138
1
2
3
15
14
13
12
11
10
9
7
1
6
8
6
4
5
A
B
C
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V
C
C
G
N
D
G1
G2A
G2B
D1
A8
A10
D7 A13
A5
VCC
VCC
RST
D3
A8
A2
A0
D4
A9
A5
A15
A3
J 2
CON1
1
D0
A14
A4
D0
D3
VCC
A7
A
[
1
5
.
.
0
]
A6
A7
A10
A12
VCC
R1 10K
J 1
CON1
1
D6
A2
A15
A9
A12
D7
A0
A4
R2 10K
D1
VCC
D[7..0]
D5
D4
A11
A14
D2
D6
R4 10K
U2
2764
10
9
8
7
6
5
4
3
25
24
21
23
2
11
12
13
15
16
17
18
19
2
8
1
4
22
27
1
20
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
O0
O1
O2
O3
O4
O5
O6
O7
V
C
C
G
N
D
OE
PGM
VPP
CE
A3
A1
VCC
A1
CLK
R3 10K
D2
D5
A13
U1
Z80
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
24
16
17
26
25
23
6
1
1
2
9
20
18
14
15
12
8
7
9
10
13
27
19
21
28
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
WAIT
INT
NMI
RST
BUSRQ
BUSAK
CLK
V
C
C
G
N
D
IORQ
HALT
D0
D1
D2
D3
D4
D5
D6
D7
M1
MREQ
RD
REFSH
WR
A11
U1A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
Q1
U4A
7408
1
2
3
U2A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
S1
DSTM2
CLR
HI
U3A
74107
1
4
1
3
3
2
12
J
K
C
L
R
Q
Q
CLK
Q2
Q0
S1
DSTM1
CLK
68

D1
DIODE
Q1
EC103M/TO
R4
RESISTOR VAR
R3
R
J 1
220~
1
2
R2
4.7K
J 2
DONG CO
12
R1 1K
+
C1
CAPACITOR POL

69

R7 3.9K
R3 3.9K
R6 1K
Q1
2N1208
Q2
2N1208
12V
Q3
2N5680
R4 39K
R5 10K
R2
9K
C1
470uF/10V
J 1
QUAT
1
2
R1 KTY10

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

Q3
2N2222
D3
DIODE
R1
39K
R6
100K
Q2
2N2222
C1
0.1uF/600V
J 1
220~
1
2
D2
DIODE
J 2
DONG CO
1
2 R3
12K
SW1
SW MAG-SPDT
R5
220
C2
100uF
R4
3.3K
R2 68K
D1
DIODE
Q1
T2801
L1
INDUCTOR FERRITE

Bai Giang Orcad

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Bai Giang Orcad

Uploaded by

Copyright:

Available Formats

Bi ging Orcad Nguyn Thy Bnh- KTT

You might also like