EC6504 Microprocessor and Microcontroller Lecture Notes All 5 Units

EC6504
Microprocessors and
Microcontrollers
DEPARTMENTS: CSE,IT,ECE,ECE,MECH
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
1
Microprocessor
Microprocessor (P) is the brain of a computer
that has been implemented on one
semiconductor chip.
The word comes from the combination micro and
processor.
Processor means a device that processes
whatever(binary numbers, 0s and 1s)
To process means to manipulate. It describes all
manipulation.
Micro - > extremely small
2
Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.
Microprocessor ?
A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
4
Applications
Calculators
Accounting system
Games machine
Instrumentation
Traffic light Control
Multi user, multi-function environments
Military applications
Communication systems
5
MICROPROCESSOR HISTORY
DIFFERENT PROCESSORS AVAILABLE

Socket
Pinless
Processor
Processor
Slot
Processor
Processor
Slot
7
Development of Intel Microprocessors
8086 - 1979
286 - 1982
386 - 1985
486 - 1989
Pentium - 1993
Pentium Pro - 1995
Pentium MMX -1997
Pentium II - 1997
Pentium II Celeron - 1998
Pentium II Zeon - 1998
Pentium III - 1999
Pentium III Zeon - 1999
Pentium IV - 2000
Pentium IV Zeon - 2001
GENERATION OF PROCESSORS
Processor
Bits
Speed
8080
2 MHz
8086
16
4.5 10
MHz
8088
16
4.5 10
MHz
80286
16
10 20
MHz
80386
32
20 40
MHz
80486
32
40 133
MHz
9
GENERATION OF PROCESSORS
Processor
Bits
Speed
Pentium
32
60 233
MHz
Pentium
Pro
32
150 200
MHz
Pentium II,
Celeron ,
Xeon
32
233 450
MHz
Pentium
III, Celeron
, Xeon
32
450 MHz
1.4 GHz
Pentium IV,
Celeron ,
Xeon
32
1.3 GHz
3.8 GHz
Itanium
64
800 MHz
3.0 GHz
10
Intel 4004
Introduced in 1971.
It was the first microprocessor
by Intel.
It was a 4-bit P.
Its clock speed was 740KHz.
It had 2,300 transistors.
It could execute around
60,000 instructions per
second.
11
Intel 4040
Introduced in 1971.
It was also 4-bit P.
12
8-bit Microprocessors
13
Intel 8008
Introduced in 1972.
It was first 8-bit P.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.
14
Intel 8080
Introduced in 1974.
Its clock speed was
2 MHz.
It had 6,000
transistors.
15
Intel 8085
Introduced in 1976.
Its clock speed was 3 MHz.
Its data bus is 8-bit and
address bus is 16-bit.
Could execute 7,69,230
instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.
16
16-bit Microprocessors
17
INTEL 8086
Introduced in 1978.
Its clock speed is 4.77 MHz, 8 MHz

and 10 MHz, depending on the
version.
Its data bus is 16-bit and address
bus is 20-bit.
Could execute 2.5 million
instructions per second.
It could access 1 MB of memory.
It had 22,000 instructions.
It had Multiply and Divide

instructions.
18
INTEL 8088
Introduced in 1979.
It was created as a
cheaper version of
Intels 8086.
It was a 16-bit processor
with an 8-bit external
bus.
19
INTEL 80186 & 80188
Introduced in 1982.
They were 16-bit Ps.
Clock speed was 6 MHz.
80188 was a cheaper

version of 80186 with an
8-bit external data bus.
20
INTEL 80286
Introduced in 1982.
It was 16-bit P.
Its clock speed was 8

MHz.
Its data bus is 16-bit

and address bus is 24bit.
It could address 16 MB
of memory.
It had 1,34,000
transistors.
21
32-BIT MICROPROCESSORS
22
INTEL 80386
Introduced in 1986.

It could address 4 GB of
memory.
It had 2,75,000
transistors.
Its clock speed varied
from 16 MHz to 33 MHz
depending upon the
various versions.
23
INTEL 80486
Introduced in 1989.
It had 1.2 million

transistors.
from 16 MHz to 100
MHz depending upon
the various versions.
8 KB of cache memory
was introduced.
24
INTEL PENTIUM
Introduced in 1993.
It was originally named

80586.
MHz.
25
INTEL PENTIUM PRO
Introduced in 1995.
It had 21 million
transistors.
Cache memory:
8 KB for instructions.
8 KB for data.
26
INTEL PENTIUM II
Introduced in 1997.

MHz to 500 MHz.
Could execute 333
million instructions per
second.
27
INTEL PENTIUM II XEON
Introduced in 1998.
It was designed for

servers.
MHz to 450 MHz.
28
INTEL PENTIUM III
Introduced in 1999.

from 500 MHz to 1.4
GHz.
It had 9.5 million
transistors.
29
INTEL PENTIUM IV
Introduced in 2000.
Its clock speed was from

1.3 GHz to 3.8 GHz.
It had 42 million
transistors.
30
INTEL DUAL CORE
Introduced in 2006.
It is 32-bit or 64-bit P.
31
32
64-BIT MICROPROCESSORS
33
Intel Core 2
Intel Core i3
34
INTEL CORE I5
INTEL CORE I7
35
Basic Terms
Bit: A digit of the binary number { 0 or 1 }
Nibble: 4 bit
Byte: 8 bit word: 16 bit
Double word: 32 bit
Data: binary number/code operated by an
instruction
Address: Identification number for memory
locations
Clock: square wave used to synchronize various
devices in P
Memory Capacity = 2^n ,
n->no. of address lines
36
BUS CONCEPT
BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3.CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to P
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a P system
37
3 logic levels are:
TRISTATE LOGIC
High State (logic 1)

Low state (logic 0)
High Impedance state
High Impedance: output is not being driven to any defined logic level
by the output circuit.
38
Basic Microprocessors System

Central Processing Unit
Input
Devices
Arithmetic-Arithmetic
Control
Logic
Unit
ProcessingUnit
Data into
Information
Primary
Storage
Unit
Keyboard,
Mouse
etc
Output
Devices
Monitor
Printer
Disks, Tapes,
Optical Disks
Secondary Storage Devices
39
UNIT
1
THE 8086 MICROPROCESSOR
40
8086 Microprocessor-introduction
INTEL launched 8086 in 1978
8086 is a 16-bit microprocessor with
16-bit Data Bus {D0-D15}
20-bit Address Bus {A0-A19} [can access upto
2^20= 1 MB memory locations] .
It has multiplexed address and data bus

AD0-AD15 and A16A19.
It can support upto 64K I/O ports
41
8086 Microprocessor
It provides 14, 16-bit registers.
8086 requires one phase clock with a 33%
duty cycle to provide optimized internal
timing.
Range of clock:
5 MHz for 8086
8Mhz for 8086-2
10Mhz for 8086-1
42
INTEL 8086 - Pin Diagram/Signal Description
43
INTEL 8086 - Pin Details
Power Supply
5V 10%
Ground
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
Clock
If high for
minimum 4
clks
Duty cycle: 33%

44
Address/Data Bus:
Contains address
bits A15-A0 when ALE
is 1 & data bits D15
D0 when ALE is 0.
Address Latch Enable:

When high,
multiplexed
address/data bus
contains address
information.
45
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
46
Direct
Memory
Access
Hold
Hold
acknowledge
47
Address/Status Bus
Address bits A19
A16 & Status bits S6
S3
48
BHE#, A0:
Bus High Enable/S7
0,0: Whole word

(16-bits)
Enables most
significant data bits
D15 D8 during read
or write operation.
0,1: High byte

to/from odd address
1,0: Low byte
to/from even address
S7: Always 1.
1,1: No selection
49
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins

Maximum Mode
Pins
50
Minimum Mode- Pin Details
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
Data Bus Enable
51
Maximum Mode - Pin Details
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive
Status Signal
Inputs to 8288 to
generate eliminated
signals due to max
mode.
52
Lock Output
Used to lock peripherals
off the system
Activated by using the
LOCK: prefix on any
instruction
DMA
Request/Grant
Lock Output
53
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)
54
8086 Internal Architecture

8086 employs parallel processing
8086 CPU has two parts which operate at the
same time
Bus Interface Unit

Execution Unit
CPU functions
1. Fetch
2. Decode
3. Execute
8086 CPU
Bus Interface
Unit (BIU)
Execution Unit
(EU)
55
Bus Interface Unit

Sends out addresses for memory locations
Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data to Input/Output ports
56
Execution Unit
Tells BIU (addresses) where to fetch
instructions or data
Decodes & Executes instructions
Dividing the work between BIU & EU
speeds up processing
57
Architecture Diagram of 8086
58
Memory
Interface
BIU
EXTRA SEGMENT (ES)

CODE SEGMENT (CS)
STACK SEGMENT (SS)

DATA SEGMENT (DS)
Instruction Queue
INSTRUCTION POINTER (IP)
Instruction
Decoder
AH
AL
BH
BL
CH
CL
DH
DL
ARITHMETIC
LOGIC UNIT
CONTROL
SYSTEM
STACK POINTER (SP)

BASE POINTER (BP)
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
OPERANDS
FLAGS
EU
59
Execution Unit
Main components are
Instruction Decoder
Control System
Arithmetic Logic Unit
General Purpose Registers
Flag Register
Pointer & Index registers
60
Instruction Decoder
Translates instructions fetched from memory
into a series of actions which EU carries out
Control System
Generates timing and control signals to
perform the internal operations of the
microprocessor
Arithmetic Logic Unit

EU has a 16-bit ALU which can ADD,
SUBTRACT, AND, OR, increment, decrement,
complement or shift binary numbers
61
General Purpose Registers

EU has 8 general
purpose registers
Can be individually
used for storing 8-bit
data
AL register is also
called Accumulator
Two registers can also
be combined to form
16-bit registers
The valid register pairs
are AX, BX, CX, DX
AH
AL
BH
BL
CH
CL
DH
DL
AH
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
62
Flag Register
8086 has a 16-bit flag register
Contains 9 active flags
There are two types of flags in 8086
Conditional flags six flags, set or reset
by EU on the basis of results of some
arithmetic operations
Control flags three flags, used to control
certain operations of the processor
63
Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF
1.
CF
CARRY FLAG
2.
PF
PARITY FLAG
3.
AF
AUXILIARY CARRY
4.
ZF
ZERO FLAG
5.
SF
SIGN FLAG
6.
OF
OVERFLOW FLAG
7.
TF
TRAP FLAG
8.
IF
INTERRUPT FLAG
9.
DF
DIRECTION FLAG
Conditional Flags
(Compatible with 8085,
except OF)
Control Flags
64
Flag Register
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the

lowest nibble, i.e, bit three during
addition, or borrow for the lowest
nibble,
i.e,
bit
three,
during
subtraction.
This flag is set, when there is

a carry out of MSB in case of
addition or a borrow in case
of subtraction.
Sign Flag
Zero Flag
Parity Flag
This flag is set, when the

result of any computation
is negative
This flag is set, if the result of

the computation or comparison
performed by an instruction is
zero
This flag is set to 1, if the lower

byte of the result contains even
number of 1s ; for odd number
of 1s set to zero.
15
14
13
12
11
10
OF
DF
IF
TF
SF
ZF
Over flow Flag
This flag is set, if an overflow occurs, i.e, if the result of a signed

operation is large enough to accommodate in a destination
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set.
Direction Flag
This is used by string manipulation instructions. If this flag bit

is 0, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto incrementing mode.
4
AF
2
PF
0
CF
Tarp Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize
external mask interrupts; clearing IF
disables these interrupts.
65
Registers, Flag
8086 registers
categorized
into 4 groups
Sl.No.
1
Type
General purpose
register
15
14
13
12
11
10
OF
DF
IF
TF
SF
ZF
Register width
4
AF
PF
CF
Name of register
16 bit
AX, BX, CX, DX
8 bit
AL, AH, BL, BH, CL, CH, DL, DH
Pointer register
16 bit
SP, BP
Index register
16 bit
SI, DI
Instruction Pointer
16 bit
IP
Segment register
16 bit
CS, DS, SS, ES
Flag (PSW)
16 bit
Flag register
66
Registers and Special Functions

Register
Name of the Register
Special Function
AX
16-bit Accumulator
Stores the 16-bit results of arithmetic and logic

operations
AL
8-bit Accumulator
Stores the 8-bit results of arithmetic and logic

operations
BX
Base register
Used to hold base value in base addressing mode

to access memory data
CX
Count Register
Used to hold the count value in SHIFT, ROTATE

and LOOP instructions
DX
Data Register
Used to hold data for multiplication and division

operations
SP
Stack Pointer
Used to hold the offset address of top stack

memory
BP
Base Pointer
Used to hold the base value in base addressing

using SS register to access data from stack
memory
SI
Source Index
Used to hold index value of source operand (data)

for string instructions
DI
Data Index
Used to hold the index value of destination

operand (data) for string operations
67
Bus Interface Unit

Main Components are
Instruction Queue
Segment Registers
Instruction Pointer
68
Memory
Interface
BIU
EXTRA SEGMENT (ES)

CODE SEGMENT (CS)
STACK SEGMENT (SS)

DATA SEGMENT (DS)
Instruction Queue
INSTRUCTION POINTER (IP)
Instruction
Decoder
AH
AL
BH
BL
CH
CL
DH
DL
ARITHMETIC
LOGIC UNIT
CONTROL
SYSTEM
STACK POINTER (SP)

BASE POINTER (BP)
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
OPERANDS
FLAGS
EU
69
Instruction Queue
8086 employs parallel processing
When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU
70
Pipelining
EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
So the presence of a queue in 8086
speeds up the processing
Fetching the next instruction while the
current instruction executes is called
pipelining
71
Memory Segmentation
8086 has a 20-bit address bus
So it can address a maximum of 1MB of
memory
8086 can work with only four 64KB segments
at a time within this 1MB range
These four memory segments are called
Code segment
Stack segment
Data segment
Extra segment
72
Memory
64KB Memory
Segment
00000H
2
3
4
4
Only 4 such segments can be

addressed at a time
5
6
7
8
9
10
1MB
Address
Range
11
12
13
14
15
16
FFFFFH
73
Code Segment
That part of memory from where BIU is
currently fetching instruction code bytes
Stack Segment
A section of memory set aside to store
addresses and data while a subprogram
executes
Data & Extra Segments

Used for storing data values to be used in
the program
74
Memory
Code Segment
00000H
2
3
4
Data & Extra

Segments
5
6
7
8
9
10
1MB
Address
Range
11
12
13
14
15
Stack Segment
16
FFFFFH
75
Segment Registers
hold the upper 16-bits of the starting
address for each of the segments
The four segment registers are
CS (Code Segment register)

DS (Data Segment register)
SS (Stack Segment register)
ES (Extra Segment register)
76
Memory
1
CS
1000 0H
00000H
Code Segment
3
4
DS
ES
4000 0H
5000 0H
Data Segment
Extra Segment
Starting Addresses
of Segments
7
8
9
10
1MB
Address
Range
11
12
13
14
15
SS
F000 0H
Stack Segment
FFFFFH
77
Address of a segment is of 20-bits

A segment register stores only upper 16bits
BIU always inserts zeros for the lowest 4bits of the 20-bit starting address.
E.g. if CS = 348AH, then the code
segment will start at 348A0H
A 64-KB segment can be located
anywhere in the memory, but will start at
an address with zeros in the lowest 4-bits
78
Instruction Pointer (IP) Register

a 16-bit register
Holds 16-bit offset, of the next instruction
byte in the code segment
BIU uses IP and CS registers to generate
the 20-bit address of the instruction to be
fetched from memory
79
Physical Address Calculation

Start of Code Segment
348A0H
00000H
Data
Segment
IP = 4214H
Code Byte
Memory
38AB4H
MOV AL, BL
Code
Segment
Extra
Segment
7
8
9
CS
IP
Physical Address
348A0 H
+ 4214 H
38AB4 H
1MB
Address
Range
10
11
12
13
14
15
Stack
Segment
80
FFFFFH
Stack Segment (SS) Register

Stack Pointer (SP) Register
Upper 16-bits of the starting address of
stack segment is stored in SS register
It is located in BIU
SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
It is located in EU
81
Other Pointer & Index Registers

Base Pointer (BP) register
Source Index (SI) register
Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data
word in one of the segments
82
ADDRESSING
MODES OF
8086
83
Various Addressing Modes

1.
2.
3.
4.
5.
6.
7.
8.
Immediate Addressing Mode

Register Addressing Mode
Direct Addressing Mode
Register Indirect Addressing Mode
Index Addressing Mode
Based Addressing Mode
Based & Indexed Addressing Mode
Based & Indexed with displacement Addressing
Mode
9. Strings Addressing Mode
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
84
1. IMMEDIATE ADDRESSING MODE

The instruction will specify the name
of the register which holds the data
to be operated by the instruction.
Source data is within the

instruction
Ex: MOV AX,10AB
AL=ABH, AH=10H
85
2.REGISTER ADDRESSING MODE

In immediate addressing mode, an
8-bit or 16-bit data is specified as
part of the instruction
Ex: MOV AX,BL

MOV AX,BL
86
3. DIRECT ADDRESSING MODE

Memory address is supplied with in
the instruction
Mnemonic: MOV AH,[MEMBDS]
AH
[1000H]
But the memory address is not
index or pointer register
87
4. REGISTER INDIRECT ADDRESSING MODE

Memory address is supplied in an index or
pointer register
EX:
MOV AX,[SI] ;
AL [SI] ; AH [SI+1]
JMP [DI] ;
IP
[DI+1: DI]
INC BYTE PTR [BP] ; [BP]
[BP]+1
DEC WORD PTR [BX] ;
[BX+1:BX]
[BX+1:BX]-1
88
5.Indexed Addressing Mode

Memory address is the sum of index
register plus displacement
MOV AX,[SI+2] AL [SI+2]; AH
JMP [DI+2]
IP [BX+3:BX+2]
[SI+3]
89
6. Based Addressing Mode

Memory address is the sum of the BX or BP
base register plus a displacement within
instruction
Ex:
MOV AX,[BP+2] AL [BP+2]; AH [BP+3]
JMP [BX+2]
IP [BX+3:BX+2]
90
7.BASED & INDEX ADDRESSING MODES

Memory address is the sum of the index register
& base register
Ex:
MOV AX,[BX+SI] ; AL [BX+SI] ; AH [BX+SI+1]
JMP [BX+DI] ;
IP
[BX+DI+1 : BX+DI]
INC BYTE PTR [BP+SI] ; [BP]
[BP]+1
DEC WORD PTR [BP+DI] ;
[BX+1:BX]
[BX+1:BX]-1
91
8. BASED & INDEXED WITH DISPLACEMENT ADDRESSING MODE

Memory address is the sum of an index register ,
base register and displacement within instruction
MOV AX,[BX+SI+6] ; AL
[BX+SI+6] ; AH
JMP [BX+DI+6] ;
IP
[BX+SI+7]
[BX+DI+7 : BX+DI+6]
INC BYTE PTR [BP+SI+5] ;

DEC WORD PTR [BP+DI+5] ;
92
9. Strings Addressing Mode

The memory source address is a register SI in the
data segment, and the memory destination
address is register DI in the extra segment
Ex: MOVSB
If DF=0 SI
DF=1 SI
[ES:DI]
SI+1
SI-1
[DS:SI]
, DI
, DI
DI+1
DI-1
93
INSTRUCTION
SET of 8086
94
Instruction set basics

Instruction:- An instruction is a binary pattern designed
inside a microprocessor to perform a specific function.
Opcode:- It stands for operational code. It specifies the type
of operation to be performed by CPU. It is the first field in
the machine language instruction format.
E.g. 08 is the opcode for instruction MOV X,Y.
Operand:- We can also say it as data on which operation
should act. operands may be register values or memory
values. The CPU executes the instructions using information
present in this field. It may be 8-bit data or 16-bit data.
95
Instruction set basics

Assembler:- it converts the instruction into sequence of
binary bits, so that this bits can be read by the processor.
Mnemonics:- these are the symbolic codes for either
instructions or commands to perform a particular
function.
E.g. MOV, ADD, SUB etc.
96
Types of instruction set of 8086

microprocessor
(1). Data Copy/Transfer instructions.
(2). Arithmetic & Logical instructions.
(3). Branch instructions.
(4). Loop instructions.
(5). Machine Control instructions.
(6). Flag Manipulation instructions.
(7). Shift & Rotate instructions.
(8). String instructions.
97
(1). Data copy/transfer instructions.

(1). MOV Destination, Source
There will be transfer of data from source to destination.

Source can be register, memory location or immediate
data.
Destination can be register or memory operand.
Both Source and Destination cannot be memory location
or segment registers at the same time.
E.g.
(1). MOV CX, 037A H;
(2). MOV AL, BL;
(3). MOV BX, [0301 H];
98
BEFORE
EXECUTION
AX
AFTER
EXECUTION
MOV BX,AX
2000H
BEFORE
EXECUTION
A
H
AL
B
H
BL
C
H
CL
D
H
DL
2000H
AFTER
EXECUTION
MOV CL,M
40
BX
A
H
AL
B
H
BL
C
H
CL 40
D
H
DL
40
99
Stack Pointer
It is a 16-bit register, contains the address of the data

item currently on top of the stack.
Stack operation includes pushing (providing) data on

to the stack and popping (taking)data from the stack.
Pushing operation decrements stack pointer and

Popping operation increments stack pointer. i.e.
there is a last in first out (LIFO) operation.
100
(2). Push Source

Source can be register, segment register or
memory.
This instruction pushes the contents of specified
source on to the stack.
In this stack pointer is decremented by 2.
The higher byte data is pushed first (SP-1).
Then lower byte data is pushed (SP-2).
E.g.:
(1). PUSH AX;
(2). PUSH DS;
(3). PUSH [5000H];
101
INITIAL POSITION
(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE
(2) STACK POINTER
HIGHER BYTE
DECREMENTS SP & STORES LOWER

BYTE
(3) STACK
POINTER
LOWER BYTE
HIGHER BYTE
102
BEFORE EXECUTION
SP
2002H
BH
BL
CH
10
DH
CL
50
DL
2000H
2001H
2002H
PUSH CX
AFTER EXECUTION
SP
2000H
BH
CH
DH
BL
10
CL
DL
2000H
50
2001H
10
50
2002H
103
(3) POP Destination

Destination can be register, segment register or
memory.
This instruction pops (takes) the contents of
specified destination.
In this stack pointer is incremented by 2.
The lower byte data is popped first (SP+1).
Then higher byte data is popped (SP+2).
E.g.
(1). POP AX;
(2). POP DS;
(3). POP [5000H];
104
(1) STACK
POINTER
INITIAL POSITION AND READS LOWER

BYTE
LOWER BYTE
INCREMENTS SP & READS HIGHER

BYTE
(2) STACK POINTER
LOWER BYTE
HIGHER BYTE
INCREMENTS SP
LOWER BYTE
HIGHER BYTE
(3) STACK
POINTER
105
BEFORE EXECUTION
SP 2000H
BH
BL
2000H 30
2001H 50
2002H
POP BX
AFTER EXECUTION
SP 2002H
2000H 30
2001H 50
BH 5
2002H
BL 30
106
(4). XCHG Destination, source;

This instruction exchanges contents of Source with
destination.
It cannot exchange two memory locations directly.
The contents of AL are exchanged with BL.
The contents of AH are exchanged with BH.
E.g.
(1). XCHG BX, AX;
(2). XCHG [5000H],AX;
107
BEFORE EXECUTION
AFTER EXECUTION
AH 20 AL 40
AH 70
AL 80
BH 70 BL 80
BH 20
BL 40
XCHG AX,BX
108
(5)IN AL/AX, 88-bit/16

bit/16--bit port address
It reads from the specified port address.
It copies data to accumulator from a port with 8bit or 16-bit address.
DX is the only register is allowed to carry port
address.
E.g.
(1). IN AL, 80H;
(2). IN AX,DX; //DX contains address of 16-bit
port.
109
BEFORE EXECUTION
PORT
80H
10
AL
IN AL,80H
AFTER EXECUTION
PORT
80H
10
AL 10
110
OUT 88-bit/16
bit/16--bit port address, AL/AX
It writes to the specified port address.
It copies contents of accumulator to the port
with 8-bit or 16-bit address.
DX is the only register is allowed to carry port
address.
E.g.
(1). OUT 80H,AL;
(2). OUT DX,AX; //DX contains address of 16-bit
port.
111
BEFORE EXECUTION
PORT
50H
10
AL 40
OUT 50H,AL
AFTER EXECUTION
PORT
50H
40
AL 40
112
(7) XLAT
Also known as translate instruction.

It is used to find out codes in case of code conversion.
i.e. it translates code of the key pressed to the
corresponding 7-segment code.
After execution this instruction contents of AL register
always gets replaced.
E.g. XLAT;
113
8.LEA
8.
LEA 1616-bit register (source), address (dest.)
LEA Also known as Load Effective Address
(LEA).
It loads effective address formed by the
destination into the source register.
E.g.
(1). LEA BX,Address;
(2). LEA SI,Address[BX];
114
(9). LDS 16-bit register (source), address (dest.);

(10). LES 16-bit register (source), address (dest.);
LDS Also known as Load Data Segment (LDS).

LES Also known as Load Extra Segment (LES).
It loads the contents of DS (Data Segment) or ES
(Extra Segment) & contents of the destination to
the contents of source register.
E.g.
(1). LDS BX,5000H;
(2). LES BX,5000H;
115
(1). LDS BX,5000H;

(2). LES BX,5000H;
15
BX 20
10
7
0
10
5000H
20
DS/ES 40
30
5001H
30
5002H
40
5003H
116
(11). LAHF:- This instruction loads the AH register

from the contents of lower byte of the flag register.
This command is used to observe the status of the
all conditional flags of flag register.
E.g. LAHF;
(12). SAHF:- This instruction sets or resets all
conditional flags of flag register with respect to the
corresponding bit positions.
If bit position in AH is 1 then related flag is set
otherwise flag will be reset.
E.g. SAHF;
117
PUSH & POP

(13). PUSH F:- This instruction decrements the
stack pointer by 2.
It copies contents of flag register to the memory
location pointed by stack pointer.
E.g. PUSH F;
(14). POP F:- This instruction increments the stack
pointer by 2.
It copies contents of memory location pointed by
stack pointer to the flag register.
E.g. POP F;
118
(2). Arithmetic Instructions
These instructions perform the

operations like:
Addition,
Subtraction,
Increment,
Decrement.
119
(2). Arithmetic Instructions

(1). ADD destination, source;
This instruction adds the contents of source operand with

the contents of destination operand.
The source may be immediate data, memory location or
register.
The destination may be memory location or register.
The result is stored in destination operand.
AX is the default destination register.
E.g. (1). ADD AX,2020H;

(2). ADD AX,BX;
120
AFTER EXECUTION
BEFORE EXECUTION
AH
10
AL
10
ADD AX,2020H
AH 30
AL 30
1010
+2020
3030
BEFORE EXECUTION
AFTER EXECUTION
AH 10
AL 10
AH 30
AL 30
BH 20
BL
BH 20
BL 20
20
ADD AX,BX
121
ADC destination, source
This instruction adds the contents of source

operand with the contents of destination operand
with carry flag bit.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in destination operand.
AX is the default destination register.
E.g. (1). ADC AX,2020H;
(2). ADC AX,BX;
122
(3) INC source

This instruction increases the contents of source
operand by 1.
The source may be memory location or register.
The source can not be immediate data.
The result is stored in the same place.
E.g. (1). INC AX;

(2). INC [5000H];
123
BEFORE EXECUTION
AH 10
AL 10
INC AX
BEFORE EXECUTION
5000H
1010
AFTER EXECUTION
AH 10
AL 11
AFTER EXECUTION
INC [5000H]
5000H
1011
124
4. DEC source
This instruction decreases the contents of
source operand by 1.
The source may be memory location or register.
The source can not be immediate data.
The result is stored in the same place.
E.g. (1). DEC AX;

(2). DEC [5000H];
125
BEFORE EXECUTION
AH 10
AL 10
DEC AX
BEFORE EXECUTION
5000H
1010
AFTER EXECUTION
AH 10
AL 09
AFTER EXECUTION
DEC [5000H]
5000H
1009
126
(5) SUB destination, source;

This instruction subtracts the contents of source
operand from contents of destination.
register.
The result is stored in the destination place.
E.g. (1). SUB AX,1000H;

(2). SUB AX,BX;
127
BEFORE EXECUTION
AH 20
AL 00
AFTER EXECUTION
SUB AX,1000H
AH 10
AL 00
2000
-1000
=1000
BEFORE EXECUTION
AH 20
AL
00
BH 10
BL
00
AFTER EXECUTION
SUB AX,BX
AH 10
AL
00
BH 10
BL
00
128
(6). SBB destination, source;
Also known as Subtract with Borrow.

This instruction subtracts the contents of source
operand & borrow from contents of destination
operand.
register.
The result is stored in the destination place.
E.g. (1). SBB AX,1000H;
(2). SBB AX,BX;
129
BEFORE EXECUTION
B 1
AFTER EXECUTION
SBB AX,1000H
AH 10 AL 19
AH 20 AL 20
BEFORE EXECUTION
2020
- 1000
10201=1019
AFTER EXECUTION
B 1
AH
20
AL
20
BH
10
BL
10
SBB AX,BX
AH 10
AL 19
BH 10
BL
10
2050
130
(7). CMP destination, source
Also known as Compare.

This instruction compares the contents of source
operand with the contents of destination operands.
register.
Then resulting carry & zero flag will be set or reset.
E.g. (1). CMP AX,1000H;
(2). CMP AX,BX;
131
BEFORE EXECUTION
AH
10
AL
00
BH
10
BL
00
D=S: CY=0,Z=1
D>S: CY=0,Z=0
D<S: CY=1,Z=0
CMP AX,BX
BEFORE EXECUTION
AH
10
AL
00
BH
00
BL
10
CMP AX,BX
BEFORE EXECUTION
AH
10
AL
00
BH
20
BL
00
CMP AX,BX
AFTER EXECUTION
CY
AFTER EXECUTION
CY
AFTER EXECUTION
CY
1 Z
132
AAA (ASCII Adjust after Addition):

The data entered from the terminal is in ASCII format.
In ASCII, 0 9 are represented by 30H 39H.
This instruction allows us to add the ASCII codes.
This instruction does not have any operand.
Other ASCII Instructions:

AAS (ASCII Adjust after Subtraction)
AAM (ASCII Adjust after Multiplication)
AAD (ASCII Adjust Before Division)
133
DAA (Decimal Adjust after Addition)

It is used to make sure that the result of adding two BCD numbers is
adjusted to be a correct BCD number.
It only works on AL register.
DAS (Decimal Adjust after Subtraction)

It is used to make sure that the result of subtracting two BCD
numbers is adjusted to be a correct BCD number.
It only works on AL register.

134
MUL operand
Unsigned Multiplication.
Operand contents are positively signed.
Operand may be general purpose register or memory
location.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
E.g. (1). MUL BH
(2). MUL CX
// AX= AL*BH; // (+3) * (+4) = +12.

// AX=AX*CX;
135
IMUL operand
Signed Multiplication.
Operand contents are negatively signed.
Operand may be general purpose register, memory location
or index register.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
E.g. (1). IMUL BH
(2). IMUL CX
// AX= AL*BH;
// (-3) * (-4) = 12.
// AX=AX*CX;
136
DIV operand
Unsigned Division.
Operand may be register or memory.
Operand contents are positively signed.
Operand may be general purpose register or
memory location.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
E.g. MOV AX, 0203 // AX=0203
MOV BL, 04
IDIV BL
// BL=04
// AL=0203/04=50 (i.e. AL=50 & AH=03)
137
IDIV operand
Signed Division.
Operand may be register or memory.
Operand contents are negatively signed.
Operand may be general purpose register or
memory location.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
E.g. MOV AX, -0203
MOV BL, 04
DIV BL
AH=03)
// AX=-0203
// BL=04
// AL=-0203/04=-50 (i.e. AL=-50 &
138
Multiplication and Division Examples
139
140
141
142
LOGICAL (or) Bit Manipulation

Instructions
These instructions are used at the bit level.
These instructions can be used for:
Testing a zero bit
Set or reset a bit
Shift bits across registers
143
Bit Manipulation Instructions(LOGICAL Instructions)

AND
Especially used in clearing certain bits (masking)

xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
Examples:
AND BL, 0FH
OR
Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111

(Set the upper four bits)
144
XOR
Used in Inverting bits
xxxx xxxx XOR 0000 1111 = xxxxxxxx
-Example:
Clear bits 0 and 1, set bits 6 and 7, invert
bit 5 of register CL:
AND CL, FCH ;
OR CL, C0H ;
XOR CL, 20H ;
145
1111 1100B
1100 0000B
0010 0000B
SHL Instruction
The SHL (shift left) instruction performs a logical left shift
on the destination operand, filling the lowest bit with 0.
0
CF
mov dl,5d
shl dl,1
146
SHR Instruction
The SHR (shift right) instruction performs a logical right shift
on the destination operand. The highest bit position is filled

with a zero.
0
CF
MOV DL,80d
SHR DL,1
SHR DL,2
147
; DL = 40
; DL = 10
SAR Instruction
SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.
CF
An arithmetic shift preserves the number's sign.

MOV DL,-80
SAR DL,1
SAR DL,2
148
; DL = -40
; DL = -10
Shifting left n bits multiplies the operand by 2n

For example, 5 * 22 = 20
Shifting right n bits divides the operand by 2n
For example, 80 / 23 = 10
149
mov dl,5
Before:
00000101
=5
shl dl,1
After:
00001010
= 10
ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the Carry flag
and into the lowest bit

No bits are lost
CF
150
MOV Al,11110000b
ROL Al,1
; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4
; DL = F3h
ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry flag and
into the highest bit

No bits are lost
CF
151
MOV AL,11110000b
ROR AL,1
; AL = 01111000b
MOV DL,3Fh
ROR DL,4
; DL = F3h
RCL Instruction
RCL (rotate carry left) shifts each bit to the left
Copies the Carry flag to the least significant bit
Copies the most significant bit to the Carry flag
CF
CLC
MOV BL,88H
RCL BL,1
RCL BL,1
152
;
;
;
;
CF = 0
CF,BL = 0 10001000b
CF,BL = 1 00010000b
CF,BL = 0 00100001b
RCR Instruction
RCR (rotate carry right) shifts each bit to the right
Copies the Carry flag to the most significant bit
Copies the least significant bit to the Carry flag
CF
STC
MOV AH,10H
RCR AH,1
153
; CF = 1
; CF,AH = 00010000 1
; CF,AH = 10001000 0
Branching Instructions (or)

Program Execution Transfer
Instructions
These instructions cause change in the sequence of the execution
of instruction.
This change can be through a condition or sometimes
unconditional.
The conditions are represented by flags.
154
CALL Des:
This instruction is used to call a subroutine or function or
procedure.
The address of next instruction after CALL is saved onto stack.
RET:
It returns the control from procedure to calling program.
Every CALL instruction should have a RET.
155
SUBROUTINE & SUBROUTINE HANDILING INSTRUCTIONS

Main program
Subroutine A
First Instruction
Call subroutine A
Next instruction
Call subroutine A
Next instruction
156
Return
JMP Des:
This instruction is used for unconditional jump from one place to
another.
Jxx Des (Conditional Jump):

All the conditional jumps follow some conditional statements or any
instruction that affects the flag.
157
Conditional Jump Table

Mnemonic
158
Meaning
JA
Jump if Above
JAE
Jump if Above or Equal
JB
Jump if Below
JBE
Jump if Below or Equal
JC
Jump if Carry
JE
Jump if Equal
JNC
Jump if Not Carry
JNE
Jump if Not Equal
JNZ
Jump if Not Zero
JPE
Jump if Parity Even
JPO
Jump if Parity Odd
JZ
Jump if Zero
Loop Des:
This is a looping instruction.
The number of times looping is required is placed in the CX
register.
With each iteration, the contents of CX are decremented.

ZF is checked whether to loop again or not.
159
String Instructions
String in assembly language is just a sequentially stored bytes or
words.
There are very strong set of string instructions in 8086.

By using these string instructions, the size of the program is
considerably reduced.
160
CMPS Des, Src:

It compares the string bytes or words.
SCAS String:
It scans a string.
It compares the String with byte in AL or with word in
AX.
161
MOVS / MOVSB / MOVSW:

It causes moving of byte or word from one string to another.
In this instruction, the source string is in Data Segment and
destination string is in Extra Segment.
SI and DI store the offset values for source and destination index.
162
REP (Repeat):
This is an instruction prefix.
It causes the repetition of the instruction until CX becomes zero.
E.g.: REP MOVSB STR1, STR2
It copies byte by byte contents.
REP repeats the operation MOVSB until CX becomes zero.
163
Processor Control Instructions

These instructions control the processor itself.
8086 allows to control certain control flags that:
causes the processing in a certain direction
processor synchronization if more than one microprocessor
attached.
164
STC
It sets the carry flag to 1.
CLC
It clears the carry flag to 0.
CMC
It complements the carry flag.
165
STD:
It sets the direction flag to 1.
If it is set, string bytes are accessed from higher memory address to
lower memory address.
CLD:
It clears the direction flag to 0.
If it is reset, the string bytes are accessed from lower memory
address to higher memory address.
166
HLT instruction HALT processing
The HLT instruction will cause the 8086 to stop fetching and
executing instructions.
NOP instruction
this instruction simply takes up three clock cycles and does no

processing.
LOCK instruction
this is a prefix to an instruction. This prefix makes sure that during

execution of the instruction, control of system bus is not taken by other
microprocessor.
WAIT instruction
this instruction takes 8086 to an idle condition. The CPU
will not do any processing during this.
167
INSTRUCTION SET-summary
1.DATA TRANSFER INSTRUCTIONS
Mnemonic
Meaning
Format
Operation
Move
Mov D,S
(S) (D)
Exchange
XCHG D,S
(S)
Load Effective Address
LEA Reg16,EA
EA
pushes the operand into top of

stack.
PUSH BX
POP
pops the operand from top of

stack to Des.
POP BX
IN
transfers the operand from

specified port to accumulator
register.
IN AX,0028
OUT
transfers the operand from

accumulator to specified
port.
OUT 0028,BX
MOV
XCHG
LEA
PUSH
(D)
(Reg16)
168
2. ARITHMETIC INSTRUCTIONS
Mnemonic
SUB
Meaning
Subtract
Format
SUB D,S
Operation
(D) - (S)
Borrow
(D)
(CF)
(D) - (S) - (CF)
(D)
SBB
Subtract with
borrow
SBB D,S
DEC
Decrement by one
DEC D
NEG
Negate
NEG D
DAS
Decimal adjust for

subtraction
DAS
Convert the result in AL to packed

decimal format
AAS
ASCII adjust for

subtraction
AAS
(AL) difference (AH) dec by 1 if

borrow
ADD
Addition
ADD D,S
(S)+(D)
ADC
Add with carry
ADC D,S
(S)+(D)+(CF)
INC
Increment by one
INC D
(D)+1 (D)
AAA
ASCII adjust for

addition
AAA
If the sum is >9, AH
Decimal adjust for

addition
DAA
DAA
(D) - 1
(D)
(D)
(D)
carry (CF)
carry (CF)
is incremented by 1
Adjust AL for decimal Packed BCD
169
3. Bit Manipulation Instructions(Logical Instructions)

Mnemonic
Meaning
Format
Operation
AND
Logical AND
AND D,S
(S) (D) (D)
OR
Logical Inclusive OR
OR D,S
(S)+(D) (D)
XOR
Logical Exclusive OR
XOR D,S
(S) + (D)(D)
NOT
LOGICAL NOT
NOT D
(D) (D)
170
Shift & Rotate Instructions

Mnemonic
SAL/SHL
Meaning
Format
Shift arithmetic Left/

Shift Logical left
SAL/SHL D, Count
SHR
Shift logical right
SHR D, Count
SAR
Shift arithmetic
right
SAR D, Count
Mnemonic
Meaning
Format
ROL
ROR
Rotate Left
ROL D,Count
Rotate Right
ROR D,Count
RCL
Rotate Left through Carry
RCL D,Count
RCR
Rotate right through Carry
RCR D,Count
171
4. Branching or PROGRAM
EXECUTION TRANSFER INSTRUCTIONS
CALL - call a subroutine
RET - returns the control from procedure to calling
program
JMP Des Unconditional Jump

Jxx Des conditional Jump (ex: JC 8000)
Loop Des
172
5. STRING INSTRUCTIONS
CMPS Des, Src - compares the string bytes
SCAS String - scans a string
MOVS / MOVSB / MOVSW - moving of byte or
word
REP (Repeat) - repetition of the instruction
173
6. PROCESSOR CONTROL INSTRUCTIONS
STC set the carry flag (CF=1)

CLC clear the carry flag (CF=0)
STD set the direction flag (DF=1)
CLD clear the direction flag (DF=0)
HLT stop fetching & execution
NOP no operation(no processing)
LOCK - control of system bus is not taken by other P
WAIT - CPU will not do any processing
ESC - P does NOP or access a data from memory for coprocessor
174
Assembler
Directives
175
Directives Expansion
176
ASSUME Directive - The ASSUME directive is

used to tell the assembler that the name of
the logical segment should be used for a
specified segment.
DB(define byte) - DB directive is used to
declare a byte type variable or to store a byte
in memory location.
DW(define word) - The DW directive is used
to define a variable of type word or to reserve
storage location of type word in memory.
177
DD(define double word) :This directive is used

to declare a variable of type double word or
restore memory locations which can be
accessed as type double word.
DQ (define quadword) :This directive is used
to tell the assembler to declare a variable 4
words in length or to reserve 4 words of
storage in memory .
DT (define ten bytes):It is used to inform the
assembler to define a variable which is 10
bytes in length or to reserve 10 bytes of
storage in memory.
178
END- End program .This directive indicates the

assembler that this is the end of the program
module. The assembler ignores any
statements after an END directive.
ENDP- End procedure: It indicates the end of
the procedure (subroutine) to the assembler.
ENDS-End Segment: This directive is used with
the name of the segment to indicate the end
of that logical segment.
EQU - This EQU directive is used to give a
name to some value or to a symbol.
179
PROC - The PROC directive is used to identify

the start of a procedure.
PTR -This PTR operator is used to assign a
specific type of a variable or to a label.
ORG -Originate : The ORG statement
changes the starting offset address of the
data.
180
Directives examples
ASSUME CS:CODE cs=> code segment

ORG 3000
NAME DB THOMAS
POINTER DD 12341234H
FACTOR EQU 03H
181
Assembly Language
Programming(ALP)
8086
182
Program 1: Increment an 8-bit number

MOV AL, 05H
INC AL
Move 8-bit data to AL.

Increment AL.
Program 2: Increment an 16-bit number

MOV AX, 0005H
INC AX
Move 16-bit data to AX.

Increment AX.
183
Program 3: Decrement an 8-bit number

MOV AL, 05H
DEC AL

Decrement AL.
Program 4: Decrement an 16-bit number

MOV AX, 0005H
DEC AX

Decrement AX.
184
Program 5: 1s complement of an 8-bit number.

MOV AL, 05H
NOT AL

Complement AL.
Program 6: 1s complement of a 16-bit

number.
MOV AX, 0005H
NOT AX

Complement AX.
185
MOV AL, 05H

NOT AL
INC AL

Complement AL.
Increment AL

number.
MOV AX, 0005H
NOT AX
INC AX

Complement AX.
Increment AX
186
MOV AL, 05H

NOT AL
INC AL

Complement AL.
Increment AL

number.
MOV AX, 0005H
NOT AX
INC AX

Complement AX.
Increment AX
187
Program 9: Add two 8-bit numbers

MOV AL, 05H
MOV BL, 03H
ADD AL, BL
Move 1st 8-bit number to AL.

Move 2nd 8-bit number to BL.
Add BL with AL.
Program 10: Add two 16-bit numbers

MOV AX, 0005H
MOV BX, 0003H
ADD AX, BX
Move 1st 16-bit number to AX.

Move 2nd 16-bit number to BX.
Add BX with AX.
188
Program 11: subtract two 8-bit numbers

MOV AL, 05H
MOV BL, 03H
SUB AL, BL

subtract BL from AL.
Program 12: subtract two 16-bit numbers

MOV AX, 0005H
MOV BX, 0003H
SUB AX, BX
Move 1st 16-bit number to AX.

Move 2nd 16-bit number to BX.
subtract BX from AX.
189
Program 13: Multiply two 8-bit unsigned

numbers.
MOV AL, 04H

MOV BL, 02H
MUL BL

Multiply BL with AL and the result will
be in AX.
Program 14: Multiply two 8-bit signed

numbers.
MOV AL, 04H
MOV BL, 02H
IMUL BL

Multiply BL with AL and the result will
be in AX.
190
Program 15: Multiply two 16-bit unsigned

numbers.
MOV AX, 0004H

MOV BX, 0002H
MUL BX

Multiply BX with AX and the result will
be in DX:AX {4*2=0008=> 08=> AX , 00=> DX}
Program 16: Divide two 16-bit unsigned

numbers.
MOV AX, 0004H
MOV BX, 0002H
DIV BX
Divide BX from AX and the result will be in AX & DX
{4/2=0002=> 02=> AX ,00=>DX}
(ie: Quotient => AX , Reminder => DX )
191
Detailed coding
16 BIT ADDITION
192
Detailed coding
16 BIT SUBTRACTION
193
16 BIT MULTIPLICATION
194
16 BIT DIVISION
195
SUM of N numbers
L1:
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005
MOV DX,0000
ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
5 NUMBERS TO BE TAKEN SUM
196
Average of N numbers
L1:
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005
MOV DX,0000
ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
DIV CX
MOV [1200],AX
HLT
5 NUMBERS TO BE TAKEN AVERAGE
AX=AX/5(AVERAGE OF 5 NUMBERS)
197
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,
Erode
FACTORIAL of N
L1:
MOV CX,0005 5 Factorial=5*4*3*2*1=120

MOV DX,0000
MOV AX,0001
MUL CX
DEC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
198
ASCENDING ORDER
199
200
DECENDING ORDER
Note: change the coding
JNB L1 into JB L1
in the LINE 10
201
LARGEST, smallest NUMBER IN AN

ARRAY
202
LARGEST NUMBER
203
SMALLEST NUMBER
204
Modular
Programming
205
Generally , industry-programming projects consist

of thousands of lines of instructions or operation
code.
The size of the modules are reduced to a humanly
comprehensible and manageable level.
Program is composed from several smaller
modules. Modules could be developed by
separate teams concurrently.OBJ modules
(Object modules).
The .OBJ modules so produced are combined
using a LINK program.
Modular programming techniques simplify the
software development process
206
CHARACTERISTICS of module:
1. Each module is independent of other modules.
2. Each module has one input and one output.
3. A module is small in size.
4. Programming a single function per module is a goal
Advantages of Modular Programming:
It is easy to write, test and debug a module.
Code can be reused.
The programmer can divide tasks.
Re-usable Modules can be re-used within a program
DRAWBACKS:
Modular programming requires extra time and memory
207
MODULAR PROGRAMMING:
1.LINKING & RELOCATION
2.STACKS
3.Procedures
4.Interrupts & Interrupt Routines
5.Macros
208
LINKING &
RELOCATION
209
LINKER
A linker is a program used to join together several
object files into one large object file.
The linker produces a link file which contains the
binary codes for all the combined modules.
The linker program is invoked using the following
options.
C> LINK
or
C>LINK MS.OBJ
210
The loader is a part of the operating system

and places codes into the memory after
reading the .exe file
A program called locator reallocates the
linked file and creates a file for permanent
location of codes in a standard format.
211
Creation and execution of a program
212
Loader
->Loader is a utility program which takes object code as
input prepares it for execution and loads the
executable code into the memory .
->Loader is actually responsible for initializing the
process of execution.
Functions of loaders:
1.It allocates the space for program in the memory(Allocation)

2.It resolves the code between the object modules(Linking)
3. some address dependent locations in the program, address constants
must be adjusted according to allocated space(Relocation)
4. It also places all the machine instructions and data of corresponding
programs and subroutines into the memory .(Loading)
213
Relocating loader (BSS Loader)

When a single subroutine is changed then all
the subroutine needs to be reassembled.
The binary symbolic subroutine (BSS) loader
used in IBM 7094 machine is relocating loader.
In BSS loader there are many procedure
segments
The assembler reads one sourced program
and assembles each procedure segment
independently
214
The output of the relocating loader is the object program

The assembler takes the source program as input; this source
program may call some external routines.
SEGMENT COMBINATION:
ASM-86 assembler regulating the way segments with the
same name are concatenated & sometimes they are overlaid.
Form of segment directive:
Segment name
SEGEMENT
Combine-type
Possible combine-type are:
PUBLIC
COMMON
STACK
AT
MEMORY
215
Procedures
216
Procedure is a part of code that can be called from

your program in order to make some specific task.
Procedures make program more structural and
easier to understand.
syntax for procedure declaration:
name PROC
. ; here goes the code
. ; of the procedure ...
RET
name ENDP
here PROC is the procedure name.(used in top & bottom)
RET - used to return from OS. CALL-call a procedure
PROC & ENDP complier directives
CALL & RET - instructions
217
EXAMPLE 1 (call a procedure)

ORG 100h
CALL m1
MOV AX, 2
RET ;
return to operating system.
m1 PROC
MOV BX, 5
RET ;
return to caller.
m1 ENDP
END
The above example calls procedure m1, does MOV BX, 5 &
returns to the next instruction after CALL: MOV AX, 2.
218
Example 2 : several ways to pass

parameters to procedure
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2
CALL m2
CALL m2
CALL m2
RET
m2 PROC
MUL BL
RET
m2 ENDP
END
; return to operating system.
; AX = AL * BL.
; return to caller.
value of AL register is update every time the
procedure is called.
final result in AX register is 16 (or 10h) 219
220
Stack is an area of memory for keeping

temporary data.
STACK is used by CALL & RET instructions.
PUSH -stores 16 bit value in the stack.
POP -gets 16 bit value from the stack.
PUSH and POP instruction are especially useful
because we don't have too much registers to operate
1. Store original value of the register in stack (using
PUSH).
2. Use the register for any purpose.
3. Restore the original value of the register from stack
(using POP).
221
Example-1 (store value in STACK using

PUSH & POP)
ORG 100h
MOV AX, 1234h
PUSH AX
; store value of AX in stack.
MOV AX, 5678h
; modify the AX value.
POP AX
; restore the original value of AX.
RET
END
222
Example 2: use of the stack is for

exchanging the values
ORG 100h
MOV AX, 1212h
; store 1212h in AX.
MOV BX, 3434h
; store 3434h in BX
PUSH AX
; store value of AX in stack.
PUSH BX
; store value of BX in stack.
POP AX
; set AX to original value of BX.
POP BX
; set BX to original value of AX.
RET
END
push 1212h and then 3434h, on pop we will
first get 3434h and only after it 1212h 223
MACROS
224
Macros are just like procedures, but not really.

Macros exist only until your code is compiled
After compilation all macros are replaced with
real instructions
several macros to make coding easier(Reduce
large & complex programs)
Example (Macro definition)
name MACRO [parameters,...]
<instructions>
ENDM
225
Example1 : Macro Definitions

SAVE
MACRO
PUSH AX
PUSH BX
PUSH CX
ENDM
RETREIVE
MACRO
POP CX
POP BX
POP AX
ENDM
definition of MACRO name SAVE
Another definition of MACRO name RETREIVE
226
227
MACROS with Parameters

Example:
COPY MACRO x, y
; macro named
COPY with
2 parameters{x, y}
PUSH AX
MOV AX, x
MOV y, AX
POP AX
ENDM
228
INTERRUPTS
&
INTERRUPT SERVICE
ROUTINE(ISR)
229
INTERRUPT & ISR ?

Interrupts is to break the sequence of
operation.
While the CPU is executing a program, on
interrupt breaks the normal sequence of
execution of instructions, diverts its execution
to some other program called Interrupt
Service Routine (ISR)
230
231
232
233
Maskable Interrupt: An Interrupt that can be

disabled or ignored by the instructions of CPU
are called as Maskable Interrupt.
Non- Maskable Interrupt: An interrupt that
cannot be disabled or ignored by the instructions
of CPU are called as Non- Maskable Interrupt.
Software interrupts are machine instructions
that amount to a call to the designated interrupt
subroutine, usually identified by interrupt
number. Ex: INT0 - INT255
234
235
236
237
238
239
INTERRUPT VECTOR TABLE
256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS
1. TYPE 0 TO TYPE 4 INTERRUPTSThese Are Used For Fixed Operations And Hence Are Called
Dedicated Interrupts
2. TYPE 5 TO TYPE 31 INTERRUPTS

Not Used By 8086,reserved For Higher Processors Like 80286
80386 Etc
3. TYPE 32 TO 255 INTERRUPTS

Available For User, called User Defined Interrupts These Can
Be H/W Interrupts And Activated Through Intr Line Or Can Be
240
S/W Interrupts.
Type 0 Divide Error Interrupt

Quotient is too large cant be fit in AL/AX or Divide By Zero
{AX/0=}
Type 1 Single Step Interrupt

used for executing the program in single step mode by setting Trap Flag
To Set Trap Flag PUSHF
MOV BP,SP
OR [BP+0],0100H;SET BIT8
POPF
Type 2 Non Maskable Interrupt

This Interrupt is used for executing ISR of NMI Pin (Positive Egde Signal). NMI
cant be masked by S/W
Type 3 Break Point Interrupt

used for providing BREAK POINTS in the program
Type 4 Over Flow Interrupt

used to handle any Overflow Error after signed arithmetic
241
PRIORITY OF INTERRUPTS
Interrupt Type
INT0, INT3-INT 255,

NMI(INT2)
INTR
SINGLE STEP
Priority
Highest
Lowest
242
Byte &
String
Manipulation
243
Move,
compare,
store,
load,
scan
Refer String Instructions in Instruction Set

Slide No: 160-163
244
Byte Manipulation
Example 1:
MOV AX,[1000]
MOV BX,[1002]
AND AX,BX
MOV [2000],AX
HLT
Example 2:
MOV AX,[1000]
MOV BX,[1002]
OR AX,BX
MOV [2000],AX
HLT
Example 3:
MOV AX,[1000]
MOV BX,[1002]
XOR AX,BX
MOV [2000],AX
HLT
Example 4:
MOV AX,[1000]
NOT AX
MOV [2000],AX
HLT
245
STRING MANIPULATION
1. Copying a string (MOV SB)
L1
MOV CX,0003
MOV SI,1000
MOV DI,2000
CLD
MOV SB
DEC CX
JNZ L1
HLT
copy 3 memory locations
decrement CX
246
2. Find & Replace
247
DEPARTMENTS: CSE,IT,ECE,ECE,MECH
Regulation : 2013
UNIT-2
8086 SYSTEM
BUS STRUCTURE
248
8086 signals or Pin Diagram
Refer UNIT-1 Slide No: 43-54
249
GND 1
40
0V=0,
AD14
reference
AD13
for all
AD12
voltages
AD11
AD10
AD9
AD8
AD7
INTEL
Time-multiplexed
8086
Address / Data Bus AD6
AD5
(bidirectional)
AD4
AD3
AD2
Hardware
interrupt requests AD1
AD0
(inputs)
NMI
INTR
2...5MHz,
1/3 duty cycle CLK
GND 20
21
(input)
Minmode operation
signals (MN/MX=1)
Timemultiplexed
Address Bus
/Status signals
(outputs)
Vcc
AD15 5V10%
A16/S3
Maxmode operation
A17/S4
signals (MN/MX=0)
A18/S5
A19/S6
___
BHE/S7
Control Operation Mode,
___ (HIGH)
MN/MX
Bus
___
(input):
RD
(in,out)
___ ____
1 = minmode
HOLD (RQ/GT0)
___ ____
(8088 generates all
HLDA
(RQ/GT1)
___
______
the needed control
WR__
(LOCK)
__
signals for a small
IO/M
(S2)
__
__
Status
system),
DT/R
(S1)
____
__
signals
DEN
(S0)
(outputs)
0 = maxmode
ALE
(QS0)
_____
(8288 Bus
INTA
(QS1)
_____
Controller expands
TEST
Interrupt
the status signals to
READY
acknowledge
generate more
250
RESET
(output)
control signals)
MINIMUM MODE SIGNALS
251
MAXIMUM MODE SIGNALS
252
SYSTEM BUS
TIMING
253
System Timing Diagrams

T-State:
One clock period is referred to as a T-State
T-State
An operation takes an integer number of T-States
CPU Bus Cycle:

A bus cycle consists of 4 or more T-States
T1
T2
T3
T4
254
Memory Read Timing Diagrams

Dump address on address bus.
Issue a read ( RD ) and set M/ IO to 1.
Wait for memory access cycle.
255
Memory Write Timing Diagrams
Dump address on address bus.

Dump data on data bus.
Issue a write ( WR ) and set M/ IO to 1.
256
Bus Timing
During T 1 :
The address is placed on the Address/Data bus.
Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address
onto the address bus and set the direction of data transfer on data bus.
During T 2 :
8086 issues the RD or WR signal, DEN , and, for a write, the data.
DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
This cycle is provided to allow memory to access data.
READY is sampled at the end of T 2 .
If low, T 3 becomes a wait state.
Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
All bus signals are deactivated, in preparation for next bus cycle.
Data is sampled for reads, writes occur for writes.
257
Setup & Hold Time
Setup time The time before the rising edge of the clock, while the data
must be valid and constant
Hold time The time after the rising edge of the clock during which the data
must remain valid and constant
258
WAIT State
A wait state (Tw) is an extra clocking period, inserted

between T2 and T3, to lengthen the bus cycle, allowing
slower memory and I/O components to respond.
The READY input is sampled at the end of T2, and again,
if necessary in the middle of Tw. If READY is 0 then a
Tw is inserted.
259
Basic
configurations
260
BASIC CONFIGURATIONS1.Minimum Mode 2.Maximum Mode

Minimum mode(MN/MX=Vcc)
Pin #33 (MN/MX) connect to +5V

Pin 24-31 are used as memory and I/O control signal
The control signals are generated internally by the 8086/88
More cost-efficient
Maximum mode(MN/MX=GND)
Pin #33 (MN/MX) connect to Ground
Some control signals are generated externally by the 8288
bus controller chip
Max mode is used when math processor is used.
261
Minimum Mode 8086 System

8086 is operated in minimum mode by
MN/MX pin to logic 1 ( Vcc ).
In this mode, all the control signals are given
out by the microprocessor chip itself.
262
263
Explain Minimum mode Signals also: Refer Slide No 47-54
264
265
266
MAXIMUM MODE
267
Explain Maximum mode Signals also: Refer Slide No 47-54
8288 BUS CONTROLLER
268
269
270
MULTIPROCESSOR
CONFIGURATIONS
271
Coprocessor 8087
Multiprocessor
configuration
272
Multiprocessor configuration
Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.
Maximum mode of 8086 is designed to implement 3
basic multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)
273
Coprocessors and Closely coupled configurations are

similar in that both the 8086 and the external processor
shares the:
- Memory
- I/O system
- Bus & bus control logic
- Clock generator
274
Co-processor Intel 8087
8087
instructions
are inserted
in the 8086
program
8086 and 8087 reads

instruction bytes and
puts them in the
respective queues
NOP
8087 instructions have
11011 as the MSB of
their first code byte
275
Coprocessor / Closely Coupled

Configuration
276
TEST pin of 8086

Used in conjunction with the WAIT instruction in
multiprocessing environments.
This is input from the 8087 coprocessor.
During execution of a wait instruction, the CPU checks this
signal.
If it is low, execution of the signal will continue; if not, it
will stop executing.
277
1.Coprocessor Execution Example

Coprocessor cannot take control of the bus, it does everything through the CPU
278
2.Closely Coupled Execution Example
Closely Coupled
processor may take
control of the bus
independently.
Two 8086s cannot
be closely coupled.
279
3.Loosely Coupled Configuration

has shared system bus, system memory, and system
I/O.
each processor has its own clock as well as its own
memory (in addition to access to the system resources).
Used for medium to large multiprocessor systems.
Each module is capable of being the bus master.
Any module could be a processor capable of being a bus
master, a coprocessor configuration or a closely coupled
configuration.
280
281
Loosely Coupled Configuration

No direct connections between the modules.
Each share the system bus and communicate through
shared resources.
Processor in their separate modules can simultaneously
access their private subsystems through their local
busses, and perform their local data references and
instruction fetches independently. This results in
improved degree of concurrent processing.
Excellent for real time applications, as separate modules
can be assigned specialized tasks
282
Advantages of Multiprocessor
Configuration
1. High system throughput can be achieved by having more than
one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and normally resides on

a separate PC board. One can be added or removed without affecting the
others in the system.
3. A failure in one module normally does not affect the breakdown

of the entire system and the faulty module can be easily
detected and replaced
4. Each bus master has its own local bus to access dedicated
memory or IO devices. So a greater degree of parallel processing
can be achieved.
283
INTRODUCTION
TO ADVANCED
PROCESSORS
284
Intel family of microprocessor, bus and memory sizes

Microproces
sor
80186
Data bus
width
16
Address bus Memory size

width
20
1M
80286
16
24
16M
80386 DX
32
32
4G
80486
32
32
4G
Pentium 4 &
core 2
64
40
1T
285
80186
286
80286
287
80386
288
TEXT BOOK References

Main Book:
1. Microprocessors and Interfacing, Programming and Hardware by Doughlas
V.Hall
Other Authors:
2. Microcomputer Systems: The 8086 / 8088 Family -Architecture,
Programming and Design by Yu-Cheng Liu, Glenn A.Gibson
3. INTEL Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486,
Pentium, Prentium ProProcessor, Pentium II, III, 4 by Barry B. Bery
4. Advanced microprocessor and peripherals by A K RAY
5. 8085 Microprocessor - Ramesh Gaonkar (MP history, Basics)
LOCAL AUTHOR:
6.8086 Microprocessor by Nagoor Kani
289
Documents References
8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON
( PROFESSOR AND DEAN(ACADEMIC),VCET,Erode)
I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR and
DEAN(SA),VCET,Erode
8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of
Physics,Maharajas College ,Ernakulam
8086 architecture By Er. Swapnil Kaware
8086 presentations by Gursharan Singh Tatla (Eazynotes.com)
Microprocessor - Ramesh Gaonkar
8086 micro processor prasadpawaskar
8086 class notes-Y.N.M by MURTHY Y.N
Introduction to 8086 Microprocessor by Rajvir Singh
8086 micro processor by Poojith Chowdhary
8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar
Intel microprocessor history by Ramzi_Alqrainy
290
Website References
http://80864beginner.com/
www.eazynotes.com
www.slideshare.net
www.scribd.com
www.docstoc.com
www.slideworld.com
www.nptel.ac.in
http://opencourses.emu.edu.tr/
http://engineeringppt.blogspot.in/
http://www.pptsearchengine.net/
www.4shared.com
http://8085projects.info/
291
NPTEL Lecture Materials References

Microprocessor and Peripheral Devices by Dr.
Pramod Agarwal , IIT Roorkee
Link: http://nptel.ac.in/courses/108107029/
Microprocessors and Microcontrollers by Prof.
Krishna Kumar IISc Bangalore
link: http://nptel.ac.in/courses/106108100/
292
EC6504 Microprocessors and Microcontrollers

Dept: CSE,IT,ECE,MECH Regulation : 2013
UNIT-3
UNITI/O
INTERFACING
Presented by
C.GOKUL,AP/EEE
293
Data Transfers
Synchronous ----- Usually occur when

peripherals are located within the same
computer as the CPU. Close proximity
allows all state bits change at same
time on a common clock.
Asynchronous ----- Do not require that
the source and destination use the
same system clock.
294
295
MEMORY DEVICES
I/O DEVICES
296
interface memory (RAM, ROM, EPROM'...)

or I/O devices to 8086 microprocessor.
Several memory chips or I/O devices can
connected to a microprocessor. An address
decoding circuit is used to select the
required I/O device or a memory chip.
IO mapped IO V/s Memory Mapped

IO
Memory Mapped IO
IO is treated as memory.
16-bit addressing.
More Decoder Hardware.
Can address 216=64k
locations.
Less memory is available.
IO Mapped IO
IO is treated IO.
8- bit addressing.
Less Decoder
Hardware.
Can address 28=256
locations.
Whole memory address
space is available.
297
298
Memory Mapped IO
Memory Instructions are

used.
Memory control signals
are used.
Arithmetic and logic
operations can be
performed on data.
Data transfer b/w register
and IO.
IO Mapped IO
Special Instructions are
used like IN, OUT.
Special control signals
are used.
Arithmetic and logic
operations can not be
performed on data.
Data transfer b/w
accumulator and IO.
299
Parallel communication
interface
INTEL 8255
300
8255 PPI
The 8255 chip is also called as Programmable

Peripheral Interface.
The Intels 8255 is designed for use with Intels
8-bit, 16-bit and higher capability
microprocessors
The 8255 is a 40 pin integrated circuit (IC),
designed to perform a variety of interface
functions in a computer environment.
It is flexible and economical.
PIN DIAGRAM OF 8255
301
Signals of 8085
302
8255 PIO/PPI
It has 24 input/output lines which may be

individually programmed.
2 groups of I/O pins are named as
Group A (Port-A & Port C Upper)
Group B (Port-B & Port C Lower)
3 ports(each port has 8 bit)
Port A lines are identified by symbols PA0-PA7
Port B lines are identified by symbols PB0-PB7
Port C lines are identified by PC0-PC7 , PC3-PC0
ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)
303
D0 - D7: data input/output lines for the
device. All information read from and

written to the 8255 occurs via these 8 data
lines.
CS (Chip Select). If this line is a logical 0, the

microprocessor can read and write to the
8255.
RESET : The 8255 is placed into its reset
state if this input line is a logical 1
304
RD : This is the input line driven by the

microprocessor and should be low to
indicate read operation to 8255.
WR : This is an input line driven by the
microprocessor. A low on this line
indicates write operation.
A1-A0 : These are the address input lines
and are driven by the microprocessor.
305
306
Control Logic
CS signal is the master Chip Select

A0 and A1 specify one of the two I/O Ports
CS
A1
A0
Selected
0
0
0
0
0
0
1
1
0
1
0
1
Port A
Port B
Port C
Control
Register
8255 is not
selected
Block Diagram of 8255A
307
Block Diagram of 8255

(Architecture)
It has a 40 pins of 4 parts.
1. Data bus buffer
2. Read/Write control logic
3. Group A and Group B controls
4. Port A, B and C
308
309
1. Data bus buffer
This is a tristate bidirectional buffer used

to interface the 8255 to system data bus.
Data is transmitted or received by the
buffer on execution of input or output
instruction by the CPU.
310
2. Read/Write control logic
This unit accepts control signals ( RD, WR ) and

also inputs from address bus and issues
commands to individual group of control blocks
( Group A, Group B).
It has the following pins.
CS , RD , WR , RESET , A1 , A0
311
3. Group A and Group B controls
These block receive control from the CPU

and issues commands to their respective
ports.
Group A - PA and PCU ( PC7 PC4)
Group B PB and PCL ( PC3 PC0)
a) Port A: This has an 8 bit latched/buffered

O/P and 8 bit input latch. It can be
programmed in 3 modes mode 0, mode 1,
mode 2.
312
b) Port B: It can be programmed in mode 0,

mode1
c) Port C : It can be programmed in mode 0
313
314
Modes of Operation of 8255
Bit Set/Reset(BSR) Mode
Set/Reset bits in Port C
I/O Mode
Mode 0 (Simple input/output)

Mode 1 (Handshake mode)
Mode 2 (Bidirectional Data Transfer)
1. BSR Mode
315
B3
B2
B1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit/pin of port C
selected
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Concerned only with the 8-bits of Port C.

Set or Reset by control word
Ports A and B are not affected
316
2. I/O MODE
a) Mode 0 (Simple Input or Output):
Ports A and B are used as Simple I/O

Ports
Port C as two 4-bit ports
Features
Outputs are latched

Inputs are not latched
Ports do not have handshake or
interrupt capability
317
318
b) Mode 1: (Input or Output with

Handshake)
Handshake signals are exchanged

between MPU & Peripherals
Features
Ports A and B are used as Simple I/O Ports

Each port uses 3 lines from Port C as
handshake signals
Input & Output data are latched
interrupt logic supported
319
320
c) Mode 2: Bidirectional Data Transfer
Used primarily in applications such as data

transfer between two computers
Features
Ports A can be configured as the bidirectional

Port
Port B in Mode 0 or Mode 1.
Port A uses 5 Signals from Port C as handshake
signals for data transfer
Remaining 3 Signals from Port C Used as
Simple I/O or handshake for Port B
Write a program to initialize 8255 in the configuration

below.(assume address of the CW register as 23H).
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input
Solution:
1
Program:
MVI A,AEH ; LOAD CONTROL WORD
OUT 23H
; SEND CONTROL WORD
= AEH
321
322
Port A: Output, Port B: Output,

Port CU: Output, Port CL: Output
Solution:
1
= 80H
The control word register for the above ports of Intel

8255 is 80H.
323
Port A: Input, Port B: Input,

Port CU: Input, Port CL: Input
Solution:
1
= 9BH
The control word register for the above ports of intel

8255 is 9BH.
Basics of serial communication

1. Transmitter:
- A parallel-in, serial-out
shift register
Receiver:
- A serial-in, parallel-out
shift register.
2.
324
Parallel Transfer
TRANSMITTER
Receiver
325
Serial communication
interface
INTEL 8251 USART
326
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
(USART)
Programmable chip designed for

synchronous and asynchronous serial data
transmission
28 pin DIP
Coverts the parallel data into a serial stream
of bits suitable for serial transmission.
Receives a serial stream of bits and convert
it into parallel data bytes to be read by a
microprocessor.
327
328
BLOCK DIAGRAM
329
Five Sections
Read/Write Control Logic

Interfaces the chip with MPU
Determine the functions according to the control word
Monitors data flow
Transmitter
Converts parallel word received from MPU into serial bits
Transmits serial bits over TXD line to a peripheral.
Receiver
Receives serial bits from peripheral
Converts serial bits into parallel word
Transfers the parallel word to the MPU
Data Bus Buffer- 8 bit Bidirectional bus.
Modem Controller
Used to establish data communication modems over
telephone line
330
Input Signals
CS Chip Select
When this signal goes low, 8251 is selected by

MPU for communication
C/D Control/Data
When this signal is high, the control register

or status register is addressed
When it is low, the data buffer is addressed
Control and Status register is differentiated by
WR and RD signals, respectively
331
332
WR Write
RD Read
writes in the control register or sends outputs to the

data buffer.
This connected to IOW or MEMW
Either reads a status from status register or accepts
data from the data buffer
This is connected to either IOR or MEMR
RESET - Reset
CLK - Clock
Connected to system clock

Necessary for communication with microprocessor.
333
CS C/D RD WR
0
Function
MPU writes instruction in the
control register
MPU reads status from the status
register
MPU outputs the data to the Data
Buffer
MPU accepts data from the Data
Buffer
USART is not Selected
334
Control Register
16-bit register
This register can be accessed an output port
when the C/D pin is high
Status Register
Checks ready status of a peripheral
Data Buffer
Transmitter Section
Accepts parallel data and converts it into

serial data
Two registers
Buffer Register
Output Register
To hold eight bits

Converts eight bits into a stream of serial bits
Transmits data on TxD pin with appropriate

framing bits(Start and Stop)
335
Signals Associated with Transmitter

Section
TxD Transmit Data

Serial bits are transmitted on this line
TxC Transmitter Clock
Controls the rate at which bits are transmitted
TxRDY Transmitter Ready
Can be used either to interrupt the MPU or
indicate the status
TxE Transmitter Empty
Logic 1 on this line indicate that the output
register is empty
336
Receiver Section
Accepts serial data from peripheral and

converts it into parallel data
The section has two registers
Input Register
Buffer Register
337
Signals Associated with Receiver

Section
RxD Receive Data
Bits are received serially on this line and

converted into parallel byte in the receiver input
RxC Receiver Clock

RxRDY Receiver Ready
It goes high when the USART has a character in

the buffer register and is ready to transfer it to
the MPU
338
Signals Associated with Modem

Control
DSR- Data Set Ready
DTR Data Terminal Ready
device is ready to accept data when the 8251 is

communicating with a modem.
RTS Request to send Data
Normally used to check if the Data Set is ready when

communicating with a modem
the receiver is ready to receive a data byte from

modem
CTS Clear to Send
339
Control words
340
341
342
343
344
Interfacing of 8255(PPI) with 8085 processor:
345
346
11347
Programming 8251
8251 mode register
Number of
Stop bits
00: invalid
01: 1 bit
10: 1.5 bits
11: 2 bits
Parity enable
0: disable
1: enable
Parity
0: odd
1: even
Character length
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
Mode register
Baud Rate
00: Syn. Mode
01: x1 clock
10: x16 clock
11: x64 clock
11348
8251 command register

EH
IR
RTS
ER
SBRK RxE
DTR
TxE
command register
TxE: transmit enable

DTR: data terminal ready, DTR pin will be low
RxE: receiver enable
SBPRK: send break character, TxD pin will be low
ER:
error reset
RTS: request to send, CTS pin will be low
IR:
internal reset
EH:
enter hunt mode (1=enable search for SYN character)
11349
8251 status register

DSR
SYNDET
FE
OE
TxRDY:
RxRDY:
TxEMPTY:
PE:
OE:
FE:
SYNDET:
DSR:
PE
TxEMPTY
RxRDY
TxRDY
transmit ready
receiver ready
transmitter empty
parity error
overrun error
framing error
sync. character detected
data set ready
status
register
350
351
The analog to digital converter chips 0808

and 0809 are 8-bit CMOS,successive
approximation converters.
Successive approximation technique is one
of the fast techniques for analog to digital
conversion. The conversion delay is 100 s
at a clock frequency of 640 kHz.
352
353
354
355
356
357
The digital to analog converters convert

binary numbers into their analog equivalent
voltages or currents.
Techniques are employed for digital to analog
conversion.
i. Weighted resistor network
ii. R-2R ladder network
iii. Current output D/A converter
358
The DAC find applications in areas like digitally controlled

gains, motor speed control, programmable gain amplifiers,
digital voltmeters, panel meters, etc.
In a compact disk audio player for example a 14 or16-bit
D/A converter is used to convert the binary data read off
the disk by a laser to an analog audio signal.
Characteristics :
1. Resolution: It is a change in analog output for one LSB
change in digital input.
It is given by(1/2^n )*Vref. If n=8 (i.e.8-bit DAC)
1/256*5V=39.06mV
2. Settling time: It is the time required for the DAC to settle
for a full scale code change.
359
DAC 0800 8-bit Digital to Analog converter
Features:
i. DAC0800 is a monolithic 8-bit DAC manufactured by
National semiconductor.
ii. It has settling time around 100ms
iii. It can operate on a range of power supply voltage i.e.
from 4.5V to +18V. Usually the supply V+ is 5V or +12V.
The V- pin can be kept at a minimum of -12V.
iv. Resolution of the DAC is 39.06mV
360
361
362
TIMER/COUNTER
363
RD: read signal

WR: write signal
CS: chip select signal
A0, A1: address lines
Clock :This is the clock input for the counter.
The counter is 16 bits.
Out :This single output line is the signal that
is the final programmed output of the device.
Gate :This input can act as a gate for the
clock input line, or it can act as a start pulse,
364
365
366
8254 Programming
11-367
8254 Modes
Gate is low the
count will be
paused
Mode 0: An events counter enabled with G.
Gate is high
Will continue
counting
Mode 1: One-shot mode. s Counter will be reloaded

After gate high.
Gate is
High output
will be high
368
Mode 2: Counter generates a series of pulses 1 clock

pulse wide
cycle is repeated until

reprogrammed or G pin
set to 0
Mode 3: Generates a continuous square-wave with G set to 1
If count is even, 50% duty cycle

otherwise OUT is high 1 cycle
longer
369
Mode 4: Software triggered one-shot.
In the last counting

Will be stop
(not repeated)
Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

In the last count
Out will be low
370
371
Keyboard/Display
Controller
INTEL 8279
372
The INTEL 8279 is specially developed

for interfacing keyboard and display devices
to 8085/8086 microprocessor based
system
373
Simultaneous keyboard and display

operations
Scanned keyboard mode
Scanned sensor mode
8-character keyboard FIFO
1 6-character display
374
375
Keyboard section
Display section
Scan section
CPU interface section
376
377
378
The keyboard section consists of 8 return

lines RL0 - RL7 that can be used to form the
columns of a keyboard matrix.
It has two additional input : shift and
control/strobe. The keys are automatically
debounced.
The two operating modes of keyboard
section are 2-key lockout and N-key rollover.
In the 2-key lockout mode, if two keys are

pressed simultaneously, only the first key is
recognized.
In the N-key rollover mode simultaneous
keys are recognized and their codes are
stored in FIFO.
The keyboard section also have an 8 x 8
FIFO (First In First Out) RAM.
The FIFO can store eight key codes in the scan
keyboard mode. The status of the shift key and
control key are also stored along with key code. The
8279 generate an interrupt signal (IRQ)when there
is an entry in FIFO.
379
380
The display section has eight output lines

divided into two groups A0-A3 and B0-B3.
The output lines can be used either as a
single group of eight lines or as two groups
of four lines, in conjunction with the scan
lines for a multiplexed display.
The output lines are connected to the
anodes through driver transistor in case of
common cathode 7-segment LEDs.
381
The cathodes are connected to scan lines

through driver transistors.
The display can be blanked by BD (low) line.
The display section consists of 16 x 8 display
RAM. The CPU can read from or write into
any location of the display RAM.
382
The scan section has a scan counter and four scan

lines, SL0 to SL3.
In decoded scan mode, the output of scan lines will
be similar to a 2-to-4 decoder.
In encoded scan mode, the output of scan lines
will be binary count, and so an external decoder
should be used to convert the binary count to
decoded output.
The scan lines are common for keyboard and
display.
383
The CPU interface section takes care of data

transfer between 8279 and the processor.
This section has eight bidirectional data
lines DB0 to DB7 for data transfer between
8279 and CPU.
It requires two internal address A =0 for
selecting data buffer and A = 1 for selecting
control register of8279.
384
The control signals WR (low), RD (low), CS

(low) and A0 are used for read/write to
8279.
It has an interrupt request line IRQ, for
interrupt driven data transfer with processor.
The 8279 require an internal clock
frequency of 100 kHz. This can be obtained
by dividing the input clock by an internal
prescaler.
385
All the command words or status words are written or

read with A0 = 1 and CS = 0 to or from 8279.
a) Keyboard Display Mode Set : The format of the command word to select different
modes of operation of 8279 is given below with its bit definitions.
D7
D6
D5
D4
D3
D2
D1
D0
386
SENSOR MATRIX
SENSOR MATRIX
387
B) Programmable clock :
The clock for operation of 8279 is obtained by

dividing the external clock input signal by a
programmable constant called prescaler.
PPPPP is a 5-bit binary constant.
The input frequency is divided by a decimal constant
ranging from 2 to 31, decided by the bits of an internal
prescaler, PPPPP.
D7
D6
D5
D4
D3
D2
D1
D0
c) Read
below.
FIFO / Sensor RAM : The format of this command is given 388

D7
D6
D5
D4
D3
D2
D1
D0
AI
AI Auto Increment Flag

AAA Address pointer to 8 bit FIFO RAM
X- Dont care
This word is written to set up 8279 for reading FIFO/ sensor RAM.
In scanned keyboard mode, AI and AAA bits are of no use. The
8279 will automatically drive data bus for each subsequent read, in
the same sequence, in which the data was entered.
In sensor matrix mode, the bits AAA select one of the 8 rows of
RAM.
If AI flag is set, each successive read will be from the subsequent
RAM location.
389
d) Read
Display RAM :
This command enables a programmer to read the display RAM data.

D7
D6
D5
D4
D3
D2
D1
D0
AI
The CPU writes this command word to 8279 to prepare it for

display RAM read operation.
AI is auto increment flag and AAAA, the 4-bit address points to
the 16-byte display RAM that is to be read.
If AI=1, the address will be automatically, incremented after
each read or write to the Display RAM.
The same address counter is used for reading and writing.
390
d) Write
Display RAM :
This command enables a programmer to write the display RAM data.

D7
D6
D5
D4
D3
D2
D1
D0
AI
AI Auto increment Flag.

AAAA 4 bit address for 16-bit display RAM to be
written.
e) Display Write Inhibit/Blanking :
D7
D6
D5
D4
D3
D2
D1
D0
IW
IW
BL
BL
IW - inhibit write flag

BL - blank display bit flags
391
g) Clear
Display RAM :
D7
D6
D5
D4
D3
D2
D1
D0
CD2
CD1
CD0
CF
CA
CD2
ENABLES CLEAR DISPLAY

WHEN CD2=1
CD1
CD0
0X - All zeros ( x dont care ) AB=00

10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
11 - All ones (AB =FF), i.e. clear RAM
CD2 must be 1 for enabling the clear display command.

If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly same
as above.
If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared and
IRQ line is pulled down and the sensor RAM pointer is set to row
0.
If CA=1, this combines the effect of CD and CF bits.
392
h) End
Interrupt / Error mode Set :

D7
D6
D5
D4
D3
D2
D1
D0
E- Error mode
X- dont care
For the sensor matrix mode, this command lowers the

IRQ line and enables further writing into the RAM.
Otherwise, if a change in sensor value is detected, IRQ
goes high that inhibits writing in the sensor RAM.
For N-Key roll over mode, if the E bit is programmed to
be 1, the 8279 operates in special Error mode
393
INTERRUPT
CONTROLLER
394
If we are working with an 8086, we have a

problem here because the 8086 has only
two interrupt inputs, NMI and INTR.
If we save NMI for a power failure interrupt,
this leaves only one interrupt for all the other
applications. For applications where we have
interrupts from multiple source, we use an
external device called a priority interrupt
controller ( PIC ) to the interrupt signals into
a single interrupt input on the processor.
395
396
Interrupt Request Register (RR): The

interrupts at IRQ input lines are handled by
Interrupt Request internally. IRR stores all
the interrupt request in it in order to serve
them one by one on the priority basis.
In-Service Register (ISR): This stores all the
interrupt requests those are being served,
i.e. ISR keeps a track of the requests being
served.
Priority Resolver : This unit determines the
priorities of the interrupt requests appearing

simultaneously. The highest priority is selected and
stored into the corresponding bit of ISR during INTA
pulse. The IR0 has the highest priority while the
IR7 has the lowest one, normally in fixed priority
mode. The priorities however may be altered by
programming the 8259A in rotating priority mode.
Interrupt Mask Register (IMR) : This register

stores the bits required to mask the interrupt
inputs. IMR operates on IRR at the direction
of the Priority Resolver.
397
Interrupt Control Logic: This block manages

the interrupt and interrupt acknowledge
signals to be sent to the CPU for serving one
of the eight interrupt requests. This also
accepts the interrupt acknowledge (INTA)
signal from CPU that causes the 8259A to
release vector address on to the data bus.
Data Bus Buffer : This tristate bidirectional
buffer interfaces internal 8259A bus to the
microprocessor system data bus. Control
words, status and vector information pass
through data buffer during read or write
operations.
398
399
Read/Write Control Logic: This circuit accepts

and decodes commands from the CPU. This
block also allows the status of the 8259A to
be transferred on to the data bus.
Cascade Buffer/Comparator: This block stores
and compares the IDs all the 8259A used in system.

The three I/O pins CASO-2 are outputs when the
8259A is used as a master. The same pins act as
inputs when the 8259A is in slave mode. The 8259A
in master mode sends the ID of the interrupting
slave device on these lines. The slave thus selected,
will send its preprogrammed vector address on
the data bus during the next INTA pulse.
8237DMA CONTROLLER
400
Introduction:
Direct Memory Access (DMA) is a method of allowing data
to be moved from one location to another in a computer

without intervention from the central processor (CPU).
It is also a fast way of transferring data within (and
sometimes between) computer.
The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily disabled.
The DMA controller temporarily borrows the address bus,
data bus and control bus from the microprocessor and
transfers the data directly from the external devices to a
series of memory locations (and vice versa).
401
The 8237 DMA controller

Supplies memory and I/O with control signals and addresses during DMA
transfer
4-channels (expandable)
0: DRAM refresh
1: Free
2: Floppy disk controller
3: Free
1.6MByte/sec transfer rate

64 KByte section of memory address capability with single programming
fly-by controller (data does not pass through the DMA-only memory to I/O
transfer capability)
Initialization involves writing into each channel:
i) The address of the first byte of the block of data that must be transferred (called
the base address).
ii) The number of bytes to be transferred (called the word count).
402
8237 pins
CLK: System clock
CS: Chip select (decoder output)
RESET: Clears registers, sets mask register
READY: 0 for inserting wait states
HLDA: Signals that the p has relinquished buses
DREQ3 DREQ0: DMA request input for each channel
DB7-DB0: Data bus pins
IOR: Bidirectional pin used during programming
and during a DMA write cycle
IOW: Bidirectional pin used during programming
and during a DMA read cycle
EOP: End of process is a bidirectional signal used as input to terminate a DMA process or
as output to signal the end of the DMA transfer
A3-A0: Address pins for selecting internal registers
A7-A4: Outputs that provide part of the DMA transfer address
HRQ: DMA request output
DACK3-DACK0: DMA acknowledge for each channel.
AEN: Address enable signal
ADSTB: Address strobe
MEMR: Memory read output used in DMA read cycle
MEMW: Memory write output used in DMA write cycle
403
8237 block diagram
404
Block Diagram Description
1.
2.
3.
4.
5.
It containing Five main Blocks.

Data bus buffer
Read/Control logic
Control logic block
Priority resolver
DMA channels.
405
DATA BUS BUFFER:

It contain tristate ,8 bit bi-directional buffer.
Slave mode ,it transfer data between
microprocessor and internal data bus.
Master mode ,the outputs A8-A15 bits of
memory address on data lines

(Unidirectional).
READ/CONTROL LOGIC:
It control all internal Read/Write operation.
Slave mode ,it accepts address bits and control
signal from microprocessor.
Master mode ,it generate address bits and control
signal.
406
Control logic block
1.
2.
3.
It contains ,
Control logic
Mode set register and
Status Register.
CONTROL LOGIC:
Master mode ,It control the sequence of DMA

operation during all DMA cycles.
It generates address and control signals.
It increments 16 bit address and decrement 14 bit
counter registers.
It activate a HRQ signal on DMA channel Request.
Slave ,mode it is disabled.
407
DMA controller details
408
Programming and
applications Case
studies
409
1.Traffic Light control

2.LED display
3.LCD display
4.Keyboard display interface
5.Alarm Controller
1. TRAFFIC
LIGHT
CONTROL
410
Traffic lights, which may also be known as stoplights, traffic
lamps, traffic signals, signal lights, robots or semaphore, are

signaling devices positioned at road intersections, pedestrian
crossings and other locations to control competing flows of
traffic.
INTERFACING TRAFFIC LIGHT WITH 8086
The Traffic light controller section consists of 12 Nos.
point leds arranged by 4Lanes in Traffic light interface card.
Each lane has Go(Green), Listen(Yellow) and Stop(Red) LED
is being placed.
411
LAN Direction
412
8086 LINES
MODULES
CIRCUIT DIAGRAM TO INTERFACE TRAFFIC LIGHT WITH 8086
413
8086 ALP:
414
1100: START: MOV BX, 1200H

MOV CX, 0008H
MOV AL,[BX]
MOV DX, CONTROL PORT
OUT DX, AL
INC BX
NEXT:
MOV AL,[BX]
MOV DX, PORT A
OUT DX,AL
CALL DELAY
INC BX
LOOP NEXT
JMP START
DELAY:
PUSH CX
MOV CX,0005H
REPEAT:
MOV DX,0FFFFH
LOOP2:
DEC DX
JNZ LOOP2
LOOP REPEAT
POP CX
RET
Lookup Table
1200
1201
1205
1209
120D
1211
415
80H
21H,09H,10H,00H (SOUTH WAY)
0CH,09H,80H,00H (EAST WAY)
64H,08H,00H,04H (NOURTH WAY)
24H,03H,02H,00H (WEST WAY)
END
2. LED DISPLAY
416
Light Emitting Diodes (LED) is the most commonly

used components, usually for displaying pins digital states.
Typical uses of LEDs include alarm devices, timers and
confirmation of user input such as a mouse click or keystroke.
INTERFACING LED
Anode is connected through a resistor to GND & the
Cathode is connected to the Microprocessor pin. So when
the Port Pin is HIGH the LED is OFF & when the Port Pin is
LOW the LED is turned ON.
417
PIN ASSIGNMENT WITH 8086
418
INTERFACE LED WITH 8255
419
8086 ALP LED interface

1100: START: MOV AL, 80
MOV DX, FF36
OUT DX, AL
BEGIN: MOV AL, 00
MOV DX, FF30
OUT DX, AL
CALL DELAY
MOV AL, FF
OUT DX, AL
CALL DELAY
JMP BEGIN
DELAY: MOV CX, FFFF
PO: DEC CX
JNE PO
RET
420
3. LCD DISPLAY
421
422
HARDWARE CONFIGURATION OF LCD

WITH 8051/8086/8085
423
LCD INTERFACING WITH 8086

TRAINER KIT
GPIO- I (8255) J1 Connector
PORTS
Control port
PORT A
PORT B
PORT C
ADDRESS
FF26
FF20
FF22
FF24

PORTS
Control port
PORT A
PORT B
PORT C
424
ADDRESS
FF36
FF30
FF32
FF34
425
Used in UNIT 5 also
LCD INTERFACING WITH 8051 TRAINER KIT

PORTS
Control port
PORT A
PORT B
PORT C
426
ADDRESS
4003
4000
4001
4002
427
4. Keyboard display interface
428
HARDWARE DESCRIPTION OF 8279 INTERFACE CARD

Keyboard and display is configured in the encoded mode.
In the encoded mode, a binary count sequence is put on the scan
lines SL0-SL3. These lines must be externally decoded to provide
the scan lines for keyboard and display. A 3 to 8 decoder
74LS138 is provided for this purpose. The S0-S1 output lines of
this decoder are connected to the two rows of the keyboard.
And QA0 to QA7 is connected to 7 Segment Display
429
430
PIN DIAGRAM OF 8279
PIN DIAGRAMOF 74LS138
431
432
433
MVI A, 00H
OUT 81H
MVI A, 34H
OUT 81H
MVI A, 0BH
SIM
EI
HERE:
JMP HERE
Interrupt service routine
MVI A, 40H
OUT 81H
IN 80H
MVI H, 62H
MOV L, A
MVI A, 80H
OUT 81H
MOV A, M
OUT 80H
EI
RET
Initialize keyboard/display in encoded

scan keyboard 2 key lockout mode
Initialize prescaler count
Load mask pattern to enable RST 7.5
mask other interrupts
Enable Interrupt
Wait for the interrupt
Initialize 8279 in read FIFO RAM mode
Get keycode
Initialize memory pointer to point
7-Segment code
: Initialize 8279 in write display RAM mode
: Get the 7 segment code
: Write 7-segment code in display RAM
: Enable interrupt
: Return to main program
434
5. ALARM
CONTROLLER
Relevant
Material
Not exact
435
436
GPIO- I J1 Connecter
PORTS
ADDRESS
Control port
FF26
PORT A
FF20
PORT B
FF22
PORT C
FF24
GPIO- II J1 Connecter
PORTS
ADDRESS
Control port
FF36
PORT A
FF30
PORT B
FF32
PORT C
FF34
TEXT BOOK References

Main Book:
1. Microprocessors and Interfacing, Programming and Hardware by Doughlas
V.Hall
Other Authors:
2. Microcomputer Systems: The 8086 / 8088 Family -Architecture,
Programming and Design by Yu-Cheng Liu, Glenn A.Gibson
3. INTEL Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486,
Pentium, Prentium ProProcessor, Pentium II, III, 4 by Barry B. Bery
4. Advanced microprocessor and peripherals by A K RAY
LOCAL AUTHOR:
5.8086 Microprocessor by Nagoor Kani
ONLINE MATERILALS:
www.vtulearning.com
437
8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON ( PROFESSOR

AND DEAN(ACADEMIC),VCET,Erode)
I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE PROFESSOR and
DEAN(SA),VCET,Erode
8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of
Physics,Maharajas College ,Ernakulam
8086 architecture By Er. Swapnil Kaware
8086 presentations by Gursharan Singh Tatla (Eazynotes.com)
Interfacing 8255 by Anuja Bhakuni in Technology
Microprocessor and-interfacing by Akshay Makadiya
Interfacing is for microprocessor by R-THANDAIAH PRABU M.E., Lecturer ECE
Microprocessor - Ramesh Gaonkar
8086 micro processor prasadpawaskar
8086 class notes-Y.N.M by MURTHY Y.N
Introduction to 8086 Microprocessor by Rajvir Singh
8086 micro processor by Poojith Chowdhary
438
Website References
http://80864beginner.com/
www.eazynotes.com
www.slideshare.net
www.scribd.com
www.docstoc.com
www.slideworld.com
www.nptel.ac.in
www.4shared.com
439

Microprocessor and Peripheral Devices by Dr.
Pramod Agarwal , IIT Roorkee
Link: http://nptel.ac.in/courses/108107029/
440
441

Dept: CSE,IT,ECE,MECH
Regulation : R2013
Microcontrollers
Introduction
Presented by
C.GOKUL,AP/EEE
442
CPU for Computers

No RAM, ROM, I/O on CPU chip itself
Example: Intel's x86, Motorolas 680x0
443
A smaller computer
On-chip RAM, ROM, I/O ports...
Example: Motorolas 6811, Intels 8051, Zilogs
Z8 and PIC
444
Microcontroller
Microprocessor
CPU is stand-alone, RAM,

ROM, I/O, timer are
separate
Designer can decide on the
amount of ROM, RAM and
I/O ports.
CPU, RAM, ROM, I/O and timer

are all on a single chip
Fix amount of on-chip ROM, RAM,
I/O ports
For applications in which cost,
power and space are critical
Expansive
Not Expansive
General-purpose
Single-purpose
445
Home
Appliances, intercom, telephones, security systems, garage door

openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment etc.
Office
Telephones, computers, security systems, fax machines,

microwave, copier, laser printer, color printer, paging etc.
Auto
Trip computer, engine control, air bag, ABS, instrumentation,

security system, transmission control, entertainment, climate
control, cellular phone, keyless entry
446
447

8051 CPU Operation

1. Features
2. Pin Diagram
3. Block Diagram
448
8051 Microcontroller
Intel introduced 8051, developed in the year 1981.
The 8051 is an 8-bit processor
The CPU can work on only 8 bits of data at a time
The 8051 became widely popular after allowing

other manufactures to make and market any
flavor of the 8051.
449
8051 Family
The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
Add external ROM to it
You lose two ports, and leave only 2 ports for I/O operations
450
8051 Features
64KB Program Memory address space
64KB Data Memory address space
4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
32 bidirectional and individually addressable I/0 lines
Two 16-bit timer/counters
6-source/5-vector interrupt structure with two priority
levels
On-chip clock oscillator
451
Pin Description of the 8051

8051 family members (e.g., 8751, 89C51, 89C52,
DS89C4x0)
Have 40 pins dedicated for various functions such as I/O, RD,
WR, address, data, and interrupts.
DIP(dual in-line package),
Some companies provide a 20-pin version of the 8051

with a reduced number of I/O ports for less demanding
applications
452
Pin Diagram of the 8051
453
XTAL1 and XTAL2

The 8051 has an on-chip oscillator but requires an
external clock to run it
A quartz crystal oscillator is connected to inputs XTAL1 (pin19)
and XTAL2 (pin18)
The quartz crystal oscillator also needs two capacitors of 30 pF
value
454
XTAL1 and XTAL2 ..

If you use a frequency source other than a crystal
oscillator, such as a TTL oscillator:
It will be connected to XTAL1
XTAL2 is left unconnected
455
XTAL1 and XTAL2 ..

The speed of 8051 refers to the maximum oscillator
frequency connected to XTAL.
We can observe the frequency on the XTAL2 pin using
the oscilloscope.
456
RST
RESET pin is an input and is active high (normally low)
Upon applying a high pulse to this pin, the microcontroller will
reset and terminate all activities
457
EA
EA, external access, is an input pin and
must be connected to Vcc or GND
Normally EA pin is connected to Vcc
EA pin must be connected to GND to
indicate that the code or data is stored
externally.
458
PSEN and ALE

PSEN, program store enable, is an
output pin
This pin is connected to the OE pin of the
external memory.
For External Code Memory, PSEN = 0
For External Data Memory, PSEN = 1
ALE pin is used for demultiplexing the
address and data.
459
I/O Port Pins

The four 8-bit I/O ports P0, P1, P2
and P3 each uses 8 pins.
460
Port 0
Port 0 is also designated as AD0-AD7.
When connecting an 8051 to an external
memory, port 0 provides both address
and data.
The 8051 multiplexes address and data
through port 0 to save pins.
ALE indicates if P0 has address or data.
When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7
461
Port 1 and Port 2

In 8051-based systems with no external
memory connection:
Both P1 and P2 are used as simple I/O.
In 8051-based systems with external

memory connections:
Port 2 must be used along with P0 to provide
the 16-bit address for the external memory.
P0 provides the lower 8 bits via A0 A7.
P2 is used for the upper 8 bits of the 16-bit
address, designated as A8 A15, and it cannot
be used for I/O.
462
Port 3
Port 3 can be used as input or output.
Port 3 has the additional function of
providing some extremely important
signals
463
Pin Description Summary

PIN
TYPE
NAME AND FUNCTION
Vss
Ground: 0 V reference.
Vcc
Power Supply: This is the power supply voltage for normal,

idle, and power-down operation.
P0.0 - P0.7
I/O
Port 0: Port 0 is an open-drain, bi-directional I/O port. Port

0 is also the multiplexed low-order address and data
bus during accesses to external program and data
memory.
P1.0 - P1.7
I/O
Port 1: Port I is an 8-bit bi-directional I/O port.
P2.0 - P2.7
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the

high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7
I/O
Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also

serves special features as explained.
464
Pin Description Summary

PIN
TYPE
NAME AND FUNCTION
RST
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE
Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN*
Program Store Enable: The read strobe to external program

memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during
each access to external data memory.
EA*/VPP
External Access Enable/Programming Supply Voltage: Vpp

pin also receives the programming supply voltage Vpp
during Flash programming. (applies for 89c5x MCU's)
465
General Block Diagram of 8051

Interrupt
Control
4K
ROM
Timer 0
128 B
RAM
Timer 1
CPU
OSC
Bus
Control
Serial
Port
4 I/O Ports
P0
P1
P2
P3
TXD RXD
466
Detailed Block Diagram
467
8051
Memory Space
468
64K
External
External
8051 Memory Structure
60K
64K
SFR
EXT
INT
EA = 0
EA = 1
Program Memory
4K
128
Data Memory
469
Internal RAM Structure

Direct
Addressing
Only
Direct &
Indirect
Addressing
SFR [ Special Function

Registers]
128 Byte Internal RAM
470
Special
Function
Register [SFR]
471
Special Function Registers [SFR]
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode472
SFR Registers & their Addresses

MOV 0E0H,#55H
MOV A,#55H
;is the same as

;which means load 55H into A (A=55H)
MOV 0F0H,#25H
MOV B,#25H
;is the same as

;which means load 25H into B (B=25H)
MOV 0E0H,R2
MOV A,R2
;is the same as

;which means copy R2 into A
MOV 0F0H,R0
MOV B,R0
;is the same as

;which means copy R0 into B
473
SFR Addresses ( 1 of 2 )
474
SFR Addresses ( 2 of 2 )
475
Example
476
Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry
Parity
Auxiliary Carry
User Flag 0
User Flag 1
Register Bank Select
Overflow
477
8051 instructions that affects flag
478
128 Byte RAM

There are 128 bytes of RAM in the 8051.
Assigned addresses 00 to 7FH
The 128 bytes are divided into 3 different

groups as follows:
General Purpose
Area
BIT Addressable
Area
128 BYTE
INTERNAL RAM
Reg Bank 3
1. A total of 32 bytes from locations 00 to 1F

hex are set aside for register banks and the
stack.
2. A total of 16 bytes from locations 20H to 2FH
Reg Bank 2
are set aside for bit-addressable read/write Register
Banks
memory.
Reg Bank 1
3. A total of 80 bytes from locations 30H to 7FH
Reg Bank 0
are used for read and write storage, called
scratch pad.
479
8051 RAM with addresses
480
8051 Register Bank Structure

Bank 3
R0
R1
R2
R3
R4
R5
R6
R7
Bank 2
R0
R1
R2
R3
R4
R5
R6
R7
Bank 1
R0
R1
R2
R3
R4
R5
R6
R7
Bank 0
R0
R1
R2
R3
R4
R5
R6
R7
481
8051 Register Banks with address
482
8051 Programming Model
483
8051 Stack
The stack is a section of RAM used by the CPU to store
information temporarily.
This information could be data or an address
The register used to access the stack is called the SP

(stack pointer) register
The stack pointer in the 8051 is only 8 bit wide, which means
that it can take value of 00 to FFH
484
8051 Stack
The storing of a CPU register in the stack is called a PUSH
SP is pointing to the last used location of the stack
As we push data onto the stack, the SP is incremented by one
This is different from many microprocessors
Loading the contents of the stack back into a CPU

register is called a POP
With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer is
decremented once
485
INSTRUCTION
SET OF
8051
486
8051 Instruction Set

The instructions are grouped into 5 groups
Arithmetic
Logic
Data Transfer
Boolean
Branching
487
1. Arithmetic Instructions
ADD
8-bit addition between the accumulator (A) and a
second operand.
The result is always in the accumulator.
The CY flag is set/reset appropriately.
ADDC
8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.
488
ADD Instruction
ADD A, source
;ADD the source operand to

the accumulator
MOV A, #03H
MOV B,#02H
ADD A,B
;load 03H into A

;load 02H into B
;add B register to accumulator
;(A = A + B)= 05
489
SUBB
Subtract with Borrow.
A A - <operand> - CY.
The result is always saved in the
accumulator.
The CY flag is set/reset appropriately.
490
SUBB Instruction
SUBB A, source
;ADD the source operand to

the accumulator
MOV A, #03H
MOV B,#02H
SUBB A,B
;load 03H into A

;load 02H into B
;add B register to accumulator
;(A = A - B)= 01
491
INC
Increment the operand by one. Ex: INC DPTR

The operand can be a register, a direct address, an
indirect address, the data pointer.
DEC
Decrement the operand by one. Ex: DEC B
The operand can be a register, a direct address, an

indirect address.
MUL AB / DIV AB
Multiply A by B and place result in A:B.

Divide A by B and place result in A:B.
492
Multiplication of Numbers
MUL AB
; A B, place 16-bit result in B and A
MOV A,#05
MOV B,#03
MUL AB
;load 05H to reg. A

;load 03H in reg. B
;05 * 03 = 000F where B = 00 and A = 0F
Table 6-1:Unsigned Multiplication Summary (MUL AB)

Multiplication
Operand 1
Operand 2
Result
byte byte
A=low byte,
B=high byte
493
Division of Numbers
MOV A
A,#05
,#05 ;load 05H to reg. A
MOV B,#03
B,#03 ;load 03H in reg. B
DIV AB
;05/03 =>Quotient = 01
01,Reminder
,Reminder = 02
where B = 02 and A = 01
Table 6-2:Unsigned Division Summary (DIV AB)
Division
Numerator
Denominator
Quotient
Remainder
byte / byte
494
ADD A,@Rn A = A+ memory pointed to Rn

DA A
Decimal Adjust A {BCD addition}
ADDC A,@Rn
SUBB A,@Rn
INC @Ri
495
2. Logical
instructions
496
ANL D,S
-Performs logical AND of destination & source
-Destination : A/memory;
-Source : data/register/memory
- Eg: ANL A,#0FH ANL A,R5
ORL D,S
-Performs logical OR of destination & source

- Eg: ORL A,#28H ORL A,@R0
497
XRL D,S
-Performs logical XOR of destination & source
- Eg: XRL A,#28H
XRL A,@R0
CPL A
-Compliment accumulator
-gives 1s compliment of accumulator data
SWAP A
-Exchange the upper & lower nibbles of accumulator
498
RL A
-Rotate data of accumulator towards left without
carry
RLC A
- Rotate data of accumulator towards left with carry
RR A
-Rotate data of accumulator towards right without
carry
RRC A
- Rotate data of accumulator towards right with
carry
499
3. Data Transfer
Instructions
500
MOV Instruction
MOV destination, source ; copy source to destination.
MOV A,#55H ;load value 55H into reg. A
MOV R0,A
;copy contents of A into R0
;(now A=R0=55H)
MOV R1,A
;(now A=R0=R1=55H)
MOV R2,A
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into R3
;(now R3=95H)
MOV A,R3
;copy contents of R3 into A
;now A=R3=95H
501
MOVX
Data transfer between the accumulator and
a byte from external data memory.
MOVX
MOVX
MOVX
MOVX
A, @Ri
A, @DPTR
@Ri, A
@DPTR, A
502
PUSH / POP
Push and Pop a data byte onto the stack.
The data byte is identified by a direct
address from the internal RAM locations.
PUSH
POP
DPL
40H
503
XCH
Exchange accumulator and a byte variable
XCH
XCH
XCH
A, Rn
A, direct
A, @Ri
504
4.Boolean variable
instructions
505
CLR:
The operation clears the specified bit indicated in
the instruction
Ex: CLR C
clear the carry
SETB:
The operation sets the specified bit to 1.
CPL:
The operation complements the specified bit
indicated in the instruction
506
ANL C,<Source-bit>
-Performs AND bit addressed with the carry bit.
- Eg: ANL C,P2.7 AND carry flag with bit 7 of P2
ORL C,<Source-bit>
-Performs OR bit addressed with the carry bit.

- Eg: ORL C,P2.1 OR carry flag with bit 1 of P2
507
XORL C,<Source-bit>
-Performs XOR bit addressed with the carry bit.
- Eg: XOL C,P2.1 OR carry flag with bit 1 of P2
MOV P2.3,C
MOV C,P3.3
MOV P2.0,C
508
5. Branching
instructions
509
Program branching instructions are

used to control the flow of actions in
a program
Some instructions provide decision
making capabilities and transfer
control to other parts of the program.
e.g. conditional and unconditional
branches
510
Jump Instructions
All conditional jumps are short jumps
Target address within -128 to +127 of PC
LJMP (long jump): 3-byte instruction

2-byte target address: 0000 to FFFFH
Original 8051 has only 4KB on-chip ROM
SJMP (short jump): 2-byte instruction

1-byte relative address: -128 to +127
511
Call Instructions
LCALL (long call): 3-byte instruction
2-byte address
Target address within 64K-byte range
ACALL (absolute call): 2-byte instruction

11-bit address
Target address within 2K-byte range
512
The 8051 provides 2 forms for the return

instruction:
Return from subroutine RET

Return from ISR RETI
513
514
8051
Addressing
Modes
515
8051 Addressing Modes

The CPU can access data in various ways, which are
called addressing modes
1.
2.
3.
4.
5.
Immediate
Register
Direct
Register indirect
External Direct
516
1. Immediate Addressing Mode

The source operand is a constant.
The immediate data must be preceded by the pound sign, #
Can load information into any registers, including 16-bit DPTR
register
DPTR can also be accessed as two 8-bit registers, the high byte DPH and
low byte DPL
517
2. Register Addressing Mode

Use registers to hold the data to be manipulated.
The source and destination registers must match in size.

MOV DPTR,A will give an error
The movement of data between Rn registers is not allowed

MOV R4,R7 is invalid
518
3. Direct Addressing Mode

It is most often used the direct addressing mode to
access RAM locations 30 7FH.
The entire 128 bytes of RAM can be accessed.
Contrast this with immediate addressing mode, there is
no # sign in the operand.
519
Stack and Direct Addressing Mode

Only direct addressing mode is allowed for pushing or
popping the stack.
PUSH A is invalid.
Pushing the accumulator onto the stack must be coded
as PUSH 0E0H.
520
4. Register Indirect Addressing Mode

A register is used as a pointer to the data.
Only register R0 and R1 are used for this purpose.
R2 R7 cannot be used to hold the address of an
operand located in RAM.
When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the @ sign.
521

Write a program to copy the value 55H into RAM memory locations 40H
to 41H using (a) direct addressing mode, (b) register indirect addressing
mode without a loop, and (c) with a loop.
522

The advantage is that it makes accessing data dynamic
rather than static as in direct addressing mode.
Looping is not possible in direct addressing mode.
Write a program to clear 16 RAM locations starting at
RAM address 60H.
523
5. External Direct
External Memory is accessed.
There are only two commands that use External Direct
addressing mode:
MOVX A, @DPTR
MOVX @DPTR, A
DPTR must first be loaded with the address of external
memory.
524
8051
Assembly
Language
Programming(ALP)
525
ADDITION OF TWO 8 bit Numbers

ADDRESS
9100
LABEL
START
MNEMONICS
CLR C
MOV R0, #00
MOV A,#05
MOV B,#03
ADD A,B
MOV DPTR,#9200
JNC AHEAD
INC R0
AHEAD
MOV X @DPTR,A
INC DPTR
MOV A,R0
MOV X @DPTR,A
HERE
SJMP HERE
526
SUBTRACTION OF TWO 8 bit Numbers

ADDRESS
9100
LABEL
START
MNEMONICS
CLR C
MOV R0, #00
MOV A,#05
MOV B,#03
SUBB A,B
MOV DPTR,#9200
JNC AHEAD
INC R0
AHEAD
MOV X @DPTR,A
INC DPTR
MOV A,R0
MOV X @DPTR,A
HERE
SJMP HERE
527
Multiplication Concept
MUL AB
; A B, place 16-bit result in B and A
MOV A,#25H
MOV B,#65H
MUL AB
;load 25H to reg. A

;load 65H in reg. B
;25H * 65H = E99 where B = 0EH and A = 99H
Table 6-1:Unsigned Multiplication Summary (MUL AB)

Multiplication
Operand 1
Operand 2
Result
byte byte
A=low byte,
B=high byte
528
Division Concept
DIV AB ; divide A by B
MOV A,#95H
MOV B,#10H
DIV AB
;load 95 into A
;load 10 into B
;now A = 09 (quotient) and B = 05 (remainder)
Table 6-2:Unsigned Division Summary (DIV AB)

Division
Numerator
Denominator
Quotient
Remainder
byte / byte
529
DIVISION OF TWO 8 bit

Numbers
MULTIPLICATION OF TWO
8 bit Numbers
Address
9000
Label
START
Mnemonics
MOV A,#05
Address
9000
Label
START
MOV A,#05
MOV F0,#03
MOV F0,#03
MUL AB
DIV AB
MOV DPTR,#9200
MOV DPTR,#9200
MOVX @ DPTR,A
MOVX @ DPTR,A
INC DPTR
INC DPTR
MOV A,F0
MOV A,F0
MOVX @DPTR,A
HERE
Mnemonics
MOVX @DPTR,A
SJMP HERE
HERE
SJMP HERE
530
Average of Five(or N) 8 bit Numbers
LOOP:
MOV 40H, #05H

MOV 41H, #04H
MOV 42H, #03H
MOV 43H, #02H
MOV 44H, #01H
MOV R0, #40H
MOV R5, #05H
MOV B,R5
CLR A
ADD A,@R0
INC R0
DJNZ R5,LOOP
DIV AB
MOV 55H,A
END
store I st number in location 40H
store I st number address 40H in R0

store the number 05H in R5
store the number 05H in B
Clear Acc
Save the quotient in location 55H

531
Checking an input bit

JNB (jump if no bit) ; JB (jump if bit = 1)
532
Switch Register Banks
533
Pushing onto Stack
534
Popping from Stack
535
Looping
536
Loop inside a Loop (Nested Loop)
537
Conditional Jump Example
538
Conditional Jump Example
539
540

Presented by
C.GOKUL,AP/EEE
8051
TIMERS
541
8051 Timer/Counter
OSC
12
C /T 0
C /T 1
TLx
THx
(8 Bit) (8 Bit)
TFx
(1 Bit)
T PIN
TR
INTERRUPT
Gate
INT PIN
542
TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is high
and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T*:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).
543
TMOD Register
The TMOD byte is not bit addressable.
544
TCON Register
545
8051
Timer
Modes
8051 TIMERS
Timer 0
Timer 1
Mode 0
Mode 0
Mode 1
Mode 1
Mode 2
Mode 2
Mode 3
546
TIMER 0
OSC
12
C /T 0
C /T 1
TL0 TH0
TF0
T 0 PIN
TR0
INTERRUPT
Gate
INT 0 PIN
547
TIMER 0 Mode 0
13 Bit Timer / Counter
OSC
12
C /T 0
C /T 1
T 0 PIN
TL0
(5 Bit)
TH0
(8 Bit)
TF0
INTERRUPT
TR 0
Gate
INT 0 PIN
Maximum Count = 1FFFh (0001111111111111)

548
TIMER 0 Mode 1
OSC
12
C /T 0
C /T 1
T 0 PIN
TL0
(8 Bit)
TH0
(8 Bit)
TF0
INTERRUPT
TR 0
Gate
INT 0 PIN
Maximum Count = FFFFh (1111111111111111)

549
TIMER 0 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC
12
C /T 0
C /T 1
T 0 PIN
TL0
(8 Bit)
TH0
(8 Bit)
TF0
INTERRUPT
TR 0
Reload
Gate
INT 0 PIN
TH0
(8 Bit)
Maximum Count = FFh (11111111)

550
TIMER 0 Mode 3
Two - 8 Bit Timer / Counter
OSC
12
C /T 0
C /T 1
T 0 PIN
TL0
(8 Bit)
TF0
INTERRUPT
TH0
(8 Bit)
TF1
INTERRUPT
TR 0
Gate
INT 0 PIN
OSC
12
TR1
551
TIMER 1
OSC
12
C /T 0
C /T 1
TL1 TH1
TF1
T 1PIN
TR1
INTERRUPT
Gate
INT 1 PIN
552
TIMER 1 Mode 0
OSC
12
C /T 0
C /T 1
T 1PIN
TL1
(5 Bit)
TH1
(8 Bit)
TF1
INTERRUPT
TR1
Gate
INT 1 PIN
Maximum Count = 1FFFh (0001111111111111)

553
TIMER 1 Mode 1
OSC
12
C /T 0
C /T 1
T 1PIN
TL1
(8 Bit)
TH1
(8 Bit)
TF1
INTERRUPT
TR1
Gate
INT 1 PIN
Maximum Count = FFFFh (1111111111111111)

554
TIMER 1 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC
12
C /T 0
C /T 1
T 1PIN
TL1
(8 Bit)
TH1
(8 Bit)
TF1
INTERRUPT
TR1
Reload
Gate
INT 1 PIN
TH1
(8 Bit)
Maximum Count = FFh (11111111)

555
Programming Timers
Example: Indicate which mode and which timer are
selected for each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV
TMOD, #12H
Solution: We convert the value from hex to binary.
(a) TMOD = 00000001, mode 1 of timer 0 is selected.
(b) TMOD = 00100000, mode 2 of timer 1 is selected.
(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1
are selected.
556
Programming Timers
Find the timers clock frequency and its period for
various 8051-based system, with the crystal frequency
11.0592 MHz when C/T bit of TMOD is 0.
Solution:
1/12 11.0529 MHz = 921.6 MHz;

T = 1/921.6 kHz = 1.085 us
557
558
8051
Serial
Port
559
Basics of Serial Communication

Computers transfer data in two ways:
Parallel: Often 8 or more lines (wire conductors) are used to
transfer data to a device that is only a few feet away.
Serial: To transfer to a device located many meters away, the
serial method is used. The data is sent one bit at a time.
560
Basics of Serial Communication

Serial data communication uses two methods
Synchronous method transfers a block of data at a time
Asynchronous method transfers a single byte at a time
There are special ICs made by many manufacturers for

serial communications.
UART (universal asynchronous Receiver transmitter)
USART (universal synchronous-asynchronous Receivertransmitter)
561
Asynchronous Start & Stop Bit

Asynchronous serial data communication is widely used
for character-oriented transmissions
Each character is placed in between start and stop bits, this is
called framing.
Block-oriented data transfers use the synchronous method.
The start bit is always one bit, but the stop bit can be
one or two bits
The start bit is always a 0 (low) and the stop bit(s) is 1
(high)
562
Asynchronous Start & Stop Bit
563
Data Transfer Rate

The rate of data transfer in serial data communication is
stated in bps (bits per second).
Another widely used terminology for bps is baud rate.
It is modem terminology and is defined as the number of
signal changes per second
In modems, there are occasions when a single change of signal
transfers several bits of data
As far as the conductor wire is concerned, the baud rate

and bps are the same.
564
8051 Serial Port
Synchronous and Asynchronous

SCON Register is used to Control
Data Transfer through TXd & RXd pins
Some time - Clock through TXd Pin
Four Modes of Operation:
Mode 0
Mode 1
Mode 2
Mode 3
:Synchronous Serial Communication

:8-Bit UART with Timer Data Rate
:9-Bit UART with Set Data Rate
:9-Bit UART with Timer Data Rate
565
Registers related to Serial

Communication
1. SBUF Register
2. SCON Register
3. PCON Register
566
SBUF Register
SBUF is an 8-bit register used solely for serial communication.
For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
The moment a byte is written into SBUF, it is framed with the
start and stop bits and transferred serially via the TxD line.
SBUF holds the byte of data when it is received by 8051 RxD
line.
When the bits are received serially via RxD, the 8051 deframes
it by eliminating the stop and start bits, making a byte out of
the data received, and then placing it in SBUF.
567
SBUF Register
Sample Program:
568
SCON Register
SM0 SM1 SM2 REN TB8 RB8
Set to Enable
Serial Data
reception
Enable Multiprocessor
Communication Mode
9th Data Bit

Sent in Mode 2,3
TI
RI
Set when a Charactor received
Set when Stop bit Txed

9th Data Bit
Received in Mode 2,3
569
8051 Serial Port Mode 0

The Serial Port in Mode-0 has the following features:
1. Serial data enters and exits through RXD
2. TXD outputs the clock
3. 8 bits are transmitted / received
4. The baud rate is fixed at (1/12) of the oscillator frequency
570

1. Serial data enters through RXD
2. Serial data exits through TXD
3. On receive, the stop bit goes into RB8 in SCON
1. Start bit (0)
2. Data bits (8)
3. Stop Bit (1)
5. Baud rate is determined by the Timer 1 over flow rate.

571

3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is programmable

572

3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is determined by Timer 1 overflow rate.

573
Programming Serial Data Transmission

1. TMOD register is loaded with the value 20H, indicating the use of timer
1 in mode 2 (8-bit auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data
transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode
1, where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is written into SBUF
register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx to see
if the character has been transferred completely.
8. To transfer the next byte, go to step 5
574
Programming Serial Data Reception

1. TMOD register is loaded with the value 20H, indicating the use of timer 1
in mode 2 (8-bit auto-reload) to set baud rate.
2. TH1 is loaded to set baud rate
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB RI, xx to see if
an entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are moved into a safe
place.
8. To receive the next character, go to step 5.
575
Doubling Baud Rate

There are two ways to increase the baud rate of data
transfer
1. By using a higher frequency crystal
2. By changing a bit in the PCON register
PCON register is an 8-bit register.
When 8051 is powered up, SMOD is zero

We can set it to high by software and thereby double the baud rate.
576
Doubling Baud Rate (cont)
577
8051
Interrupts
578
INTERRUPTS
An interrupt is an external or internal event that
interrupts the microcontroller to inform it that a device
needs its service
A single microcontroller can serve several devices by two
ways:
1. Interrupt
2. Polling
579
Interrupt Vs Polling
1. Interrupts
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device.
The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
The microcontroller continuously monitors the status of a
given device.
When the conditions met, it performs the service.
After that, it moves on to monitor the next device until every
one is serviced.
580
Interrupt Vs Polling
The polling method is not efficient, since it wastes much of
the microcontrollers time by polling devices that do not
need service.
The advantage of interrupts is that the microcontroller can
serve many devices (not all at the same time).
Each devices can get the attention of the microcontroller
based on the assigned priority.
For the polling method, it is not possible to assign priority
since it checks all devices in a round-robin fashion.
The microcontroller can also ignore (mask) a device request
for service in Interrupt.
581
Steps in Executing an Interrupt

1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e:
not on the stack).
3. It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted.
582
Six Interrupts in 8051

Six interrupts are allocated as follows:
1. Reset power-up reset.
2. Two interrupts are set aside for the timers.
one for timer 0 and one for timer 1
3. Two interrupts are set aside for hardware external

interrupts.
P3.2 and P3.3 are for the external hardware interrupts INT0
(or EX1), and INT1 (or EX2)
4. Serial communication has a single interrupt that

belongs to both receive and transfer.
583
What events can trigger Interrupts?

We can configure the 8051 so that any of the following
events will cause an interrupt:
Timer 0 Overflow.
Timer 1 Overflow.
Reception/Transmission of Serial Character.
External Event 0.
External Event 1.
We can configure the 8051 so that when Timer 0

Overflows or when a character is sent/received, the
appropriate interrupt handler routines are called.
584
8051 Interrupt Vectors
585
8051 Interrupt related Registers

The various registers associated with the use of
interrupts are:
TCON - Edge and Type bits for External Interrupts 0/1
SCON - RI and TI interrupt flags for RS232
IE - Enable interrupt sources
IP - Specify priority of interrupts
586
Enabling and Disabling an Interrupt

Upon reset, all interrupts are disabled (masked),
meaning that none will be responded to by the
microcontroller if they are activated.
The interrupts must be enabled by software in order for
the microcontroller to respond to them.
There is a register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling
(masking) the interrupts.
587
Interrupt Enable (IE) Register

--
EA : Global enable/disable.
--- : Reserved for additional interrupt hardware.
MOV IE,#08h
or
SETB ET1
ES : Enable Serial port interrupt.

ET1 : Enable Timer 1 control bit.
EX1 : Enable External 1 interrupt.
ET0 : Enable Timer 0 control bit.
EX0 : Enable External 0 interrupt.
588
Enabling and Disabling an Interrupt

Example: Show the instructions to (a) enable the serial interrupt,
timer 0 interrupt, and external hardware interrupt 1 and (b)
disable (mask) the timer 0 interrupt, then (c) show how to disable
all the interrupts with a single instruction.
Solution:
(a) MOV IE,#10010110B ;enable serial, timer 0, EX1
Another way to perform the same manipulation is:
SETB IE.7 ;EA=1, global enable

SETB IE.4 ;enable serial interrupt
SETB IE.1 ;enable Timer 0 interrupt
SETB IE.2 ;enable EX1
(b) CLR IE.1 ;mask (disable) timer 0 interrupt only

(c) CLR IE.7 ;disable all interrupts
589
Interrupt Priority
When the 8051 is powered up, the priorities are assigned according
to the following.
In reality, the priority scheme is nothing but an internal polling
sequence in which the 8051 polls the interrupts in the sequence
listed and responds accordingly.
590
Interrupt Priority
We can alter the sequence of interrupt priority by assigning a
higher priority to any one of the interrupts by programming a
register called IP (interrupt priority).
To give a higher priority to any of the interrupts, we make the
corresponding bit in the IP register high.
591
Interrupt Priority (IP) Register
Reserved
PS
PT1 PX1
PT0
PX0
Serial Port
Timer 1 Pin
INT 1 Pin
INT 0 Pin
Timer 0 Pin
Priority bit=1 assigns high priority

Priority bit=0 assigns low priority
592
593
KEYBOARD
INTERFACING
KEYBOARD INTERFACING
Keyboards are organized in a matrix of rows
and columns
The CPU accesses both rows and columns
through ports .
Therefore, with two 8-bit ports, an 8 x 8
matrix of keys can be connected to a
microprocessor
When a key is pressed, a row and a
column make a contact
594
Otherwise, there is no connection

between rows and columns
In IBM PC keyboards, a single
microcontroller takes care of hardware
and software interfacing
A 4x4 matrix connected to two ports
The rows are connected to an
output port and the columns are
connected to an input port
595
4x4 matrix
596
597
598
Identify the row and column of the pressed key

for each of the following.
(a) D3 D0 = 1110 for the row, D3 D0 = 1011
for the column
(b) D3 D0 = 1101 for the row, D3 D0 = 0111
for the column
Solution:
(a) The row belongs to D0 and the column

belongs to D2; therefore, key number 2 was
pressed.
(b) The row belongs to D1 and the column
belongs to D3; therefore, key number 7 was
pressed.
599
600
601
Stepper Motor
Interfacing
602
Stepper Motor Interfacing

Stepper motor is a widely used device that
translates electrical pulses into mechanical movement.
Stepper motor is used in applications such as; disk
drives, dot matrix printer, robotics etc
It has a permanent magnet rotor called the shaft which
is surrounded by a stator. Commonly used stepper
motors have four stator windings
Such motors are called as four-phase or unipolar stepper
motor.
603
604
605
Step angle:
Step angle is defined as the minimum degree of rotation
with a single step.
No of steps per revolution = 360 / step angle
Steps per second = (rpm x steps per revolution) / 60
Example: step angle = 2
No of steps per revolution = 180
606
A switch is connected to pin P2.7. Write an ALP to monitor the status of

the SW. If SW = 0, motor moves clockwise and if SW = 1, motor
moves anticlockwise
SETB P2.7
MOV A, #66H
MOV P1,A
TURN: JNB P2.7, CW

RL A
ACALL DELAY
MOV P1,A
SJMP TURN
CW: RR A
ACALL DELAY
MOV P1,A
SJMP TURN
607
Full step
608
LCD Interfacing
{before discussed in Unit 3 LCD

interfacing using 8086}
Slide number 127,128 in

Unit 3
609
Already discussed in UNIT 3 also
610
HARDWARE CONFIGURATION OF LCD

WITH 8051/8086/8085
611
LCD INTERFACING WITH 8051 TRAINER KIT

PORTS
Control port
PORT A
PORT B
PORT C
612
ADDRESS
4003
4000
4001
4002
613
A/D Interfacing
{before discussed in Unit 3 A/D

614
Interfacing ADC to 8051

ADC0804 is an 8 bit successive approximation analogue to digital
converter from National semiconductors. The features of ADC0804
are differential analogue voltage inputs, 0-5V input voltage range, no zero
adjustment, built in clock generator, reference voltage can be externally
adjusted to convert smaller analogue voltage span to 8 bit resolution etc.
615
Steps for converting the analogue input and reading the

output from ADC0804
Make CS=0 and send a low to high pulse to WR pin to

start the conversion.
Now keep checking the INTR pin. INTR will be 1 if
conversion is not finished and INTR will be 0 if
conversion is finished.
If conversion is not finished (INTR=1) , poll until it is
finished.
If conversion is finished (INTR=0), go to the next step.
Make CS=0 and send a high to low pulse to RD pin to
read the data from the ADC.
616
617
The circuit initiates the ADC to convert a given analogue input ,

then accepts the corresponding digital data and displays it on the
LED array connected at P0. For example, if the analogue input
voltage Vin is 5V then all LEDs will glow indicating 11111111 in
binary which is the equivalent of 255 in decimal. AT89s51 is the
microcontroller used here. Data out pins (D0 to D7) of the
ADC0804 are connected to the port pins P1.0 to P1.7 respectively.
LEDs D1 to D8 are connected to the port pins P0.0 to P0.7
respectively. Resistors R1 to R8 are current limiting resistors. In
simple words P1 of the microcontroller is the input port and P0 is
the output port. Control signals for the ADC (INTR, WR, RD and CS)
are available at port pins P3.4 to P3.7 respectively. Resistor R9 and
capacitor C1 are associated with the internal clock circuitry of the
ADC. Preset resistor R10 forms a voltage divider which can be used
to apply a particular input analogue voltage to the ADC. Push
button S1, resistor R11 and capacitor C4 forms a debouncing reset
mechanism. Crystal X1 and capacitors C2,C3 are associated with the
clock circuitry of the microcontroller.
618
Program:
MOV P1,#11111111B
MAIN: CLR P3.7
SETB P3.6
CLR P3.5
SETB P3.5
WAIT:
JB P3.4,WAIT
CLR P3.7
CLR P3.6
MOV A,P1
CPL A
MOV P0,A
SJMP MAIN
// initiates P1 as the input port

// makes CS=0
// makes RD high
// makes WR low
// low to high pulse to WR for starting
conversion
// polls until INTR=0
// ensures CS=0
// high to low pulse to RD for reading the
data from ADC
// moves the digital data to accumulator
// complements the digital data
// outputs the data to P0 for the LEDs
// jumps back to the MAIN program END
619
D/A Interfacing
{before discussed in Unit 3 D/A

620
Digital-to-analog (DAC) converter

The digital-to-analog converter (DAC) is a device widely used to convert
digital pulses to analog signals.
Two methods of creating a DAC:
Binary weighted and R/2R ladder.
The vast majority of integrated circuit DACs, including the MC1408
(DAC0808) used in this section, use the R/2R method since it can achieve a
much higher degree of precision. The first criterion for judging a DAC is its
resolution, which is a function of the number of binary inputs. The
common ones are 8, 10, and 12 bits. The number of data bit inputs
decides the resolution of the DAC since the number of analog output
levels is equal to 2, where n is the number of data bit inputs. Therefore,
an 8-input DAC such as the DAC0808 provides 256 discrete voltage (or
current) levels of output.
Similarly, the 12-bit DAC provides 4096 discrete voltage levels. There
are also 16-bit DACs, but they are more expensive.
621
8051 Connection to DAC808
622
program to send data to the DAC to

generate a stair-step ramp
623
SENSOR
INTERFACING
take temperature sensor for example
624
625
626
EXTERNAL
MEMORY
INTERFACING
627
Access to External Memory

Port 0 acts as a multiplexed address/data bus. Sending
the low byte of the program counter (PCL) as an
address.
Port 2 sends the program counter high byte (PCH)
directly to the external memory.
The signal ALE operates as in the 8051 to allow an
external latch to store the PCL byte while the multiplexed
bus is made ready to receive the code byte from the
external memory.
Port 0 then switches function and becomes the data bus
receiving the byte from memory.
628
629
Books References
Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay,
630
The 8051 Microcontroller and Embedded Systems: Using

Assembly and C
Programming and Interfacing the 8051 Microcontroller by
SencerYeralan ,Ashutosh Ahluwalia
The 8051 Microcontroller by by I. Scott MacKenzie
Programming & Customizing the 8051 Microcontroller by
Michael Predko
Microcontrollers by RajKamal
8051 microcontroller by Suresh P. Nair[ME, (PhD)] MIEEE Professor&Head Department of Electronics and
Communication Engineering Royal College of Engineering and Technology
8051 Microcontroller by Dr. M. Gopikrishna ,Assistant Professor of Physics,Maharajas College ,Ernakulam
8051 Microcontroller By Er. Swapnil Kaware
8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education
8051 MICROCONTROLLER by Prathyusha Institute of Technology & Management in Education
www.pantechsolutions.net/
Embedded systems, 8051 microcontroller by Amandeep Alag in Education
8051 microcontroller features by Tech_MX in Technology
8051 microcontroller by Gaurav Verma in Engineering
8051 (microcontroller)class1 by Nitin Ahire in Education
8051 microcontroller by Bibek Kattel in Education
8051 microcontroller by Jhemi22 in Education
8051 microcontrollers by Chih-Hsiang Tang in Technology
Embedded systems, 8051 microcontroller by Amandeep Alag
Embedded C programming based on 8051 microcontroller by Gaurav Verma
Microcontroller 8051 features & application
MICROCONTROLLER-8051 Features & Applications Dr. Y .Narasimha Murthy Ph.D., Sri Saibaba National
College
631
Website References
http://amcmp.blogspot.in/2012/06/8051-micro-controller.html
http://www.mikroe.com/chapters/view/65/chapter-2-8051-microcontroller-architecture/
https://www.pantechsolutions.net/project-kits/user-guide-for-lcd-interface-card
http://www.slideshare.net/pantechsolutions/interfacing-stepper-motor-with-8051
LCD DIsplay
stepper motor
https://www.pantechsolutions.net/microcontroller-boards/adc-0809-interfacing-with-8086-ps2-lab-kit ADC interface

https://www.pantechsolutions.net/microcontroller-boards/dac-0800-interfacing-with-8086-ps2-lab-kit
https://www.pantechsolutions.net/microcontroller-boards/led-interfacing-with-8086-ps2-lab-kit
www.vtulearning.com
www.eazynotes.com
www.slideshare.net
www.scribd.com
www.docstoc.com
www.slideworld.com
www.nptel.ac.in
www.4shared.com
DAC interface
LED Interface
632

633

EC6504 Microprocessor and Microcontroller Lecture Notes All 5 Units

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EC6504

DIFFERENT PROCESSORS AVAILABLE

Development of Intel Microprocessors

It was first 16-bit P.

Its clock speed is 4.77 MHz, 8 MHz

It could access 1 MB of memory.

It had 22,000 instructions.

It had Multiply and Divide

It was also 16-bit P.

INTEL 80186 & 80188

They were 16-bit Ps.

Clock speed was 6 MHz.

80188 was a cheaper

Its clock speed was 8

Its data bus is 16-bit

It was first 32-bit P.

Its data bus is 32-bit

It was also 32-bit P.

It had 1.2 million

It was also 32-bit P.

It was originally named

INTEL PENTIUM PRO

It was also 32-bit P.

It was also 32-bit P.

Its clock speed was 233

INTEL PENTIUM II XEON

It was also 32-bit P.

It was designed for

INTEL PENTIUM III

It was also 32-bit P.

Its clock speed varied

It was also 32-bit P.

Its clock speed was from

INTEL DUAL CORE

3 logic levels are:

High State (logic 1)

Basic Microprocessors System

Secondary Storage Devices

It has multiplexed address and data bus

INTEL 8086 - Pin Diagram/Signal Description

INTEL 8086 - Pin Details

Duty cycle: 33%

INTEL 8086 - Pin Details

Address Latch Enable:

INTEL 8086 - Pin Details

INTEL 8086 - Pin Details

INTEL 8086 - Pin Details

INTEL 8086 - Pin Details

Bus High Enable/S7

0,0: Whole word

0,1: High byte

INTEL 8086 - Pin Details

Minimum Mode Pins

Minimum Mode- Pin Details

Maximum Mode - Pin Details

Maximum Mode - Pin Details

Maximum Mode - Pin Details

8086 Internal Architecture

Bus Interface Unit

Bus Interface Unit

Architecture Diagram of 8086

EXTRA SEGMENT (ES)

STACK SEGMENT (SS)

INSTRUCTION POINTER (IP)