Chapter 6

Sequential Logic Circuits

6.1 Introduction of Sequential Logic Circuits

Feature of Sequential circuit:
Basic unit: FF ( gates + feedback lines )
Memory
inputs
Output
depends on former state
Logic
circuit

Synchronous
FFs are triggered at CLK same edge
Asynchronous

Sequential circuits structure:

Combinational Logic + FF +
X

Z
Combinational
Logic
Q

X: outside inputs
w

Zoutside output

FF

W: control inputs -- J, K, D, T
Q: state of FF
2

 X
Z

Relationships of them:
Output equation

Z = F ( X , Q)

Driving equation

W = H ( X , Q)

Characteristic equation Q n +1 = G (W , Q n )

Sequential circuit

Mealy-type () Output Z

Qn
X

Moore-type () Output Z ~ Qn

6.2 Synchronic Sequential Circuit Analysis

Analysis: Given a circuit, describe its operation.

Example 1: Analysis the sequential circuit

1)

Inputs
Outputs

Control inputs
Z

States

J0, K0, J1, K1

Q1 (MSB), Q0
4

2) Equations
Output equation

Z = ( X Q1n ) Q0n

Driving equation

J 0 = X Q1n

J1 = X Q0n

K0 = 1

K1 = 1

Characteristic equation

Q0n+1 = J 0 Q0n + K0Q0n = ( X Q1n )Q0n

Q1n +1 = J1 Q1n + K1Q1n = ( X Q0n ) Q1n

3) State table and State diagram

Given: input X , Qn XQn
Ask: output Z , Qn+1 Z Qn+1

Q1n +1 = ( X Q0n ) Q1n

Q0n +1 = ( X Q1n )Q0n

State table
n
n
X Q1 Q0

X=0

0
0
0
0

0
0
1
1

0
1
0
1

1 0 0
X=1

1 0 1
1 1 0
1 1 1

Q1n +1

0
1
0
0
1
0
0
0

Q0n +1

1
0
0
0
0
0
1
0

Z = ( X Q1n ) Q0n

0
0
1
0
1
0
0
0

Q1n +1 = Q0n Q n1

X=0

Q0n +1 = Q1n Q0n

Z = Q1n Q0n
Q1n +1 = Q0n Q1n

X=1

Q0n +1 = Q1n Q0n

Z = Q1n Q0n
6

State diagram

X/Z

Q1Q0

State table
n
n
n +1
Q0n+1
X Q1 Q0 Q1

0/0

0/0
11

00

1/0

01

1/0
1/1

1/0
0/0

0/1

0
0
0
0

0
0
1
1

0
1
0
1

0
1
0
0

1
0
0
0

Z
0
0
1
0

1
1
1
1

0
0
1
1

0
1
0
1

1
0
0
0

0
0
1
0

1
0
0
0

10

CLK

Every conversion line is corresponding to one row in truth table

7

4) Circuit function
0/0
0/0

00

11 1/0

01

1/0
1/1

1/0

0/1

0/0

10

3
X=0, 3Z1
X=1, 3Z1
8

Example 2. Analyze the following sequential circuit

Q3

J3

Q3

K3

=1

Q2

J2

Q1

J1

Q2

K2

Q1

K1

CLK

FFCLK
1.
J3 = Q2n

J2 = Q1n

J1 = Q2n + Q3n

K3 = Q2nQ1n

K2 = Q3 n

K1 = Q2n +Q3n = Q2nQ3n

9

2.
n +1
Q3

= J 3 Q3n + K 3Q3n = Q 2n Q3n + (Q 2n Q1n )Q3n

Q2n +1 = J 2 Q2n + K 2Q2n = Q1n Q2n + Q3nQ2n

Q1n +1 = J 1 Q1n + K 1Q1n = (Q2n + Q3n )Q1n + Q2nQ3nQ1n

3.
n
Q3n Q2 Q1n

0
0
0
0

0
0
1
1

0
1
0
1

1 0

1 0
1 1
1 1

1
0
1

Q3n +1 Q2n +1 Q1n +1

0
0
1
1
0
1
1
0

0
1
0
0
0
1
1
1

0
0
1
0
1
0
1
1

Q3n+1

=Q2n
Q3n = 0
=Q2nQ1n Q n = 1
3

Q2n+1

=Q1n
=Q3n

Q2n = 0
Q2n = 1

=Q2n+Q3n

Q1n = 0

=Q2nQ3n

Q1n = 1

Q1

n+1

10

n
Q3n Q2 Q1n

0
0
0
0

0
0
1
1

0
1
0
1

1 0

1 0
1 1
1 1

1
0
1

Q3n +1 Q2n +1 Q1n +1

0
0
1
1
0
1
1
0

0
1
0
0
0
1
1
1

0
0
1
0
1
0
1
1

000 is isolated state

4.
Q3Q2Q1

cannot self start

000

001

010

101
110

100

011

111
11

6.3 Synchronous Sequential Circuit Design

Known State diagram

Request Circuit
Design steps:
1) Determine state and state diagram
2) State simplification
3) State distribution (encoding)
4) Select FF
5) Qn+1 equations and control inputs J, K, D, T
6) Circuit
7) Self start
12

Example 1. 5 (P130, 6.4)

1
/0
001

000
/1

100

5 valid states

/0

/0

010
011

Q3nQ2nQ1n

/0

3 FF

5 < 23
/Z

Q3n+1Q2n+1Q1n+1
Z
Q3nQ2n

Q1n

2 K-map
Q3n+1
Q1

Q3nQ2n
n

00 01 11 10

0 0
1 0 1
0 0

Q2n+1

00 01 11 10

0 1
1 0 0
0 0
Q1n+1

Q3nQ2n

Q1n

00 01 11 10

0 0
1 1

1 0
0

Q3nQ2n

Q1n

00 01 11 10

1 0
1 0 0
0 1

13

3
Q3n+1
Q1

Q2n+1

Q3nQ2n
n

00 01 11 10

0 0
1 0 1
0 0

Q3n+1 = Q2nQ1n

Q1n+1

Q3nQ2n

Q1n

00 01 11 10

0 0
1 1

1 0
0

Q2n+1 = Q1nQ2n+ Q1nQ2n

= D3

= Q1nQ2n

D3 = Q2nQ1n

= T2 Q2n
T2 = Q1n

Z
Q1

Q3nQ2n
n

Q3nQ2n

Q1n

00 01 11 10

1 0
1 0 0
0 1

Q1n+1 = Q3nQ1n
= D1
or

J1 = Q3n
K1 = 1

00 01 11 10

0 1
1 0 0
0 0

Z = Q3n
14

4
D3 =

Q2nQ1n

5
Circuit
Z

T2 = Q1

J1 = Q3n

Z = Q3n

K1 = 1
11
Q3

10
D3

Q3

Q2
Q2

10
T2

Q1

J1

Q1

K1

1
CLK

6
101110111

111 100
110 010
101 010

/1

/1

/1

15

Example 2.
X
1
1Y = 1Y = 0 (P132. 6.5)
1
S01
S11
X=1, 1
S21
S311
X/Y

0/0
0/0

S0
0/0

S3
1/1

1/0

S1
1/0

0/0
1/1

S2
16

2 State simplification
:
:

S2 S3 S2 S3 S2
0/0

0/0

0/0

S0
0/0

S3
1/1

1/0
0/0

1/1

S1
1/0

0/0

S0

1/0
0/0

S2

S1
1/0

S2
1/1

17

3 State distribution and encoding

S0 = 00
S1 = 01
S2 = 11

State table
n
n
n +1
Q0n+1 Y
X Q1 Q0 Q1

0/0

0/0

00

01

1/0

1/0

0/0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
X
0

0
0
X
0

0
0
X
0

1
1
1
1

0
0
1
1

0
1
0
1

0
1
X
1

1
1
X
1

0
0
X
1

11
1/1

18

n
n
n +1
Q0n+1 Y
X Q1 Q0 Q1

4)
Q1n+1
Q0n

XQ1n

00

01

11

10

Q1n +1 = XQ0n = D1

D1 = XQ0n

Q0n+1
Q0n

XQ1n

00

01

11

10

0 0

1 0

Q0n +1 = X = D0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
X
0

0
0
X
0

0
0
X
0

1
1
1
1

0
0
1
1

0
1
0
1

0
1
X
1

1
1
X
1

0
0
X
1

Y XQ n
1 00 01
Q0n

11 10

Y= XQ1n

D0 = X
19

5)

2 D-FFs

D1 = XQ0n

Y= XQ1n

D0 = X
6)

20

00

01

0/0

0/0

00

01

1/0

0/0

0/0

10

1/1

1/0

11
1/1

21

Example 3.JK (P134

6.6)
0/0

1/0

0/0

00

10

1/1

State table (from state diagram)

X/Z

1/0

11
0/0

Determine state (FF) and state table

State number
FF number

n FFs 2n states
2n-1 states
3 < 22

2n

n FFs

2 FF

Q2n Q1n Q2n +1 Q1n +1 Z

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1
1

0
0
1
1

0
1
0
1

1
1
1

0
1
0

0
0
0

1
0

1
0

0
1

22

Select FF (K-map, group 1s)

Q2n+1

2# FF
Q2

n+1

= XQ2 + XQ1

Q1n

2 groups, need a JK-FF

Q2n+1 = J2Q2n + K2Q2n

Q2n+1
Q1

XQ2n

00

01

11

10

1
0

1
1

Q2

Q2n

XQ2n

00

01

11

10

1
0

1
1

J2 = ?
Q2n+1 =

K2 = ?

Q2n +

Q2n

Q2n+1 = XQ2n + (X + Q1n)Q2n

= XQ2n + XQ1n Q2n

Q2n

J2 = X
K2 = XQ1n

23

Find the simplest form if the control inputs could be found.

Otherwise, determine the inputs first.

1# FF

Q1n+1
Q1n

JK-FF

XQ2n

00

01

0
1

11

1
0

Q1n+1 = J1Q1n + K1Q1n

XQ2nQ1n

+ XQ1

10

Q1n

Q1n
J1 = XQ2n
K1 = X
24

Output Z

Z
Q1n

XQ2n

0
1

00

01

11

10

0
1

Z = XQ1n

Logic circuit
X
J2 = X

& J Q1
1

K2 = XQ1n
K1

J1 = XQ2n

Q1

J2

Q2

& K2

CLK

K1 = X
25

Discuss01 state

Q2n+1
Q1

0/0

XQ2n

00

0 0
1 0

0/0

1/0
00

10

01

11

10

11

10

1/1
1/1

11
0/0

K-map
XQ2nQ1n = 001, (Z=0)
Q2n1Q1n+1 =01,
XQ2nQ1n = 101, (Z=1)
Q2n1Q1n+1 =10,

Q1n+1

1/0
01

Q1n

0/0

XQ2n

00

01

0 0

1 1

Z XQ2n
00 01

Q1n

11 10

1
26

6.4 Counter
CLK

6.4.1 4-bit IC Counter 74161 (M-16)

74161160

Circuit

p.136

Q3Q2Q1Q0
| | | |
D3D2D1D0

27

Symbol
MSB

IEEE

Q0 Q1 Q2 Q3
CO
74161
LD
CLK
CLR D0 D1 D2 D3

CTT
CTP

Output Q3 Q2 Q1 Q0
Data input D3 D2 D1 D0
Direct clear CLR
Control ENT (CTT), ENP (CTP)
Load LOAD
Carry out RCO (CO)
28

74161 Function table

D0 D1 D2 D3

Function

Direct set 0

Q3Q2Q1Q0 = 0000

Load

Q3Q2Q1Q0 = D3D2D1D0

CLR LD ENT ENP CLK

1 0

D0 D1 D2 D3

1 1 0
1 1 0

No change RCO=0
No change

1 1 1 1

M-16 counter

RCO = ENTQ3 Q2 Q1 Q0
ENT=1,
Q3Q2Q1Q0 = 1111M-16
RCO = 1.
RCO = 0
29

CLR
LOAD

30

74161 IEEE symbol

16 (16

Counter

0
M:

CLR

LOAD

G:

M1 (
), C5
D

ENT
ENP
CLK
D0
D1
D2
D3

CTR DIV 16
CT=0
M1
M2 3CT=15
G3
G4
C5/2,3,4+
1,5D

RCO
M2, G3, G4 ,
CLK , 1
Q0
Q1
Q2
Q3

[1]
[2]
[4]
[8]

15G3
CO=1

31

Example 1: 7416111 (6.7 P141)

Implement a modulus -11 counter using 74161
Method 1: Set 0 using LD 0
ENT = ENP =1, CLR =1,

max state 1010

D3D2D1D0 = 0000

NAND gate

Output LD
&

0 9NAND gate = 1
(LD=1), count
10th CLK comes,
Q3Q2Q1Q0=1010, LD=0
Next CLK (11th) comes,
Q3Q2Q1Q0 = D3D2D1D0 = 0000

0
0
0
0

0
1
0
1
32

State diagram
/RCO

/0

/0
0010

0001

/0

/0
0011

0100

0000

0101

/0
1010

Waveforms
CLK

/0

1001

0111

1000
/0

/0
4

0110
/0

/0

10

11

/0

12

Q0

Q0

Q1

Q2
Q3
RCO
33

Method 2: Loading complement (

0000 ~ 1111
16 states

5 (0101) ~ 15 (1111)
11 states
&

&

1
0
1
0

1
1
1
1

1
0
1
0

34

State diagram
/RCO

0101

/1

/0

1111

0110

/0

/0

1110

0111

/0

/0

1000

1101

/0

/0

1001

1100

/0

/0

1010

1011

/0

3 ~ 13

12--.exe

35

Method 3: Set 0 using CLR

&

0
ENT = ENP = LD = 1

D3 D2 D1 D0 =

Q3Q2Q1Q0 = 1011

1
1
0
1

State diagram
1st CLK

0000
1011

0001

0010

0011

0100

11th CLK

1010

0101
1001

10th CLK

1000

0111

0110
36

1st CLK

0000

0001

0010

0011

0100

11th CLK

1011

1010

0101
1001

1000

0111

0110

10th CLK

Waveforms
CLK
Q0

10

11

12

glitch

Q1
Q2
Q3

1
37

Example 2: Design a modulus - 24 counter using 74161

Max state: 23 (10111)

two 74161

1
0

1
1
1
0

CLK

1
0
0
0

low

high

38

Example 3: Determine the modulus of the following circuit.

M=?

1
0

0
1
0
1

0
0
1
0

01010100 84
01001010 74

0
0
1
0

1
0
1
0

M = 84 74 + 1 = 11
39

6.4.2 IC Counter 74160 (M-10)

8421BCD
Modulus-10, others are as same as 74161. 0
RCO = ENT Q3 Q0

When Q3Q2Q1Q0 = 1001,

RCO = 1

40

Example: Design a 60 s counter using 74160.

7416060

1
0

1
1

1
0
1
0

CLK
supply

5: 0101
41

6.4.3 IC Counter 74163 (M-16)

Synchronous clear function (0
other functions are as same as 74161 16
Synchronous clear 0: when CLR =0 and next CLK comes,
Q3 Q 2 Q1Q 0 =0000
Example:
Design a modulus -11 counter
using74163 synchronous clear
function. (CLR)
74163
11
Max state 1010
LD
74161

&

1
1

0
1
0
1
42

6.4.4 IC Counter 74290

1. 74290 Function
Modulus - 2 - 5 - 10 asynchronous counter (

Q0

Q1 Q2 Q3

M-2 counter, output Q0

1

CLK0

M-2

M-5

CLK1

T0 Q 0

CLK0

M-5 counter, output Q3Q2Q1

S9(1) S9(2) R0(1) R0(2)
J1 Q1

FF

CLK1 1 K1

J 3 Q3

T2 Q2
1

K3
43

Symbol

Function
(1) Asynchronous clear 0
When

S9(1) S9(2) = 0 (low)

R0(1) = R0(2) = 1 (high)
Q3Q2Q1Q0 = 0000

(2) Asynchronous set 9 9

When S9(1) = S9(2) = 1
Q3Q2Q1Q0 = 1001
(3) Count
Asynchronous input

When

S9(1) S9(2) = 0
R0(1) R0(2) = 0

CLK

44

2. Applications of 74290
(1) Modulus-2 Counters

0
0
0
0

S9(1) S9(2) = 0
R0(1) R0(2) = 0
CLK input from CLK0,
Q0 output, implement M-2

CLK

CLK

(2) Modulus-5 Counters

Q0
Q1
Q2
Q3

S9(1) S9(2) = 0
R0(1) R0(2) = 0
CLK input from CLK1, Q3Q2Q1 output, implement M-5

45

(3) 8421BCD Code Modulus-10 Counters

S9(1) S9(2) = 0 R0(1) R0(2) = 0
0
0
0
0

CLK input from CLK0,

Q0

CLK1

At the negative edge of Q0

(CLK1 changes from 1 to 0 ),
M-5 count.

CLK

1
2
4
8

CLK0
Q0

CLK1

M-5 counter
Weight of outputs
Q3Q2Q1Q0 : 8 4 2 1

1
CLK0

T0 Q0

J1 Q1

CLK1 1 K1

J3 Q3

T2 Q2

K3

46

(4) 8421 BCD Code Modulus- Counters

Using direct set 0 R0
Example : M-7 counter

8421 decimal

connect: 8421 BCD base 10

Q0 CLK1
S9(1) = S9(2) = 0

0
0

CLK CLK0
Output Q3Q2Q1Q0 = 0111
AND gate

CLK

AND gate R0 (direct clear)

1
1
1
0

Q3Q2Q1Q0 = 0111, 0
0111 glitch
70000 ~ 0110

&

47

(5) 8421 BCD Cascaded Counters

When the modulus >10

74290 cascade connection

Example:
Design a 8421BCD
code modulus-46
counter using 74290.
(6.9)

8421 decimal
carry out

6 (0110)

4 (0100)
48

or

carry out
Waveforms:

CP
Q0
Q1
Q2
Q3

Q310CLKCLK0

10

(Q0Q3)

49

6.10 32768
Hz741611 Hz
32768 = 215151 Hz
474161(4)Q2

1Hz

Frequency divided-by-24 device

28

212

215
50

(74161 74160 74163 74290)

Load-1
Clear

-1

74161160163RCOENT ENP
74290Q3CLK0

6.5

Registers

Register: A part of the CPU where groups of binary digits are stored as the computer is
processing them (e.g. D Flip-flop).
64-bit CPU (AMD64, IA-64): CPU GPRs(General-Purpose Registers)

6.5.1 Classifications of Registers

1. Parallel In/Parallel Out Registers /
4 D-FFs constitute a register
Q0

Q1

Q
D
D0

D
D1

Q3

Q2

Q
R

74LS175
Q

Q
R

D
D2

D
D3

R
CR
CLK

At CP positive edge, 4 input data parallel in

and state Q3Q2Q1Q0 = D3D2D1D0 parallel out

52

2. Serial In /Serial Out Shift Left Registers (/

Serial data output
Q3 D3

Q2 D2

Q1 D1

Q0 D0

DSL

Serial data input

1011
shift left

CLK

One CLK comes, shift left one bit.

CLK

Example
Q3Q2Q1Q0 =1001 initially
Serial in: 1011 (DSL ),

1
2
3
4

Serial
Q3Q2Q1Q0
out

1
0
0
1
1

1
0
0
1
1

0
0
1
1
0

0
1
1
0
1

1
1
0
1
1

Serial in

1011

after 4 CLK, Q3Q2Q1Q0 =1011

53

3. Serial In /Parallel Out Shift Left Registers (/)

Parallel out
Q3
Q3

Q2
D3

Q1
Q2

D2

Q0
Q1

D1

Q0

D0

DSL

Serial in

CLK

54

4. Shift Left Ring Registers (

The serial output is connected back to the serial input.

Q3

D3

Q2

D2

Q1

D1

Q0

D0

DSL

CLK

FF

0001
= ?

55

1
State diagram

0001

0010

1000

0100

The ring register is also called ring counter

Note: n FFs n states Modulusn
Waveforms

CLK
Q0
Q1
Q2
Q3
56

5. Shift Left Twisted-Ring Registers (

Q3

D3

Q2

D2

Q1

D1

Q0

Q 3 DSL

DSL

D0

Q3

CLK

Q3Q2Q1Q0 =0001 initially

0001
0000

0011
1000

state diagram
0111
1100

Q0Q1Q2Q3

1111
1110

Twisted-ring counter n FF Modulus- 2n

Johnson
counter
57

6. Serial In /Serial Out Shift Right Registers

DSR

D0 Q0

Shift right

D1 Q1

D2 Q2

D3 Q3

Serial out

CLK

7. Serial In /Parallel Out Shift Right Registers

Parallel out
Q0
DSR

D0 Q0

Q1
D1 Q1

Q2
D2 Q2

Q3
D3 Q3

CLK
58

8. Shift Right Ring Registers

DSR

D0 Q0

D1 Q1

D2 Q2

D3 Q3

CLK

Ring counter
9. Shift Right Twisted-Ring Registers

DSR

D0 Q0

D1 Q1

D2 Q2

D3 Q3
Q3

CLK

Twisted-ring counter
59

6.5.3 IC Register 74194

Multifunction register
Circuit P. 148

Symbol
Q0 Q1 Q2 Q3 M
1
DSR
M0
74194
DSL
CLK D0 D1 D2 D3

CLR

Q3Q2Q1Q0 data output

D3D2D1D0 data input
DSR DSL serial in
M1 M0 control (model)
IEEE

60

CLR = 0, direct reset

CLK positive edge triggered

74194 function
M1 M 0

Function

0
0
1
1

No change

0
1
0
1

Shift Right
Shift Left
Parallel In

Q0 Q1 Q2 Q3
D0 D1 D2 D3

9
61

(1) Parallel in/out

(2)Serial in/serial out shift left

1
1
1

1
0
1

CLK

CLK

D0
D1
D2
D3

Parallel
inputs

Q0
Q1
Q2
Q3

Parallel
outputs

Serial out
(shift left)

Serial in
shift left

62

(3)Serial in/parallel out shift left

1
0
1

CLK

Parallel outputs
Q0
Q1
Q2
Q3

Serial in
shift left

63

Q0 DSL

(4) Shift left ring register

Set M1 =1, M0 =1 first, parallel in at CLK rising edge,

Q0Q1Q2Q3 = D0D1D2D3 =0001
Then set M0 =0, CLK comes shift left M-4 counter

1
0

CLK

1
0001

Q0Q1Q2Q3
0010

0
0
0
1

1000

0100

64

(5) Shift left twisted-ring register

M1= 1,

1
0
1

1, parallel in
M0=

CLK

Q0Q1Q2Q3 = D0D1D2D3

0, twisted-ring

Q0 connect to DSL
1

D0D1D2D3

65

(6) Serial in/serial out

shift right register

(7) Serial in/parallel out

shift right register

1
1
0

1
1
0

CLK

CLK

Serial in
1 1 0 1

1
1
0
1

Serial in
shift right

Parallel
outputs

Serial out
shift right

After 4 CLKs
66

(8) Shift right ring register

1
1

CLK

Q3 DSR
M0 =1

0
0
0
1

M1 =

1, CP comes
Q0Q1Q2Q3 = D0D1D2D3
0, CP comes
shift right ring

Modulus 4 counter
67

(9) Shift right twisted-ring register

1
1

Q3 connect to DSR
M0= 1,

0
CLK

1, parallel in
M1=

Q0Q1Q2Q3 = D0D1D2D3

0, twisted-ring
D0D1D2D3

Only two kinds of state diagram

Q0Q1Q2Q3

0000

1000

1100

1110

0101

0010

1001

0100

0001

0011

0111

1111

1011

0110

1101

1010

D0D1D2D3

Modulus 8 counter68

Example 1. Design a M-6 ring counter using 74194

6 FFs

1
1

1
1

CLK
0
0

1
0
0
0

CLK

1
0
0
0

0
0

69

Example 2. Design a M-6 twisted-ring counter using 74194

and draw its state diagram.
3 FFs

Shift left

Q1Q2Q3
001

1
0
1
CLK

011

000

111
100

0
0
1

110

010

1
101
70

Homeworks:
6.1,

6.2 ,

6.8

6.12

6.19

6.21

6.3,

6.5K1=1,

6.15

71