ST7 Manual VI

BIN DCH T TI LIU ST7 USER GUIDE CA
STMICROELECTRONICS
TP.HCM, THNG 1 NM 2008
TI LIU HNG DN S DNG ST7 ST GROUP
MC LC
MC LC...................................................................................................................................... 2
TNG QUAN V VI IU KHIN........................................................................................... 5
I.
GII THIU KHI QUT V VI IU KHIN ..................................................................... 6
II.
PHN LOI ................................................................................................................................... 6
III.
CU TRC TNG QUAN CA VDK:.................................................................................. 7
VI IU KHIN ST7................................................................................................................... 9
I.
GII THIU ................................................................................................................................ 10
II.
S CHN .............................................................................................................................. 11
III.
S B NH V THANH GHI....................................................................................... 12
IV.
VNG NH LP TRNH FLASH (Flash Programming Memory). ................................. 14
1.
Gii thiu.........................................................................................................................14
2.
c im chnh (main features).................................................................................15
3.
Ch lp trnh (Programming Modes)....................................................................15
4.
Giao tip ICC (ICC Interface).....................................................................................16
5.
Bo v vng nh ( Memory Protection). ...................................................................16
6.
Ti liu lin quan (Related Documentation). ...........................................................17
7.
M t thanh ghi (Register description). .....................................................................17
V.
DATA EEPROM.......................................................................................................................... 17
1.
Gii thiu (Introduction). ..............................................................................................17
2.
c im chnh. ............................................................................................................18
3.
Truy xut b nh . ..........................................................................................................18
VI.
B X L TRUNG TM (Central Processing Unit).......................................................... 19
1.
Gii thiu.........................................................................................................................19
2.
c im chnh. ............................................................................................................19
3.
Cc thanh ghi ni. ........................................................................................................20
VII.
NGT........................................................................................................................................ 23
1.
Ngt mm khng che c .......................................................................................24
2.
Ngt ngoi ......................................................................................................................24
3.
Ngt thit b ngoi vi .....................................................................................................24
VIII.
CC CNG I/O : .................................................................................................................... 28
1.
Gii thiu:........................................................................................................................28
2.
Chc nng:....................................................................................................................28
3.
Thc thi cc cng I/O ..................................................................................................30
4.
Cc chn khng c s dng ................................................................................31
5.
Ch tit kim nng lng.......................................................................................31
6.
Ngt .................................................................................................................................31
IX.
CC THIT B NGOI VI C TCH HP: ................................................................ 31
1.
B nh thi Watchdog (WDG) : ................................................................................31
2.
B nh thi 12 bit t ng np li ..............................................................................33
3.
Giao tip ngoi vi ni tip (SPI) ...................................................................................45
4.
B chuyn i tn hiu tng t sang tn hiu s......................................................59
X.
TP LNH ASSEMBLER CA VI IU KHIN ST7 ......................................................... 65

1.
Cc lnh s hc.............................................................................................................65
2.
Cc lnh Logic ..............................................................................................................66
3.
Cc lnh x l bit............................................................................................................66
4.
Cc lnh nhy................................................................................................................67
5.
Cc lnh di chuyn d liu..........................................................................................68
6.
Mt s lnh khc............................................................................................................68
XI.
1.
CC CH INH A CH CA H VI IU KHIN ST7 ...................................... 71

nh a ch tc thi.....................................................................................................71
2.
nh a ch trc tip ngn..........................................................................................71
3.
nh a ch trc tip di.............................................................................................71
4.
nh a ch NO OFFSET INDEXED...............................................................................72
5.
nh a ch SHORT INDEXED ADDRESSING ..............................................................72
6.
nh a ch LONG INDEXED .......................................................................................72
7.
nh a ch gin tip ngn.........................................................................................72
8.
nh a ch gin tip di ............................................................................................72
9.
nh a ch SHORT INDIRECT INDEXED......................................................................73
10.
nh a ch LONG INDIRECT INDEXED ..................................................................73
11.
nh a ch tng i .............................................................................................73
12.
Thao tc trn bit........................................................................................................73
TNG QUAN V VI IU KHIN
I. GII THIU KHI QUT V VI IU KHIN

B Vi x l c kh nng vt bc so vi cc h thng khc v kh nng tnh ton, x l,
v thay i chng trnh linh hot theo mc ch ngi dng, c bit hiu qu i vi cc
bi ton v h thng ln.Tuy nhin i vi cc ng dng nh, tm tnh ton khng i hi
kh nng tnh ton ln th vic ng dng vi x l cn cn nhc. Bi v h thng d ln hay
nh, nu dng vi x l th cng i hi cc khi mch in giao tip phc tp nh nhau. Cc
khi ny bao gm b nh cha d liu v chng trnh thc hin, cc mch in giao tip
ngoi vi xut nhp v iu khin tr li, cc khi ny cng lin kt vi vi x l th mi
thc hin c cng vic. kt ni cc khi ny i hi ngi thit k phi hiu bit tinh
tng v cc thnh phn vi x l, b nh, cc thit b ngoi vi. H thng c to ra kh
phc tp, chim nhiu khng gian, mch in phc tp v vn chnh l trnh ngi thit
k. Kt qu l gi thnh sn phm cui cng rt cao, khng ph hp p dng cho cc h
thng nh.
V mt s nhc im trn nn cc nh ch to tch hp mt t b nh v mt s mch
giao tip ngoi vi cng vi vi x l vo mt IC duy nht c gi l Microcontroller-Vi iu
khin.
Mt s c im khc nhau gia vi x l v VK:
V phn cng: VXL cn c ghp thm cc thit b ngoi vi bn ngoi nh b nh, v
cc thit b ngoi vi khc, c th to thnh mt bn mch hon chnh. i vi VK th
bn thn n l mt h my tnh hon chnh vi CPU, b nh, cc mch giao tip, cc b
nh thi v mch iu khin ngt c tch hp bn trong mch.
V cc c trng ca tp lnh: Do ng dng khc nhau nn cc b VXL v VK cng
c nhng yu cu khc nhau i vi tp lnh ca chng. Tp lnh ca cc VXL thng mnh
v cc kiu nh a ch vi cc lnh cung cp cc hot ng trn cc lng d liu ln nh
1byte, byte, word, double word,... cc b VK, cc tp lnh rt mnh trong vic x l
cc kiu d liu nh nh bit hoc mt vi bit.
Do VK cu to v phn cng v kh nng x l thp hn nhiu soi vi VXL nn gi
thnh ca VXL cng r hn nhiu. Tuy nhin n vn kh nng p ng c tt c cc
yu cu ca ngi dng.
Vi iu khin c ng dng trong cc dy chuyn t ng loi nh, cc robot c chc
nng n gin, trong my git, t v.v...
II. PHN LOI

i. di thanh ghi
Da vo di ca cc thanh ghi v cc lnh ca VK m ngi ta chia ra

cc loi VK 8bit, 16bit, hay 32bit....
Cc loi VK 16bit do c di lnh ln hn nn cc tp lnh cng nhiu
hn, phong ph hn. Tuy nhin bt c chng trnh no vit bng VK 16bit
chng ta u c th vit trn VDK 8bit vi chng trnh thch hp
ii. Kin trc CISC v RISC
VXL hoc VDK CISC l VDK c tp lnh phc tp. Cc VDK ny c mt s
lng ln cc lnh nn gip cho ngi lp trnh c th linh hot v d dng
hn khi vit chng trnh.
VDK RISC l VDK c tp lnh n gin. Chng c mt s lng nh cc
lnh n gin. DO , chng i hi phn cng t hn, gi thnh thp hn, v
nhanh hn so vi CISC. Tuy nhin n i hi ngi lp trnh phi vit cc
chng trnh phc tp hn, nhiu lnh hn.
iii. Kin trc Harvard v kin trc Vonneumann
Kin trc Harvard s dng b nh ring bit cho chng trnh v d liu. Bus
a ch v bus d liu c lp vi nhau nn qu trnh truyn nhn d liu n
gin hn
Kin trc Vonneumann s dng chung b nh cho chng trnh v d liu.
iu ny lm cho VK gn nh hn, gi thnh nh hn.
Mt s loi VDK c trn th trng:
- VDK MCS-51: 8031, 8032, 8051, 8052, ...
- VDK ATMEL: 89Cxx, AT89Cxx51..
- VDK AVR AT90Sxxxx
- VDK PIC 16C5x, 17C43...
III. CU TRC TNG QUAN CA VDK:

i. CPU:
L tri tim ca h thng. L ni qun l tt c cc hot ng ca VK. Bn
trong CPU gm:
+ ALU l b phn thao tc trn cc d liu
+ B gii m lnh v iu khin, xc nh cc thao tc m CPU cn thc hin
+ Thanh ghi lnh IR, lu gi opcode ca lnh c thc thi
+Thanh ghi PC, lu gi a ch ca lnh k tip cn thc thi
+ Mt tp cc thanh ghi dng lu thng tin tm thi
ii. ROM:
ROM l b nh dng lu gi chng trnh. ROM cn dng cha s liu
cc bng, cc tham s h thng, cc s liu c nh ca h thng. Trong qu
trnh hot ng ni dung ROM l c nh, khng th thay i, ni dung ROM

ch thay i khi ROM ch xa hoc np chng trnh.
iii. RAM:
RAM l b nh d liu. B nh RAM dng lm mi trng x l thng tin,
lu tr cc kt qu trung gian v kt qu cui cng ca cc php ton, x l
thng tin. N cng dng t chc cc vng m d liu, trong cc thao tc
thu pht, chuyn i d liu.
iv. BUS:
BUS l cc ng dn dng di chuyn d liu. Bao gm: bus a ch, bus
d liu , v bus iu khin
v. B nh thi: c s dng cho cc mc ch chung v thi gian.
vi. Watchdog:
B phn dng reset li h thng khi h thng gp bt thng.
vii. ADC:
B phn chuyn tn hiu analog sang tn hiu digital. Cc tn hiu bn ngoi i
vo VDK thng dng analog. ADC s chuyn tn hiu ny v dng tn hiu
digital m VDK c th hiu c.
VI IU KHIN ST7
10
I. GII THIU
ST7LITE2 l thnh vin ca h vi iu khin ST7. Tt c thit b ST7 c bn da trn nhn 8 bit
chun cng nghip bnh thng, nt c bit l c mt tp lnh nng cao.
ST7LITE2 m t b nh Flash vi kh nng lp trnh in-circuit(ICP) v in-application (IAP)theo
khi tng byte mt.
Di s iu khin ca phn mm, thit b ST7LITE2 c th c t ch WAIT (i), SLOW
(chm), hay HALT (ngh), s tiu th nng lng gim xung khi ng dng trng thi nhn ri (idle)
hay tm ngh (stand by).
Tp lnh v ch nh a ch ca ST7 cho thy sc mnh v tnh linh hot i vi nhng ngi
pht trin phn mm, cho php thit k m ng dng ngn gn v t hiu qu cao. Thm vo , tt c
vi iu khin ST7 c c im tnh ton trn tng bit, tnh ton s khng du 8x8 v ch nh a ch
gin tip.
Thit b c mt module debug trn chip (DM) h tr debug trn mch(ICD-in-circuit debugging).
II. S CHN
11
12
III. S B NH V THANH GHI

Nh c thy trong figure 4, MCU c kh nng nh a ch n 64 k bytes b nh v c nhng
thanh ghi xut/nhp.
B nh bao gm 128 bytes nh v cc thanh ghi phn cng (Hardware register) xem bng 2, 384
bytes RAM, 256 bytes EEPROM v 8 kbytes b nh lp trnh. Khng gian b nh RAM dnh ti 128
bytes cho vng stack c nh a ch t 0180F ti 01FFh.
Nhng bytes a ch cao nht cha trng thi reset v bng vector ngt.
Vng nh Flash cha 2 sector(Figure 4) c nh x vo tm a ch cao nht v vy bng reset v
vector ngt c nh v sector 0 (F000h FFFFh).
Kch thc ca Flash sector 0 v nhng la chn thit b khc c nh dng bi option byte.
Quan trng (Important): vng nh dnh sn (reserved) khng bao gi c truy sut. Truy sut
vng nh ny c th c nhng nh hng khng lng trc c trn thit b.
13
14
Ghi ch: x = khng xc nh, R/W = c/ghi

Ch :
1. Ni dung ca thanh ghi DR ca cc cng giao tip I/O ch c th c c cu hnh ng
xut. Trong cu hnh ng nhp, gi tr ca cc chn I/O s c tr v thay v ni dung ca
thanh ghi DR.
2. Cc bit lin i vi nhng chn khng s dng phi c gi gi tr khi to ca n.
IV. VNG NH LP TRNH FLASH (Flash Programming Memory).

1. Gii thiu.
B nh ca ST7 s dng cng ngh Xflash( Extended Flash), Xflash l flash m rng, c th c
xa bng in v lp trnh theo byte hoc cho n khi 32 bytes song song.
Thit b Xflash c th c lp trnh off-board( c cm vo cng c lp trnh) hoc on-board ty
vo phng php lp trnh In-circuit programming hay In-application programming.
Vic t chc b nh theo ma trn cho php mi sector c lp trnh v xa khng nh hng n
sector khc.
15
2. c im chnh (main features).
ICP (In-circuit programming)
IAP (In-application programming)
ICT (In-circuit testing) - load v thc thi mu kim tra ng dng ca user trong Ram
Kch thc sector 0 c thit lp bi option byte
Bo v c v ghi
3. Ch lp trnh (Programming Modes).

ST7 c th c lp trnh theo 3 cch:
Lp trnh bnh thng, ch ny s dng Flash sector 0 v 1, option byte v data EEPROM
(nu c) c th c lp trnh hay xa .
In-Circuit Programming: ch ny s dng vng nh Flash sector 0 v 1, option byte v

EEPROM (nu c) c th c lp trnh hay xa khng cn tho thit b ra khi board ng dng.
In-Application programming: ch ny,vng nh sector 1 v d liu trong vng

EEPROM(nu c) c th c lp trnh hay xa m khng ly thit b ra khi board ng dng
trong lc ng dng ang chy.
3.1. In-circuit programming(ICP).
ICP s dng giao thc c gi l ICC (In-ccuit communication) cho php mt vi iu khin cm
trn board mch in (PCB-printed ccuit board) giao tip vi thit b lp trnh bn ngoi thng qua cp .
ICP hot ng theo 3 bc:
a ST7 vo ch ICC : iu ny c thc hin bng cch iu khin chui tn hiu c bit
thng qua chn ICCCLK/DATA trong lc chn RESET mc thp. khi ST7 vo ch ICC, n
tm thy vector RESET c bit ch ti b nh h thng ca c cha th tc giao thc ICC. Th
tc ny cho php ST7 nhn bytes t giao tip ICC.
Np code driver ICP vo trong ram t chn ICCDATA.
Thi hnh don m va np vo trong ram lp trnh vng nh FLASH.
Ph thuc vo on m c np vo ram , lp trnh vng nh FLASH c th b thay i (s bytes

chng trnh, nh v chng trnh, hay la chn giao tip tun t np chng trnh).
3.2. In-Application programming (IAP).
16
Ch ny s dng mt chng trnh iu khin IAP c np vo sector 0 bi ngi s dng

trc ( in ICP mode).
Ch ny c iu khin hon ton bi phn mm ca user. iu ny cho php n uyn chuyn
vi ng dng ca user.
Ch IAP c th c dng lp trnh mi vng nh tr secter 0, y l vng cm khng c
ghi hoc xa v n dng phc hi trong trng hp thc thi chng trnh b li.
4. Giao tip ICC (ICC Interface).

ICP cn ti thiu t 4 cho n 6 chn kt ni vi cng c lp trnh. Nhng chn ny l:
RESET: Reset thit b.
VSS : Devide power supply ground.
ICCCLK: Cng nhp d liu tun t ICC .
CLKIN/PB4: Chn nhn xung CLOCK t bn ngoi.
VDD: Ngun cung cp cho ng dng.
5. Bo v vng nh ( Memory Protection).

C hai kiu bo v vng nh khc nhau: bo v c v bo v ghi xa c dng bi c nhn.
5.1. Bo v c (read-out protection).
Bo v c, khi c chn cung cp s bo v da trn ngun gc ni dung vng nh chng trnh

v da trn truy sut ghi ti vng nh Flash.
Trong thit b Flash , s bo v ny c b i bi la chn ti lp trnh. Trong trng hp ny, c
b nh d liu E2 v b nh lp trnh c t ng xa v thit b c th c lp trnh li. bo v c
ph thuc vo loi thit b:
Trong thit b Flash , n c cho php v loi b thng qua bit FMP_R trong byte la chn
(option byte).
Trong thit b rom n c cho php bi la chn mt n c bit trong danh sch la chn
(option byte).
5.2. Bo v ghi xa vng nh Flash (Flash Write/eraser Protection).
Bo v ghi /xa , khi c thit lp th khng th overwrite v xa b nh chng trnh. N khng

dng vi d liu E2 . mc ch ca n cung cp ch bo mt cao cho ng dng v ngn chn mi
thay i ni dung vng nh.
17
Cnh bo: mi ln thit lp ch bo v ny, n c th khng bao gi c xa. Thit b Flash

c bo v ghi th khng ti lp trnh c na. bo v ghi/xa c cho php thng qua bit FMP_W
trong byte option.
6. Ti liu lin quan (Related Documentation).

c thm chi tit v lp trnh Flash v giao thc ICC, tham kho The ST7 Flash programming
reference manual v The ST7 ICC protocol reference manual.
7. M t thanh ghi (Register description).

Thanh ghi trng thi/iu khin Flash (Flash control/status register-FCSR)
C kh nng c /ghi.
Gi tr reset: 0000 0000 (00h)
RASS key th 1: 0101 0110 (56h)
RASS key th 2: 1010 1110 (AEh)
Ch : thanh ghi ny phc v cho lp trnh s dng ICP, IAP hay cc phng php lp trnh khc.
N iu khin lp trnh Flash v tc v xa.
Khi mt EPB hay cng c lp trnh khc c s dng( in socket or ICP mode), the RASS keys
c gi mt cch t ng.
V. DATA EEPROM
1. Gii thiu (Introduction).
B nh ch c c kh nng lp trnh xa bng in(EEPROM) c dng lu tr d liu. S
dng EEPROM yu cu mt giao thc truy xut c bn c m t trong chng ny.
18
2. c im chnh.
Ln n 32 byte c lp trnh trong cng chu k
EEPROM in th n (mono-voltage)
Chu k lp trnh v xa
iu khin ni ca chu k lp trnh ton cc
Qun l ch WAIT
Bo v c
3. Truy xut b nh .
Ch truy xut c /ghi vng nh DATA EEPROM c iu khin bi bit E2LAT ca thanh ghi
trng thi/ iu khin EEPROM(EECSR). Biu trong hnh 7 m t nhng ch truy xut vng nh
khc nhau.
Tc v c( Read Operation [E2LAT = 0]).
EEPROM c th c c nh b nh ROM bnh thng khi bit E2LAT ca thanh ghi EECSR
c xa.
19
i vi ST7, DATA EEPROM cng c th c dng thc thi m my. Trnh ghi ln vng nh
DATA EEPROM khi n ang thc thi lnh, iu ny c th dn ti mt on code khng c mong
i c thc thi.
Tc v ghi (E2LAT = 1)
truy xut ch ghi, bit E2LAT phi c lp bi phn mm( bit E2PGM cn li c xa)
VI. B X L TRUNG TM (Central Processing Unit).

1. Gii thiu.
CPU c kin trc 8-bit v c 6 thanh ghi ni cho php tnh ton d liu 8 bits mt cch hiu qu.
2. c im chnh.
63 lnh c bn.
C kh nng nhn 8 bit vi 8 bit nhanh.
17 ch nh a ch chnh.
Hai thanh ghi nh ch s 8 bits.
Thanh ghi stack pointer 16 bits.
Ngt phn cng c th che.
Ngt phn mm khng th che.
20
3. Cc thanh ghi ni.

Su thanh ghi ni c ch trong hnh 10 th khng xut hin trong vng b nh v c truy xut
bng nhng cu lnh c bit.
THANH GHI TCH LY (Accumulator-A):
Thanh ghi A l mt thanh ghi dng chung 8-bit thng dng cha ton hng v kt qu ca cc
php ton s hc v logic v dng tnh ton.
THANH GHI CH S (X v Y):
Trong ch nh a ch bng ch s, hai thanh ghi 8 bits ny thng dng to ra nhng a ch
trc tip hoc cha kt qu tm thi cho vic tnh ton .Thanh ghi Y khng b nh hng bi lnh gi
nhng chng trnh con( khng push vo hoc pop ra stack).
Program counter(PC): PC l thanh ghi 16-bit cha a ch ca lnh k tip c thc thi bi
CPU. N c to bi hai thanh ghi 8-bit, PCL l 8 bits thp, PCH l 8 bits cao
CONDITION CODE REGISTER (CC):
21
c / Ghi.
Gi tr khi to : 111x1xxx
Thanh ghi CC 8-bit cha trng thi ngt qung v 4 c trng thi ca kt qu va c tnh ton.
Thanh ghi ny c th c iu khin bi lnh push v pop.
Nhng bit ny c th c truy xut ring r hay c iu khin bi nhng cu lnh c bit.
Bit H (half cary): Bit ny c lp bi phn cng khi c nh xut hin gia bit 3 v 4 trong ALU
khi thc hin lnh ADD hoc ADC. N cng c reset bi phn cng khi thc hin nhng lnh trn.
H = 0: khng c half carry xut hin.
H = 1: c half carry xut hin.
Bit ny c kim tra bng lnh JRH hoc JRNH . bit H rt c ch trong chng trnh BCD.
Bit I (interrup mask): Bit ny c lp bi phn cng khi bc vo interrup hoc bng phn mm
kha tt c interrup ngoi tr interrup mm TRAP. Bit ny c xa bi phn mm
I = 0: cho php ngt
I = 1: cm ngt
Bit ny c iu khin bi lnh RIM,SIM,IRET v c kim tra bi lnh JRM v JRNM.
Bit N (Negative): Bit ny c set v clear bi phn cng. n biu din du kt ca qu ca php
ton s hc , n chnh l bit th 7 ca kt qu.
0: kt qu ca php tnh cui cng l dng hoc bng 0.
1: kt qu ca php tnh cui cng l m.
Bit ny c truy sut bi lnh JRMI v JRPL.
Bit Z (zero): Bit ny c lp v xa bi phn cng. bit ny ch ra rng kt qu ca php ton l 0.
0: kt qu php ton khc khng.
1: kt qu php ton bng khng.
Bit ny c truy xut bi lnh kim tra JREQ v JRNE.
22
Bit C (nh/mn): Bit ny c lp v xa bi phn cng v phn mm. n ch ra rng c trn

hoc mn xy ra khi thc hin php ton s hc.
0: khng c nh hoc mn xut hin.
1: c nh hoc mn xut hin.
Bit ny c iu khin bi lnh SCF, RCF v kim tra bi lnh JRC v JRNC. N cng b nh
hng bi lnh dch v quay.
STACK POINTER (SP) :
c / ghi.
Gi tr khi to: 01FFh
Stack pointer l mt thanh ghi 16 bits lun lun ch n byte k tip trong vng stack. N b gim
i sau khi y d liu vo vng stack v tng ln sau khi ly d liu ra khi vng stack( Figure 11) .
Vng stack c 128 bytes c a ch t 0180h ti 01FFh . Sau khi reset MCU hay sau lnh reset
stack(RSP) con tr stack cha gi tr 01FFh( bit sp0 n sp6 c lp) a ch cao nht ca vng
stack .
Ch : khi vt qua a ch thp ca vng stack(0180h) con tr stack s ch n a ch cao nht
ca stack(01FFh) , v vy d liu trc s b ghi ln v b mt. Trng hp tng t khi stack
vt qua a ch cao nht ca stack.
Stack thng dng lu a ch tr v khi gi chng trnh con (tr v PC ca lnh tip theo li
gi chng trnh con ) v ng cnh CPU( PC+X+A+CC) khi c interrup .
23
VII. NGT
Nhn ST7 c th b ngt bi mt hoc hai yu t khc nhau: Cc ngt phn cng c th che
v ngt phn mm khng th che (TRAP). Lu qu trnh ngt c ch ra trong Figure 20.
Ngt c th che phi c khi ng bng cch gn 0 cho bit I c th c phc v. Tuy
nhin, vic v hiu ngt c th c cht v v tin hnh khi n chng c kch hot.
Ch : Sau khi reset, tt c cc ngt b v hiu ha.
Khi mt ngt c phc v:
Qu trnh bnh thng b nh ch sau khi thc thi xong lnh hin ti.
Cc thanh ghi PC, X, A v CC c lu vo trong stack.
Bit I ca thanh ghi CC c gn 1 ngn khng cho thm lnh ngt no c thc hin.
Thanh ghi PC c np gi tr vector ngt ca lnh ngt c phc v v lnh u tin
ca th tc phc v ngt s c tm np.
Th tc phc v ngt nn c kt thc bng cu lnh IRET phc hi trng thi cc thanh
ghi c a vo stack. Sau lnh IRET, bit I c xa v 0 v chng trnh chnh c phc
hi.
Qun l quyn u tin
Mc nh, mt phc v ngt khng th b ngt qung v bit I c gn gi tr 1 bi phn cng
bt u mt tc v ngt.
24
Trong trng hp khi mt vi ngt c din ra ng thi, quyn u tin do phn cng ch
nh s quyt nh mt trong s c thc hin trc.
Ngt v Ch tit kim nng lng
Tt c cc ngt cho php b x l thot khi ch tit kim nng lng WAIT. Ch c mt
s cc ngt ngoi c kh nng cho php b x l thot khi ch tit kim nng lng HALT.
1. Ngt mm khng che c

Ngt ny c bt u khi cu lnh TRAP c thc thi m khng cn quan tm n trng
thi ca bit I. N s c phc v nh trong lu Figure 20.
2. Ngt ngoi
Vector ngt ngoi c th c np vo thanh ghi PC nu xy ra s kin ngt ngoi tng ng
v bit I c xa v 0. Nhng ngt ny cho php b x l thot khi ch tit kim nng lng
HALT
Cc tnh ngt ngoi c chn thng qua thanh ghi hn hp hoc thanh ghi ngt (nu c)
Mt ngt ngoi c kch hot s c cht v yu cu ngt s t ng b xa khi bt u th
tc phc v ngt.
3. Ngt thit b ngoi vi

Cc c ngt thit b ngoi vi khc nhau trong thanh ghi trng thi c th gy ra ngt khi
chng c kch hot nu c 2 iu kin:
25
Bit I trn thanh ghi CC c gi tr 0.

Bit kch hot tng ng c gn gi tr 1 trn thanh ghi iu khin.
Nu mt trong hai iu kin trn khng tha mn, Ngt s b kha v i cho n khi tha
mn.
Xa mt yu cu ngt c thc hin theo mt trong cc cch sau:
Ghi gi tr 0 vo bit tng ng trn thanh ghi trng thi

Truy xut thanh ghi trng thi trong khi c c gn 1 v tip sau l c hoc ghi mt
thanh ghi kt hp.
Ch : Qu trnh xa trn s reset li cht ni. V th cc ngt ang trong trng thi i s b
mt nu qu trnh trn c thc thi.
THANH GHI EXTERNAL INTERRUPT CONTROL (EICR)

c/Ghi
Gi tr khi to : 0000 0000 (00h)
Bit 7:6 = IS3[1:0] -tnh nhy ei3
26
Nhng bit ny ch ra tnh nhy ngt cho ei3 (Cng B0) theo nh bng 6.
Nhng bit ny ch ra tnh nhy ngt cho ei2 (Cng B3) theo nh bng 6.
Nhng bit ny ch ra tnh nhy ngt cho ei1 (Cng A7) theo nh bng 6.
Nhng bit ny ch ra tnh nhy ngt cho ei0 (Cng A0) theo nh bng 6.
Ch :
Thanh ghi 8 bit ny ch c th c ghi khi bit I trn thanh ghi CC c gn gi tr 1.

Thay i nhy ca mt ngt ngoi s xa ngt ang trong trng thi ch ny. iu
ny c th c s dng xa nhng ngt khng mong mun ang trong trng thi
ch.
THANH GHI EXTERNAL INTERRUPT SELECTION (EISR)

c/Ghi
Gi tr khi to: 0000 1100 (0Ch)
Bit 7:6 = ei3[1:0] Chn chn ei3

Cc bit ny c ghi bng phn mm. Chng lc chn cc chn giao tip cng B c s
dng cho ngt ngoi ei3 nh bng di y.
27

Cc bit ny c ghi bng phn mm. Chng lc chn cc chn giao tip cng B c s
1) Trng thi reset
1) Trng thi reset

2) PB4 khng th c s dng nh mt ngt ngoi trong ch HALT
Cc bit ny c ghi bng phn mm. Chng lc chn cc chn giao tip cng A c s
* Trng thi reset

Cc bit ny c ghi bng phn mm. Chng lc chn cc chn giao tip cng A c s
* Trng thi reset

Bit 1:0 = c dnh sn
28
VIII. CC CNG I/O :

1. Gii thiu:
Cc cng I/O dng truyn d liu. Mi cng c th cha n 8 chn. Mi chn u c th
c lp trnh l cng xut hay cng nhp. Bn cnh , mt s chn c th cn c cc chc
nng khc.
2. Chc nng:
Mi cng u c mt thanh ghi Data (DR) v mt thanh ghi Data Direction (DDR). Thanh
ghi Option (OR)- Thanh ghi dng quy nh cng xut hay nhp- th c th c cung cp
hoc khng.
Mi chn I/O c lp trnh vi cc bit tng ng trn cc thanh ghi DDR, DR hay OR: bit x
tng ng vi chn x ca cng.
29
2.1. Ch cng nhp
Gn 0 cho bit DDRx tng ng vi vic chn chn x l cng nhp. ch ny, bit DR s
cha gi tr t chn I/O tng ng.
Bit OR (nu c) dng thit lp cc ch cho cng nhp: th ni (floating) hay ko ln
(pull-up).
Ch :
1. Ghi gi tr vo thanh ghi DR s lm sa i gi tr ca cht (latch) nhng khng lm thay
i trng thi ca chn nhp.
2. Khng s dng cc lnh c/sa/ghi (BSET/BRET) sa gi tr thanh ghi DR
30
Ty vo thit b, c th thit lp mt cng I/O nh l mt cng nhn tn hiu ngt bng cch
gn gi tr 1cho bit ORx tng ng. chc nng ny mt tn hiu kch cnh hoc mt tn hiu s
trn cng nhp s sinh ra mt yu cu ngt thng qua vector ngt tng ng.
Vic nhn tn hiu kch cnh ln hay xung s c lp trnh c lp cho mi vector ngt.
Thanh ghi External Interrupt Control (EICR) hoc thanh ghi hn hp (Miscellaneous) s iu
khin cc trng thi ny, ty vo tng thit b.
2.2. Ch cng xut
Thit lp mt chn l cng xut bng cch gn 0 cho bit DDRx tng ng. Vic ghi bit DR
s gn mt gi tr s vo cng I/O thng qua cht. Vic c bit DR s tr v gi tr c cha
trc .
2.3. Chc nng thay th (alternative function):
Rt nhiu cng I/O c mt hoc nhiu chc nng alternate. Vic ny c th bao gm xut tn
hiu t, hoc nhn tn hiu vo mt thit b ngoi vi on-chip. Bng m t chn s m t tn hiu
ca thit b ngoi vi no c th l tn hiu xut/ nhp n cng no.
Mt tn hiu n t mt thit b ngoi vi on-chip c th l tn hiu xut trn mt chn I/O.
lm iu ny, chng ta s kch hot thit b ngoi vi on-chip nh l mt cng xut ( thit lp bit
trong thanh ghi Control ca thit b ngoi vi). Khi vic thit lp cc thit b ngoi vi s c u
tin cao hn vic thit lp cc cng I/O tiu chun. Trng thi ca cng I/O c th c c
a ch ca thanh ghi Data DR ca chn I/O tng ng.
Khi I/O c thit lp chc nng alternate th n s c th ni (floating), v nu trng
thi ko ln (pull-up) s lm tng s tiu th in nng. Trc khi s dng I/O nh mt cng
nhp alternate, phi thit lp n khng c ngt. Nu khng vic ngt c th b sai lch.
Cc cng I/O m c th c thit lp chc nng alternate cho c cc tn hiu tng t ln
cc tn hiu s th cn thm mt s ch c bit. Ngi s dng phi iu khin cc thit b
ngoi vi sao cho cc tn hiu khng n cng mt thi im ti cng mt chn.
3. Thc thi cc cng I/O

Vic thc thi phn cng trn mi cng I/O ph thuc vo vic thit lp cc thanh ghi DDR
hoc OR v chc nng ca cc cng I/O c bit nh cng nhp ADC.
Chuyn i trng thi ca cc cng I/O t trng thi ny sang trng thi khc nn c thc
hin trong mt chui s kin c bo v khi cc hiu ng l khng mong i. Cc chuyn i
an ton c lit k trong Figure 32 di y.Nhng chuyn i khc c kh nng ri ro v nn
trnh v chng c th c nhng hiu ng l nh vic sinh cc ngt b sai lch.
31
4. Cc chn khng c s dng

Nhng chn khng c s dng phi c gn vi cc mc in th c nh.
5. Ch tit kim nng lng

C hai ch : Ch WAITv HALT. cc ch ny, cc cng I/O khng c bt c
hiu ng hay s thi hnh no. Cc ngt ngoi s gii phng thit b khi ch tit kim nng
lng.
6. Ngt
Mt s kin ngt ngoi xut hin khi cc bit tng ng cc thanh ghi DDR v OR l 1 v
bit I trong thanh ghi CC b xa v 0 (lnh RIM).
IX. CC THIT B NGOI VI C TCH HP:

1. B nh thi Watchdog (WDG) :
1.1. Gi i thiu :
B nh thi Watchdog c dng pht hin cc s c li phn mm, xy ra do mt tc

nhn bn trong hay mt iu kin lun l khng bit trc khin chng trnh ng dng hot
ng khng theo trnh t bnh thng. B phn Watchdog s to s kin reset MCU vo cui
mt khong thi gian nh trc, nu chng trnh khng np li ni dung ca b m trc khi
bit T6 tr v 0
1.2. Cc c im chnh:
B m li t do kh lp trnh
Reset kh lp trnh
Reset (nu watchdog c kch hot) khi bit T6 tr v 0
C th chn reset ch HALT (tit kim nng lng) (thit lp bng cch chnh sa
byte option)
Phn cng Watchdog c th c chn bng Option Byte
32
1.3. M t chc nng:
Gi tr b m c cha trong thanh ghi CR (bit T[6:0]), gim sau mi 16000 chu k my,
v di khong thi gian m c th c lp trnh bi ngi s dng.
Nu watchdog c kch hot ( bit WDGA c gi tr 1) v khi b m 7-bit T[6:0] m ngc t
40h v 3Fh (T6 tr v 0), n s reset lai MCU ( thi gian trung bnh l 30.10-6s).
Chng trnh ng dng phi thit lp gi tr cho thanh ghi CR trong nhnng khong thi gian
u n trnh vic MCU b reset. B m c s dng l mt b m chy c lp: n m
xung c khi watchdog b v hiu. Gi tr trong thanh ghi CR phi nm gia FFh v C0h :
Bit WDGA c gi tr 1 (watchdog c kch hot)

Bit T6 phi c gi tr 1 MCU khng b reset
Cc bit T[5:0] cha gi tr s m, th hin khong thi gian cn li trc khi watchdog
reset MCU
Sau mt ln reset, watchdog s b v hiu ha. Sau khi c kch hot, khng th v hiu ha
li watchdog, tr khi MCU c reset
33
1.4. Chn WatchDog bng phn cng
Nu phn cng Watchdog c la chn bi Option Byte th watchdog s lun c kch

hot v bit WDGA trong thanh ghi CR s khng c s dng.
1.5. Ngt
Khng s dng ngt i vi thit b ngoi vi Watchdog

1.6. M t thanh ghi iu khin (CR)
Gi tr khi to: 0111 1111 (7Fh)
Bit 7 = Bit kch hot WDRA

Bit ny c gn gi tr l 1 bng phn mm v ch b xa bng phn cng sau khi reset
Khi WDGA =1, watchdog c kch hot, c th sinh tn hiu reset MCU
WDGA =0, watchdog b v hiu ha
Bit WDGA khng c s dng nu watchdog c chn trong Option Byte.
Bit 6:0 = T[6:0] - b nh thi 7-bit
Nhng bit ny cha gi tr m xung. MCU s c reset khi n m t 40h ti 3Fh ( T6
tr v 0)
2. B nh thi 12 bit t ng np li
2.1. Gii thiu
B nh thi 12 bit t ng np li c th c s dng cho cc mc ch ni chung v thi

gian. N da trn mt b m ln chay c lp 12-bit vi mt thanh ghi bt tn hiu nhp v bn
knh ng ra PWM. C 6 chn giao tip vi bn ngoi:
Bn ng ra PWM
Chn ATIC cho chc nng bt tn hiu nhp

Chn BREAK
2.2. c im chnh
Mt b m 12 bit vi thanh ghi 12 bit t ng np li (ATR)

C th s dng ngt trn
Sinh 4 tn hiu PWMx c lp
Tn s 2KHz-4KHz
Duty-cycles c th lp trnh c
iu khin cc tnh (polarity)
Ch ng xut c th lp trnh c
C th s dng ngt so snh
Bt tn hiu nhp
Thanh ghi bt tn hiu nhp 12 bit (ATICR)
Kch hot mt qu trnh bng tn hiu kch cnh ln hoc kch cnh xung.
C th s dng ngt IC
34
35
2.3. M t chc nng
Ch PWM
Ch ny cho php cc chn ng xut PWMx sinh ln n 4 tn hiu Pulse Width
Modulated (xung c iu chnh rng). Cc ng xut PWMx c th c kch hot hoc v
hiu bng cc bit OEx trong thanh ghi PWMCR
Tn s PWM v Duty Cycle
Bn tn hiu PWM c chung mt tn s (fPWM) c iu khin bi chu k b m v gi tr
thanh ghi ATR.
fPWM = fCOUNTER / (4096 ATR)
Theo cch thc di y,
Nu fCOUNTER l 32 MHz, th gi tr ti a ca fPWM l 8 MHz (Gi tr ATR = 4092), gi

tr ti thiu l 8 MHz ( Gi tr ATR = 0)
Nu fCOUNTER l 4 MHz, th gi tr ti a ca fPWM l 2 MHz (Gi tr ATR = 4094), gi tr
ti thiu l 1 MHz ( Gi tr ATR = 0)
Gi tr ln nht ca ATR l 4094 v n phi thp hn gi tr DCR trong trng hp ny l

4095
Lc khi ng, b m bt u m t 0.
Khi b m ln b trn (s kin OVF), gi tr Duty Cycle c np trc c chuyn vo
thanh ghi Duty Cycle (DCR) v cc tn hiu PWMx c gn mc cao. Khi b m ln t n
gi tr DCRx th tn hiu PWMx c gn mc thp. thu c tn hiu trn chn PWM, th
ni dung ca thanh ghi DCRx tng ng phi ln hn ni dung ca thanh ghi ATR
Cc bit cc tnh c th c dng o ngc tn hiu bt k trong 4 tn hiu xut. Qu
trnh o ngc c ng b vi vic trn s m nu bit TRAN trn thanh ghi TRANCR c
gn gi tr 1 (gi tr khi to).
36
Ch so snh ng xut
s dng chc nng ny, np mt gi tr 12-bit vo thanh ghi DCRxH v DCRxL. Khi b
m ln CNTR t n gi tr cha trong cc thanh ghi DCRxH v DCRxL, bit CMPF trong
thanh ghi PWMxCSR s c gn 1 v mt yu cu ngt c sinh nu bit CMPIE c gn 1.
Ch : Chc nng so snh ng xut ch c hiu lc khi gi tr DCRx khc 0 (gi tr khi to).
Chc nng Gin on (Break)
Chc nng Gin on c s dng shutdown trong tnh trn khn cp.
Chc nng Gin on c kch hot bi mt chn BREAK (tch cc mc thp). s dng
chn BREAK th trc phi gn gi tr 1 cho bit BPEN trong thanh ghi BREAKCR bng
phn mm.
Khi chn BREAK xut hin gi tr mc thp, bit BA s c gn 1 v chc nng Gin on
s c kch hot
Phn mm c th gn gi tr 1 cho bit BA kch hot chc nng gin on m khng cn s
dng chn BREAK.
Khi chc nng gin on c kch hot (Bit BA = 1):
Khun mu Gin on (Cc bit PWM[3:0] trong thanh ghi BREAKCR) c gn vo

cc chn xut PWMx (sau khi qua b o).
B m 12 bit PWM c gn gi tr khi to.
ARR, DCRx v cc thanh ghi tng ng c gn gi tr khi to.
Thanh ghi PWMCR c reset.
Khi chc nng Gin on b v hiu sau khi thc hin gin on (bit BA c chuyn t 1
sang 0), vic iu khin cc ng xut PWM c chuyn sang cho cc thanh ghi Ng giao tip
(Port Register).
37
Bt tn hiu nhp
Thanh ghi 12 bit ATICR c s dng cht gi tr ca b m ln 12 bit chy t do sau
mt kch cnh ln hay xung c nhn thy trn chn ATIC. Khi mt s kin bt tn hiu xy
ra, bit ICF c gn 1 v thanh ghi ATICR cha gi tr ca b m ln. Mt ngt IC s c
sinh nu bit ICIE c gn gi tr 1. Thanh ghi ATICR l mt thanh ghi ch c v lun cha gi
tr ca b m ln chy t do vo thi im bt tn hiu ng nhp gn nht. Hn na vic bt tn
hiu nhp s b chn trong khi bit ICF c gi tr 1.
38
2.4. Ch tit kim nng lng
Ch SLOW: Tn s ng vo c chia cho 32

Ch WAIT: B nh thi AT khng hot ng
Ch ACTIVE-HALT: B nh thi AT tm ngh tr khi CK0=1,CK1=0 v OVFIE=1
Ch HALT: B nh thi AT tm ngh
2.5. Ngt
S kin CMP v IC cng nh x n mt vector ngt nh nhau.

S kin OVF c nh xa n mt vector ring.
Cc s kin trn s sinh tn hiu ngt nu bit kch hot c gn vo thanh ghi ATCSR v
mt n ngt trn thanh ghi CC c reset (Lnh RIM)
2.6. M t cc thanh ghi
THANH GHI TIMER CONTROL STATUS (ATCSR)

c/Ghi
Gi tr khi to: 0x00 0000 (x0h)
39
Bit 7 = c dnh sn.

Bit 6 = ICF - C bt tn hiu nhp.
Bit ny c gn gi tr 1 bng phn cng v gn v 0 bng phn mm khi c thanh ghi
ATICR (Khi c gi tr ca thanh ghi ATICRH hoc ATICRL s lm c chuyn v 0). Vic ghi
gi tr ln bit ny s khng lm thay i gi tr ca n.
0: Khng c s kin bt tn hiu nhp no.
1: Mt s kin bt tn hiu nhp xy ra.
Bit 5 = ICIE - Khi ng ngt IC.
Bit ny c gn gi tr 0, 1 bng phn mm.
0: V hiu ha ngt IC (input capture)
1: Khi ng ngt IC
Bit 4:3 = CK[1:0] Chn xung b m
Nhng bit ny c gn gi tr 1 bng phn mm v 0 bng phn cng (sau khi reset). Cc
bit ny dng chn tn s xung ca b m
Bit 2 = OVF C trn

Bit ny c gn 1 bng phn cng v 0 bng phn mm khi c thanh ghi TCSR. N ch ra
s chuyn gi tr b m t FFFh sang gi tr ATR
0: Khng c s kin trn b m.
1: C s kin trn b m.
Bit 1 = OVFIE Khi ng ngt trn
Bit nay c c hoc ghi bng phn mm v c xa v 0 bng phn cng, sau khi reset
0: Ngt CMPF b v hiu
40
1: Ngt CMPF c kch hot

THANH GHI COUNTER LOW (CNTRL)
Ch c
Gi tr khi to: 0000 0000 (00h)
THANH GHI COUNTER HIGH (CNTRL)

c/Ghi
Gi tr khi to: 0000 0000 (00h)
Bit 15:12 = c dnh sn

Bit 11:0 = CNTR [11:0] Gi tr b m.
Thanh ghi 12 bit ny c c bng phn mm v xa v 0 bng phn cng sau khi c
reset. B m bt u tng lin tc ngay sau khi mt xung b m c chn. thu c gi tr
12 bit, phn mm nn c gi tr b m trong hai tc v c k tip nhau, LSB trc. Khi mt
s kin trn b m xy ra, b m s bt u li t gi tr c ch nh trn thanh ghi ATR.
THANH GHI AUTORELOAD HIGH (ATRH)
c/Ghi
Gi tr khi to: 0000 0000 (00h)
THANH GHI AUTORELOAD LOW (ATRL)

c/Ghi
Gi tr khi to: 0000 0000 (00h)
41
Bit 11:0 = ATR[11:0] Thanh ghi t ng np li.

y l mt thanh ghi 12 bit c ghi bng phn mm. Gi tr thanh ghi ATR c np mt
cch t ng vo b m ln khi xy ra trn b m. Gi tr thanh ghi c s dng thit lp
tn s PWM.
THANH GHI IU KHIN NG XUT PWM OUTPUT CONTROL (PWMCR)
c/Ghi
Gi tr khi to: 0000 0000 (00h)
Cc bit 7:0 = OE[3:0] - khi ng ng xut PWMx.

Nhng bit ny c gn gi tri 1 hoc 0 bng phn mm v b gn 0 bng phn cng sau khi
reset.
0: ch PWM b v hiu ha.
1: ch PWM c kch hot.
THANH GHI PWMx CONTROL STATUS (PWMxCSR)
c/ Ghi
Gi tr khi to: 0000 0000 (00h)
Bit 7:2 = c dnh sn, phi lun trng thi 0.

Bit 1 = OPx -Cc tnh ng xut PWMx .
Bit ny c c/ ghi bng phn mm v b gn 0 sau khi reset. Bit ny dng lc chn cc
tnh cho tn hiu PWM.
0: Tn hiu PWM khng b o cc tnh.
42
1: Tn hiu PWM b o cc tnh.

Bit 0 = CMPFx -C so snh PWMx.
Bit ny c gn 1 bi phn cng v gn 0 bng phn mm khi c thanh ghi PWMxCSR.
N cho bit khi no gi tr ca b m ln t n gi tr ca thanh ghi DCRx.
0: Gi tr b m ln cha bng gi tr thanh ghi DCR.
1: Gi tr b m ln t n gi tr thanh ghi DCR.
THANH GHI BREAK CONTROL (BREAKCR)
c/ Ghi
Gi tr khi to: 0000 0000 (00h)
Bit 7:6 = c dnh sn. Lun gi tr 0.

Bit 5 = BA Kch hot gin on .
Bit ny c c/ ghi bng phn mm, b gn 0 bng phn cng sau khi reset v gn mt
bng phn cng khi chn BREAK mc thp. N dng kch hot hoc v hiu chc nng
gin on.
0: Gin on khng c kch hot
1: Gin on c kch hot.
Bit 4 = BPEN Kch hot chn Break
Bit ny c c/ghi bng phn mm v b gn 0 sau khi reset.
0: Chn break b v hiu ha
1: Chn break c kch hot.
Bit 3 = PWM[3:0] Mu hnh ngt.
Cc bit ny c c/ghi bi phn mm v b gn 0 sau khi reset. Chng c s dng
thit lp trng thi n nh cho tn hiu ng xut PWMx khi chc nng Gin on c kch
hot.
THANH GHI PWMx DUTY CYCLE HIGH (DCRxH)
c/ Ghi
Gi tr khi to: 0000 0000 (00h)
43
THANH GHI PWMx DUTY CYCLE LOW (DCRxL)

c/ Ghi
Gi tr khi to: 0000 0000 (00h)
Bit 15:12 = c dnh sn.

Bit 11:0 = DCR[11:0] Gi tr Duty Cycle PWMx
Gi tr 12 bit ny c ghi bng phn mm. N ch ra gi tr Duty Cycle ca tn hiu ng
xut PWM tng ng.
ch PWM (OEx= 1 trn thanh ghi PWMCR), cc bit DCR[11:0] ch ra Duty Cycle ca
tn hiu ng xut PWM tng ng. ch So snh ng xut, n cha gi tr c so snh vi
gi tr ca b m ln 12 bit.
THANH GHI INPUT CAPTURE HIGH (ATICRH)
Ch c.
Gi tr khi to: 0000 0000 (00h)
THANH GHI INPUT CAPTURE LOW (ATICRL)

Ch c.
Gi tr khi to: 0000 0000 (00h)
Cc bit 15:12 = c dnh sn.

Cc bit 11:0 = ICR[11:0] D liu bt ng vo.
44
y l mt thanh ghi 12 bit c th c c bi phn mm v b gn 0 sau khi reset. Thanh

ghi ATICR cha gi tr b bt ca thanh ghi 12 bit CNTR khi c tn hiu kch cnh ln hoc
xung chn ATIC. Vic bt tn hiu ch c thc hin khi c ICF c gi tri 0.
THANH GHI TRANSFER CONTROL (TRANCR)
c/ Ghi
Gi tr khi to: 0000 0001 (01h)
Cc bit 7:1 = c dnh sn. Lun c gi tr 0.

Bit 0 = TRAN Kch hot truyn
Bit ny c c/ ghi bng phn mm, b gn 0 bi phn mm sau mi ln hon thnh vic
truyn v gn 1 sau khi reset.
45
3. Giao tip ngoi vi ni tip (SPI)

3.1. Gi i thiu
Thit b giao tip ngoi vi ni tip SPI cho php truyn thng ni tip ng b v song cng
hon ton vi mt thit b bn ngoi. Mt h thng SPI c th cha mt Master v mt hoc
nhiu Slave hoc ch cha mt trong hai.
3.2. c im chnh
Truyn song cng, ng b (trn 3 tuyn)

Truyn n cng, ng b (trn 2 tuyn)
Thao tc Master hay Slave
Su tn s ch master (fCPU /4 max.)
Tn s ch slave (fCPU /2 max.)
Qun l SS bng phn mm hoc phn cng
Pha v cc tnh xung c th lp trnh c
46
C ngt kt thc truyn

Ghi xung t, Li Ch Master v c trn
3.3. M t chung
Hnh 42 ch ra s bn trong ca mt SPI. C 3 thanh ghi:

Thanh ghi SPI Control (SPICR)
Thanh ghi SPI Control/Status (SPICSR)
Thanh ghi SPI Data (SPIDR)
SPI c ni vi thit b bn ngoi thng qua 3 chn:
MISO: d liu Master In/ Slave Out
MOSI: d liu Master Out / Slave In
SCK: Xung ni tip ng xut bi SPI master v ng nhp bi SPI slave
SS: Chn slave:
Tn hiu xut ny cho php SPI master giao tip vi cc slave ring l v trnh cc xung t
d liu trn cc tuyn d liu. Cc ng nhp slave SS c th c iu khin bi cc cng giao
tip chun trn thit b master.
47
M t chc nng
Mt v d n gin ca vic ni gia mt master n v mt slave n c minh ha trong

hnh 43
48
Cc chn MOSI c ni vi nhau v cc chn MISO cng c ni vi nhau. Theo cch

ny th d liu c truyn mt cch ni tip gia master v slave (bit c trng s cao c thc
hin trc).
Vic giao tip lun lun c bt u bng master. Khi thit b master truyn d liu n
mt thit b slave thng qua chn MOSI, thit b slave s hi m bng vic gi d liu ti thit b
master thng qua chn MISO. Theo , y l mt giao tip song cng, vi hai d liu xut v
nhp c ng b vi cng mt tn hiu xung (c cung cp bi thit b master thng qua
chn SCK).
s dng tuyn d liu n, cc chn MISO v MOSI phi c kt ni ti mi nt (trong
trng hp ny ch c th l giao tip n cng).
Bn mi quan h nh thi d liu/ xung clock c th c th c chn (hnh 46) nhng
master v slave phi c lp trnh vi cng mt ch nh thi
Qun l vic chn slave
Nh mt s thay th cho vic dng chn SS iu khin tn hiu chn slave, chng trnh
ng dng c th qun l tn hiu chn slave bng phn mm bng cch thit lp gi tr cho bit
SSM trong thanh ghi SPICSR
49
Khi chn slave bng phn mm bng cch s dng bit CSS trong thanh ghi SPICSR, chn SS
c t do s dng cho cc ng dng khc.
ch Master:
Tn hiu SS bn trong phi lun c gi mc cao.
ch Slave:
C hai trng hp ph thuc vo mi quan h inh thi d liu/xung clock
Nu CPHA=1 (d liu b kha cnh th 2 ca xung clock):
Tn hiu SS bn trong phi c gi mc thp trong sut qu trnh truyn. N ch ra

rng trong cc ng dng slave n, chn SS c th c ni trc tip vo VSS, hoc c
t do lm mt cng giao tip chun v thay th bng vic s dng phn mm qun
l tn hiu chn slave (SSM=1 v SSI=0 trong thanh ghi SPICSR)
Nu CPHA=0 (d liu c kha cnh th nht ca xung clock):
Tn hiu SS bn trong phi c gi mc thp trong sut byte c truyn v c ko

ln mc cao gia cc byte cho php slave ghi vo thanh ghi dch chuyn (shift
register). Nu SS khng c ko ln mc cao th s xut hin li xung t ghi khi slave
ghi vo thanh ghi dch chuyn.
50
Qu trnh hot ng ch Master
Trong ch master, xung clock ni tip c xut trn chn SCK. Tn s xung clock, cc
tnh v pha c nh cu hnh bng phn mm bi thanh ghi SPICSR.
Ch : Trng thi nhn ri ca SCK phi tng ng vi cc tnh c chn trn thanh ghi
SPICSR (SCK c ko ln cao nu CPOL = 1 v ko xung thp nu CPOL = 0).
thao tc SPI ch master, thc hin theo cc bc theo trt t :
Ghi gi tr cho thanh ghi SPICR:

Chn tn s xung clock bng cch thit lp cc bit SPR[2:0].
Chn cc tnh xung clock v pha xung clock bng cch thit lp cc bit CPOL v CPHA.
Figure ch ra bn cch nh cu hnh c th s dng.
Ch : Slave phi c cng cc gi tr CPOL v CPHA nh master.
Ghi gi tr vo thanh ghi SPICSR:
Gn gi tr 1 cho bit SSM v bit SSI hoc gn 0 cho bit SSM v ni chn SS vi mc cao
hon thnh qu trnh truyn byte
Ghi gi tr vo thanh ghi SPICR:
Gn cc bit MSTR v SPE bng 1
Ch : MSTR v SPE ch c gn khi SS mc cao
Qu trnh truyn bt u khi phn mm ghi 1 byte ln thanh ghi SPIDR.
Qu trnh chuyn ch master
Khi phn mm ghi vo thanh ghi SPIDR, byte d liu c np vo thanh ghi dch chuyn 8bit v sau c dch chuyn mt cch ni tip vo chn MOSI theo th t bit c trng s cao
thc hin trc.
Khi qu trnh truyn d liu hon thnh:
Bit SPIF c gn 1 bi phn cng.
Mt yu cu ngt c sinh nu bit SPIE mang gi tr 1 v mt n ngt trn thanh ghi
CCR b xa.
51
Vic xa bit SPIF v 0 c thc hin sau mi qu trnh sau y:
Mt truy cp n thanh ghi SPICSR trong khi SPIF ang c gi tr 1.

c thanh ghi SPIDR
Ch : Trong khi SPIF c gi tr 1, tt c cc qu trnh ghi vo thanh ghi APIDR b ngn

chn, cho n khi thanh ghi SPICSR c c.
Bit SPIR c th b xa v 0 trong sut mt qu trnh truyn k tip ; tuy nhin, n phi phi
c gn v 0 trc bit SPIF th hai trnh hin tng Overrun ( trn)
3.4. Pha v cc tnh xung clock
Bn mi quan h nh thi c th c chn bng phn mm, s dng cc bit CPOL v

CPHA (Figure 46). S kt hp ca cc bit cc tnh xung CPOL v pha xung CPHA s la chn
vic bt tn hiu s c kch hot do tn hiu kch cnh ln hay xung.
Hnh 46 trnh by mt qu trnh truyn SPI vi bn cch kt hp ca cc bit CPHA v
CPOL.
3.5. C li
Li ch Master (MODF)
Li ch master xy ra khi mt thit b master c chn SS b ko xung mc thp.

Khi li ch master xy ra:
Bit MODF c gn 1 v mt yu cu ngt SPI s c sinh nu bit SPIE =1.

Bit SPE b reset. N ngn chn tt c cc ng xut ca thit b v v hiu ha SPI.
Bit MSTR b reset, v buc thit b chuyn sang ch slave.
Vic xa bit MODF v 0 c thc hin bng phn mm, qua qu trnh sau:
52
53
Truy xut c thanh ghi SPICSR trong khi MODF ang c gi tr 1.

Ghi vo thanh ghi SPICR.
Ch : trnh bt k xung t no khi ng dng c nhiu slave, chn SS phi c ko ln

mc cao trong sut qu trnh xa bit MODF v 0. Cc bit SPE v MSTR c th phc hi v trng
thi nguyn thy trong sut hoc sau qu trnh ny.
Phn cng khng cho php ngi dng ghi 1 vo cc bit SPE v MSTR trong khi bit MODF
c gn 1 tr khi ang trong qu trnh gn bit MODF v 0 trn.
mt thit b slave, bit MODF khng th c gn 1, nhng trong mt cu hnh a master
th cc thit b c th ch slave vi bit MODF =1.
Bit MODF ch ra rng c th c mt xung t gia cc master v cho php phn mm
iu khin n bng cch s dng th tc ngt v reset h thng hoc tr v trng thi mc nh.
Trng thi Overrun (trn) (OVR)
Mt trng Overrun din ra khi thit b master gi mt byte d liu m thit b slave cha xa
bit SPIF- c thay i trong ln truyn byte trc .
Khi xy ra li Overrun:
Bit OVR c gn 1 v mt yu cu ngt s c sinh nu bit SPIE = 1.
Trong trng hp ny, b m nhn cha gi tr byte c gi sau ln cui cng bit SPIF
c gn gi tr 0. Vic c thanh ghi SPIDR s tr v gi tr ca byte ny. Tt c nhng byte
khc s b mt.
Bit OVR s b xa v 0 khi cc tc v c thanh ghi SPICSR.
Li xung t ghi(WCOL)
54
Mt li xung t ghi xy ra khi phn mm c gng ghi ln thanh ghi SPIDR trong khi mt
qu trnh truyn d liu ang c thc hin vi mt thit b bn ngoi. Khi iu xy ra, qu
trnh truyn tip tc c thc hin cn tc v ghi s khng thnh cng.
Xung t ghi c th xy ra c master ln slave.
Ch : Mt xung t c s khng bao gi xy ra v d liu nhn c c t vo b
m- ni m mi truy cp lun c ng b vi tc v ca CPU
Bit WCOL trong thanh ghi SPICSR s c gn 1 nu xy ra xung t ghi.
S khng c ngt SPI no c sinh khi bit WCOL vn cn gi tr 1
Vic xa bit WCOL v 0 c thc hin thng qua mt trnh t cc thao tc phn mm (hnh
47).
Cu hnh mt master nhiu slave
C hai loi h thng SPI:
H thng n master
H thng a master
Mt h thng n master in hnh vi mt thit b master v bn thit b slave c trnh

by trong hnh 48.
Thit b master la chn cc thit b slave ring bit bng cch s dng bn chn ca cng
song song iu khin bn chn SS ca cc thit b slave.
Cc chn SS c ko ln mc cao trong sut qu trnh reset lm cho cc cng giao tip ca
thit b master phi tr thnh ng nhp, khi cc thit b slave s b v hiu ha.
Ch : ngn chn nhng xung t ng truyn trn tuyn MISO, thit b master ch cho
php mt thit b slave c kch hot trong sut mt qu trnh truyn.
55
tng an ton, cc thit b slave c th hi m li cc thit b master vi cc byte d liu

nhn c. Khi master s nhn byte trc li t thit b slave nu tt c cc chn MISO
v MOSI u c kt ni v cc slave khng ghi vo thanh ghi SPIDR ca n.
Ngi s dng cng c th cu hnh mt h thng c nhiu master. H thng a master ny
ch yu c iu khin bng cc bit trong thanh ghi SPICR v bit MODF trong thanh ghi
SPICSR.
3.6. Ch tit kim nng lng
Ch WAIT: SPI khng hot ng. Thit b s thot khi ch WAIT bng s kin ngt.
Ch HALT: Cc thanh ghi SPI b ng bng
ch HALT, SPI khng c kch hot. Chc nng SPI c phc hi khi thit b c
nh thc bi mt lnh ngt c chc nng gii phng khi ch HALT.
3.7. Ngt
56
Cc s kin ngt SPI c nh x ti cng mt vecter ngt. Chng s sinh mt tn hiu ngt
nu bit Enable Control tng ng c gn 1 v mt n ngt trong thanh ghi CC c reset
(lnh RIM).
3.8. M t thanh ghi
THANH GHI CONTROL (SPICR)

c/Ghi
Gi tr kh to: 0000 xxxx (0xh)
Bit 7 = SPIE Cho php ngt SPI.

Bit ny dc gn 1 hay 0 bng phn mm.
0: Ngt b chn.
1: Mt ngt SPI c sinh khi kt thc vic truyn thng, li ch master, hoc li Overrun
(SPIF=1,MODF=1 hay OVR=1 trong thanh ghi SPICSR)
Bit 6 = SPE- Cho php ng xut SPI
Bit ny c gn gi tr 1 hoc 0 bng phn mm. N cng c gn 0 bng phn cng khi
SS=0 ch master. Bit SPE b gn 0 sau khi reset, v khi SPI s c php kt ni vi cc
chn bn ngoi.
0: Cc cng I/O c t do cho cc mc ch xut nhp ni chung
1: Chn xut nhp ca SPI s kch hot chc nng alternate (tr thanh cng giao tip cho
SPI)
Bit 5 = SPR2- Kch hot b chia
Bit ny c gn 0 hay 1 bng phn mm v b gn 0 sau khi reset. N c s dng vi cc
bit SPR[1:0] thit lp gi tr baud rate
0: b chia 2 c kch hot
1: b chia 2 khng c kch hot
Ch : Bit ny khng c tc ng trong ch slave.
Bit 4 = MSTR -Ch master
Bit ny c gn 1 hoc 0 bng phn mm. N cng c gn 0 bng phn cng khi SS=0
trong ch master.
57
0: ch slave.
1: ch master. Chc nng ca chn SCK chuyn t mt ng nhp thnh mt ng xut v
chc nng ca cc chn MISO v MOSI th ngc li.
Bit 3 = CPOL Cc tnh xung
Bit ny c gn gi tr 1 hoc 0 bng phn mm. Bit ny xc nh trang thi nhn ri ca
xung ni tip. Bit CPOL tc ng c trong ch master ln ch slave
0: Chn SCK c trng thi nhn ri mc thp.
1: Chn SCK c trng thi nhn ri mc cao.
Bit 2 = CPHA Pha xung clock
Bit ny c gn 0 hoc 1 bng phn mm.
0: Kch cnh bt tn hiu c tnh l s chuyn trng thi u tin ca xung clock
1: Kch cnh bt tn hiu c tnh l s chuyn trang thi ln th hai ca tn hiu.
Ch : Slave phi c cng thit lp CPOL v CPHA nh master
Bit 1:0 = SPR[1:0] Tn s xung clock
Cc bit ny c gn gi tr bng phn mm. c s dng cng vi bit SPR2, chng dng
la chn gi tri baud rate ca xung ng ra ni tip SCK ch master.
Note: Hai bit ny khng c tc ng trong ch slave
THANH GHI CONTROL/STATUS (SPICSR)

c/Ghi (Mt s bit ch c)
Gi tr khi to : 0000 0000 (00h)
58
Bit 7 = SPIF C truyn d liu (ch c)

Bit ny c gn 1 bi phn cng khi qu trinh truyn c hon tt. Mt ngt s c sinh
nu SPIE= 1 trong thanh ghi SPICR. N c xa bi mt qu trnh phn mm (mt truy cp
n thanh ghi SPICSR theo sau bi vic c thanh ghi SPIDR).
0: Truyn d liu ang c thc hin hoc c b gn gi tr 0.
1: D liu c truyn gia cc thit b, v c mt thit b bn ngoi c truyn hon tt.
Bit 6 = WCOL Trng thi xung t ghi (ch c)
Bit ny c gn 1 bi phn cng khi vic ghi vo thanh ghi SPIDR dc thc hin trong
mt qu trnh truyn. N c xa bi mt qu trnh phn mm (hnh 47)
0: Khng c s xung t ghi no xy ra.
1: C mt xung t ghi c phat hin.
Bit 5 = OVR Mi Overrun SPI ( ch c)
Bit ny c gn 1 bi phn cng khi byte hin ti c nhn trong thanh ghi dch chuyn
sn sng c chuyn vo thanh ghi SPIDR trong khi SPIF =1. Mt ngt s c sinh nu
trong thanh ghi SPICR , bit SPIE=1.
0: Khng c li Overrun.
1: Pht hin li Overrun.
Bit 4 = MODF - C li ch master (ch c).
Bit ny c gn 1 bi phn cng khi chn SS b ko xung mc thp trong ch master.
Mt ngt SPI s c sinh nu trong thanh ghi SPICR , bit SPIE=1. Bit ny c xa v 0 bng
mt qu trnh phn mm ( Mt truy cp ti thanh ghi SPICSR trong khi MODFF =1, theo sau
l vic ghi vo thanh ghi SPICR).
0: Khng c li ch master no c pht hin.
1: Mt li ch master c pht hin.
Bit 3 = c dnh sn, phi gi gi tr 0.
Bit 2 = SOD V hiu ha ng xut SPI
Bit ny c gn 1 hoc 0 bng phn mm. Khi c gn 1, n v hiu ha chc nng
alternate ca ng xut SPI (MOSI ch master/MISO ch slave)
0: Ng xut SPI c kch hot (nu SPE = 1).
1: NG xut SPI b v hiu ha.
Bit 1= SSM- Qun l SS.
59
Bit ny c gn 0 hoc 1 bng phn mm. Khi c gn 1, n v hiu ha chc nng

alternate ca chn SS v s dung gi tr ca bit SS thay th.
0: iu khin bng phn cng (iu khin SS bng chn ngoi).
1: iu khin bng phn mm ( iu khin tn hiu SS bn trong bng bit SS. Chn ngoi SS
s c t do thc hin cc mc ch I/O chun).
Bit 0= SSI Ch SS ni
Bit ny c gn 0 hoc 1 bng phn mm. N hot ng nh mt chip seclect dng
la chon slave hot ng.
0: Slave c la chn.
1: Slave khng c la chn.
THANH GHI XUT NHP D LIU (SPIDR)
c/Ghi
Gi tr khi to: Khng c nh ngha
Thanh ghi SPIDR c s dng truyn v nhn d liu trn cc tuyn ni tip. thit b
master, vic ghi gi tr vo thanh ghi ny s bt u vic truyn,nhn ca byte khc.
Ch : Trong sut chu k xung clock cui cng bit SPIF c gn gi tr 1, mt bn sao ca
byte d liu nhn c trong thanh ghi dch chuyn s c chuyn vo b m. Khi ngi dng
c thanh ghi xut nhp d liu SPIDR th trn thc t d liu trn vng m s c c. Tuy
nhin, vic ghi gi tr ln thanh ghi SPIDR s gn gi tr trc tip ln thanh ghi dch chuyn
truyn i.
4. B chuyn i tn hiu tng t sang tn hiu s

4.1. Gii thiu
60
B chuyn i t tn hiu tng t sang tn hiu s (ADC) l mt mt chuyn i tun t xp

x vi mu ni v xoay vng. ADC c ln ti 7 knh nhp tn hiu tng t a thnh phn, cho
php n c th chuyn i cc mc in p tng t t 7 ngun khc nhau.
Kt qu chuyn i c cha trong Thanh ghi D liu 10 bit (10 bit Data Register). B
chuyn i A/D c iu khin thng qua mt thanh ghi iu khin trng thi (Control/Status
Register).
4.2. Cc c im chnh
B chuyn i 10 bit
Ln ti 7 knh vi ng nhp a thnh phn (multiplexed input)
Xp x lin tc tuyn tnh
Thanh ghi D liu (DR) cha kt qu
C trng thi bo chuyn i hon tt
Bit bt/tt ( tit kim nng lng)
4.3. M t chc nng

4.3.1. Ngun nng lng tng t
VDDA v VSSA l mc cao hay thp tng ng vi mc in p ca cc chn. Trong mt vi

thit b n c kt ni bn trong vi cc chn VDD v VSS.
chnh xc ca vic chuyn i v th c th b nh hng bi vic rt in p v nhiu khi
ti qu nng hoc s dng ngun khng hp l.
61
4.3.2. B khuch i in p nhp
Mc in p nhp c th c khoch i bi h s 8 bng cch gn bit AMPSEL trn thanh

ghi ADCDRL bng 1.
Khi b khoch i c kch hot, phm vi ng nhp l 0V n VDD /8.
V d, nu VDD =5V, th ADC c th chuyn i mc in p trong khong 0V n 430 mV
vi phn gii l tng l 0,6 mV (ngang vi phn gii 13 bit trong khong VSS n VDD ).
Ch : B khuych i c iu khin bt hay tt l nh vo bit ADON trn thanh ghi
ADCSR, v th khng cn thm thi gian khi ng khi s dng b khuych i.
4.3.3. Kt qu chuyn i
Qu trnh chuyn i l monotonic, c ngha l kt qu chuyn i s khng tng nu tn

hiu tng t ng vo khng tng v ngc li.
Nu in p ng vo (VAIN) ln hn VDDA (tham chiu in p mc cao) th kt qu chuyn
i l FFh trong thanh ghi ADCDRH v 03h trong thanh ghi ADCDRL (trong thanh ghi
ADCDRH v ADCDRL l 00 00h (khng c du hiu bo trn).
62
Nu in p ng vo (VAIN) nh hn VDDA (tham chiu in p mc thp) th kt qu chuyn

i trong thanh ghi ADCDRH v ADCDRL l 00 00h.
B chuyn i A/D l tuyn tnh v kt qu s ca vic chuyn i c lu trong cc thanh
ghi ADCDRH v ADCDRL.
RAIN l tr khng ln nht c khuyn co cho mt tn hiu tng t ng vo. Nu tr
khng qu cao s lm gim chnh xc do vic ly mu khng hon thanh trong thi gian c
phn cng.
4.3.4. Chuyn i AD
Cc ng nhp tn hiu tng t phi c cu hnh nh l ng nhp, khng ko ln, khng

ngt. Tham kho chng Cc cng xut nhp (I/O). S dng cc chn ny nh l cc ng nhp
tn hiu tng t khng lm nh hng n kh nng c c nh l mt cng nhp logic.
Trong thanh ghi ADCCSR:
- Chn cc bit CS[2:0] quy nh cc knh tng t cn chuyn i.
Ch Qu trnh chuyn i ADC
Trong thanh ghi ADCCSR:
Gn bit ADON bng 1 kch hot b chuyn i ADC v khi ng qu trnh chuyn i.
T lc ny, ADC s thc hin mt qu trnh chuyn i lin tc cc knh c chn.
Khi mt qu trnh chuyn i hon thnh:
Bit EOC c gn 1 bi phn cng.
Kt qu c cha trong thanh ghi ADCDR.
Vic c thanh ghi ADCDRH s xa bit EOC v 0.

c 10 bit ni trn, thc hin theo cc bc sau:
1. Thm d bit EOC
2. c thanh ghi ADCDRL
3. c thanh ghi ADCDRH. Vic ny s xa bit EOC v 0 mt cch t ng.
4.3.5. Ch tit kim nng lng
Ch : B chuyn i A/D c th b v hiu ha khi gn 0 cho bit ADON. c im ny cho

php tit kim nng lng tiu th khi khng c qu trnh chuyn i cn thit no v gia hai
qu trnh chuyn i n.
Ch WAIT: B chuyn i A/D khng hot ng
63
Ch HALT: B chuyn i A/D b v hiu ha. Sau khi thot khi ch Halt, B
chuyn i A/D cn mt thi gian n nh tSTAB trc khi c th thc hin qu trnh
chuyn i mt cch chnh xc)
4.4. Ngt
Khng c ngt i vi thit b ADC.

4.5. M t thanh ghi
Thanh ghi iu khin trng thi (ADCCSR)

c/Ghi (tr bit th 7 ch c)
Gi tr khi to: 0000 0000 (00h)
Bit 7 = EOC Kt thc qu trnh chuyn i

Bit ny c gn 1 bi phn cng. N c xa v 0 bng phn mm khi c thanh ghi
ADCDRH.
0: Qu trinh chuyn i cha hon thnh
1: Qu trnh chuyn i hon thnh
Bit 6 = ADON B chuyn i A/D bt
Bit ny c gn 1 hoc 0 bng phn mm
0: B chuyn i A/D v b khuych i c tt
1: B chuyn i A/D v b khuych i c bt
Bit 4:3 = c dnh ring. Phi c gi bng 0.
Bit 2:0 = CH[2:0] Chn knh
Cc bit ny c gn 1 hoc 0 bng phn mm. Chng la chn ng nhp tng t
chuyn i.
64
Ch : S lng knh ph thuc vo loi thit b
THANH GHI D LIU CAO (ADCDRH)

Ch c
Gi tr khi to: xxxx xxxx (xxh)
Bit 7:0 = D[9:2] - Cc MSB ca kt qu chuyn i

Bit 4 = AMPCAL Bit chnh b khuych i
Bit ny c gn gi tr 1 hay 0 bng phn mm. Ngi s dng c ngh s dng bit
ny chnh ADC khi b khuych i c bt. Khi gn bit ny bng 1 th ng ra ca b
khuych i s c lin kt ni vi 0v. Khi , ng ra ADC tng ng c th c s dng
loi tr li amplifier-offset.
0: Tt chnh
1: Bt chnh (in p ng vo ca b khuych i c gn 0v)
Bit 3= SLOW Ch chm (SLOW)
Bit nay c gn 1 hoc 0 bng phn mm. N c s dng cng vi bit SPEED thit
lp tc xung clock cho ADC, c ch ra bng sau.
Bit 2 = AMPSEL- Bit chn b khuych i

0: B khuych i c chn
65
1:B khuych i khng c chn

Bit 1:0 = D[1:0] LSB ca gi tr kt qu
Ch
MHz
Khi
AMPSEL=1
th
bt
buc
FADC
phi
nh
X. TP LNH ASSEMBLER CA VI IU KHIN ST7

1. Cc lnh s hc
ADC d,s : Cng d vi s, v c nh

d <= d+s+C
Dest l thanh ghi A, Source l mem. Flags H,N,Z,C
ADD d,s : Cng s vo d
d <= d+s
Dest l thanh ghi A, Source l mem. Flags H,N,Z,C
SBC d,s : Tr d bi s v c nh
d <=d-s-C
Dest l A. Source l mem. Flags N,Z,C
SUB d,s : tr d cho s
d <=d-s
Dest l A. Source l mem. Flag N,Z,C
MUL d,s : Nhn d bi s
d:s <=d*s
Dest l A,X,Y. Source l A,X,Y. Flags H=0,C=0
DEC d : tng d.
d <= d+1.
Dest l reg, mem. Flags N,Z
INC d : gim d.
d <= d-1.
Dest l reg, mem. Flags N,Z
CP d,s : So snh s hc
{N,Z,C} = Test (d-s)
Dest l reg, source l mem. Flags N=0,Z=1
hn
hoc
bng
2. Cc lnh Logic
AND d,s : And d v s

d <= d AND s
Dest l thanh ghi A, Source l mem. Flags N,Z
OR d,s : OR d vi s
d <=d OR s
Dest l A. Source l mem. Flags N,Z
XOR d,s : Exclusive OR d v s
d <= d XOR s
Dest A. Source mem. Flag N,Z
CPL d : B s hc ca d.
d <= d XOR FF.
Dest l reg, mem. Flags N,Z,C=1
NEG d : ph nh ca d (phn b 2)
d <= (d XOR FF) + 1 or 00 d
Dest l reg, mem. Flags N,Z,C
RLC d: Quay tri (gm c bit nh)
Dest l reg, mem. Flag N,Z,C

RRC d: Quay phi (gm c bit nh)

SLA : Dich tri i s (bng vi SLL d=1)

SLL : Dich tri lun l

SRA : Dich phi i s (bng vi SLL one)

SRL : Dich phi lun l
Dest l reg, mem. Flag N=0,Z,C
SWAP d: Swap nibbles (???)
d(7:4) <=> d(3:0)
3. Cc lnh x l bit
BRES d,b : reset bit cho d

d <= d AND (2**b)
Dest l mem
BSET d,b : set bit cho d
d <= d OR (2**b)
66
Dest l mem
CLR d : Xa d.
d <= 00.
Dest l reg, mem. Flags N=0,Z=1
BCP d,s : So snh bt ca thanh ghi A vi mem
{N,Z} <= s AND d
Dest l thanh ghi A, Source l mem. Flags N,Z
RCF : reset c nh
C = 0. Flag C=0
WFI : Ch ngt .Flag I =0
RSP : reset stack pointer
SP = reset value
SCF : Thit lp c nh
C=1
RIM: Reset mt n chng ngt
I=0
SIM : Thit lp mt n chng ngt
I=1
4. Cc lnh nhy
JP d : nhy tuyt i n d.
PC <= d.
Dest l mem.
JRA d : nhy tng i mt on d. (always ???)
PC <= PC + d.
Dest l mem.
JRT d : nhy tng i nu true.
PC <= PC + d.
Dest l mem.
JRF d : khng bao gi nhy (???).Dest l mem.
BTJF d,b,rel : Nhy nu bit l false
PC=PC+rel IF (d AND (2**b))=0
Dest l mem. Flags C
BTJF d,b,rel : Nhy nu bit l true
PC=PC+rel IF (d AND (2**b))!=0
Dest l mem. Flags C
JRIH d : Nhy nu Port INT pin = 1. (no port interrupts)??
JRIL d : Nhy nu Port INT pin = 0. (port interrupts)??
JRH d : nhy nu H=1
H = 1? . Dest l mem
JRNH d : nhy nu H=0
H = 0? . Dest l mem
JRM d : nhy nu I=1
I= 1? . Dest l mem
JRNH d : nhy nu I=0
I = 0? . Dest l mem
67
JRMI d : nhy nu N=1

N= 1? (tr) . Dest l mem
JRPL d : nhy nu N=0
N = 0? (cng).
JREQ d : nhy nu Z=1
Z= 1? (bng) . Dest l mem
JRNE d : nhy nu Z=0
Z = 0? (khng bng). Dest l mem
JRC d : nhy nu C=1
C= 1? . Dest l mem
JRNC d : nhy nu C=0
C = 0? . Dest l mem
JRULT d : nhy nu C=1
Nhy nu unsigned < . Dest l mem
JRUGE d : nhy nu C=0
Nhy nu unsigned >= . Dest l mem
JRUGT d : nhy nu C + Z=0
Nhy nu unsigned > . Dest l mem
JRULE d : nhy nu C + Z=1
Nhy nu unsigned <= . Dest l mem
5. Cc lnh di chuyn d liu
LD d,s : Load s vo d
d <=s
Dest l reg, mem. Source l mem, reg. Flags N,Z
POP d : Ly phn t nh stack
d <= (++SP)
Dest l reg,CC. Flags H,I,N,Z,C
PUSH d : y phn t vo nh stack
o (--SP) <= d
Source l reg,CC.
6. Mt s lnh khc
CALL d : Gi th tc con . Dest l mem

CALLR d : Gi th tc con relative?? (tng i). Dest l mem
RET : Tr v th tc con
MSB(PC)=(++SP)
LSB(PC)=(++SP)
HALT : tm ngh, tm dng. Flag l I=0
IRET : Tr v trng thi trc khi ngt.
Pop CC,A,X,PC. Flag: H,I,N,Z,C
NOP : khng ton t (???)
Dest reg, mem. Flag N,Z
TNZ d: Kim tra Neg & Zero
68
69
{N,Z} = Test (d)

Dest reg, mem. Flag N,Z
TRAP : Ngt (phn mm) . Flag I =1
Cc t kha:
d:
Destination
s:
Source
SP :
16 bit Stack pointer
PC :
Program Counter
CC:
Condition
Code
Register
<= , <=> :
Chuyn ni dung ca
mt v tr n v tr khc
A:
Accumulator register
X:
X index register
Y:
Y index register
ndx :
X or Y index register
reg :
mem :
rel:
b:
an 8 bit file register
Flag :
H:
I:
N:
Z:
C:
A, X or Y register
Memory location
Relative jump label
Bit address within
Haft carry bit
Interrupt mask bit
Negative bit
Zero bit
Carry/Borrow bit
1. .BELL (Ring bell on console) .BELL

2. BYTE (Define byte in object code) BYTE <exp or "string">,[,<exp or "string">]
3. BYTES (Label type definition: type = byte) BYTES
4. CEQU (Equate pre-existing label to expression label) CEQU <equ>
5. .CTRL (Send control codes to the printer) .CTRL <ctrl> [,<ctrl>]
6. DATE (Define 12-byte ASCII date into object code) DATE
7. DC.B (Define byte(s) in object code) DC.B <exp> or "string">, [,<exp or "string">]
8. DC.W (Define word(s) in object code) DC.W <exp>[,<exp>]
9. DC.L (Define long word(s) in object code) DC.L <exp>[,<exp>]
10. #DEFINE (Define manifest constant) #DEFINE <CONSTANT ID> <real characters>
11. DS.B (Define byte space in object code) DS.B [optional number of bytes]
12. DS.W (Define word space in object code) DS.W [optional number of words]
13. DS.L (Define long space in object code) DS.L [optional number of long words]
14. END (End of source code) END
15. EQU (Equate the label to expression label) EQU <EXPRESSIONS>
16. EXTERN (Declare external labels) EXTERN
17. #ELSE (Conditional ELSE) #ELSE
18. #ENDIF (Conditional terminator) #ENDIF
19. FCS (Form constant string) FCS <"string"> |<byte> ["string"> |<byte>|]...
20. .FORM (Set form length of the listing device) .FORM <exp>
21. GROUP (Name area of source code) GROUP <exp>
22. #IF (Start conditional assembly) #IF <exp>
23. #IF1 (IF condition that must be satisfied in pass #1 to be true ) #IF1
24. #IF2 (IF condition that must be satisfied in pass #2 to be true) #IF2
70
25. #IFB (Conditional on argument being blank ) #IFB <arg>

26. #IFIDN (Conditional on arguments being identical) #IFIDN <arg-1> <arg-2>
27. #IFDEF (Conditional on argument being defined) #IFDEF <exp>
28. #IFLAB (Conditional on argument being a label ) #IFLAB <arg>
29. #INCLUDE (Insert external source code file) #INCLUDE "filename>"
30. INTEL (Force Intel-style radix specifier) INTEL
31. .LALL (List whole body of macro cells) .LALL
32. .LIST (Enable listing (default)) .LIST
33. #LOAD (Load named object file at link time) #LOAD "pathname\filename[.ext]"
34. LOCAL (Define labels as local to macro) LOCAL <arg>
35. LONG (Define long word in object code) LONG <exp>[,exp>...]
36. LONGS (Default new label length long) LONGS
37. MACRO (Define macro template <macro>) MACRO [param-1] [,param-2]...
38. MEND (End of macro definition) MEND
39. MOTOROLA (Force Motorola-style radix specifier ) MOTOROLA
40. .NOCHANGE (List original #DEFINE strings) .NOCHANGE
41. .NOLIST (Turn off listing) .NOLIST
42. %OUT (Output string ton the console) %OUT string
43. .PAGE (Perform a form feed) .PAGE
44. PUBLIC (Make labels public ) PUBLIC <arg>
45. REPEAT (Assembly-time loop initiator) REPEAT
46. .SALL (Suppress all of the body of called macro) .SALL
47. SEGMENT (Start of a new segment) |<name>|SEGMENT <align><combine>'<class>' [cod]
48. .SETDP (Set base address for direct page) .SETDP <base address>
49. SKIP (Insert given number of bytes with an initialization value) SKIP <number of bytes>,
<value to fill>
50. STRING (Define a byte-level string) STRING <exp or "string">, [,<exp or "string">...]
51. SUBTTL (Define a subtitle for listing heading) SUBTTL "<Subtitle string>"
52. .TAB (Set listing field lengths) .TAB <label>, <opcode>, <operand>,<comment>
53. TEXAS (Texas Instruments-style radix specifier) TEXAS
54. TITLE (Define main title for listing) TITLE "<Title string>"|
55. UNTIL (Assembly time loop terminator ) UNTIL <exp>
56. WORD ( word in object code) WORD <exp>[, <exp>...]
57. WORDS (Default new label length word) WORDS
58. .XALL (List only code producing macro lines) .XALL
59. ZILOG (Force Zilog-style radix specifiers ) ZILOG
71
XI. CC CH INH A CH CA H VI IU KHIN ST7

Mi dng Assembler gm 4 fields:
Label : Nhn nhn dng
Operation : ch nh cc lnh thao tc cho assembly
Operand: i tng m lnh thao tc
Comment : ghi cc ghi ch lin quan n dng lnh
V d :
substract sub A, #$22 ; substract $22 to the value hold by A
INHERENT
+ OP code ch ra y cc thng tin CPU thc hin thao tc (Lnh inherent di 1byte)
V d:
RCF - Reset c nh ; RSP - Reset Stack Pointer
HALT ; WFI Ch tiu th thp
TRAP Ngt (phn mm)
RET - Return ; IRET -Interrupt Return
SIM Thit lp Interrupt Mask ; RIM - Reset Interrupt Mask
PUSH A ; POP Y cc lnh trn stack
1. nh a ch tc thi
BCP A, #$FF
XOR A, #%01001110
LD X, #255
V d: LD A, #$55 => A c gi tr $55
2. nh a ch trc tip ngn

Khng gian c th nh a ch l 00 FF
INC variable
NEG variable
SRA variable
V d nu label l mt symbol 8bit c nh ngha l $86 th lnh INC symbol s lm tng ni

dung nh $86 ln 1 v
3. nh a ch trc tip di
Khng gian c th nh a ch l 0000 FFFF
72
CP Y, VARIABLE
SBC A, VARIABLE
V d nu label l mt symbol 16bit c nh ngha l $F1D6 th lnh ADD A,label s cng ni

dung thanh ghi A vi ni dung v tr $F1D6
4. nh a ch NO OFFSET INDEXED
Khng gian c th nh a ch l 00-FF
CPL (X)
DEC (Y)
OR A, (X)
V d X cha gi tr $D4 th lnh CPL (X) s ly phn b ca ni dung nh $D4
5. nh a ch SHORT INDEXED ADDRESSING

Khng gian c th nh a ch l 000- 1FE
RRC (variable, X)
SWAP (variable, Y)
V d nu label l mt symbol 8bit c nh ngha l $90, v X c gi tr 03 th lnh RRC

(label,X) s quay phi (bao gm c nh) nh ti a ch $93.
6. nh a ch LONG INDEXED
Khng gian c th nh a ch l 0000-FFFF
ADD A, (variable, Y)
XOR A, (variable, X)
V d nu label l mt symbol 16bit c nh ngha l $2E6D , X= 02 th lnh LD X (label,X) s

em gi tr nh $2E6F gn cho X.
7. nh a ch gin tip ngn

Khng gian c th nh a ch l 00 FF
TNZ [variable]
CLR [variable]
V d nu label l mt symbol 8bit c nh ngha l $4B th lnh SWAP [label] s tro 4bit cao
v bn bit thp ca ni dung nh $4B
8. nh a ch gin tip di
Khng gian c th nh a ch l 0000 FFFF
73
ADC A, [variable.w]
BCP A, [variable.w]
V d nu label l mt symbol 8bit c nh ngha l $40 th lnh LD A, [label.w] s gn cho A

ni dung ca nh c a ch l ni dung ca nh $40 v $41 ($40 cha trng s cao, $41 cha trng
s thp)
9. nh a ch SHORT INDIRECT INDEXED

Khng gian c th nh a ch l 000- 1FE
RLC ([variable], Y)
LD X, ([variable], X)
V d nu label l mt symbol 8bit c nh ngha l $C8, X= 04 th lnh CLR ([label], X) s xa

ni dung ca nh c a ch l ni dung nh $C8 cng thm vi 4
10.
nh a ch LONG INDIRECT INDEXED
Khng gian c th nh a ch l 0000- FFFF
SUB A, ([variable.w], X)
AND A, ([variable.w], Y)
V d nu label l mt symbol 16bit c nh ngha l $40, X= 01 th lnh

LD
A,
([label.w],X) s gn cho A ni dung ca nh c a ch l ni dung ca hai nh $40 v $41 cng
thm vi 01 (X)
11.
nh a ch tng i
Khng gian c th nh a ch trc tip l PC-128 n PC+127
JRUGE label
CALLR label
Khng gian c th nh a ch gin tip l PC-128 n PC+127
12.
JRNC [label]
JRH [label]
Thao tc trn bit
Khng gian c th nh a ch trc tip l 00 FF

V d variable c gi tr 11000000. Sau khi thc hin lnh BSET variable, #2 c gi tr l 11000010
Khng gian c th nh a ch gin tip l 00 FF
V d variable c gi tr $86. Lnh BRES [variable], #7 s thc hin thao tc ln ni dung nh
$86
74

ST7 Manual VI

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ST7 Manual VI

Uploaded by

Copyright:

Available Formats

BIN DCH T TI LIU ST7 USER GUIDE CA

TP.HCM, THNG 1 NM 2008

TI LIU HNG DN S DNG ST7 ST GROUP

GII THIU KHI QUT V VI IU KHIN ..................................................................... 6

PHN LOI ................................................................................................................................... 6

CU TRC TNG QUAN CA VDK:.................................................................................. 7

GII THIU ................................................................................................................................ 10

VNG NH LP TRNH FLASH (Flash Programming Memory). ................................. 14

c im chnh (main features).................................................................................15

Ch lp trnh (Programming Modes)....................................................................15

Giao tip ICC (ICC Interface).....................................................................................16

Bo v vng nh ( Memory Protection). ...................................................................16

Ti liu lin quan (Related Documentation). ...........................................................17

M t thanh ghi (Register description). .....................................................................17

Gii thiu (Introduction). ..............................................................................................17

Truy xut b nh . ..........................................................................................................18

B X L TRUNG TM (Central Processing Unit).......................................................... 19

Cc thanh ghi ni. ........................................................................................................20

TI LIU HNG DN S DNG ST7 ST GROUP

Ngt mm khng che c .......................................................................................24

Ngt ngoi ......................................................................................................................24

Ngt thit b ngoi vi .....................................................................................................24

CC CNG I/O : .................................................................................................................... 28

Thc thi cc cng I/O ..................................................................................................30

Cc chn khng c s dng ................................................................................31

Ch tit kim nng lng.......................................................................................31

CC THIT B NGOI VI C TCH HP: ................................................................ 31

B nh thi Watchdog (WDG) : ................................................................................31

B nh thi 12 bit t ng np li ..............................................................................33

Giao tip ngoi vi ni tip (SPI) ...................................................................................45

B chuyn i tn hiu tng t sang tn hiu s......................................................59

TP LNH ASSEMBLER CA VI IU KHIN ST7 ......................................................... 65

Cc lnh Logic ..............................................................................................................66

Cc lnh di chuyn d liu..........................................................................................68

CC CH INH A CH CA H VI IU KHIN ST7 ...................................... 71

TI LIU HNG DN S DNG ST7 ST GROUP

nh a ch trc tip ngn..........................................................................................71

nh a ch trc tip di.............................................................................................71

nh a ch SHORT INDEXED ADDRESSING ..............................................................72

nh a ch LONG INDEXED .......................................................................................72

nh a ch gin tip ngn.........................................................................................72

nh a ch gin tip di ............................................................................................72

nh a ch SHORT INDIRECT INDEXED......................................................................73

nh a ch LONG INDIRECT INDEXED ..................................................................73

Thao tc trn bit........................................................................................................73

TI LIU HNG DN S DNG ST7 ST GROUP

TNG QUAN V VI IU KHIN

TI LIU HNG DN S DNG ST7 ST GROUP

I. GII THIU KHI QUT V VI IU KHIN

II. PHN LOI

TI LIU HNG DN S DNG ST7 ST GROUP

Da vo di ca cc thanh ghi v cc lnh ca VK m ngi ta chia ra

III. CU TRC TNG QUAN CA VDK:

TI LIU HNG DN S DNG ST7 ST GROUP

trnh hot ng ni dung ROM l c nh, khng th thay i, ni dung ROM

TI LIU HNG DN S DNG ST7 ST GROUP

TI LIU HNG DN S DNG ST7 ST GROUP

TI LIU HNG DN S DNG ST7 ST GROUP

TI LIU HNG DN S DNG ST7 ST GROUP

III. S B NH V THANH GHI

TI LIU HNG DN S DNG ST7 ST GROUP

TI LIU HNG DN S DNG ST7 ST GROUP

Ghi ch: x = khng xc nh, R/W = c/ghi

IV. VNG NH LP TRNH FLASH (Flash Programming Memory).