ECE 546 - VLSI Systems Design

Lecture 10: Ratioed Logic,

Pass Transistor Logic
Fall 2012
W. Rhett Davis
NC State University
with significant material from Rabaey, Chandrakasan, and Nikoli
W. Rhett Davis

NC State University

Slide 1

ECE 546

Fall 2012

Announcements

Homework #4 Due Today

Homework #5 Due in 1 Week

Midterm Exam in 2 Weeks

W. Rhett Davis

NC State University

Slide 2

ECE 546

Fall 2012

Summary of Last Lecture

What physical quantities do the following values

represent?

Intrinsic Delay
Logical Effort
Electrical Effort
Gate Effort

When is the delay minimized for a chain of logic gates

(in the method of logical effort)?

What are some of the methods to improve the

performance of a Complementary CMOS gate?

W. Rhett Davis

NC State University

Slide 3

ECE 546

Fall 2012

Todays Lecture

Ratioed Logic
(6.2.2)

Pass-Transistor Logic
(6.2.3)

W. Rhett Davis

NC State University

Slide 4

ECE 546

Fall 2012

Ratioed Logic
VDD
Resistive
Load

VDD
Depletion
Load

RL

PDN

F
In1
In2
In3

VSS
(a) resistive load

PMOS
Load
VSS

VT < 0

F
In1
In2
In3

VDD

F
In1
In2
In3

PDN
VSS

PDN
VSS

(b) depletion load NMOS

(c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

W. Rhett Davis

NC State University

Slide 5

ECE 546

Fall 2012

Comparison of Logic Families

Complementary CMOS

Ratioed Logic

Full Swing

Reduced Swing
(smaller noise margin)

No Static Power

Static Power

tpHL = tpLH
if sized correctly

tpLH > tpHL

Large PMOS
parasitic capactiances

much smaller
parasitic capactiances

W. Rhett Davis

NC State University

Slide 6

ECE 546

Fall 2012

Pseudo-NMOS

VDD

VOH = VDD
VOL = ?
A

F
CL

To find VOL, Use KCL at node F

Equation (6.27)
What region of operation for
NMOS?
PMOS?

W. Rhett Davis

NC State University

Slide 7

ECE 546

Fall 2012

VOL calculation
2
2

VDSATp

VOL
k n VDD VTn VOL
0
k p VDD VTp VDSATp
2
2

assume VOL << (VDD-VTn)

remove VOL2/2 term
simplify
VOL

W. Rhett Davis

VDSATp
k p VDD VTp VDSATp

k n VDD VTn

very close to equation (6.28)

How would you compute static power?
remember to include channel-length modulation ()
when computing static power
How would you include DIBL?
NC State University

Slide 8

ECE 546

Fall 2012

Modified Equation (6.28)

Use this Equation on HW#5

Thanks to Harun Demircioglu for this derivation

W. Rhett Davis

NC State University

Slide 9

ECE 546

Fall 2012

Pseudo-NMOS VTC
3.0

2.5

W/Lp = 4

Vout [V]

2.0

1.5

W/Lp = 2
1.0

0.5

W/Lp = 0.5

W/Lp = 1

W/Lp = 0.25
0.0
0.0

0.5

1.0

1.5

2.0

2.5

Vin [V]

W. Rhett Davis

NC State University

Slide 10

ECE 546

Fall 2012

Improved Loads
VDD

M1

Enable

M2

M1 >> M2

F
A

CL

Adaptive Load

W. Rhett Davis

NC State University

Slide 11

ECE 546

Fall 2012

Improved Loads (2)

VDD

VDD

M1

M2

Out
A
A
B
B

Out

PDN1

PDN2

VSS

VSS

Differential Cascode Voltage Switch Logic (DCVSL)

W. Rhett Davis

NC State University

Slide 12

ECE 546

Fall 2012

Todays Lecture

Ratioed Logic
(6.2.2)

Pass-Transistor Logic
(6.2.3)

W. Rhett Davis

NC State University

Slide 13

ECE 546

Fall 2012

Pass-Transistor Logic

Inputs

B
Switch

Out

A
Out

Network

B
B

N inputs, N transistors
No static power consumption (ideally)

W. Rhett Davis

NC State University

Slide 14

ECE 546

Fall 2012

Example: AND Gate

Whats wrong with this gate?

How could you fix the problem?

W. Rhett Davis

NC State University

Slide 15

ECE 546

Fall 2012

Complete the Truth Table

A
0
0
1
1

W. Rhett Davis

NC State University

Slide 16

B
0
1
0
1

ECE 546

Fall 2012

NMOS-Only Logic

3.0

In

VD D

0.5 m/0.25 m

1.5 m/0.25 m
Out
0.5 m/0.25 m

Voltage [V]

In
Out

2.0

1.0

0.0

0.5

1.5

Time [ns]

W. Rhett Davis

NC State University

Slide 17

ECE 546

Fall 2012

NMOS-only Switch
C = 1.8V

C = 1.8 V
M2
A = 1.8 V

A = 1.8 V
X

X
Mn
M1

CL

VX does not pull up to 1.8V, but 1.8V - VTN

Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
W. Rhett Davis

NC State University

Slide 18

ECE 546

Fall 2012

Body Effect
VT VT 0

2F VSB 2F

= body-effect coefficient
F = Fermi Potential

L-H transition

H-L transition

DD

X
SB

W. Rhett Davis

NC State University

Slide 19

ECE 546

Fall 2012

Finding VX
VX VDD VT VDD VT 0 Bn VDD VX

2 f 2 f

DD

VX
0

VTn

VDD-VTn

SB

VDD = 2.5 V
= 0.4
F = -0.3 V
Bn = 0 V/V

W. Rhett Davis

NC State University

Slide 20

ECE 546

Fall 2012

Finding tpLH
VDD

+
VSB

VX

tp = 0.69 Req CL

Remember that

W. Rhett Davis

NC State University

Vhigh = VDD VTn(max)

Vlow = 0
Vmid = (VDD VTn(max))/2
This causes some error,
since Vmid VDD/2,
but this error is small

VTn will change for every

value of VX!
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ECE 546

Fall 2012

Cascading Pass-Transistors

What is the voltage swing at node y

for each case?

W. Rhett Davis

NC State University

Slide 22

ECE 546

Fall 2012

Cascading Pass-Transistors

In complementary CMOS, current to charge

the load capacitance comes from the supply.

Where does it come from in Pass-Transistor

Circuits?

B
A

W. Rhett Davis

NC State University

Slide 23

ECE 546

Fall 2012

Pass-Transistor Energy
T

E0 1 p (t )dt VDD iSUPPLY (t )dt

T

dVout
VDD CL
dt VDDCL
dt
0

V DD VTn

dV

out

C LVDD VDD VTn

Note that its not CL(VDD-VTn)2!

W. Rhett Davis

NC State University

Slide 24

ECE 546

Fall 2012

Techniques to Deal with Static Power

3.0

In

M2
A = 1.8 V

X
Mn
M1

Voltage [V]

C = 1.8 V
Out

2.0

1.0

0.0

0.5

1.5

Time [ns]

W. Rhett Davis

NC State University

Slide 25

ECE 546

Fall 2012

Solution 1: Level Restoring Transistor

VDD
VDD

Level Restorer
Mr
B
A

Mn

M2
X

Out
M1

Advantage: Full Swing

Restorer adds capacitance, takes away pull down current at X
Ratio problem
W. Rhett Davis

NC State University

Slide 26

ECE 546

Fall 2012

Restorer Sizing

Voltage [V]

3.0

2.0

Upper limit on restorer size

Pass-transistor pull-down
can have several transistors in
stack

W/Lr =1.75/0.25
W/L r =1.50/0.25

1.0
W/Lr =1.0/0.25
0.0

W. Rhett Davis

100

200

W/L r =1.25/0.25
300
Time [ps]

NC State University

400

500

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ECE 546

Fall 2012

Solution 2: Pass-Transistor with VT=0

VDD
VDD

0V

2.5V

VDD

Out

0V

2.5V

WATCH OUT FOR LEAKAGE CURRENTS

W. Rhett Davis

NC State University

Slide 28

ECE 546

Fall 2012

Solution 3: Transmission Gate

C

B
C

C
C = 2.5 V
A = 2.5 V
B
CL
C=0V

W. Rhett Davis

NC State University

Slide 29

ECE 546

Fall 2012

Resistance of Transmission Gate

30
2.5 V

Resistance, ohms

Rn
20

Rp

2.5 V

Rn
Vou t
Rp

10

0
0.0

W. Rhett Davis

0V
R n || R p

1.0

Vou t , V

NC State University

2.0

Slide 30

ECE 546

Fall 2012

High-Performance Pass-Transistor Logic

A
A
B
B

Pass-Transistor
Network

(a)
A
A
B
B

Inverse
Pass-Transistor
Network

Complementary PassTransistor Logic

Presence of complementary
outputs eliminates the need
for inverters
Requires more transistors
B

F=AB

F=A+B

F= AB
AND/NAND

W. Rhett Davis

F=A

(b)

F =A+B

A
XOR/XNOR

OR/NOR

NC State University

F =A

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ECE 546

Fall 2012

Pass-Transistor Based Multiplexer

S

VDD
S

V DD

M2
F

S
M1
B

GND
In1
W. Rhett Davis

NC State University

Slide 32

In2
ECE 546

Fall 2012