Professional Documents
Culture Documents
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H tr iu khin Ethernet
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Mi cng thc cht c qun l bi cc thanh ghi PORTA, PORTB, PORTC, PORTD,
PORTE nm trong b nh RAM ca vi iu khin. Xem hnh sau:
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l i din cho cc chn cng A, PORTB l i din cho cc chn cng B v.v. Cc
thanh ghi ny c a ch xc nh v khng c dng cho cc mc ch khc
1
RA5
0
RA4
1
RA3
0
RA2
1
RA1
RA0
X: khng quan tm.
Tng t nh vy vi PORTB,PORT C,PORTD,PORTE.
Tnh a chc nng ca mt chn trn vi iu khin:
Nhn vo s chn ca vi iu khin, ta c th thy mt s chn ca vi iu khin c
tn gm nhiu phn vi du gch cho. V d: RA0/AN0, RC7/RX/DT, RC6/TX/CK
y chnh l tnh a chc nng ca mt chn trn vi iu khin hay cn gi l s dn
knh.
ngha ca n l:
Bnh thng nu khng c ci t th tc c cc chn trn 5 cng A, B, C, D, E l cc
chn vo ra s I/O.
Nu trong chng trnh ta c ci t mt chc nng no nh RS232, ADC hoc PWM
v.v th cc chn tng ng vi chc nng s hot ng theo chc nng . Khi
chn ny s khng c dng lm chn vo ra s nh bnh thng na.
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V d: bnh thng chn RA0/ANO l chn vo ra s RA0, nu chc nng ADC vi knh
vo tn hiu analog l knh 0 c ci t khi chn RA0 /AN0 s l chn vo ca b
ADC, tc l hot ng theo chc nng AN0.
Tng t nh vy, khi ci t giao tip vi thit b ngoi vi theo chun RS232, chn vo
ra s RC7/RX/DT s hot ng nh u vo d liu RS232 tc l chc nng RX ca
chn ny.
Gi d nh l:
chn RB.m (m=0-7) l u ra, tc Output th gi tr TRISB.m l 0
L u vo, tc Input th gi tr TRISB.m l 1
Tng t nh vy i vi cc chn trn cc cng cn li
2. Ngn ng lp trnh cho vi iu khin PIC- CCS:
2.1 Cc ngn ng lp trnh cho vi iu khin PIC:
Ngn ng lp trnh cho vi iu khin PIC c 2 loi:
-
Ngn ng lp trnh bc cao: c nhiu loi, c pht trin theo ngn ng C, nh:
CCS, HTPIC, PIC BASIC v.v
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delay_ms(2);// S dng hm to tr 2 ms
output_high(PIN_A4); // s dng hm a gi tr chn RA4 ln mc cao
output_b((MAP[n%10]) ^ 0x00);
output_low(PIN_A5);
delay_ms(2);
output_high(PIN_A5);
}
// Kt thc chng trnh con hin th
//============================================
// Bt u chng trnh chnh
// y l ni vi iu khin bt u chy lnh
//============================================
void main()
{
int i,count;
count=0;
while(TRUE)
{
for (i=0;i<=50;i++)
display(count);
// dispay 50 times
count=(count==99) ? 1: count+1;
}
}
2.2.2 Cu trc ca mt chng trnh vit bng CCS:
2.2.2.1 Khai bo tin x l:
Bt u mt chng trnh vit bng ngn ng CCS l phn khai bo tin x l:
1. u tin l phn khai bo file header: #include <tn chip dng.h>
V d: # include <16f877a.h>
Vic khai bo ny thc cht l chp c file 16f877a.h vo chng trnh ny.
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}
Cng nhc li l trong mt chng trnh CCS , vi iu khin s chy t chng trnh
chnh, hay ni cch khc l t dng lnh u tin sau void main().
Cc chng trnh con ch c gi ti cc li gi chng trnh con trong chng trnh
chnh hoc t cc chng trnh con khc. Chng trnh con phc v ngt ch c chy
khi c ngt xy ra, v ngt c cho php (s bn k hn trong cc bi hc sau).
2.2.3 Cc cu trc thut ton ca ngn ng CCS:
Cu trc thut ton ca ngn ng CCS k tha 100% t ngn ng C. y xin nhc li
mt s cc cu trc hay dng:
-
Cu trc IF:
o If (biu thc)
Lnh1;
Else lnh2;
V d: if (x==25)
x=1;
else
x=x+1;
Cu trc lp While:
o While (biu thc)
{
Cc lnh;
}
V d: While (count<20)
{
Output_B(count);
Count=count+1;
}
Ch : while(1) s thc hin cc lnh trong khi while ny mi mi
Cu trc lp FOR:
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Case gi tr n: lnh n
Break;
[default: lnh n+1; break;]
}
V d: switch (cmd)
{
}
CNG TY TNHH CNG NGH CAO ATECKO
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Output_low (chn): cho chn xung mc logic thp (mc in p 0V), chn c
th l:
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2.2.7 Cc hm to tr:
Cc hm to tr gm delay_cycles(), delay_us(), delay_ms. To mt khong thi gian tr
t lc lnh c thc hin. Ch l phi s dng khai bo tin x l # use
delay(clock=tn s) th mi dng c cc lnh ny.
-
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Hin th cnh bo, bo li: thng thng dng led n. C th hin th theo kiu dng
nhiu mu khc nhau hoc bt tt v.v
Trong bi ny s gii thiu 2 cch hin th u, phn hin th bng my tnh s c cp trong
bi hc v chun giao tip RS232.
2.1 Hin th bng led n:
y l cch hin th n gin nht.
Thng thng cch hin th ny dng bo mt trng thi no y ca thit b nh trng thi
lm vic ca ngun (li hoc khng li), cng nh cc khi chc nng khc.
C rt nhiu loi led n dng hin th. Phng php n gin nh sau:
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Nh gii thiu phn trn, thc cht led 7 on gm 8 hoc 7 led n ni vi nhau. V vy
iu khin thanh led n sng, cch thc hin phn cng nh hnh 2.1.
C th hn, nh dng led chung anod nh hnh v trn. Mi u vo a,b,c,d,e,f,g,h c ni vi
mt chn ca vi iu khin, tng ng l RB0, RB1, ..RB7, thng qua cc in tr phn p 200
ohm, u anod chung c ni vi ngun. led n sng n gin ta a chn vi iu khin
ni vi led xung mc thp.
Nh trn hnh 2.4 trn, led 7 on hin th s 2 th cc led a,b,d,e,g sng; cc led c, f tt. Gi tr
sng tng ng chn vi iu khin ni vo mc 0, gi tr tt tng ng vi chn vi iu khin
ni vi mc 1.
Do ni dung ca thanh ghi PORTB l:
0
y l m led 7 on ca s 2
Nh vy, chng ta lu mt iu rng, d liu xut ra led 7 on l m led tng ng vi s cn
xut
M led tng ng vi cc s t 0 n 9 l:
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0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90
Cch iu khin led 7 on chung catod th ngc li.
2.2.3 Hin th nhiu led 7 on dng vi iu khin:
Trong thc t, ta phi dng nhiu led 7 on hin th.
Vy gii quyt vic hin th nhiu led nh th no?
V d: hin th s 35 bng 2 led 7 on.
i chiu vi cch hin th 1 led 7 on, ta ngh n gin ch l dng 1 cng hin th s 3, 1 cng
khc hin th s 5.
Nh vy ta mt 2 cng. Hin th 4 led th mt 4 cng => ton b chn trn vi iu khin dng cho
vic hin th ledKhng cn chn giao tip vi cc thit b khc nh bn phm, u vo s
khc v.v Khng kh thi!
Ta c phng php tit kim chn hn gii quyt:
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Cho chn RA4 (chn ni vi led hng chc) xung mc thp, transistor th nht m do
tip gip BE thun, chn RA5 ln mc cao (chn ni vi led hng n v), transistor th
hai khng m. Vy ch c led hng chc c cp ngun.
iu khin tng t cho led hng n v c cp ngun, led hng chc khng cp
ngun, xut d liu m led s 5 ra cng B. Led n v hin th s 5.
Quay li bc th nht
Nh vy, s 3 hin th 10ms, s 5 hin th 10ms v quay vng nh vy. Thi gian ny rt nhanh,
do hiu ng ca mt, ta cm gic nh s 35 hin th cng lc. Bi ton c gii quyt, ta ch mt
c 10 chn iu khin 2 led.
Cch hin th nhiu led cng tng t nh vy.
Cng gii thch thm l do dng transistor ni vo RA4, RA5. Do chn vi iu khin c dng
khong vi chc mA, y l chn cp ngun cho led 7 on, mi led n trong Led 7 on mt
20mA vy c led 7 on mt trn 100mA. V vy ta phi dng transistor khuch i dng.
2.3 Hin th dng LCD:
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7
8
9
10
11
12
13
14
D0
D1
D2
D3
D4
D5
D6
D7
RS
RW
E
4
5
6
1
2
3
VSS
VDD
VEE
LM016L
VSS: Chn t
RS:
R/W:
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E: Chn cho php (Enable). Sau khi lnh hoc d liu c chun b trn ng d
liu, to xung mc cao-mc thp s bt u qu trnh LCD nhn d liu hoc lnh t vi
iu khin.
Gi m lnh xung LCD theo cc ng d liu (RD0-RD7 nu dng ch 8 bit, R4R7 nu dng ch 4 bit)
To tr vi chu k lnh
M lnh nh gii thiu trong phn trn ty thuc vo tng lnh, y gii thiu mt s lnh
c bn nh sau:
. Lnh ci t ch lm vic:
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DL
I/D
DL:
= 1: 8 bit
= 0: 4 bit
= 1: 2 dng
= 0 1 dng
N:
F:
I/D:
= 1 tng a ch
= 0 gim a ch
S:
C: ci t hin th con tr
B: nhp nhy v tr k t
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. Lnh t v tr hin th ca k t:
C
a ch dng 1: 00- 0F
a ch dng 2: 40-4F
To tr vi chu k lnh
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File: LCD_lib_4bit:
#include <stddef.h>
#define LCD_RS
PIN_B2
#define LCD_EN
PIN_B3
#define LCD_D4
PIN_B4
#define LCD_D5
PIN_B5
#define LCD_D6
PIN_B6
#define LCD_D7
PIN_B7
#define Line_1
0x80
#define Line_2
0xC0
#define Clear_Scr
0x01
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delay_ms(20);
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LCD_SetData ( swap ( cX ) );
LCD_PulseEnable();
}
LCD_PulseEnable();
LCD_SetData ( swap ( cX ) );
LCD_PulseEnable();
}
#separate void LCD_PulseEnable ( void )
{
output_high ( LCD_EN );
delay_us ( 3 );
// was 10
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output_low ( LCD_EN );
delay_ms ( 3 );
// was 5
}
#separate void LCD_SetData ( unsigned int CX )
{
output_bit ( LCD_D4, CX & 0x01 );
output_bit ( LCD_D5, CX & 0x02 );
output_bit ( LCD_D6, CX & 0x04 );
output_bit ( LCD_D7, CX & 0x08 );
}
Chng trnh ng dng:
LCD1
LM016L
C1
30pF
8
9
10
1
R9
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
4K
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
33
34
35
36
37
38
39
40
D0
D1
D2
D3
D4
D5
D6
D7
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
7
8
9
10
11
12
13
14
2
3
4
5
6
7
OSC1/CLKIN
OSC2/CLKOUT
RS
RW
E
13
14
4
5
6
CRYSTAL
1
2
3
X1
C2
VSS
VDD
VEE
UDK
30pF
15
16
17
18
23
24
25
26
19
20
21
22
27
28
29
30
PIC16F877A
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VOID MAIN()
{
LCD_INIT();
LCD_PUTCHAR('X');
DELAY_MS(1000);
LCD_PUTCHAR('I');
DELAY_MS(1000);
LCD_PUTCHAR('N');
DELAY_MS(1000);
LCD_PUTCHAR(' ');
DELAY_MS(1000);
LCD_PUTCHAR('C');
DELAY_MS(1000);
LCD_PUTCHAR('H');
DELAY_MS(1000);
LCD_PUTCHAR('A');
DELAY_MS(1000);
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LCD_PUTCHAR('O');
BI 3: B NH THI - TIMER
3.1 Gii thiu:
CNG TY TNHH CNG NGH CAO ATECKO
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Trong cc ng dng ca vi iu khin trong thc t, vic nh thi (to mt khong thi gian gia
2 s kin) cc thao tc l vic thng xuyn xy ra.
thc hin vic ny, ta c 2 cch:
-
Timer2: 8 bit, hot ng phc v chc nng PWM (Pulse Width Modulation- iu ch
rng xung)
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. Khi
=1s
(s) gi tr TMR s t gi tr
Ngc li, ta mun thc hin nh thi khong thi gian t sau mt s kin 1 nh sau:
-
S kin 1
S kin 2
Ta lm cc bc:
-
S kin 1
n gi tr
-t) = t (s)
Vy khong thi gian t sau s kin 1 (khi TMR bt u c gn) n s kin 2 (ngay sau khi
bit c c set) l t ng nh yu cu ca ta.
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V d: nh thi 200 (s) dng Timer0 (8 bit; n=1; gi tr ti a l 255) ta cho TMR0= 255200=55 ri bt u cho m ln.
3.2.2 Ch b m:
Khi c ci t trong ny, mt chn chc nng trn vi iu khin s tr thnh chn u vo xung
ca b m. V d: chn RA4 i vi Timer0 v RC0 i vi Timer1. Hot ng ca n c nt
ging vi ch nh thi.
Khi c ci t hot ng trong ch b m, Gi tr ca thanh ghi TMR s t ng tng ln
1 n v khi c mt xung vo chn u vo xung ca timer . Khi gi tr ca TMR0 t n gi
tr ti a, bit c ca Timer s c set ln mc 1 v TMR b xa, TMR=0.
Nh vy, v cch hot ng trong ch ny ch khc vi ch nh thi ch, thay v TMR t
ng tng ln sau mi chu k lnh, th TMR tng ln khi c mt xung i vo chn u vo xung
ca Timer .
Dng xung c xc nh l sn m hay sn dng ph thuc vo vic ci t bit chn dng
xung tng ng trn thanh ghi ca vi iu khin.
Nguyn l hot ng nh thi v b m ny cng ng vi cc b vi iu khin, vi x l khc.
Ta i vo kho st c th 2 Timer0 v Timer1 ca vi iu khin PIC.
3.3 Timer 0:
3.3.1 Nguyn l hot ng:
Timer 0 c di 8 bit Thanh ghi cha gi tr m l TMR0 (s m ti a l 255). Hot ng
2 ch l nh thi v b m.
hot ng ch nh thi, ta cho bit T0CS (bit 5 ca thanh ghi Option_Reg) mc 0. Khi
, gi tr ca thanh ghi TMR0 s t ng tng ln 1 n v sau mi chu k lnh ca vi iu khin.
hot ng ch b m, ta cho bit T0CS (bit 5 ca thanh ghi Option_Reg) mc 1. Khi
, gi tr ca thanh ghi TMR0 s t ng tng ln 1 n v sau khi c mt xung i vo chn RA4
ca vi iu khin. Vic chn xung l dng sn ln hay sn xung ph thuc vo bit T0SE (bit 4
ca thanh ghi Option_Reg l 0 hay 1.
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Nh vy, thi gian nh thi ti a cng nh s xung m c khi TMR0 trn s tng ln 64 ln.
Tng t vi cc t l khc.
Thc ra, Timer 0 chia s b chia tn s Prescale vi mt ch khc ca vi iu khin- ch
Watchdog Timer. Vic chn ch ny c thc hin khi cho bit PSA (bit 3 ca thanh ghi
Option_Reg) gi tr 0. Ch ny s c nghin cu sau. y ta ch quan tm n b chia tn
s dnh cho Timer 0 khi PSA=1. V vy trong s trn ta ch quan tm n cc ng n ghi
ch thm bng ng thng mng.
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Bit TMR0IE: Bit ny bng 1 cho php ngt Timer 0. S kin ngt xy ra khi c s trn
TMR0 t 255 xung 0.
Bit TMR0IF: Bit c xc nhn gi tr TMR0 b trn t 255 v 0
RTCC_INTERNAL: ch nh thi
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3.4 Timer 1:
3.4.1 Nguyn l hot ng:
Timer 1 c di 16 bit. Gi tr ca b m timer 1 c lu trong 2 thanh ghi 8 bit TMR1H v
TMR1L. Timer 1 cng c 2 ch c ci t bi bit TMR1CS (bit 1 ca thanh ghi T1CON):
-
TMR1CS = 0: Ch nh thi
T1SYNC = 0: B m ng b
T1SYNC = 1: B m khng ng b
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T1CKPS1-T1CKPS0
T l chia tn s
00
1:1
01
1:2
10
1:4
11
1:8
=1: RC1
=0: RC0
=1: Khng ng b
=0: Khng ng b
=1: Ch b m
=0: Ch b nh thi
=1: Bt Timer 1
=0: Tt Timer 1
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Kqt
kqt kqt
Kqt
kqt
kqt TMR1IF
Bit TMR1IF l bit c ca timer 1. Bit c set ln gi tr 1 khi xy ra trn 2 thanh ghi TMR1L v
TMR2H t 65535 v 0.
T1_INTERNAL: ch nh thi
T1_EXTERNAL: ch b m khng ng b
T1_EXTERNAL_SYNC: ch b ng b
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BI TP:
3.1 Cho s mch nh sau:
C1
30pF
X1
C2
CRYSTAL
30pF
U1
13
14
OSC1/CLKIN
OSC2/CLKOUT
RB0/INT
RB1
RB2
RA0/AN0
RB3/PGM
RA1/AN1
RB4
RA2/AN2/VREF-/CVREF
RB5
RA3/AN3/VREF+
RB6/PGC
RA4/T0CKI/C1OUT
RB7/PGD
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
2
3
4
5
6
7
8
9
10
R9
4K
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
33
34
35
36
37
38
39
40
R1
268
R2
220
15
16
17
18
23
24
25
26
R3
222
R4
220
19
20
21
22
27
28
29
30
R5
220
R6
220
PIC16F877A
R7
220
Q1
R8
PNP
4K
R10
Q2
PNP
10k
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X1
CRYSTAL
C2
30pF
U1
13
14
2
3
4
5
6
7
RC
4K
8
9
10
R9
4K
OSC1/CLKIN
OSC2/CLKOUT
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
33
34
35
36
37
38
39
40
R1
268
R2
220
15
16
17
18
23
24
25
26
R3
222
R4
220
19
20
21
22
27
28
29
30
R5
220
R6
220
PIC16F877A
R7
220
Q1
R8
PNP
4K
Q2
R10
PNP
10k
X1
C2
CRYSTAL
30pF
LCD1
U1
8
9
10
1
R9
4K
LM016L
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
15
16
17
18
23
24
25
26
+12v
RV?
1k
+88.8
19
20
21
22
27
28
29
30
PIC16F877A
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D0
D1
D2
D3
D4
D5
D6
D7
RS
RW
E
+12v
7
8
9
10
11
12
13
14
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
33
34
35
36
37
38
39
40
VSS
VDD
VEE
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
4
5
6
2
3
4
5
6
7
OSC1/CLKIN
OSC2/CLKOUT
1
2
3
13
14
BI 4: NGT
4.1 Ngt l g:
Ngt hiu theo ngha n gin l cc s kin ngu nhin lm gin on qu trnh ca mt s kin
ang xy ra. c th d hiu khi nim mi ny ta cng a ra mt v d trong thc t nh sau:
V d: Trong gi hc trn lp, ta ang hc bi, c chung in thoi hoc c bn gi, ta phi
dng hot ng hc bi li tr li in thoi hoc ra gp bn. S kin in thoi reo chung,
hay bn b gi c gi l s kin ngt, vic ta tr li in thoi hay ra gp bn l chng trnh
phc v ngt. Vic ang hc bi c xem l chng trnh chnh.
Ngt c thc hin khi v ch khi ci t cho php n. Nh trong v d trn, nu s kin ngtin thoi reo xy ra, nu gio vin v bn thn ta cho php mnh tr li in thoi khi ang hc
bi th khi c in thoi ta mi nghe.
Vi iu khin cng c ngt. Cch x l ca n cng tng t nh v d trn.
C th hot ng ca vi iu khin khi c s kin ngt xy ra v ngt c cho php:
-
Ti y, vi iu khin s thc hin chng trnh con phc v ngt do ngi lp trnh
lp trnh t trc.
Sau khi thc hin xong chng trnh con phc v ngt, vi iu khin ly li a ch ca
lnh k tip c lu v thc hin tip chng trnh ang thc hin d lc cha c
ngt
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Ngun ngt: ngun ngt l nguyn nhn gy ra ngt. Nh trong v d trn, ngun ngt c
th
L in thoi gi hoc bn gi
Chng trnh con phc v ngt: l chng trnh vi iu khin x l khi c s kin ngt
xy ra do ngi lp trnh lp trnh ra
V d nh ta tr li hoc chy ra khi phng gp bn
Bit cho php ngt: tc vic cho php vi iu khin chy chng trnh con phc v ngt
khi c s kin ngt xy ra. Trong vi iu khin PIC, mi ngt c bit cho php ca n. Bit
ny tn cng bng ch E (enable), nm trong cc thanh ghi chuyn dng. Mun cho php
ngt , ta phi a bit cho php ngt tng ng ln gi tr 1. Ngt ch thc s c cho
php ngt khi ta cho bit cho php ngt ton cc GIE (Global Interrupt Enable) ln mc 1.
Ta hnh dng nh sau: khi c s kin ngt- in thoi gi, nu ta cho php mnh nghe
in thoi (tc bit cho php ngt ca ngt c set ln 1) ng thi thy gio cho php
(bit cho php ngt ton cc GIE c ln mc 1) th ta mi nghe in thoi (cho chng
trnh con phc v ngt hot ng).
Mt s cc ngt khc, nh cc ngt ngoi vi bao gm ADC, PWM v.v Mun cho php n
cn phi a bit cho php ngt ngoi vi ln mc 1.
C ngt: l bit phn nh trng thi ca s kin ngt. Mi ngt c mt bit c. Khi bit c
ny bng 1 ngha l s kin ngt tng ng vi c xy ra. Ta hnh dung nh ting
chung ca in thoi l c ngt, chung rung bo c s kin ngt- c in thoi xy ra.
Cc bit ny tn cng bng t F (Flag- c). Lu l d mt ngt c c cho php hay
khng th c ngt vn c set ln 1 khi c s kin ngt xy ra. (D ta c c php nghe
in thoi hay khng th chung in thoi vn c reo).
Lp ngt c bn: bao gm cc ngt c bn nh ngt trn timer 0, ngt ngoi, ngt thay
i trng thi ca cc chn PortB (RB4-RB7). Bit cho php ngt v bit c tng ng l
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Lp ngt ngoi vi: bao gm cc ngt ngoi vi nh ngt trn timer 1 (TMR1IE,
TMR1IF), ngt trn Timer 2(TMR2IE, TMR2IF), ngt hon thnh vic chuyn i ADC
(ADCIE, ADCIF), ngt hon thnh vic nhn k t trong truyn thng RS232 (RCIE,
RCIF), ngt hon thnh vic truyn k t trong truyn thng RS232 (TXIE, TXIF) v.v
l mun thc s cho php cc ngt ny ngoi bit cho php ngt ton cc c set phi
set c bt cho php ngt ngoi vi PEIE.
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OUTPUT_HIGH(PIN_A4);
OUTPUT_LOW(PIN_A5);
OUTPUT_D(MAP[HDV]);
DELAY_MS(15);
OUTPUT_HIGH(PIN_A5);
}
VOID MAIN()
{
// CAI DAT VAO RA CHO CONG B
SET_TRIS_B(0xFF);
// CHO PHEP NGAT NGOAI
ENABLE_INTERRUPTS(INT_EXT);
// CAI DAT SUON NGAT
EXT_INT_EDGE(H_TO_L);
// CHO PHEP NGAT TOAN CUC
ENABLE_INTERRUPTS(GLOBAL);
// VONG LAP DOI NGAT
WHILE(1)
{
HIENTHI(SODEM);
}
}
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Nh vy, lc vit chng trnh c dng ngt bng CCS, ta c nhng lu sau:
-
Trong chng trnh chnh (main), chng ta ci t ngt: cho php ngt c th, cho php
ngt ton cc. i ngt
Chng trnh con x l ngt l chng trnh con nm ngay sau ch th bin dch
#INT_XXX, trong XXX l tn ca ngt c th. V d: #INT_EXT: ngt ngoi
Trong chng trnh con x l ngt: xa c ngt, cm ngt ton cc phng khi ang x
l ngt c ngt xy ra. Sau khi x l d liu trong chng trnh con x l ngt, ta cho
php ngt ton cc li.
Trong phn tip theo, ta s kho st mt s ngt tiu biu nh ngt ngoi INT, ngt thay i trng
thi cc chn cao PORTB, ngt trn Timer 0, ngt trn Timer 1. Cc ngt ngoi vi khc s c
nhc n khi nghin cu cc modun ngoi vi ny.
S kin ngt: s kin ngt xy ra khi c xung i vo chn RB0 ca vi iu khin. Xung l
xung sn dng hay sn m ph thuc bit ci t chn dng xung, bit INTEDG ( bit 6
ca thanh ghi PTION_REG) l 1 hay khng.
Bit cho php ngt: cho php ngt ngoi, bit cho php ngt ngoi INTIE (bit 4 ca
thanh ghi INTCON) phi c set ln 1. Ngoi ra, bit cho php ngt ton cc GIE (bit 7
ca thanh ghi INTCON) cng phi c set ln 1.
C ngt: bit c ngt ngoi l bit INTIF (bit 1 ca thanh ghi INTCON) c t ng set
ln 1 khi c s kin ngt ngoi xy ra. C ny phi c xa bng chng trnh (c th l
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trong chng trnh con phc v ngt) vi iu khin qun l chnh xc cc ln ngt k
tip.
Xa c ngt: CLEAR_INTERRUPT(INT_EXT)
S kin ngt: s kin ngt xy ra khi c s thay i trng thi (1-0 hay 0-1) ca mt trong
cc chn RB7-RB4 ca PortB
Bit cho php ngt: cho php ngt ny, bit cho php ngt RBIE (bit 3 ca thanh ghi
INTCON) phi c set ln 1. Ngoi ra, bit cho php ngt ton cc GIE (bit 7 ca thanh
ghi INTCON) cng phi c set ln 1.
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C ngt: bit c ngt ngoi l bit RBIF (bit 0 ca thanh ghi INTCON) c t ng set
ln 1 khi c s kin ngt ngoi xy ra. C ny phi c xa bng chng trnh (c th l
trong chng trnh con phc v ngt) vi iu khin qun l chnh xc cc ln ngt k
tip.
Xa c ngt: CLEAR_INTERRUPT(INT_RB)
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Ngun ngt: l trng thi trn ca thanh ghi b m timer 0, TMR0 vi iu khin PIC
Bit cho php ngt: cho php ngt ny, bit cho php ngt TMR0IE (bit 5 ca thanh ghi
INTCON) phi c set ln 1. Ngoi ra, bit cho php ngt ton cc GIE (bit 7 ca thanh
ghi INTCON) cng phi c set ln 1.
C ngt: bit c ngt ngoi l bit TMR0IF (bit 2 ca thanh ghi INTCON) c t ng set
ln 1 khi c s kin ngt ngoi xy ra. C ny phi c xa bng chng trnh (c th l
trong chng trnh con phc v ngt) vi iu khin qun l chnh xc cc ln ngt k
tip.
Gn gi tr ban u cho thanh ghi TMR0, ty thuc vo thi gian m ngi lp trnh
mun (xem li bi 3): SET_TIMER0(gi tr)
Xa c ngt: CLEAR_INTERRUPT(INT_TIMER0)
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BI TP:
4.1 Cho s mch nh hnh v:
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R11
10K
U1
13
14
2
3
4
5
6
7
8
9
10
1
OSC1/CLKIN
OSC2/CLKOUT
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/W R
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
33
34
35
36
37
38
39
40
R1
268
R2
220
15
16
17
18
23
24
25
26
R3
222
R4
220
19
20
21
22
27
28
29
30
R5
220
R6
220
PIC16F877A
R7
220
Q1
R8
PNP
4K
R10
Q2
PNP
10k
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C1
R11
R12
10K
10K
30pF
X1
C2
CRYSTAL
30pF
U1
13
14
2
3
4
5
6
7
8
9
10
R9
4K
OSC1/CLKIN
OSC2/CLKOUT
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
33
34
35
36
37
38
39
40
D1
R1
268
LED-RED
D2
R2
220
LED-RED
15
16
17
18
23
24
25
26
19
20
21
22
27
28
29
30
PIC16F877A
D3
R3
222
LED-RED
D4
R4
220
LED-RED
D5
R5
220
LED-RED
D6
R6
220
LED-RED
D7
R7
220
LED-RED
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BI 5: IU CH RNG XUNG-PWM
5.1 Nguyn l hot ng:
B iu ch rng xung to xung hnh ch nht trn 2 chn RC1/CCP2 v RC2/CCP1gi tr xung 2 chn l ngc nhau (b nhau). Thc ra y l mt chc nng ca modun
CCP gm 3 chc nng: Comparation, Capture, PWM.
Nguyn l to xung nh sau:
Khi Thanh ghi b m ca b nh thi Timer 2 t gi tr bng gi tr ca thanh ghi PR2,
u ra xung RC2/CCP1 c set ln mc cao. TMR2 c reset v 0, sau m ln,
khi TMR2 t gi tr bng rng xung, chn RC2/CCP1 c reset v 0. TMR2 tip tc
m ln cho n khi bng gi tr PR2 th chu trnh s lp li nh lc u. Xung ra chn
RC1/CC21 l b ca xung trn chn RC2/CCP1 .
5.2 Chu k xung:
xc nh chu k xung ta a ra phn tch nh sau:
Nh tm hiu v cch lm vic ca cc b timer, ta bit: sau mi chu k lnh gi tr ca
TMR2 s tng ln 1 n v. Nu dng b chia tn s, gi s l 1: N th sau N chu k lnh
gi tr ca TMR2 mi tng ln 1 n v.
Mi chu k lnh gm 4 chu k xung.
CNG TY TNHH CNG NGH CAO ATECKO
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Chu k xung chnh l khong thi gian t lc TMR2=0 cho n khi TMR2=PR2. Suy ra,
tng PR2 n v, hay chnh l chu k xung s bng:
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X1
R9
RV1
10K
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
4K
33
34
35
36
37
38
39
40
LCD1
LM016L
15
16
17
18
23
24
25
26
D0
D1
D2
D3
D4
D5
D6
D7
RB0/INT
RB1
RB2
RA0/AN0
RB3/PGM
RA1/AN1
RB4
RA2/AN2/VREF-/CVREF
RB5
RA3/AN3/VREF+
RB 6/PGC
RA4/T0CKI/C1OUT
RB 7/PGD
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RE0/AN5/RD
RC1/T1OSI/CCP2
RE1/AN6/WR
RC2/CCP1
RE2/AN7/CS
RC3/SCK/SCL
RC4/SDI/SDA
MCLR/Vpp/THV
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RS
RW
E
8
9
10
+5V
OSC1/CLKIN
OSC2/CLKOUT
7
8
9
10
11
12
13
14
2
3
4
5
6
7
VSS
VDD
VEE
30pF
UDK
13
14
4
5
6
CRYSTAL
1
2
3
C2
19
20
21
22
27
28
29
30
PIC16F877A
+12V
R6
U2
2K2
1
6
5
Q5
R5
NPN
1K
OPTOCOUPLER-NPN
Q2
NPN
R7
10k
+12V
R1
1
R11
10k
D32
U1
2K2
DIODE
6
+12V
5
2
Q?
R2
4
MPSA05
1K
OPTOCOUPLER-NPN
R3
10K
RL?
OMI-SH-205D
D1
DIODE
+88.8
BI TP:
1. Lp trnh xut xung PWM c tn s l 1KHZ, rng xung l 50%
2. ng dng PWM
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#include <16F877A.h>
#fuses HS,NOWDT,NOPROTECT,NOLVP
#device *=16 adc=10
#use delay(clock=4000000)
#include <lcd_lib_4bit.c>
//#INCLUDE <KBD.C>
#define col0 PIN_B4
#define col1 PIN_B5
#define col2 PIN_B6
#define col3 PIN_B7
#define row0 PIN_B0
#define row1 PIN_B1
#define row2 PIN_B2
#define row3 PIN_B3
// Keypad layout:
char const KEYS[4][4] = {{'0','1','2','3'},
{'4','5','6','7'},
{'8','9','A','B'},
{'C','D','E','F'}
};
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char kbd_getc( ) {
static byte kbd_call_count;
static short int kbd_down;
static char last_key;
static byte col;
byte kchar;
byte row;
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kchar='\0';
if(++kbd_call_count>KBD_DEBOUNCE_FACTOR) {
switch (col) {
case 0 :
output_low(col0);
output_high(col1);
output_high(col2);
output_high(col3);
//DELAY_MS(1000);
break;
case 1 : output_high(col0);
output_low(col1);
output_high(col2);
output_high(col3);
break;
case 2 : output_high(col0);
output_high(col1);
output_low(col2);
output_high(col3);
break;
case 3 : output_high(col0);
output_high(col1);
output_high(col2);
output_low(col3);
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break;
}
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}
else // NEU KHONG CO PHIM NAO BAM, CHUYEN SANG QUET COT TIEP THEO
{
++col;
if(col>=4)
col=0;
}
}
kbd_call_count=0;//SAU 1 LAN QUET RESET KBD_CALL_COUNT VE 0, DE DOI LAN
QUET TIEP
}
return(kchar);
}
void main()
{
INT C;
INT16 value;
SET_TRIS_D(0X00);
SET_TRIS_B(0X0F);
lcd_putcmd(0x80);
lcd_init();
delay_ms(200);
OUTPUT_B(0XF0);
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while( TRUE )
{
C=KBD_GETC();
IF (C!='\0')
{
LCD_PUTCMD(0X01);
PRINTF(LCD_PUTCHAR,"%C",C);
}
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delay_ms(200);
{
DAT_THU=0;
DO
{
C=KBD_GETC();
IF (C!='\0'& c!='A'&C!='B'& c!='C'&C!='D'& c!='D'&C!='E'&C!='F')
{
DAT_THU =DAT_THU*10;
DAT_THU=DAT_THU+C-0X30;
LCD_PUTCHAR(C);
}
}WHILE(C!='E');
LCD_PUTCMD(0X01);
PRINTF(LCD_PUTCHAR,"GIA TRI PHIM BAM:");
LCD_PUTCMD(0XC2);
PRINTF(LCD_PUTCHAR,"%6LU",DAT_THU);
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