MFPGA DataManagerV1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_misc.all;
use work.MultiPhase_PKG.all;
library UNISIM;
use UNISIM.VComponents.all;
entity MFPGA_DataManagerV1 is
port
(
clk : in std_logic;
RAMclk : in std_logic;
sync : in std_logic;
reset : in std_logic;
-- RX from fifo
-- M1
M1DATAF : IN STD_LOGIC;
M1DATA : IN STD_LOGIC_VECTOR( COMM_DATA_WIDTH - 1
M1DATAOK : OUT STD_LOGIC;
--M2
--M3
--M4
--M5
--M6
-- MxTEMP from SFPGA
SFPGA_DATA_F : IN STD_LOGIC;
SFPGA_DATA : IN STD_LOGIC_VECTOR( COMM_DATA_WIDTH
SFPGA_DATA_OK : OUT STD_LOGIC;
DOWNTO 0);
DOWNTO 0);
DOWNTO 0);
DOWNTO 0);
DOWNTO 0);
DOWNTO 0);
- 1 DOWNTO 0);
-- 1st Mechanical feedback

Mech1F : IN STD_LOGIC;
POS1DATA: IN STD_LOGIC_VECTOR( DATA_WIDTH - 1 DOWNTO 0);
VEL1DATA: IN STD_LOGIC_VECTOR( DATA_WIDTH - 1 DOWNTO 0);
-- 1st Mechanical feedback
Mech2F : IN STD_LOGIC;
POS2DATA: IN STD_LOGIC_VECTOR( DATA_WIDTH - 1 DOWNTO 0);
VEL2DATA: IN STD_LOGIC_VECTOR( DATA_WIDTH - 1 DOWNTO 0);
-M1ENABLE : IN STD_LOGIC;
M2ENABLE : IN STD_LOGIC;
M3ENABLE
M4ENABLE
M5ENABLE
M6ENABLE
DATAR01
DATAR02
DATAR03
DATAR04
DATAR05
DATAR06
DATAR07
DATAR08
DATAR09
DATAR10
DATAR11
DATAR12
DATAR13
DATAR14
DATAR15
DATAR16
:
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IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
STARTTRANSMISSION : OUT STD_LOGIC := '0';

DATA01
DATA02
DATA03
DATA04
DATA05
DATA06
DATA07
DATA08
DATA09
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
:
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OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
T1 : out std_logic
);
end MFPGA_DataManagerV1;
architecture RTL of MFPGA_DataManagerV1 is
COMPONENT FIFOHandlerBRAM
GENERIC
(
DATA_WIDTH : positive := 21;
FIFO_LENGTH : positive := 32
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
WRFifoREQ : IN std_logic;
DataIN : IN std_logic_vector(20 downto 0);
RDFifoOK : IN std_logic;
WRFifoOK : OUT std_logic;
RDFifoREQ : OUT std_logic;
DataOUT : OUT std_logic_vector(20 downto 0)
);
END COMPONENT;
attribute KEEP : string;

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
ADDR01_1,ADDR01_2
ADDR02_1,ADDR02_2
ADDR03_1,ADDR03_2
ADDR04_1,ADDR04_2
ADDR05_1,ADDR05_2
ADDR06_1,ADDR06_2
ADDR07_1,ADDR07_2
ADDR08_1,ADDR08_2
ADDR09_1,ADDR09_2
ADDR10_1,ADDR10_2
ADDR11_1,ADDR11_2
ADDR12_1,ADDR12_2
ADDR13_1,ADDR13_2
ADDR14_1,ADDR14_2
ADDR15_1,ADDR15_2
ADDR16_1,ADDR16_2
:
:
:
:
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std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
std_logic_vector(13
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
(OTHERS
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
signal WRFifoREQ, RDFifoREQ, WRFifoOK, RDFifoOK : std_logic := '0';

--signal DataOUT : STD_LOGIC_VECTOR(COMM_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS =>
'0');
signal DataIN, DataOUT : STD_LOGIC_VECTOR(COMM_DATA_WIDTH DOWNTO 0) := (OTHERS
=> '0');
signal SS, T, RDREQDATA : std_logic := '0';
signal tempPOS1, tempPOS2, tempVEL1, tempVEL2 : STD_LOGIC_VECTOR(COMM_DATA_WIDT
H DOWNTO 0) := (OTHERS => '0');
signal tempMxTEMPF, FIFOReqS: STD_LOGIC := '0';
signal tempPOS1F, tempVEL1F, tempPOS2F, tempVEL2F : STD_LOGIC := '0';
signal BRAMWRstate : std_logic := '0';
signal S : std_logic := '0';
-- FIFO
signal FIFORDaddr : std_logic_vector(addr_width - 1 downto 0) := (OTHERS => '0')
;
signal FIFORDdata : std_logic_vector(data_width - 1 downto 0) := (OTHERS => '0')
;
-- BRAM
signal ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
signal
signal
signal
signal
signal
ADDR: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');

ADDRB: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
ENA, ENB, RDF : std_logic := '0';
DIA, DOB: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
tmpDOB : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
signal RxVECTOR : STD_LOGIC_VECTOR(DATA_VECTOR_LENGTH - 1 DOWNTO 0) := (OTHERS =

> '0');
signal BRAMRDcnt, BRAMRDcntT : integer := 0;
signal BRAMRDstate : std_logic := '0';
signal RDSTATE : unsigned (3 downto 0) := (OTHERS => '0');
begin
RXDATA: process(clk, reset, SFPGA_DATA_F, Mech1F, Mech2F, M1DATAF, M2DATAF, M

3DATAF, M4DATAF, M5DATAF, M6DATAF)
begin
if (rising_edge(clk)) then
if (reset = '0') then
-- Mech1
if (Mech1F = '1') then
tempPOS1 <= std_logic_vector(to_unsigned(POSITIONS(0), ADDR_WIDTH
+1)) & POS1DATA;
tempPOS1F <= '1';
tempVEL1 <= std_logic_vector(to_unsigned(VELOCITY(0), ADDR_WIDTH+
1)) & VEL1DATA;
tempVEL1F <= '1';
end if;
-- Mech2
if (Mech2F = '1') then
tempPOS2 <= std_logic_vector(to_unsigned(POSITIONS(1), ADDR_WIDTH
+1)) & POS2DATA;
tempPOS2F <= '1';
tempVEL2 <= std_logic_vector(to_unsigned
(VELOCITY(1), ADDR_WIDTH+1)) & VEL2DATA;
tempVEL2F <= '1';
end if;
case (RDSTATE) is
-- IDLE
when "0000" =>
M1DATAOK
M2DATAOK
M3DATAOK
M4DATAOK
M5DATAOK
M6DATAOK
<=
<=
<=
<=
<=
<=
'0';
'0';
'0';
'0';
'0';
'0';
SFPGA_DATA_OK <= '0';

DataIN <= (OTHERS => '0');
if
(M1DATAF = '1') then

RDSTATE <= "0001";
elsif (M2DATAF = '1') then
RDSTATE <= "0010";
RDSTATE <= "0011";
RDSTATE <= "0100";
RDSTATE <= "0101";
RDSTATE <= "0110";
elsif (SFPGA_DATA_F = '1') then
RDSTATE <= "0111";
elsif (tempVEL1F = '1') then
RDSTATE <= "1001";
elsif (tempPOS1F = '1') then
RDSTATE <= "1000";
elsif (tempVEL2F = '1') then
RDSTATE <= "1011";
elsif (tempPOS2F = '1') then
RDSTATE <= "1010";
end if;
-- READ FROM M1
when "0001" =>
DataIN <= std_logic_vector(to_unsigned(M1FPGA_DATA
_POS(to_integer(unsigned(M1DATA(COMM_DATA_WIDTH - 1 downto COMM_DATA_WIDTH - ADD
R_WIDTH)))), ADDR_WIDTH+1)) & M1DATA(COMM_DATA_WIDTH - ADDR_WIDTH - 1 downto 0);
if (FIFOReqS = '0' ) then
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
if (WRFifoOK = '1') then
M1DATAOK <= '1';
RDSTATE <= "1111";
FIFOReqS <= '0';
end if;
-- READ FROM M2
when "0010" =>
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
M2DATAOK <= '1';
RDSTATE <= "1111";

FIFOReqS <= '0';
end if;
-- READ FROM M3
when "0011" =>
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
M3DATAOK <= '1';
RDSTATE <= "1111";
FIFOReqS <= '0';
end if;
-- READ FROM M4
when "0100" =>
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
M4DATAOK <= '1';
RDSTATE <= "1111";
FIFOReqS <= '0';
end if;
-- READ FROM M5
when "0101" =>
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
M5DATAOK <= '1';
RDSTATE <= "1111";
FIFOReqS <= '0';
end if;
-- READ FROM M6
when "0110" =>
WRFifoREQ <= '1';

FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
M6DATAOK <= '1';
RDSTATE <= "1111";
FIFOReqS <= '0';
end if;
-- READ FROM SFPGA_DATA_interface
when "0111" =>
DataIN <= std_logic_vector(to_unsigned(SFPGA_DATA_
POS(to_integer(unsigned(SFPGA_DATA(COMM_DATA_WIDTH - 1 downto COMM_DATA_WIDTH ADDR_WIDTH)))), ADDR_WIDTH+1)) & SFPGA_DATA(COMM_DATA_WIDTH - ADDR_WIDTH - 1 dow
nto 0);
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
RDSTATE <= "1111";
FIFOReqS <= '0';
end if;
-- Mech 1
when "1000" =>
DATAIN <= tempPOS1;
-WRFifoREQ <=
-if (WRFifoOK
-WRFifoREQ <=
--tempPOS1F <=
--
'1';
= '1') then
'0';
RDSTATE <= "0000";
'0';
end if;

WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
RDSTATE <= "0000";
FIFOReqS <= '0';
tempPOS1F <= '0';
end if;
when "1001" =>
DATAIN <= tempVEL1;

WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
RDSTATE <= "0000"; -- go direct to idle
FIFOReqS <= '0';
tempVEL1F <= '0';
end if;
--WRFifoREQ <=
-if (WRFifoOK
-WRFifoREQ <=
--tempVEL1F <=
--
DATAIN <= tempVEL1;

'1';
= '1') then
'0';
'0';
end if;
-- if (FIFOReqS = '0' ) then

------------ Mech 2
when "1010" =>
WRFifoREQ <= '1';

FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
FIFOReqS <= '0';
tempMech1F <= '0';
end if;
DATAIN <= tempPOS2;
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
RDSTATE <= "0000";-- go direct to idle
FIFOReqS <= '0';
tempPOS2F <= '0';

end if;
when "1011" =>
DATAIN <= tempVEL2;
WRFifoREQ <= '1';
FIFOReqS <= '1';
else
WRFifoREQ <= '0';
end if;
FIFOReqS <= '0';
tempVEL2F <= '0';
end if;
-- STATUS
when "1100" =>
NULL;
when "1111" => RDSTATE <= "0000";
M1DATAOK <= '0';
M2DATAOK <= '0';
M3DATAOK <= '0';
M4DATAOK <= '0';
M5DATAOK <= '0';
M6DATAOK <= '0';
when OTHERS => RDSTATE <= "0000";
M1DATAOK <= '0';
M2DATAOK <= '0';
M3DATAOK <= '0';
M4DATAOK <= '0';
M5DATAOK <= '0';
M6DATAOK <= '0';
end case;
else
FIFOReqS <= '0';
WRFifoREQ <= '0';
DataIN <= (OTHERS => '0');
M1DATAOK <= '0';
M2DATAOK <= '0';
M3DATAOK <= '0';
M4DATAOK <= '0';
M5DATAOK <= '0';
M6DATAOK <= '0';
tempPOS1F <= '0';
tempPOS1 <= (OTHERS => '0');
tempPOS2F <= '0';
tempPOS2 <= (OTHERS => '0');
tempVEL1F <= '0';
tempVEL1 <= (OTHERS => '0');
tempVEL2F <= '0';
tempVEL2 <= (OTHERS => '0');
end if;
end if;
end process;
FifoBRAM: FIFOHandlerBRAM
GENERIC MAP (21, 32)
PORT MAP(
clk => clk,
rst => reset,
WRFifoREQ => WRFifoREQ,
WRFifoOK => WRFifoOK,
DataIN => DataIN,
RDFifoOK => RDFifoOK,
RDFifoREQ => RDFifoREQ,
DataOUT => DataOUT
);
T1 <= RDFifoREQ;
RDFifoBRAM_WRBRAM : process(clk, reset)
begin
-S <= '0';
if (BRAMWRstate = '1') then
BRAMWRstate <= '0';
RDFifoOK <= '0';
ENA <= '1';
else
ENA <= '0';
end if;
-& "0000";
if (RDFifoREQ = '1') then

ADDRA <= "00" & DATAOUT(COMM_DATA_WIDTH - 1 downto DATA_WIDTH)
ADDRA <= '0' & DATAOUT(20 downto 12) & "0000";

DIA <= X"00000" & DATAOUT(11 downto 0);
RxVECTOR(to_integer(unsigned(DATAOUT(COMM_DATA_WIDTH downto DATA_
WIDTH)))) <= '1';
RDFifoOK <= '1';
BRAMWRstate <= '1';
----------
if (DATAOUT(20 downto 12) = "00100011") then

S <= '1';
end if;
end if;
if (sync = '1') then

RxVECTOR <= (OTHERS => '0');
end if;
else
RDFifoOK <= '0';
BRAMWRstate <= '0';
ENA <= '0';
RxVECTOR <= (OTHERS => '0');
end if;
end if;
end process;
RDBRAM : process(clk, reset, sync)

begin
STARTTRANSMISSION <= '0';
if (sync = '1') then
BRAMRDcntT <= 0;
BRAMRDcnt <= 0;
-- when synch occurs, load data addresses that have to be sent
ADDR01_1 <= DATAR01(21 downto 12) & "0000";
ADDR01_2 <= DATAR01( 9 downto 0) & "0000";

RDREQDATA <= '1'; -- start reading request data
RDF <= '0';
end if;
-- start to read mandatory data only if requested data is already loaded from th
e memory, and the mandatory data is received
if (RDREQDATA = '0') then
if (RDF = '0') then -- data not readed
--------------------------------
if (M6ENABLE = '1') then -- m6 is in use

if (RxVector(M6FPGA_DATA_POS(4)) = '1') then
BRAMRDstate <= '1';
BRAMRDcnt <= 0;
end if;
elsif (M5ENABLE = '1') then -- m5 is in use
BRAMRDstate <= '1';
BRAMRDcnt <= 0;
end if;
BRAMRDstate <= '1';
BRAMRDcnt <= 0;
end if;
BRAMRDstate <= '1';
BRAMRDcnt <= 0;
end if;
BRAMRDstate <= '1';
BRAMRDcnt <= 0;
end if;
BRAMRDstate <= '1';
BRAMRDcnt <= 0;
end if;
end if;
end if;
end if;
--------------
read requested data

case (BRAMRDcnt) is
when 0 =>
ADDRB <= ADDR11_1;

BRAMRDcnt <= BRAMRDcnt + 1;
when 1 =>
when 2 =>
when 3 =>
ENB <= '1';

ENB <= '0';
-------------------------------------------------------------
when 4 =>

DATA11(23 downto 12)<= DOB(11 downto 0);
ADDRB <= ADDR11_2;
when 5 =>
ENB <= '1';
when 6 =>
when 7 =>
when 8 =>
BRAMRDcnt <= BRAMRDcnt

ENB <= '0';
DATA11(11 downto 0) <=
ADDRB <= ADDR12_1;
+ 1;
+ 1;
+ 1;
+ 1;
DOB(11 downto 0);
when 9 =>
ENB <= '1';
when 10 => BRAMRDcnt <= BRAMRDcnt + 1;
when 11 => ENB <= '0';
ADDRB <= ADDR12_2;
when 13 =>
ENB <= '1';

ENB <= '0';
DATA12(11 downto 0) <= DOB(11 downto 0);
ADDRB <= ADDR13_1;
when 14 =>
when 15 =>
when 17 =>
ENB <= '1';
when 19 => ENB <= '0';
ADDRB <= ADDR13_2;
when 21 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR14_1;
when 22 =>
when 23 =>
when 25 =>
ENB <= '1';
-------------------------------------------------------------

ENB <= '0';
ADDRB <= ADDR14_2;
when 29 => ENB <= '1';
when 26 =>
when 27 =>

ENB <= '0';
ADDRB <= ADDR15_1;
when 30 =>
when 31 =>
when 33 =>
ENB <= '1';
when 35 => ENB <= '0';
ADDRB <= ADDR15_2;
when 37 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR16_1;
when 38 =>
when 39 =>
when 41 =>
ENB <= '1';
when 43 => ENB <= '0';
ADDRB <= ADDR16_2;
when 45 =>
ENB <= '1';

ENB <= '0';
when 46 =>
when 47 =>
when 49 => BRAMRDcnt <= 0;

RDREQDATA <= '0';
-------------------------------------------------------------
when OTHERS => NULL;

end case;
end if;
-- read mandatory data
if (BRAMRDstate = '1') then
case (BRAMRDcnt) is
when 0 =>
ADDRB <= ADDR01_1;
when 1 =>
ENB <= '1';
when 2 =>
when 3 =>
when 4 =>
ENB <= '0';

ADDRB <= ADDR01_2;
when 5 =>
ENB <= '1';
when 6 =>
when 7 =>
when 8 =>

ENB <= '0';
DATA01(11 downto 0) <=
ADDRB <= ADDR02_1;
+ 1;
+ 1;
+ 1;
+ 1;
DOB(11 downto 0);
when 9 =>
ENB <= '1';
when 11 => ENB <= '0';
ADDRB <= ADDR02_2;
when 13 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR03_1;
when 14 =>
when 15 =>
when 17 =>
ENB <= '1';
-------------------------------------------------------------

ENB <= '0';
ADDRB <= ADDR03_2;
when 18 =>
when 19 =>
when 21 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR04_1;
when 22 =>
when 23 =>
when 25 =>
when 26 =>
when 27 =>
when 28 =>
when 29 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR04_2;
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR05_1;
when 30 =>
when 31 =>
when 33 =>
ENB <= '1';
when 35 => ENB <= '0';
ADDRB <= ADDR05_2;
when 37 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR06_1;
when 38 =>
when 39 =>
-------------------------------------------------------------
when 41 =>
ENB <= '1';
when 43 => ENB <= '0';
ADDRB <= ADDR06_2;
when 45 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR07_1;
when 46 =>
when 47 =>
when 49 =>
ENB <= '1';
when 51 => ENB <= '0';
ADDRB <= ADDR07_2;
when 53 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR08_1;
when 54 =>
when 55 =>
when 57 =>
ENB <= '1';
when 59 => ENB <= '0';
ADDRB <= ADDR08_2;
when 61 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR09_1;
when 62 =>
when 63 =>
---------------------------------------------------
--
when 65 =>
ENB <= '1';
when 67 => ENB <= '0';
ADDRB <= ADDR09_2;
when 69 =>
ENB <= '1';

ENB <= '0';
ADDRB <= ADDR10_1;
when 70 =>
when 71 =>
when 73 =>
ENB <= '1';
when 75 => ENB <= '0';
ADDRB <= ADDR10_2;
when 77 =>
ENB <= '1';

ENB <= '0';
when 78 =>
when 79 =>

BRAMRDstate <= '0';
RDF <= '1';
end case;
end if;
read requested data

case (BRAMRDcntT) is
when 0 =>
when 1 =>
ADDRB <= ADDR11_1;
ENB <= '1';

when 2 =>
when 3 =>
ENB <= '0';
when 4 =>
ADDRB <= ADDR11_2;
when 5 =>
ENB <= '1';
when 6 =>
when 7 =>
ENB <= '0';
when 8 =>
ADDRB <= ADDR12_1;
when 9 =>
ENB <= '1';
when 10 =>
when 11 =>
ENB <= '0';
when 12 =>
ADDRB <= ADDR12_2;
when 13 =>
ENB <= '1';
when 14 =>
when 15 =>
ENB <= '0';
when 16 =>
ADDRB <= ADDR13_1;
when 17 =>
ENB <= '1';
when 18 =>
when 19 =>
ENB <= '0';
when 20 =>
ADDRB <= ADDR13_2;
when 21 =>
ENB <= '1';
when 22 =>
when 23 =>
ENB <= '0';
when 24 =>
ADDRB <= ADDR14_1;
when 25 =>
ENB <= '1';
when 26 =>
when 27 =>
ENB <= '0';
when 28 =>
ADDRB <= ADDR14_2;
when 29 => ENB <= '1';
when 30 =>
when 31 =>
ENB <= '0';
when 32 =>
ADDRB <= ADDR15_1;
when 33 =>
ENB <= '1';
when 34 =>
when 35 =>
ENB <= '0';
when 36 =>
ADDRB <= ADDR15_2;
when 37 =>
ENB <= '1';
when 38 =>
when 39 =>
ENB <= '0';
when 40 =>
ADDRB <= ADDR16_1;
when 41 =>
ENB <= '1';
when 42 =>
when 43 =>
ENB <= '0';
when 44 =>
ADDRB <= ADDR16_2;
when 45 =>
ENB <= '1';
when 46 =>
when 47 =>
ENB <= '0';
when 48 =>

when 49 => BRAMRDcntT <= 0;
RDREQDATA <= '0';
BRAMRDstate <= '1';
end case;
BRAMRDcntT <= BRAMRDcntT + 1;
end if;
-- read mandatory data
if (BRAMRDstate = '1') then
case (BRAMRDcnt) is
when 0 =>
ADDRB <= ADDR01_1;
when 1 =>
ENB <= '1';
when 2 =>
when 3 =>
ENB <= '0';
when 4 =>
ADDRB <= ADDR01_2;
when 5 =>
ENB <= '1';
when 6 =>
when 7 =>
ENB <= '0';
when 8 =>
ADDRB <= ADDR02_1;
when 9 =>
ENB <= '1';
when 10 =>
when 11 =>
ENB <= '0';
when 12 =>
ADDRB <= ADDR02_2;
when 13 =>
ENB <= '1';
when 14 =>
when 15 =>
ENB <= '0';
when 16 =>
ADDRB <= ADDR03_1;
when 17 =>
ENB <= '1';
when 18 =>
when 19 =>
ENB <= '0';
when 20 =>
ADDRB <= ADDR03_2;
when 21 =>
ENB <= '1';
when 22 =>
when 23 =>
ENB <= '0';
when 24 =>
ADDRB <= ADDR04_1;
when 25 =>
ENB <= '1';
when 26 =>
when 27 =>
ENB <= '0';
when 28 =>
ADDRB <= ADDR04_2;
when 29 => ENB <= '1';
when 30 =>
when 31 =>
ENB <= '0';
when 32 =>
ADDRB <= ADDR05_1;
when 33 =>
ENB <= '1';
when 34 =>
when 35 =>
ENB <= '0';
when 36 =>
ADDRB <= ADDR05_2;
when 37 =>
ENB <= '1';
when 38 =>
when 39 =>
ENB <= '0';
when 40 =>
ADDRB <= ADDR06_1;
when 41 =>
ENB <= '1';
when 42 =>
when 43 =>
ENB <= '0';
when 44 =>
ADDRB <= ADDR06_2;
when 45 =>
ENB <= '1';
when 46 =>
when 47 =>
ENB <= '0';
when 48 =>
ADDRB <= ADDR07_1;
when 49 =>
ENB <= '1';
when 50 =>
when 51 =>
ENB <= '0';
when 52 =>
ADDRB <= ADDR07_2;
when 53 =>
ENB <= '1';
when 54 =>
when 55 =>
ENB <= '0';
when 56 =>
ADDRB <= ADDR08_1;
when 57 =>
ENB <= '1';
when 58 =>
when 59 =>
ENB <= '0';
when 60 =>
ADDRB <= ADDR08_2;
when 61 =>
ENB <= '1';
when 62 =>
when 63 =>
ENB <= '0';
when 64 =>
ADDRB <= ADDR09_1;
when 65 =>
ENB <= '1';
when 66 =>
when 67 =>
ENB <= '0';
when 68 =>
ADDRB <= ADDR09_2;
when 69 =>
ENB <= '1';
when 70 =>
when 71 =>
ENB <= '0';
when 72 =>
ADDRB <= ADDR10_1;
when 73 =>
ENB <= '1';
when 74 =>
when 75 =>
ENB <= '0';
when 76 =>
ADDRB <= ADDR10_2;
when 77 =>
ENB <= '1';
when 78 =>
when 79 =>
ENB <= '0';
when 80 =>
BRAMRDstate <= '0';
RDF <= '1';
end case;
end if;
else
RDF <= '0';
BRAMRDstate <= '0';
BRAMRDcnt <= 0;
BRAMRDcntT <= 0;
RDREQDATA <= '0';
DATA01 <= (OTHERS
DATA02 <= (OTHERS
DATA03 <= (OTHERS
DATA04 <= (OTHERS
DATA05 <= (OTHERS
DATA06 <= (OTHERS
DATA07 <= (OTHERS
DATA08 <= (OTHERS
DATA09 <= (OTHERS
DATA10 <= (OTHERS
DATA11 <= (OTHERS
DATA12 <= (OTHERS
DATA13 <= (OTHERS
DATA14 <= (OTHERS
DATA15 <= (OTHERS
DATA16 <= (OTHERS
STARTTRANSMISSION
end if;
end if;
end process;
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
<=
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0');
'0';
RAMB16BWER_inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 18,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 1,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INITP_00 to INITP_07: Initial memory contents.
INITP_00 => X"000000000000000000000000000000000000000000000000000000000000
0000",
INITP_01 => X"000000000000000000000000000000000000000000000000000000000000
0000",
INITP_02 => X"000000000000000000000000000000000000000000000000000000000000
0000",
INITP_03 => X"000000000000000000000000000000000000000000000000000000000000
0000",
INITP_04 => X"000000000000000000000000000000000000000000000000000000000000
0000",
INITP_05 => X"000000000000000000000000000000000000000000000000000000000000
0000",
INITP_06 => X"000000000000000000000000000000000000000000000000000000000000

0000",
INITP_07 => X"000000000000000000000000000000000000000000000000000000000000
0000",
-- INIT_00 to INIT_3F: Initial memory contents.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000
000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000
000",
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GEN
ERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "READ_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output: Port A data
DOA => OPEN,
-- 32-bit output: A port data output
DOPA => OPEN,
-- 4-bit output: A port parity output
-- Port B Data: 32-bit (each) output: Port B data
DOB => DOB,
-- 32-bit output: B port data output
DOPB => OPEN,
-- 4-bit output: B port parity output
-- Port A Address/Control Signals: 14-bit (each) input: Port A address and
control signals
ADDRA => ADDRA, -- 14-bit input: A port address input
CLKA => clk,
-- 1-bit input: A port clock input
ENA => ENA,
-- 1-bit input: A port enable input -- always enabled
REGCEA => '0', -- 1-bit input: A port register clock enable input
RSTA => '0',
-- 1-bit input: A port register set/reset input
WEA => "1111",
-- 4-bit input: Port A byte-wide write enable input -always write
-- Port A Data: 32-bit (each) input: Port A data
DIA => DIA,
-- 32-bit input: A port data input
DIPA => "0000",
-- 4-bit input: A port parity input
-- Port B Address/Control Signals: 14-bit (each) input: Port B address and
control signals
ADDRB => ADDRB, -- 14-bit input: B port address input
CLKB => clk,
-- 1-bit input: B port clock input
ENB => ENB,
-- 1-bit input: B port enable input
REGCEB => '1', -- 1-bit input: B port register clock enable input
RSTB => '0',

-- 1-bit input: B port register set/reset input
WEB => "0000",
-- 4-bit input: Port B byte-wide write enable input - always read
-- Port B Data: 32-bit (each) input: Port B data
DIB => (OTHERS => '0'),
-- 32-bit input: B port data input
DIPB => "0000"
-- 4-bit input: B port parity input
);
-- End of RAMB16BWER_inst instantiation
end RTL;

MFPGA DataManagerV1

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MFPGA DataManagerV1

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library IEEE;

-- 1st Mechanical feedback

STARTTRANSMISSION : OUT STD_LOGIC := '0';

attribute KEEP : string;

signal WRFifoREQ, RDFifoREQ, WRFifoOK, RDFifoOK : std_logic := '0';

ADDR: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');

signal RxVECTOR : STD_LOGIC_VECTOR(DATA_VECTOR_LENGTH - 1 DOWNTO 0) := (OTHERS =

RXDATA: process(clk, reset, SFPGA_DATA_F, Mech1F, Mech2F, M1DATAF, M2DATAF, M

SFPGA_DATA_OK <= '0';

(M1DATAF = '1') then

RDSTATE <= "1111";

WRFifoREQ <= '1';

if (FIFOReqS = '0' ) then

DATAIN <= tempVEL1;

DATAIN <= tempVEL1;

-- if (FIFOReqS = '0' ) then

WRFifoREQ <= '1';

tempPOS2F <= '0';

if (RDFifoREQ = '1') then

ADDRA <= '0' & DATAOUT(20 downto 12) & "0000";

if (DATAOUT(20 downto 12) = "00100011") then

if (sync = '1') then

RDBRAM : process(clk, reset, sync)

ADDR16_1 <= DATAR16(21 downto 12) & "0000";

if (M6ENABLE = '1') then -- m6 is in use

read requested data

ADDRB <= ADDR11_1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

BRAMRDcnt <= BRAMRDcnt + 1;

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

when 49 => BRAMRDcnt <= 0;

when OTHERS => NULL;

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '0';

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';

BRAMRDcnt <= BRAMRDcnt + 1;

ENB <= '1';