Digital Control of A Boost PFC With SAB80C166 Microcontroller

Lesson 6
Digital Control of a Boost PFC

with SAB80C166 Microcontroller
November 1999
Simone Buso - University of Padova - Lesson 6
Design Goals
Developing a fully digital control for a boost
power factor preregulator.
Exploiting the potentialities of digital control to
improve the systems dynamic performance.
Keeping controllers complexity as low as
possible so as to use a standard microcontroller
for the practical implementation.
November 1999
System Structure
D
+
Vg
iL
V'g
Vo
S
R
iS
A/D Converter
iS Vo
V'g
Vo ref
November 1999
g Vo
I
+
KI
PWM
+
V
KV
80C166C
3
Power Converter Design

Design Specifications:
Input Voltage ...............

Output Voltage ......................
Nominal Output Power.................
Switching Frequency ..............
Vg = 110 V RMS
Vo = 200 V
Po = 200 W
fsw = 20 KHz
Design Choice:
Use of CCM and average current mode control
November 1999

Io
iin
id
Io
+
vin
Vo
= i t
vin = 2 Vin,RMS sen()
iin = 2 Iin,RMS sen()
Po
Pin = Vin,RMS Iin,RMS =
Po = Vo Io
November 1999

2
pin () = 2 Vin,RMS Iin,RMS sen () = 2 Po sen ()

pin () = po () = Vo id ()
id () = 2
Vin,RMSIin,RMS
Vo
sen2 () = 2 Io sen2 ()
The power balance based equations are totally

independent on the PFC topology.
The 100Hz (Europe) output ripple is inherent in
the PFC operation and cannot be avoided without
distorting the input current.
November 1999

The input current equation, in the Boost PFC
topology is used to design the converter inductor.
2 Po
IL,max = Iin,max =
= 2.7 A
Vin,RMS
vin () t on = [Vo vin ()] t off
vin ()
d() = 1
,
Vo
November 1999
t on
d=
T
Peak input
current
Voltage integral
balance

vin ()
vin ()
iL =
t on =
d()
L
fs L
Inductor
current ripple
Vo
i L ,max = i L
Vo =
Vin =
4 fsw L
2
Maximum
current ripple
i L ,max = 20% IL,max = 0.54 A
Design choice
Vo
L=
= 4.6 mH
4 fsw iL,max
Needed
inductor value
November 1999

The output current equation is used to design
the output capacitor.
3
1
1
Io
Vc =
sen(2)
=
Io cos(2)d =
i C
2 in C
in C
The integration of the capacitive current

(alternating part of the output current) over half
of the period, gives the peak to peak output
voltage ripple. This depends on the load
current and on the C value.
November 1999

Imposing the voltage ripple to be:
VC < 5% Vo = 10 V
the minimum needed output capacitor value is
found:
Io
C
= 320F
in Vc
C = 470F
November 1999
10

Converter switch and diode can be selected
analyzing the current and voltage stresses:
VDS > Vo,nom= 200 V
IS,max = ID,max = IL,max +
iL,max
2
3A
Operating frequency > fsw = 20 KHz

A possible choice is the following:
NMOS BUZ60
November 1999
RURD460
11
Control Scheme
iL
D
+
Vg
Vi
R VO
S
PWM Modulator
1
Kv
A
1
Ko
Rs
A
K'vd
KR
current
error amplifier
Kvd
_
PI - I
KiD
zoh
+
sinusoidal
reference
Vx
c
x= ic
i
multiplier
Vc
_
KoD
PI -V
voltage
error amplifier
A
D
Vref
PFC DIGITAL CONTROLLER

November 1999
12
Control Strategy
The control strategy replicates the standard
analog control structure.
An inner average current control loop is
controlled by an outer voltage loop. The current
template is given by the rectified input voltage.
Some refinements are introduced exploiting the
potentialities of the digital implementation:
soft-start;
digital notch filter on the output voltage
feedback signal.
November 1999
13
Average Current Control Design

State space averaging allows to calculate the
transfer functions which are needed to design
the controllers. In the case of the current loop,
the analysis shows that:
Vo
iL
d
sL
is, with very good approximation, the transfer
function seen by the control system. The
current regulator can be designed as if the load
were purely inductive.
November 1999
14

vin
vx
+
_
Kpi + Kii
s
-sTc /2
Rs
1
sL
d
1
2Vosc
Vo
sL
i L* +
iL
Kr
Desired bandwidth: 2 kHz.

Desired phase margin: 70.
Average current value (in CCM) is attained by
synchronizing PWM and sampling processes.
November 1999
15

H [dB]
Ti (j)
Vo Kr
sL 2 Vosc
Kpi Kii
+ s
fci = 2 KHz
fzi
log (
)
Asymptotic Bode Diagram

November 1999
16

Vo R s Kr Kpi
Ti ( j) =
=1
ci L
2 Vosc
2 Vosc ci L
Kpi =
= 2.7
Vo R s Kr
Proportional gain is calculated imposing the
desired cross-over frequency.
November 1999
17

1 Kpi ci
i = 90 90 + tan
1 Kpi ci
mi = tan
ii
Kii
Integral gain is calculated imposing the

desired phase-margin.
This has to be over-sized to take into account
the holder delay.
ci Tc
zoh =
= 18
2
November 1999
18

The PI integral gain is calculated according to
the following equations:
Kii =
Kpi ci
tan(mi )
fci
fzi =
tan(mi )
Kii 9087(rad / s)
fzi 535Hz
November 1999
19

Due to the reduced current loop bandwidth, the
regulated current shows an unexpected behavior.
It appears to be phase-leading with respect to the
input voltage, from which the current reference is
extracted.
This is not desirable because it negatively affects
the systems power factor.
The practical solution is to delay the current
reference, to keep current and voltage in phase.
The following analysis discusses the origin of the
problem.
November 1999
20
Input Current Phase Displacement

[V]
[A]
3
180
ig
2
Vg
120
60
-1
- 60
-2
- 120
-3
- 180
0
10
The line current is

about 7 phaseleading the line
voltage
20
[ms]
November 1999
21

^
Vg
^
iref
^i
KI(s)
iL
G1(s) =
G2 (s)
G1 (s)
+
+
^
iL
Current control
block diagram
Vo
s V oC +
+ (1 ) iL
R
=
L
2
s LC + s + (1 )2
1
R
sC +
iL
R
G2 (s) =
=
g
L
V
2
s LC + s + (1 )2
R
November 1999
22

iL
G1( s) K I (s )
W1( s) =
=
iref 1 + G1( s) K I (s)
iL
G2 (s)
W2 (s) =
=
Vg 1 + G1(s ) KI ( s)
The closed-loop transfer

function W(s) from line
voltage to inductor
current can be calculated
from the previous block
diagram.
iL
W ( s) =
= g VO W1(s) + W2 (s)
Vg
November 1999
23

Phase Shift
[deg ]
Current Loop Gain

[dB]
m = 75
80
50
7 70
70
70
6
5
60
60
4
50
3 50
2
60
40
m = 75
1
1
Bandwidth [kHz]
November 1999
Bandwidth [kHz]
24

Analysis Final Results:
the phase displacement is high when the
current loop gain at the line frequency is
low.
the current loop gain at the line frequency is
low when the phase margin is high or the
bandwidth is low.
The phase displacement can be easily
corrected introducing a delay line between
the reference generation and the current
loop.
November 1999
25
Vin
delay = mc T
A
D
Kv
i
x= ic
c
K'vD
sinusoidal
reference
Delay line
KvD
VX
multiplier
VC
Implementation of the delay line

November 1999
26

To reduce the number of data moves the line is
implemented using address pointers.
The part of program which deals with the delay
line is the following:
OKR:
November 1999
mov R0, #line

add R0, #nline
mov [R1], ADDAT
add R1, #2
cmp R1, R0
jmp le, OKR
mov R1, #line
mov R4, [R1]
; head of the line address

; end of line address
; WRITE from A/D to k position
; k k+1
; check if end of line
; conditional jump
; if end of line, point the head
; READ from k+1 position
27
Output Voltage Control Design

voltage
error amplifier
Vref +
_
vc
rp
Kpv + K iv
gc
s
1+sCrp
Vo
1
Ko
Desired bandwidth: 20Hz.

Desired phase margin: > 70.
The loop bandwidth can be increased by notchfiltering the output voltage feedback signal to
eliminate the 100Hz ripple.
November 1999
28
Output Voltage Control Design

The design procedure for the voltage loop is
essentially the same used for the current loop.
Also in this case the systems transfer function
is given by state-space averaging analysis.
Imposing the cross-over frequency and phase
margin constraints the PI gains can be
calculated. The final results are:
c C
Kpv =
K o = 12.31
gc
Kiv = 1289 (rad / s)
November 1999
fzv 17Hz
29
Discretization of the Controllers

Since the control bandwidths are sufficiently
low, as compared to the sampling frequency, it
is possible to use a simple discretization
method, without an excessive frequency
response distortion.
In this case Euler integration method was used.
This uses the following Z-form, where Tc is the
sampling period:
1 z 1
s=
Tc
November 1999
30
Discretization of the Controllers

It is worth noting that, in these conditions, the
use of different discretization techniques, such
as the trapezoidal Z-form, only implies a small
variation of the controllers gains.
It is also worth noting that the rectangular ( Euler)
Z-form maintains the proportional gain and only
modifies the integral gain (it is multiplied by Tc).
Finally, both the PIs include anti wind-up action,
to improve the control behavior in case of
saturation.
November 1999
31
Voltage Loop Bandwidth Improvement

By means of a suitably designed digital notch
filter it is possible to eliminate the 100 Hz
component from the voltage feedback signal.
This allows to increase the voltage loop
bandwidth without causing additional distortion
in the line current, or to get a lower distortion if
the same bandwidth is maintained.
In fact, the feedback signal component, whose
compensation would imply input current
distortion can be almost totally removed.
November 1999
32
Voltage Loop Bandwidth Improvement
Vo
1
Ko
ev
A
D
Vref
(2666h)
Vc
100 Hz
notch filter
y
1
y
2
low-pass
PI -V
KoD
voltage
error amplifier
Implementation of output voltage notch filter

November 1999
33
Notch Filter Design

z
p
1
z1
|H
NOTCH
z2
= Tc
= Tc
Y1( z )
1 + b1z 1 + z 2
HNOTCH( z ) =
=
E v (z ) 1 a1z 1 a2 z 2
November 1999
34
Notch Filter Design

The filter coefficients can be designed as follows:
b1 = 2 cos( o );
a1 = 2 r cos( o );
a2 = r 2
With r = 0.95 the following values can be found:
b1 = -1.99901
November 1999
a1 = 1. 89906
a2 = -0.9025
35
Notch Filter Algorithm

ev'(k)
ev(k)
y1(k)
+5
-5
z-1
ev(k-1)
b1
a1
-1
z-1
y1(k-1)
a2
z-1
z-1
ev(k-2)
y1(k-2)
y1(k) = a1 y1(k 1) + a2 y1(k 2) + e v (k ) + b1 e v (k 1) + e v (k 2)
Implementation of output voltage notch filter

November 1999
36
Notch Filter Design

The notch filter presents some drawbacks:
the gain in the high frequency region is higher
than unity;
the filter introduces a phase rotation which
reduces the voltage loop phase margin.
Countermeasures can be taken:
compensating the high frequency amplification
with a low-pass filter;
compensating the phase rotation over-sizing
the voltage loop phase margin.
November 1999
37
Low-Pass Filter Design

|HLOW-PASS|
b/(1-a)
a
s
= Tc
Y2 ( z )
b
HLP ( z ) =
=
Y1( z) 1 az 1
November 1999
38

The design of the low-pass filter can be done as
follows:
s = 2 fs Tc = 0.1571
Normalized cut-off
frequency.
1
a=
1 s = 0.8429
1+ s
To get desired cutoff frequency.
b = 1 a= s = 0.1571
November 1999
To get unity low

frequency gain.
39

The implementation is the following:
y1(k)
+5
y2(k)
b
-5
-1
y2(k-1)
which corresponds to the following equation:

y2 (k ) = a y2 (k 1) + b y1(k )
November 1999
40
Digital Control Implementation

int T0
INIT
INT ?
no
Flow chart
of control
algorithm
November 1999
PEC channel 0
int CC1
start A/D
int A/D
end A/D
yes
1 Current Regulator
2 Current Reference
Notch Filter
3
Voltage Regulator
41

converted
variable
Is
Ug
Uo
9.7 s
9.7 s
9.7 s
EMPTY
start
A/D
Current
Loop
Iref
10.4 s
5.5 s
Output
Voltage
Voltage
Loop
Notch Filter
12 s
7.2 s
switch
command
ton/2
Tc = 50 s
Control Timing
November 1999
42

The program starts at the end of current
conversion. With respect to the modulation
period the conversion can start after a variable
delay, depending on the duty cycle:
23%<d<100%11s<t on <50s
6s<
t on
2
<25s
The current control loop always ends within the

modulation period, so that the control delay is
minimum.
November 1999
43

The other control tasks can extend in the
following modulation period. Therefore, a
modulation cycle delay has to be expected.
The external loop has a very low bandwidth, so
the delay is not critical.
Since the A/D conversion mode is continuous,
the only constraint is not to waste any
converted value.
Additionally, the total duration of the algorithm
must be lower than the modulation period.
November 1999
44

end A/D
int A/D
jmp [R15]
CUR_PI:
1
mov R15,#CUR_REF
CUR_REF:
2
VOUT :
3
mov R15,#VOUT
mov R15,#CUR_PI
Handling of the interrupt routines

November 1999
45
Experimental Measurements
[V]
[A]
165
V'g
132
99
iL
66
33
November 1999
Rectified
voltage
and
converter
input
current
46
120
[A]
4
60
- 60
- 60
- 120
- 120
-1
- 180
-1
- 180
-2
- 240
-2
- 240
[A]
[V]
Vg
3
2
ig
10 12 14 16 18 20
[ms]
without notch filter

November 1999
[V]
120
Vg
60
0
ig
10 12 14 16 18 20
[ms]
with notch filter
47
Line current spectra
[dB] 20
0
- 20
without
NOTCH filter
- 40
- 60
0
with
NOTCH filter
- 20
- 40
- 60
0
50
100 150 200 250 300 350 400 450 500
[Hz]
November 1999
48
[V]
[A]
Vo
210
140
2
iL
70
Converter
dynamic
response
without
notch filter
0
November 1999
49
[V]
210
140
[A]
Vo
iL
4
2
70
Converter
dynamic
response
with
notch filter
November 1999
50
[V]
200
Vo
150
100
ig
[A]
t soft-start
Soft-start
procedure
0
-2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

[s]
November 1999
51
References
[1] P. F. Kocybik, K. N. Bateson, "Digital Control of a ZVS Full-Bridge
DC-DC Converter", APEC Conf. Proc., 1995, pp. 687-693.
[2] W. C. So, C. K. Tse, Y. S. Lee, "An Experimental Fuzzy Controller
for DC-DC Converters", PESC Conf. Proc., 1995, pp. 1339-1345.
[3] C. Zhou, M. M. Jovanovic, "Design Trade-Offs in Continuous
Current-Mode Controlled Boost Power-Factor-Correction Circuits",
HFPC Conf. Proc., 1992, pp. 209-220.
[4] R. B. Ridley, "Average Small-Signal Analysis of the Boost PowerFactor-Correction Circuit", VPEC Seminar Proc., 1989, pp. 108-120.
[5] J. B. Williams, "Design of Feedback Loop in Unity Power Factor AC
to DC Converter", PESC Conf. Proc., 1989, pp. 959-967.
[6] G. Spiazzi, P. Mattavelli, L. Rossetto, "Methods to Improve
Dynamic Response of Power Factor Preregulators: an Overview",
European Power Electronics Conf. (EPE), Sevilla (Spain),
September 1995, Vol.3, pp.754-759.
November 1999
52

Digital Control of A Boost PFC With SAB80C166 Microcontroller

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Lesson 6

Digital Control of a Boost PFC

Simone Buso - University of Padova - Lesson 6

Simone Buso - University of Padova - Lesson 6

Simone Buso - University of Padova - Lesson 6

Power Converter Design

Input Voltage ...............

Simone Buso - University of Padova - Lesson 6

Power Converter Design

vin = 2 Vin,RMS sen()

iin = 2 Iin,RMS sen()

Simone Buso - University of Padova - Lesson 6

Power Converter Design

pin () = 2 Vin,RMS Iin,RMS sen () = 2 Po sen ()

The power balance based equations are totally

Simone Buso - University of Padova - Lesson 6

Power Converter Design

Simone Buso - University of Padova - Lesson 6

Power Converter Design

i L ,max = 20% IL,max = 0.54 A

Simone Buso - University of Padova - Lesson 6

Power Converter Design

The integration of the capacitive current

Simone Buso - University of Padova - Lesson 6

Power Converter Design

Simone Buso - University of Padova - Lesson 6

Power Converter Design

Operating frequency > fsw = 20 KHz

Simone Buso - University of Padova - Lesson 6

PFC DIGITAL CONTROLLER

Simone Buso - University of Padova - Lesson 6

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Desired bandwidth: 2 kHz.

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Asymptotic Bode Diagram

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Integral gain is calculated imposing the

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Simone Buso - University of Padova - Lesson 6

Average Current Control Design

Simone Buso - University of Padova - Lesson 6

Input Current Phase Displacement

The line current is

Simone Buso - University of Padova - Lesson 6

Input Current Phase Displacement

Simone Buso - University of Padova - Lesson 6

Input Current Phase Displacement

The closed-loop transfer

Simone Buso - University of Padova - Lesson 6

Input Current Phase Displacement

Current Loop Gain

Simone Buso - University of Padova - Lesson 6

Input Current Phase Displacement

Simone Buso - University of Padova - Lesson 6

Input Current Phase Displacement