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FOR CONVINIRNT STUDY OF MICROPROCESSORS
TWO TYPES OF MODELS ARE USED :
MN/MX
CLK M/IO
8284A
READY
CLOCK INTA
RESET
GENE-
RD
RATOR
WR
8282
DT/R
LATCH
DEN
ALE ADDR
WAIT STATE
GENERATOR AD0-
AD15
A16-A19
8286
TRAN-
ADDR/DATA CEIVER
DATA
CLK
M/IO
ALE
MEMORY ACCESS TIME
ADDR/ RESERVED VALID
A15-A0
DATA FOR DATA D15-D0
ADDR/ A19-A16
STATUS
RD/INTA
READY
DT/R
DEN
WRITE CYCLE
HERE WE WILL SEE THE ACTIVITIES CARRIED OUT
ON 8086 BUS AT VARIOUS TIME INSTANTS WHEN IT
WRITES TO A PORT OR A MEMORY LOCATION.
CLK
M/IO
ALE
ADDR/
A15-A0 DATA OUT (D15-D0)
DATA
ADDR/ A19-A16
STATUS
WR
READY
DT/R
DEN
ADDRESSING
1. ADDRESSING MEMORY
2. ADDRESSING PORTS
A11
D0
D5
D6
D7
Y0 Y1 Y7 A12
74LS138 A13
G2A G2B G1 A14
A15 RD +5V
ADDRESS DECODER WORKSHEET
A15 & A11-A8 A7-A4 A3-A0 HEX EQUI.
A14-A12 ADDRESS
ROM0 ST. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 =0 0 0 0
END 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 =0 F F F
ROM1 ST. 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 =1 0 0 0
END 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 =1 F F F
ROM2 ST. 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 =2 0 0 0
END 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 =2 F F F
ROM3 ST. 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 =3 0 0 0
END 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 =3 F F F
ROM4 ST. 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 =4 0 0 0
END 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 =4 F F F
ROM5 ST. 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 =5 0 0 0
END 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 =5 F F F
ROM6 ST. 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 =6 0 0 0
END 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 =6 F F F
ROM7 ST. 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 =7 0 0 0
END 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 =7 F F F
A SYSTEM RAM DECODER
TO THE SAME SYSTEM WE WANT TO ADD 16KB
RAM.SO ADDITIONAL HARDWARE WE REQUIRE:
A10
D0
D5
D6
D7
Y0 Y1 Y7 A11
74LS138 A12
G2A G2B G1 A13
A12 Y5
G2A
Y6
Y7
A5 A4 A3
8086 PHYSICAL MEMORY
THE TOTAL MEMORY (1MB) OF 8086 IS ARRANGED IN
TWO BANKS. AN ODD BANK AND AN EVEN BANK.
BOTH THE BANKS HAVE EQUAL NO. OF LOCATIONS.
THE ODD BANK CONTAINS ODD NUMBERED MEM.
LOCATIONS.IT IS KNOWN AS UPPER BANK.
THE EVEN BANK CONTAINS ONLY EVEN NUMBERED
MEM. LOCATIONS.IT IS KNOWN AS LOWER BANK.
THIS ARRANGE MENT IS DONE IN ORDER TO SPEED
UP THE OPERATION.
THE ARRANGEMENT AND THE SIGNAL FOLLOWED,
EXPLAINS THE SAME.
THE 8086 MEMORY BANK
UPPER BANK LOWER BANK
ODD EVEN
CS CS
BHE A1---A19 A0
D15-D8 D7-D0
ADDRESSING WITH 8086
P
A15 G2A G2B O
A5 G R
T
Y0 8255-1
S
Y1 8255-2
E
A4 Y2 8251
L
Y3 8279
74LS138 E
Y4 8275
8272 C
Y5
A3 T
Y6
Y7 RESERVED
A2 FOR FUTURE
USE.
MAP FOR PORTS
A15-A5 A4 A3 A2 A1 A0 EQUI HEX
ADDRESS
8255-1 1 0 0 0 =F F E O
=F F E 3
8255-2 1 0 0 1 =F F E 4
=F F E 7
8251 1 0 1 0 =F F E 8
=F F E B
8279 1 0 1 1 =F F E C
=F F E F
8275 1 1 0 0 =F F F 0
=F F F 3
8272 1 1 0 1 =F F F 4
=F F F 7
LINES A1 AND A0 ARE USED FOR SETTING INTERNAL
REGISTERS OF THE ADDRESSED PORT.
NOTE THAT THIS IS AN ABSOLUTE ADDRESSING.i.e.
A PORT CAN BE SELECTED FOR ONLY ONE ADDRESS.
NON-ABSOLUTE ADDRESING ALSO EXISTS.THERE A
PORT CAN BE SELECTED FOR MORE THAN ONE
ADDRESSES.
THE OFF-BOARD DECODER
THE SDK-86 USES AN OFF-BOARD CIRCUITRY .
THE PURPOSE OF THIS CIRCUITRY IS TO PRODUCE AN
ACTIVE LOW OFF BOARD SIGNAL WHENEVER THE 8086
ADDRESSES A PORT OR MEMORY WHICH IS NOT
DECODED ON THE SDK-86 BOARD.
USUALLY WHEN WE CONNECT ADDITIONAL PORT
USING DIRECT I/O, THIS DEVICE IS CONSIDERED AS
OFF-BOARD(OUT OF THE DECODING MAP OF THE
SYSTEM).
SO WHENEVER THIS PORT IS CALLED UPON,THE 8086
ASSERTS THE OFF BOARD SINAL.
TO COMMUNICATE WITH OFF BOARD DEVICES,EXTRA
HARDWARE SUCH AS 74LS138 OR AN EPROM DECODER
IS REQUIRED FOR ADDRESSING THIS DEVICE.
8088 MEMORY AND PORT
ADDRESSING
IN 8088 THERE ARE ONLY 8 DATA LINES AND 20
ADD.LINES.
THE 8088 MEMORY IS NOT DEVIDED INTO ODD
AND EVEN BANKS.BUT THERE IS ONLY A SINGLE
BANK.
THERE ARE 1MB LOCATIONS EACH 1-BYTE
LONG.SO TO READ OR WRITE A WORD 8088
REQUIRES TWO MACHINE CYCLES ALWAYS.
THE 8086 TIMING PARAMETERS