You are on page 1of 2

ABHISHEK VASHIST

537 Falcon Place, San Jose, CA, 95125 (408)859-1357 av8911@rit.edu


www.vashist01.com
OBJECTIVE
Seeking internship/co-op position in the field of ASIC Design & Verification. Available Summer/Fall 2016
EDUCATIONAL QUALIFICATION
ROCHESTER INSTITUTE OF TECHNOLOGY, Rochester, NY
Master of Science, Electrical Engineering
GPA: 3.29/4.0
ABES ENGINEERING COLLEGE, Ghaziabad, UP, INDIA
Bachelor of Technology, Electronics and Communication Engineering

December 2016 (Expected)

May 2014

TECHNICAL SKILLS
Full Custom Layout, RTL Design & Verification, Logic Synthesis, place & route and Static Timing Analysis
Hardware Description Language: VHDL, Verilog
C programming language, perl scripting, MATLAB and experience with UNIX, LINUX & Windows OS
Software Packages: Synopsys IC Compiler, Design Compiler and PrimeTime, Cadence Virtuoso, NCVerilog
and NCSim, Altera Quartus II, ModelSim 10.1d
Experience with FPGA/CPLD device programming, PCB design and experience with Git
PROJECTS
Design and implementation of Band-Gap Voltage Reference circuit
Designed and verified a Band-Gap reference circuit which produces an output that is stable with variation in
supply voltage, temperature and process variation. EDA tool cadence virtuoso was used for circuit simulation
Design & implementation of simple-complexity sequential logic circuit comprised of data path and a
control-unit
Designed and verified both non-pipelined and pipelined version of a 4-Bit Sequential Multiplier based on
computer design methodology using Verilog HDL. The final designs were emulated in an FPGA (Cyclone-IV
E) on the Altera DE0 Nano board.
Design & implementation of a complex digital system at RTL level and netlist level
Designed a Multi-channel ADPCM codec based on ITU standards G.726 & G.711 using Verilog HDL. All
modules were designed & synthesized at RTL and gate level. Sign-off included Static Timing closure, RTL,
and ATPG coverage metrics. Including test structures, the final netlist was approximately 3.2M gates.
Design of Micro-strip Components
Designed and verified functionality of various micro-strip components at 10GHz frequency. Functionality was
verified through simulation using HFSS.
Memory Access Bus Arbiter (ARB) for DTMF receiver using Verilog HDL
Designed a Memory Access Bus Arbiter (ARB) built for the Dual Tone Multi Frequency (DTMF) Receiver
using Verilog. Test-bench verification was done through simulation and performed logic synthesis, test
insertion and detailed timing analysis
Development of a CMOS standard cell library using the Cadence Design Framework
1) Using AMI (0.5m) Technology designed and verified variety of standard cells at transistor level with
custom layout and characterization of each library gate, including both DRC and LVS check
2) These standard cells were used in hierarchical development, place and route, and characterization of full
adder with boundary scan cells attached for in circuit test
EXPERIENCE
Summer Intern @ Electronics Regional Test Laboratory (North), Delhi
Summer 2013
Validated electromagnetic compatibility of electronic devices using various tests like conducted emission, radiated
emission/immunity and surge

EXTRACURRICULARS
RIT Space Exploration Group (RIT SPEX) took part in its crowdfunding campaign and a cricket enthusiast