DEPpart 3

©
R.Lauwereins
Imec 2001
Course contents
Digital
• Digital design
design
• Combinatorial circuits: without status
Combina-
torial
 Sequential circuits: with status
circuits
• FSMD design: hardwired processors
Sequential
circuits • Language based HW design: VHDL
FSMD
design
VHDL
3/1
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
• The flip-flop as building block
design
• Design of synchronous sequential
Combina-
torial
circuits
circuits
• Design of asynchronous sequential
Sequential circuits
circuits
• Basic RTL building blocks
FSMD
design
VHDL
3/2
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
 The flip-flop as building block
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
VHDL
3/3
©
R.Lauwereins
Imec 2001
The flip-flop as building block
Digital
• Definitions:
design
 Combinatorial circuit: the output is function of
Combina-
the current value of the inputs
torial
circuits
 Sequential circuit: the output is function of the
current value of the inputs and of the current
Sequential state (i.e. also function of the sequence of past
circuits
inputs)
FSMD
design
VHDL
3/4
©
R.Lauwereins
Imec 2001
The flip-flop as building block
Digital
• Definitions
design
 Asynchronous sequential circuits: outputs and
Combina-
state change as soon as an input changes
torial
circuits
 Synchronous sequential circuits: outputs and
state change only when a special input, the
Sequential clock, gets a certain value
circuits
 Clock period: duration between two
FSMD consecutive 10 transitions of the clock
design
 Clock frequency: 1 / (clock period)
VHDL  Duty cycle: (duration that the clock equals 1) /
(clock period)
 Rising edge: 01 transition of the clock
 Falling edge: 10 transition of the clock
3/5
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
Combina-  Gated SR Latch
torial
circuits  Gated D Latch
 Flip-flop sensitivity
Sequential
circuits  Flip-flop types
FSMD • Design of synchronous sequential
design
circuits
VHDL • Design of asynchronous sequential
circuits
3/6
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
torial
Sequential
design
circuits
circuits
3/7
©
R.Lauwereins
Imec 2001
SR Latch
Digital S R Q(next)
design
Set Q’ 0 0 Q
Combina- 0 1 0
torial 1 0 1
circuits
1 1 NA
Sequential Reset Q
circuits
FSMD
design
S
VHDL
Q’
Undefined
3/8
©
R.Lauwereins
Imec 2001
SR Latch
Digital
• Note that a Boolean signal now already
design
consists of 5 values:
Combina-  0: the logical signal “0”
torial
circuits  1: the logical signal “1”
 x: don’t care
Sequential
circuits  Z: high impedant
FSMD
 U: undefined
design
• The oscillation is called critical race
VHDL • The oscillation only happens when the
delay of both gates is exactly equal
• When the delays are not equal, the fastest
gates determines the end result:
implementation and run-time dependent 
undefined
3/9
©
R.Lauwereins
Imec 2001
SR Latch
Digital S R Q(next)
design
Set Q 1 1 Q
Combina- 1 0 0
torial 0 1 1
circuits
0 0 NA
Sequential Reset Q’
circuits Set and Reset active low
FSMD
design
S
VHDL
Q’
3/10
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
Combina-  Gated SR Latch
torial
Sequential
design
circuits
circuits
3/11
©
R.Lauwereins
Imec 2001
Gated SR Latch
Digital
design Set C=1: follow inputs
Combina-
Q’ C=0: latch outputs
torial
circuits Clock
Sequential
circuits Q
Reset
FSMD
design
C S R Q(next)
0 0 0 Q
VHDL
0 0 1 Q
0 1 0 Q
0 1 1 Q
1 0 0 Q
1 0 1 0
1 1 0 1
1 1 1 NA
3/12
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
torial
circuits  Gated D Latch
Sequential
design
circuits
circuits
3/13
©
R.Lauwereins
Imec 2001
Gated D Latch
D C=1: follow input
Digital C=0: latch output
design Q’
C D Q(next)
Combina-
Clock 0 0 Q
torial 0 1 Q
circuits
Q 1 0 0
Sequential 1 1 1
circuits
DQ delay when C high: L-to-H delay: 2.4+1.4+1.4=5.2

FSMD
design H-to-L delay: 1+2.4+1.4=4.8
CQ delay when D high: L-to-H delay: 2.4+1.4+1.4=5.2
VHDL when D low: H-to-L delay: 2.4+1.4=3.8
3/14
©
R.Lauwereins
Imec 2001
Gated D Latch
D C=1: follow input
S
design Q’
C D Q(next)
Combina-
Clock 0 0 Q
torial 0 1 Q
circuits
R Q 1 0 0
Sequential 1 1 1
circuits
D must not change “immediately before” H-to-L of the
clock (during the setup time); reason: clock changes
FSMD
design between the switching of D and of D’ hence Set and
Reset switch from H to L at the same time  undefined
VHDL (setup time = H-to-L of invertor)
D
C
S
D’
R
3/15
©
R.Lauwereins
Imec 2001
Gated D Latch
D C=1: follow input
S
design Q’
C D Q(next)
Combina-
Clock 0 0 Q
torial 0 1 Q
circuits
R Q 1 0 0
Sequential 1 1 1
circuits
When D switches at least setup time before the clock
FSMD transition, S and R will not switch from H to L at the
design
same time  OK (S is longer high than R, hence Q will
come high following the D input)
VHDL
D
C
S
D’
R
3/16
©
R.Lauwereins
Imec 2001
Gated D Latch
D C=1: follow input
S
design Q’
C D Q(next)
Combina-
Clock 0 0 Q
torial 0 1 Q
circuits
R Q 1 0 0
Sequential 1 1 1
circuits
FSMD Analogously, D may not switch “immediately after” H-to-L

design
of the clock (during the hold time)
VHDL
Symbol
Given values:
D Q 5.2=C to QLH
5.2/3.8 3.8=C to QHL
C Q’
3/17
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
torial
Sequential
circuits
Level-sensitive latch
FSMD Master-slave flip-flop
design
Edge-triggered flip-flop
VHDL
 Flip-flop types
circuits
circuits
3/18
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
torial
Sequential
circuits
Level-sensitive latch
design
VHDL
 Flip-flop types
circuits
circuits
3/19
©
R.Lauwereins
Imec 2001
Level sensitive latch
Digital
• All previous gated latches are level
design
sensitive
Combina-  Transparent when clock is high
torial
circuits  Remembering the last value when clock is low
Sequential
• Level sensitive latches give problems for
circuits
shift registers for example
FSMD  The input signal may ripple through multiple
design
stages during one clock-high phase
VHDL  making it very hard to meet setup/hold time
requirements
 See next slide
3/20
©
R.Lauwereins
Imec 2001
Level sensitive latch
X Y
Digital
design
D Q1 D Q2 D Q3
4/3 4/3 4/3
Combina- C C C
torial
circuits Clk
Sequential
circuits
Clk
FSMD
design
X
VHDL Q1
Q2
Q3
Two solutions:
• Master-slave
• Edge-triggered
3/21
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
torial
Sequential
circuits
FSMD Master-slave flip-flop
design
VHDL
 Flip-flop types
circuits
circuits
3/22
©
R.Lauwereins
Imec 2001
Master-slave flip-flop
X Master Slave Q1 Master Slave Y
Digital D Qm1 D Qs1 D Qm2 D Qs2
design
4/3 4/3 4/3 4/3
Combina-
C C C C
torial Clk
circuits
Sequential
circuits
Clk
FSMD
design
X
VHDL Qm1
Q1
Qm2
The master clocks at the falling clock edge

The slave clocks at the rising edge
3/23
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 SR Latch
torial
Sequential
circuits
design
Edge-triggered flip-flop
VHDL
 Flip-flop types
circuits
circuits
3/24
©
R.Lauwereins
Imec 2001
Edge-triggered flip-flop
A Set Latch Output
Digital Latch
design Set
Q
Combina-
torial Clk
circuits
Reset Q’
Sequential
circuits
B
D Reset Latch
FSMD
design
VHDL Clk
D
B
A
R
S
3/25
Q
©
Sequential Circuits
R.Lauwereins
Imec 2001

Digital  SR Latch
design
 Gated SR Latch
Combina-  Gated D Latch
torial
circuits  Flip-flop sensitivity
 Flip-flop types
Sequential
circuits
SR flip-flop
FSMD JK flip-flop
design
D flip-flop
VHDL
T flip-flop
Asynchronous set and reset
• Design of synchronous sequential circuits
• Design of asynchronous sequential circuits
3/26
©
Sequential Circuits
R.Lauwereins
Imec 2001

Digital  SR Latch
design
 Gated SR Latch
Combina-  Gated D Latch
torial
circuits  Flip-flop sensitivity
 Flip-flop types
Sequential
circuits
SR flip-flop
FSMD JK flip-flop
design
D flip-flop
VHDL
T flip-flop
3/27
©
R.Lauwereins
Imec 2001
SR flip-flop
Digital Symbol Characteristic table

design
(for design of SR flip-flop)
S Q
Combina- S R Q(next)
torial
circuits Clk 0 0 Q
R Q’ 0 1 0
Sequential 1 0 1
circuits
Triangle next to clock 1 1 NA
FSMD means positive
design edge-triggered
Negative edge-triggered
VHDL
Excitation table
Positive level triggered (for design with SR flip-flop)
Negative level triggered Q Q(next) S R

0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
3/28
©
Sequential Circuits
R.Lauwereins
Imec 2001

Digital
design
 SR Latch
 Gated SR Latch
Combina-
torial  Gated D Latch
circuits
Sequential  Flip-flop types
circuits
SR flip-flop
FSMD
design
JK flip-flop
D flip-flop
VHDL
T flip-flop
3/29
©
R.Lauwereins
Imec 2001
JK flip-flop

design
(for design of JK flip-flop)
J Q
Combina- J K Q(next)
torial
circuits Clk 0 0 Q
K Q’ 0 1 0
Sequential 1 0 1
circuits
1 1 Q’
FSMD
design
VHDL
Excitation table
(for design with JK flip-flop)
Q Q(next) J K
Circuits that use 0 0 0 x
JK flip-flops are cheaper 0 1 1 x
than those using SR flip-flops: 1 0 x 1
more don’t cares 1 1 x 0
3/30
©
Sequential Circuits
R.Lauwereins
Imec 2001

Digital
design
 SR Latch
 Gated SR Latch
Combina-
circuits
circuits
SR flip-flop
FSMD
design
JK flip-flop
D flip-flop
VHDL
T flip-flop
3/31
©
R.Lauwereins
Imec 2001
D flip-flop

design
(for design of D flip-flop)
Combina-
D Q
torial D Q(next)
circuits Clk
0 0
Q’
Sequential
1 1
circuits
FSMD
design
VHDL
Excitation table
(for design with D flip-flop)
Q Q(next) D
Designing with D flip-flop 0 0 0
is easy 0 1 1
1 0 0
1 1 1
3/32
©
Sequential Circuits
R.Lauwereins
Imec 2001

Digital
design
 SR Latch
 Gated SR Latch
Combina-
circuits
circuits
SR flip-flop
FSMD
design
JK flip-flop
D flip-flop
VHDL
T flip-flop
3/33
©
R.Lauwereins
Imec 2001
T flip-flop

design
(for design of T flip-flop)
Combina-
T Q
torial T Q(next)
circuits Clk
0 Q
Q’
Sequential
1 Q’
circuits
FSMD
design
VHDL
Excitation table
(for design with T flip-flop)
T D Q Q Q(next) T
0 0 0
Clk
0 1 1
Q’
1 0 1
1 1 0
3/34
©
Sequential Circuits
R.Lauwereins
Imec 2001

Digital
design
 SR Latch
 Gated SR Latch
Combina-
circuits
circuits
SR flip-flop
FSMD
design
JK flip-flop
D flip-flop
VHDL
T flip-flop
Asynchronous set and reset
3/35
©
R.Lauwereins
Imec 2001
Asynchronous set and reset
Preset
Digital
design A
Combina-
torial Set
circuits Q
Clk
Sequential
circuits Reset
Q’
FSMD
design B
D
VHDL
Clear
PRS
D Q
Asynchronous set and reset are
useful to put the flip-flop Clk Q’
initially in a known state
CLR
(see lab sessions)
3/36
©
R.Lauwereins
Imec 2001
Digital
• Why are the asynchronous preset and
design
clear connected to both layers of SR-flip-
Combina- flops?
torial
circuits  The first layer passes input modifications to
the second layer only at the rising clock edge
Sequential
circuits  The second layer reacts immediately, without
waiting for the rising clock edge => needed for
FSMD
design
asynchronous reaction
 If they were only connected to the second
VHDL layer, the first layer would not know in what
state the second layer was put and could give a
conflicting command to the second layer at the
next rising clock edge, e.g. reset since D=0 and
at the same time an asynchronous preset
3/37
©
R.Lauwereins
Imec 2001
Digital
• Why are the asynchronous preset and
design
clear active low?
Combina-  Because ‘wired-or’ of ‘open drain’ circuits is
torial
circuits
used to avoid short circuits when there are
multiple sources driving them:
Sequential
circuits R
FSMD
Open
design No No drain
preset preset
VHDL Implements an AND
function (hence
‘wired-or’ ...) with
unlimited number of
inputs:
preset preset The bus is only ‘1’
when all inputs to
the bus are equal to
3/38
‘1’
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
 Design of synchronous sequential
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
VHDL
3/39
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
circuits  Finite State Machine (FSM)
Sequential
 State-based or Moore-type FSM
circuits  Input-based or Mealy-type FSM
FSMD
 Step 1: State diagram
design
 Step 2: State minimization
VHDL  Step 3: State encoding
 Step 4: Choice of the flip-flop type
 Step 5: Realization of the combinatorial logic
 Step 6: Timing analysis
circuits
3/40
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
circuits  Finite State Machine (FSM)
Sequential
FSMD
design
circuits
3/41
©
R.Lauwereins
Imec 2001
Finite State Machine
Digital
• Design a modulo 4 “Counter”, that counts when
design the input “CE” (Count Enable) equals 1 and stops
counting when the input “CE” equals 0.
Combina-
torial • Step 1: translate to a Finite State Machine
circuits
(FSM):
Sequential
circuits
CE=0 CE=0
FSMD
design CE=1
Count=0 Count=1
VHDL
CE=1 CE=1
CE=0 Count=3 Count=2 CE=0
CE=1
3/42
©
R.Lauwereins Finite State Machine
Transition to the next state happens at each rising clock
Imec 2001
edge (a synchronous FSM is clocked!).
At each rising clock edge, exactly one transition condition
should be true: for each input combination, a transition
Digital
design should be specified in each of the states.
CE=0 CE=0
Combina-
torial CE=1
circuits Count=0 Count=1
Sequential
circuits
CE=1 CE=1
FSMD
design
VHDL
CE=1
1. We are in state “Count=0”

2. CE input equals 0: we are waiting at the tip of the edge
3. CE=1: wait at tip of other edge, but do not count yet!
4. Rising clock edge: go to “Count=1”, still with CE=1
5. CE input becomes 0: wait at tip of other edge
3/43 6. Rising clock edge: go to “Count=1”, with CE=0
©
R.Lauwereins
Imec 2001
Digital
• Step 2: Minimise the number of states.
design
It is already the minimum number.
Combina- • Step 3: Encode the states:
torial
circuits
Sequential
circuits
CE=0 CE=0
FSMD
CE=1
design Q1Q0=00 Q1Q0=01
VHDL
CE=1 CE=1
CE=0 Q1Q0=11 Q1Q0=10 CE=0
CE=1
3/44
©
R.Lauwereins
Imec 2001
Digital
• Step 4: Select the flip-flop type. We select
design
the D type for its simplicity.
Combina-
torial
• Step 5: Realise the circuit. See next
circuits slides:
Sequential
circuits
FSMD
design
VHDL
3/45
©
R.Lauwereins
Imec 2001
Digital
• Translate the FSM in a next-state table:
design
CE=0 CE=0
Combina-
torial CE=1
circuits
Q1Q0=00 Q1Q0=01
Sequential
circuits CE=1 CE=1
FSMD
design CE=0 Q1Q0=11 Q1Q0=10 CE=0
CE=1
VHDL
Present state Next state

Q1Q0 Q1nQ0n
CE=0 CE=1
00 00 01
01 01 10
10 10 11
3/46 11 11 00
©
R.Lauwereins
Imec 2001
Digital
• Determine the excitation functions:
design
Present state Next state
Combina- Q1Q0 Q1nQ0n
torial
circuits CE=0 CE=1
00 00 01
Sequential
circuits 01 01 10
10 10 11
FSMD
design 11 11 00
Excitation table
VHDL
for D flip-flop Q0 Q0
Q Q(next) D Q1n=D1 Q1 Q0n=D0 Q1
0 0 0
0 1 1 0 0 1 1 0 1 1 0
1 0 0 CE 0 1 0 1 CE 1 0 0 1
1 1 1
 D to be applied
3/47 is identical to Qn
©
R.Lauwereins
Imec 2001
Digital
• Implement:
design
Q0 Q0
Combina-
torial
Q1n=D1 Q1 Q0n=D0 Q1
circuits
0 0 1 1 0 1 1 0
Sequential
circuits CE 0 1 0 1 CE 1 0 0 1
FSMD CE Q1 Q0
design
Q1
VHDL Q1n
D1
Q’
Q0
Q0n
D0
Q’
3/48
©
R.Lauwereins
Imec 2001
Digital
• Step 6: Timing analysis
design CE Q1 Q0
Combina-
Q1
torial Q1n
circuits D1
Q’
Sequential
circuits
Q0
Q0n
FSMD D0
design
Q’
VHDL
Clk
CE
Q1
Q0
3/49
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
 State-based or Moore-type FSM
FSMD
design
circuits
3/50
©
R.Lauwereins
Imec 2001
State-based or Moore-type FSM
Digital
• Design a modulo 4 “Counter”, that counts
design
when the “CE” input equals 1 and stops
Combina-
counting when “CE” equals 0. The output
torial
circuits
“Y” equals 1 when the count value equals 3.
• Step 1: translate to FSM:
Sequential
circuits
CE=0 CE=0
FSMD
design
Count=0 CE=1 Count=1
VHDL Y=0 Y=0
CE=1 CE=1

Y=1 Y=0
CE=1
3/51
©
R.Lauwereins
Imec 2001
Digital • Be extremely careful about timing issues!!

design
Assume that the Y output is used as a load-enable
Combina- for a register and as the add/subtract line for an
torial
circuits adder/subtractor: when arriving in state 3, Y
becomes 1, immediately causing the
Sequential
circuits adder/subtractor to switch to “subtract” mode, but
FSMD
NOT causing the register to load a new value!!!
design The loading will only occur at the next state
VHDL
transition (i.e. the next clock edge)
LE Clocked
Register Clk
CE
Counter
Add/Subtract Combinatorial
3/52 A/S’
©
R.Lauwereins
Imec 2001
Digital
• State-based:
design
 the output is indicated for each state
Combina-  the output is only function of the current state,
torial
circuits
not of the inputs applied
 Hence, the output value is indicated in the
Sequential
circuits
circle representing the state
FSMD
design
VHDL
3/53
©
R.Lauwereins
Imec 2001
Digital
• Step 2: Minimise the number of states. This
design
is already the minimum number.
torial
circuits
Sequential
circuits
CE=0 CE=0
FSMD
design Q1Q0=00 CE=1 Q1Q0=01
Y=0 Y=0
VHDL
CE=1 CE=1
CE=0 Q1Q0=11 Q1Q0=10 CE=0

Y=1 Y=0
CE=1
3/54
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits slides:
Sequential
circuits
FSMD
design
VHDL
3/55
©
R.Lauwereins
Imec 2001
Digital
• Translate the FSM in a next-state table:
design
CE=0 CE=0
Combina-
torial Q1Q0=00 CE=1 Q1Q0=01
circuits Y=0 Y=0
Sequential
circuits CE=1 CE=1
FSMD
CE=0 Q1Q0=11 Q1Q0=10 CE=0
design
Y=1 Y=0
CE=1
VHDL
Present state Next state Outputs Y is

Q1Q0 Q1nQ0n Y only
CE=0 CE=1 dependent
on the
00 00 01 0
current
01 01 10 0 state,
10 10 11 0 not on
3/56 11 11 00 1 the inputs
©
R.Lauwereins
Imec 2001
Digital
design
Present state Next state Outputs
Combina- Q1Q0 Q1nQ0n Y
torial
circuits
CE=0 CE=1
00 00 01 0
Sequential
circuits
01 01 10 0
10 10 11 0
FSMD 11 11 00 1
design
Q0 Q0
Excitation table
VHDL
for D flip-flop Q1n=D1 Q1 Q0n=D0 Q1
Q Q(next) D
0 0 1 1 0 1 1 0
0 0 0
0 1 1 CE 0 1 0 1 CE 1 0 0 1
1 0 0
Q0
1 1 1 Y
 D to be applied 0 0
3/57 is identical to Qn Q1 0 1
©
R.Lauwereins
Imec 2001
Digital
• Implement:
design
Q0 Q0
Combina-
torial
Q1n=D1 Q1 Q0n=D0 Q1 Q0
circuits Y
0 0 1 1 0 1 1 0 0 0
Sequential
circuits CE 0 1 0 1 CE 1 0 0 1 Q1 0 1
FSMD CE Q1 Q0
design
Q1 Y
VHDL Q1n
D1
Q’
Q0
Q0n
D0
Q’
3/58
©
R.Lauwereins
Imec 2001
Digital
design CE Q1 Q0
Combina-
Q1 Y
torial Q1n
circuits D1
Q’
Sequential
circuits
Q0
Q0n
FSMD D0
design
Q’
VHDL
Clk
CE
Q1
Danger for
Q0 Glitch!
3/59 Y
©
R.Lauwereins
Imec 2001
Digital
• Is a glitch harmful?
design
 When the output with the glitch is connected to
Combina-
the clock of some clocked circuit:
torial
circuits This clocked circuit will
unintentionally clock: harmful
Sequential
circuits
Hard to debug: glitch may disappear
FSMD when probe is connected due to
design
increased capacitance and hence
VHDL also increased delay
 When the output with the glitch is connected to
a combinatorial circuit that eventually is the
input of a register:
Not harmful, since the register looks
at its input only at the clock edge
Dissipates unnecessary power
3/60
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
circuits  Input-based or Mealy-type FSM
FSMD
design
circuits
3/61
©
R.Lauwereins
Imec 2001
Input-based or Mealy-type FSM
Digital
• Design a modulo 4 “Counter”, that counts when
design the “CE” input equals 1 and stops counting when
“CE” equals 0. The “Y” output value equals 1
Combina-
torial when the count=3 while the input “CE” equals 1.
circuits
• Step 1: translate to FSM:
Sequential
circuits
CE=0/Y=0 CE=0/Y=0
FSMD
design
CE=1/Y=0
Count=0 Count=1
VHDL
CE=1/Y=1 CE=1/Y=0
CE=0/Y=0 Count=3 Count=2 CE=0/Y=0

CE=1/Y=0
3/62
©
R.Lauwereins
Imec 2001
Transition to the next state happens
Digital at each rising clock edge
design
CE=0/Y=0 CE=0/Y=0
Combina-
torial CE=1/Y=0
circuits Count=0 Count=1
Sequential
circuits
CE=1/Y=1 CE=1/Y=0
FSMD
design
CE=0/Y=0 Count=3 Count=2 CE=0/Y=0
VHDL
CE=1/Y=0
1. We are in state “Count=2”

2. CE input equals 1: wait at tip of edge with Y=0
3. Rising clock edge: go to “Count=3”, still with CE=1: Y=1
4. C input becomes 0: wait at tip of other edge with Y=0;
combinatorial circuit driven by Y reacts, clocked don’t
3/63 5. Rising clock edge: Y=0 is clocked into output register
©
R.Lauwereins
Imec 2001
Digital • Be extremely careful about timing issues!! Assume

design
that the Y output is used as a load-enable for a
Combina- register and as the add/subtract line for an
torial
circuits adder/subtractor: when arriving in state 3 with
CE=1, Y becomes 1  adder/subtractor switches to
Sequential
circuits “subtract”, but register doesn’t load new value!!!
When CE=0, Y becomes 0  adder/subtractor
FSMD
design switches to “add”, and LE=0. When the next clock
VHDL
edge comes while CE=0, register will not load.
LE Clocked
Register Clk
CE
Counter
Add/Subtract Combinatorial
3/64 A/S’
©
R.Lauwereins
Imec 2001
Digital
• Input-based:
design
 the output is specified for each state and each
Combina-
combination of inputs in that state
torial
circuits
 the output is function of the current state, and
of the applied inputs
Sequential
circuits
 Hence the output is specified next to each
transition
FSMD
design
VHDL
3/65
©
R.Lauwereins
Imec 2001
Digital
• Step 2: Minimise the number of states. This
design
is already the minimum number.
torial
circuits
Sequential
circuits
CE=0/Y=0 CE=0/Y=0
FSMD
CE=1/Y=0
design Q1Q0=00 Q1Q0=01
VHDL
CE=1/Y=1 CE=1/Y=0
CE=0/Y=0 Q1Q0=11 Q1Q0=10 CE=0/Y=0

CE=1/Y=0
3/66
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
circuits slides:
Sequential
circuits
FSMD
design
VHDL
3/67
©
R.Lauwereins
Imec 2001
Digital
• Translate FSM to next-state table:
design
CE=0/Y=0 CE=0/Y=0
Combina-
torial CE=1/Y=0
circuits
Q1Q0=00 Q1Q0=01
Sequential
circuits CE=1/Y=1 CE=1/Y=0
FSMD
design CE=0/Y=0 Q1Q0=11 Q1Q0=10 CE=0/Y=0
CE=1/Y=0
VHDL
Present state Next state/Outputs Y does

Q1Q0 Q1nQ0n/Y not only
CE=0 CE=1 depend
on the
00 00/0 01/0
current
01 01/0 10/0 state,
10 10/0 11/0 but also on
3/68 11 11/0 00/1 the inputs
©
R.Lauwereins
Imec 2001
Digital
design
Present state Next state/Outputs
Combina- Q1Q0 Q1nQ0n/Y
torial
circuits
CE=0 CE=1
00 00/0 01/0
Sequential
circuits
01 01/0 10/0
10 10/0 11/0
FSMD 11 11/0 00/1
design Q0 Q0
Excitation table Q1n=D1 Q1 Q0n=D0 Q1
VHDL
for D flip-flop
Q Q(next) D 0 0 1 1 0 1 1 0
0 0 0 CE 0 1 0 1 CE 1 0 0 1
0 1 1 Q0
1 0 0 Y Q1
1 1 1
0 0 0 0
 D to be applied
3/69 is identical to Qn CE 0 0 1 0
©
R.Lauwereins
Imec 2001
Digital
• Implement:
design
Q0 Q0 Q0
Combina-
torial
Q1n=D1 Q1 Q0n=D0 Q1 Y Q1
circuits
0 0 1 1 0 1 1 0 0 0 0 0
Sequential
circuits CE 0 1 0 1 CE 1 0 0 1 CE 0 0 1 0
FSMD CE Q1 Q0
design
Q1 Y
VHDL Q1n
D1
Q’
Q0
Q0n
D0
Q’
3/70
©
R.Lauwereins
Imec 2001
Digital
design CE Q1 Q0
Combina- Q1 Y
torial Q1n
circuits D1
Q’
Sequential
circuits
Q0
Q0n
FSMD D0
design
Q’
VHDL
Clk
CE
Q1
Danger for
Q0 Glitch!
3/71 Y
©
State-based model
R.Lauwereins
Imec 2001
Next Current
Inputs I Clock
State S* State S
Digital
design
D Q
Combina-
torial Clk
circuits
Outputs
O
Sequential S*=F(S,I)
circuits
D Q O=H(S)
Next Clk
FSMD Output
design State
Combi-
Combi-
nato-
VHDL nato-
rial
rial
Logic
Logic
D Q
Clk
3/72
©
Input-based model
R.Lauwereins
Imec 2001
Clock Next State S* Current

Inputs I State S
Digital
design
D Q
Combina-
torial Clk
circuits
Outputs
O
Sequential S*=F(S,I)
circuits
D Q O=H(S,I)
Next Clk
FSMD Output
design State
Combi-
Combi-
nato-
VHDL nato-
rial
rial
Logic
Logic
D Q
Clk
3/73
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
FSMD
 Step 1: State diagram
design
circuits
3/74
©
R.Lauwereins
Imec 2001
Step 1: construction of the FSM
• The first step in the design of synchronous sequential
Digital circuits is the construction of the FSM starting from the
design
description in natural language (ambiguous and
incomplete)
Combina-
torial • Example: Modulo-3 up/down counter
circuits  Count enable (C):
Sequential
C=1: count
circuits
C=0: do not count
 Direction (D):
FSMD
design D=1: count down
VHDL
D=0: count up
 Output (Y): Y=1 when (count equals 2 and we count
up) or when (count equals 0 and we count down)
 What is the meaning of “We count up”?
Do we have to “count” (C=1) and “up” (D=0)
or is it sufficient that the direction is “up”
(C=X and D=0)?
Ambiguous; I choose for the first
3/75
©
R.Lauwereins
Imec 2001
Digital
• First step: is this a State-based or an
design
Input-based design?
Combina-  It is Input-based, since the output depends on
torial
circuits
the state and the input
• Second step: construct the FSM starting
Sequential
circuits from the first state, for each combination
FSMD
of inputs from each state
design  See next slide
VHDL  Note: when an output needs to remain high
during several consecutive states, it should be
assigned a ‘high’ value in each of these states!!
Each output should be assigned a value in each
state!
3/76
©
R.Lauwereins
Imec 2001
CD=10
Y=1
Digital
design
CD=0X CD=0X CD=0X
Y=0 Y=0 Y=0
Combina-
torial CD=10 CD=10
circuits Y=0 Y=0
u0 u1 u2
Sequential CD=10
circuits CD=10 Y=0 CD=11
Y=1 Y=0
FSMD
design
CD=10 CD=11
Y=0 Y=1
VHDL CD=11
Y=0
d0 d1 d2
CD=11 CD=11
Y=0 Y=0
CD=0X CD=0X CD=0X
Y=0 Y=0 Y=0
CD=11
Y=1
3/77
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
FSMD
design
 Step 2: State minimization
circuits
3/78
Step 2: minimise the number of
©
R.Lauwereins
Imec 2001
states
Digital
• Goal: less states means less flip-flops
design
• Principal: equivalent behavior of two
Combina-
torial
FSMs
circuits
• Two FSMs are equivalent when they
Sequential produce the same output sequence for
the same input sequence
circuits
FSMD
design
VHDL
3/79
©
R.Lauwereins
Imec 2001
states
Digital
• Two states in an FSM may be replaced by
design
1 state when both states produce the
Combina- same outputs for the same inputs and
torial
circuits when both jump to equivalent next states
for the same inputs
Sequential
circuits
• Formally: states sj and sk are equivalent
FSMD (sjsk) if and only if
design
 iI: h(sj,i)=h(sk,i): both states produce the
VHDL same output for each combination of inputs
and
 iI: f(sj,i)f(sk,i): the next states are equivalent
for each input combination
3/80
©
R.Lauwereins
Imec 2001
states
Digital
• In practice: build the next state table out
design
of the state diagram first
Combina- PRESENT NEXT STATE / OUTPUT
torial
circuits
STATE CD=0X CD=10 CD=11
u0 u0/0 u1/0 d2/1
Sequential u1 u1/0 u2/0 d0/0
circuits
u2 u2/0 u0/1 d1/0
FSMD d0 d0/0 u1/0 d2/1
design
d1 d1/0 u2/0 d0/0
d2 d2/0 u0/1 d1/0
VHDL
3/81
©
R.Lauwereins
Imec 2001
states
Digital
• Construct the implication table: 1 square
design
per combination of 2 states
torial
circuits
u0 u0/0 u1/0 d2/1
circuits
u2 u2/0 u0/1 d1/0
FSMD d0 d0/0 u1/0 d2/1
design
d1 d1/0 u2/0 d0/0
u1 d2 d2/0 u0/1 d1/0
VHDL
u2
d0
d1
d2
u0 u1 u2 d0 d1
3/82
©
R.Lauwereins
Imec 2001
states
Digital
• Delete all combinations that have
design
different outputs for the same inputs
torial
circuits
u0 u0/0 u1/0 d2/1
circuits
u2 u2/0 u0/1 d1/0
FSMD d0 d0/0 u1/0 d2/1
design
d1 d1/0 u2/0 d0/0
u1 d2 d2/0 u0/1 d1/0
VHDL
u2
d0
d1
d2
u0 u1 u2 d0 d1
3/83
©
R.Lauwereins
Imec 2001
states
• Indicate for the remaining which next states have to be
Digital
design equivalent to make the current states equivalent
Combina-
torial
circuits PRESENT NEXT STATE / OUTPUT
Sequential
circuits
u0 u0/0 u1/0 d2/1
u1 u1/0 u2/0 d0/0
FSMD u2 u2/0 u0/1 d1/0
design
d0 d0/0 u1/0 d2/1
u1 d1 d1/0 u2/0 d0/0
VHDL
u2 d2 d2/0 u0/1 d1/0
d0 OK Minimum number
of states: 3 ie.
d1 OK
{u0,d0}=s0
d2 OK {u1,d1}=s1
{u2,d2}=s2
u0 u1 u2 d0 d1
3/84
©
R.Lauwereins
Imec 2001
states
Digital
• Construct the new next state table
design
PRESENT NEXT STATE / OUTPUT
Minimum number
Combina- of states: 3 ie. STATE CD=0X CD=10 CD=11
torial
circuits {u0,d0}=s0 u0 u0/0 u1/0 d2/1
{u1,d1}=s1 u1 u1/0 u2/0 d0/0
Sequential
{u2,d2}=s2 u2 u2/0 u0/1 d1/0
circuits
d0 d0/0 u1/0 d2/1
FSMD d1 d1/0 u2/0 d0/0
design
d2 d2/0 u0/1 d1/0
VHDL

s0 s0/0 s1/0 s2/1
s1 s1/0 s2/0 s0/0
s2 s2/0 s0/1 s1/0
3/85
©
R.Lauwereins
Imec 2001
states
Digital
• FYI: draw new state diagram
design
Combina- STATE CD=0X CD=10 CD=11
torial s0 s0/0 s1/0 s2/1
circuits
s1 s1/0 s2/0 s0/0
Sequential s2 s2/0 s0/1 s1/0
circuits
CD=10
Y=1
FSMD
design
CD=0X CD=0X CD=0X
Y=0 Y=0 Y=0
VHDL CD=10 CD=10
Y=0 Y=0
s0 s1 s2
CD=11 CD=11
Y=0 Y=0
CD=11 This could have been constructed from the begin

3/86 Y=1 -ning, but better 1 state too much than too little
©
R.Lauwereins
Imec 2001
states
Digital
• This example did not show how you should
design
manipulate the implication table
Combina- • Hence an imaginary example showing all
torial
circuits problems:
Sequential
circuits
FSMD STATE AB=00 AB=01 AB=10
design
s0 s4/1 s2/0 s1/1
VHDL s1 s2/0 s5/1 s4/1
s2 s1/1 s0/0 s3/1
s3 s2/0 s5/1 s4/1
s4 s0/0 s5/1 s1/1
s5 s2/0 s4/1 s2/1
3/87
©
R.Lauwereins
Imec 2001
states
Digital
• Construct the implication table: 1 square
design
per combination of 2 states
Combina-
torial PRESENT NEXT STATE / OUTPUT
circuits
STATE AB=00 AB=01 AB=10
circuits
s1 s2/0 s5/1 s4/1
FSMD
s2 s1/1 s0/0 s3/1
design s3 s2/0 s5/1 s4/1
s1 s4 s0/0 s5/1 s1/1
VHDL
s2 s5 s2/0 s4/1 s2/1
s3
s4
s5
s0 s1 s2 s3 s4
3/88
©
R.Lauwereins
Imec 2001
states
Digital
• Delete all combinations with different
design
outputs for same inputs
Combina-
torial PRESENT NEXT STATE / OUTPUT
circuits
circuits
s1 s2/0 s5/1 s4/1
FSMD
s2 s1/1 s0/0 s3/1
s1 s4 s0/0 s5/1 s1/1
VHDL
s2 s5 s2/0 s4/1 s2/1
s3
s4
s5
s0 s1 s2 s3 s4
3/89
©
R.Lauwereins
Imec 2001
states
• Indicate for the remaining which next states have to be
Digital
design equivalent to make the current states equivalent
Combina-
torial
Sequential
circuits
s0 s4/1 s2/0 s1/1
s1 s2/0 s5/1 s4/1
FSMD s2 s1/1 s0/0 s3/1
design
s3 s2/0 s5/1 s4/1
VHDL s1 s4 s0/0 s5/1 s1/1
1-4 s5 s2/0 s4/1 s2/1
s2 1-3
s3 OK
0-2
s4 0-2
1-4
4-5 4-5 0-2, 4-5
s5 2-4 2-4 1-2
3/90 s0 s1 s2 s3 s4
©
R.Lauwereins
Imec 2001
states
• Delete those states that are equivalent when non-
Digital
design equivalent next states would have been equivalent
Combina-
torial
Sequential
circuits
s0 s4/1 s2/0 s1/1
s1 s2/0 s5/1 s4/1
FSMD s2 s1/1 s0/0 s3/1
design
s3 s2/0 s5/1 s4/1
VHDL s1 s4 s0/0 s5/1 s1/1
1-4:
1-4 ? s5 s2/0 s4/1 s2/1
s2 1-3:OK
1-3
s3 OK
0-2:
0-2 ?
s4 0-2:
0-2 ?
1-4:
1-4 ?
4-5 4-5 0-2, 4-5
s5 2-4 2-4 1-2
3/91 s0 s1 s2 s3 s4
©
R.Lauwereins
Imec 2001
states
Digital
• Delete again as long as states are deleted
design
during an iteration
Combina-
torial
Sequential
circuits
s0 s4/1 s2/0 s1/1
s1 s2/0 s5/1 s4/1
FSMD s2 s1/1 s0/0 s3/1
design
s3 s2/0 s5/1 s4/1
VHDL s1 s4 s0/0 s5/1 s1/1
1-4: ? s5 s2/0 s4/1 s2/1
s2 1-3:OK
Minimum number
s3 OK
of states: 3 ie.
0-2: ?
s4 0-2: ?
1-4: ?
{s0,s2}=u0
4-5 4-5 0-2, 4-5 {s1,s3,s4}=u1
s5 2-4 2-4 1-2 {s5}=u2
3/92 s0 s1 s2 s3 s4
©
R.Lauwereins
Imec 2001
states
Digital
• Construct the new next state table
design
Minimum number PRESENT NEXT STATE / OUTPUT
Combina- of states: 3 ie. STATE AB=00 AB=01 AB=10
torial
circuits
{s0,s2}=u0 s0 s4/1 s2/0 s1/1
{s1,s3,s4}=u1
s1 s2/0 s5/1 s4/1
Sequential {s5}=u2
circuits s2 s1/1 s0/0 s3/1
s3 s2/0 s5/1 s4/1
FSMD
s5 s2/0 s4/1 s2/1
VHDL

u0 u1/1 u0/0 u1/1
u1 u0/0 u2/1 u1/1
u2 u0/0 u1/1 u0/1
3/93
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
FSMD
design
VHDL  Step 3: State encoding
circuits
3/94
©
R.Lauwereins
Imec 2001
Step 3: State encoding
Digital • n states require at least log2n flip-flops.

design
• There are n! possible encodings (n
Combina-
torial
choices for the first state, n-1 for the
circuits second, etc.)
Sequential
circuits
No. s0 s1 s2 s3 No. s0 s1 s2 s3
FSMD 1 00 01 10 11 13 10 00 01 11
design 2 00 01 11 10 14 10 00 11 01
3 00 10 01 11 15 10 01 00 11
VHDL 4 00 10 11 01 16 10 01 11 00
5 00 11 01 10 17 10 11 00 01
6 00 11 10 01 18 10 11 01 00
7 01 00 10 11 19 11 00 01 10
8 01 00 11 10 20 11 00 10 01
9 01 10 00 11 21 11 01 00 10
10 01 10 11 00 22 11 01 10 00
11 01 11 00 10 23 11 10 00 01
12 01 11 10 00 24 11 10 01 00
3/95
©
R.Lauwereins
Imec 2001
Step 3: State encoding
Digital
• Does the chosen encoding matters?
design
 Yes. Each choice leads to a different
Combina-
combinatorial circuit with different cost and
torial delay.
circuits
• Often chosen encodings:
Sequential
circuits  Straightforward
 Minimum-bit-change
FSMD
design  One-hot
VHDL
3/96
Step 3: State encoding:
©
R.Lauwereins
Imec 2001
Straightforward
Digital
• Straightforward encoding uses the binary
design
representation of the state number as
Combina- code (s0000, s5101, …)
torial
circuits • Straightforward encoding is mostly used
Sequential
when the state number has a physical
circuits
meaning
FSMD  E.g. a counter whose count value is sent to a
design
display
VHDL • Straightforward encoding is dangerous for
glitches and leads to non-minimal area
and power consumption: multiple bits
have to change at each state transition
(multiple bit-changes seldomly happen
concurrently; each bit-change requires some logic
to implement it; each bit-change consumes power)
3/97
©
R.Lauwereins
Imec 2001
Straightforward
Digital
design PRESENT NEXT STATE / OUTPUT
Combina- s0 s0/0 s1/0 s2/1
torial
s2 s2/0 s0/1 s1/0
Sequential
circuits
FSMD
design PRESENT NEXT STATE / OUTPUT
VHDL
00 00/0 01/0 10/1
01 01/0 10/0 00/0
10 10/0 00/1 01/0
3/98
©
R.Lauwereins
Imec 2001
Minimum-bit-change
Digital
• For minimum-bit-change encoding we
design
assign the codes such that the total
Combina- number of bit-changes for all state
torial
circuits transitions is minimal
Sequential
• Minimum-bit-change encoding is mostly
circuits
used when area and power need to be
FSMD minimized (CMOS)
design
VHDL
00 1 01 00 1 01
Gray code
counter
2 2 1 1
1 1
11 10 10 11
3/99 Straightforward Minimum-bit-change

©
R.Lauwereins
Imec 2001
Minimum-bit-change
Digital
design
s0 s0/0 s1/0 s2/1
torial
Sequential
circuits 0 1
All transitions are equally likely
FSMD Preferrably only 1 bit difference
design
between each pair of transitions
This can only be realised between
VHDL
2 two of the three pairs

STATE CD=0X CD=10 CD=11 Possible
00 00/0 10/0 11/1 encoding:
s0=00
10 10/0 11/0 00/0
s1=10
11 11/0 00/1 10/0
3/100 s2=11
©
R.Lauwereins
Imec 2001
One-hot
Digital
• Each state has 1 flip-flop, hence no
design
encoding; Q of 1 FF =1, Q of others=0
Combina-
torial
• Flip-flop cost = O(n) i.o. O(logn), hence
circuits only useful for small number of states:
Sequential
controller
• Very easy to realise: short design time
circuits
FSMD (time-to-market, e.g. exam…)

design
• Very small combinatorial circuits to drive
VHDL
the inputs of the flip-flops: cheap
combinatorial part, more expensive flip-
flop part
 An FPGA possesses per half CLB a small
combinatorial circuit and 1 flip-flop: one-hot
encoding is ideal for FPGA implementations
(except counters: too many states)
3/101
©
R.Lauwereins
Imec 2001
One-hot
Digital
design
s0 s0/0 s1/0 s2/1
torial
Sequential
circuits One-hot encoding
s0=001
FSMD
design
s1=010
s2=100
VHDL

001 001/0 010/0 100/1
010 010/0 100/0 001/0
100 100/0 001/1 010/0
3/102
©
R.Lauwereins
Imec 2001
One-hot
CD=0X CD=0X CD=0X
Digital CD=10 Y=0 Y=0 Y=0
design
Y=1 CD=10 CD=10
Y=0 Y=0
Combina-
torial s0 s1 s2
circuits
CD=11 CD=11 CD=11
Y=1 Y=0 Y=0
Sequential
circuits
FSMD
design
Q0 Q1 C Q2 C
P
VHDL D D D Y
C
3/103
D
©
R.Lauwereins
Imec 2001
One-hot
Digital
• Implementation rule for One-hot with D
design
flip-flop:
Combina-  Each arriving transition at a state needs an
torial
circuits
AND gate
Sequential
circuits
FSMD
design
VHDL
3/104
©
R.Lauwereins
Imec 2001
One-hot
CD=0X CD=0X CD=0X
Digital CD=10 Y=0 Y=0 Y=0
design
Y=1 CD=10 CD=10
Y=0 Y=0
Combina-
torial s0 s1 s2
circuits
CD=11 CD=11 CD=11
Y=1 Y=0 Y=0
Sequential
circuits
FSMD
design
P Q0 Q1 C Q2 C
VHDL S R S R S R Y
C
3/105 D
©
R.Lauwereins
Imec 2001
One-hot
Digital
• Implementation rule for One-hot with SR
design
flip-flop:
Combina-  Each arriving transition starting at another
torial
circuits
state requires an AND gate at the S input
 Each departing transition to another state
Sequential
circuits
requires an AND gate at the R input
FSMD
design
VHDL
3/106
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
FSMD
design
 Step 4: Choice of the flip-flop type
circuits
3/107
©
R.Lauwereins
Imec 2001
Step 4: Choice of the flip-flop type
Digital
• JK flip-flop
design
 Most expensive flip-flop
Combina-  Most difficult design
torial
circuits  Largest number of don’t cares: probably
cheapest (and fastest) combinatorial control
Sequential
circuits
logic
 Used when a different signal sets resp. resets
FSMD
design
the flip-flop
• SR flip-flop
VHDL
 Cheap flip-flop
 Difficult design
 Many don’t cares: probably cheap (and fast)
control logic
 Used when a different signal sets resp. resets
the flip-flop
3/108
©
R.Lauwereins
Imec 2001
Digital
• D flip-flop
design
 Cheap flip-flop
Combina-  Most easy design
torial
circuits  No don’t cares: probably most expensive (and
slowest) combinatorial control logic
Sequential
circuits  Used when the same signal sets resp. resets
the flip-flop, i.e. when the value of a signal has
FSMD
design
to be remembered temporarily
• T flip-flop
VHDL
 Cheap flip-flop
 Easy design
 No don’t cares: probably most espensive (and
slowest) combinatorial control logic
 Used for counters and frequency dividers: fast
toggling
3/109
©
R.Lauwereins
Imec 2001
Digital
• No fixed selection rule exists
design
 When we want the cheapest circuit, all variants
Combina-
have to be tried out
torial
circuits
 When the fastest design time is needed, D flip-
flops are the best choice
Sequential
circuits
 FPGAs only possess D flip-flops
FSMD
design
VHDL
3/110
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
FSMD
design
 Step 5: Realization of the combinatorial logic
circuits
3/111
Step 5: Realization of the
©
R.Lauwereins
Imec 2001
combinatorial logic: D flip-flop

Digital
• Determine the excitation functions
design Q0
PRESENT NEXT STATE / OUTPUT Y Q1
Combina-
torial STATE CD=0X CD=10 CD=11
circuits 0 0 x 0
00 00/0 01/0 10/1
Sequential 01 01/0 10/0 00/0 0 0 x 0
circuits D
10 10/0 00/1 01/0 1 0 x 0
C
FSMD 0 0 x 1
design
Excitation table Q0 Q0
VHDL
for D flip-flop Q1n=D1 Q1 Q0n=D0 Q1
Q Q(next) D
0 0 0 0 0 x 1 0 1 x 0
0 1 1 0 0 x 1 0 1 x 0
1 0 0 D D
1 0 x 0 0 0 x 1
1 1 1 C C
0 1 x 0 1 0 x 0
 D to be applied
3/112 is identical to Qn
©
R.Lauwereins
Imec 2001
combinatorial logic: D flip-flop

Q0 Q0 Q0
Digital
design
Q1n=D1 Q1 Q0n=D0 Q1 Y Q1
Combina- 0 0 x 1 0 1 x 0 0 0 x 0
torial
circuits 0 0 x 1 0 1 x 0 0 0 x 0
D D D
1 0 x 0 0 0 x 1 1 0 x 0
Sequential C C C
circuits 0 1 x 0 1 0 x 0 0 0 x 1
FSMD
design
Q1 Clr Q0 Clr
Cost: 35
VHDL D D Y
1.5 CLB
C
D
3/113
©
R.Lauwereins
Imec 2001
combinatorial logic: T flip-flop

Digital
design Q0
Combina-
circuits 0 0 x 0
00 00/0 01/0 10/1
Sequential 01 01/0 10/0 00/0 0 0 x 0
circuits D
10 10/0 00/1 01/0 1 0 x 0
C
FSMD 0 0 x 1
design
VHDL
for T flip-flop T1 Q1 T0 Q1
Q Q(next) T
0 0 0 0 0 x 0 0 0 x 0
0 1 1 0 0 x 0 0 0 x 0
1 0 1 D D
1 0 x 1 0 1 x 1
1 1 0 C C
0 1 x 1 1 1 x 0
3/114
©
R.Lauwereins
Imec 2001
combinatorial logic: T flip-flop

Q0 Q0 Q0
Digital
design
T1 Q1 T0 Q1 Y Q1
Combina- 0 0 x 0 0 0 x 0 0 0 x 0
torial
circuits 0 0 x 0 0 0 x 0 0 0 x 0
D D D
1 0 x 1 0 1 x 1 1 0 x 0
Sequential C C C
circuits 0 1 x 1 1 1 x 0 0 0 x 1
FSMD
design
Q1 Clr Q0 Clr
Cost: 32
VHDL T T Y
C
D
3/115
©
R.Lauwereins
Imec 2001
combinatorial logic: SR flip-flop

Digital
design

Combina-
circuits
00 00/0 01/0 10/1
Sequential 01 01/0 10/0 00/0
circuits
10 10/0 00/1 01/0
FSMD
design
VHDL
for SR flip-flop S1 Q1 R1 Q1
Q Q(next) S R
0 0 0 x
0 0 x x x x x 0
0 1 1 0 0 0 x x x x x 0
1 0 0 1 D D
1 0 x 0 0 x x 1
1 1 x 0 C C
0 1 x 0 x 0 x 1
3/116
©
R.Lauwereins
Imec 2001

Digital
design Q0
Combina-
circuits 0 0 x 0
00 00/0 01/0 10/1
Sequential 01 01/0 10/0 00/0 0 0 x 0
circuits D
10 10/0 00/1 01/0 1 0 x 0
C
FSMD 0 0 x 1
design
VHDL
for SR flip-flop S0 Q1 R0 Q1
Q Q(next) S R
0 x x 0 x 0 x x
0 0 0 x
0 1 1 0 0 x x 0 x 0 x x
1 0 0 1
D D
0 0 x 1 x 1 x 0
1 1 x 0 C C
1 0 x 0 0 1 x x
3/117
©
R.Lauwereins
Imec 2001

Q0 Q0
Digital S1 Q1 R1 Q1
design
0 0 x x x x x 0
Combina-
torial 0 0 x x x x x 0
circuits
D D
1 0 x 0 0 x x 1
Sequential C C
circuits 0 1 x 0 x 0 x 1
FSMD
design
Q1 C Q0 C
VHDL S R S R
C
3/118 D
©
R.Lauwereins
Imec 2001

Q0 Q0
Digital S0 Q1 R0 Q1
design
0 x x 0 x 0 x x
Combina-
torial 0 x x 0 x 0 x x
circuits
D D
0 0 x 1 x 1 x 0
Sequential C C
circuits 1 0 x 0 0 1 x x
FSMD
design
Q1 C Q0 C
VHDL S R S R
C
3/119 D
©
R.Lauwereins
Imec 2001

Q0 Q0 Q0
Digital S0 Q1 R0 Q1 Y Q1
design
0 x x 0 x 0 x x 0 0 x 0
Combina-
torial 0 x x 0 x 0 x x 0 0 x 0
circuits
D D D
0 0 x 1 x 1 x 0 1 0 x 0
Sequential C C C
circuits 1 0 x 0 0 1 x x 0 0 x 1
FSMD
design
Q1 C Q0 C
Y Cost: 32
VHDL S R S R
C
3/120 D
©
R.Lauwereins
Imec 2001
combinatorial logic: JK flip-flop

Digital
design

Combina-
circuits
00 00/0 01/0 10/1
Sequential 01 01/0 10/0 00/0
circuits
10 10/0 00/1 01/0
FSMD
design
VHDL
for JK flip-flop J1 Q1 K1 Q1
Q Q(next) J K
0 0 0 x
0 0 x x x x x 0
0 1 1 x 0 0 x x x x x 0
1 0 x 1 D D
1 0 x x x x x 1
1 1 x 0 C C
0 1 x x x x x 1
3/121
©
R.Lauwereins
Imec 2001

Digital
design Q0
Combina-
circuits 0 0 x 0
00 00/0 01/0 10/1
Sequential 01 01/0 10/0 00/0 0 0 x 0
circuits D
10 10/0 00/1 01/0 1 0 x 0
C
FSMD 0 0 x 1
design
VHDL
for JK flip-flop J0 Q1 K0 Q1
Q Q(next) J K
0 0 0 x
0 x x 0 x 0 x x
0 1 1 x 0 x x 0 x 0 x x
1 0 x 1 D D
0 x x 1 x 1 x x
1 1 x 0 C C
1 x x 0 x 1 x x
3/122
©
R.Lauwereins
Imec 2001

Q0 Q0
Digital J1 Q1 K1 Q1
design
0 0 x x x x x 0
Combina-
torial 0 0 x x x x x 0
circuits
D D
1 0 x x x x x 1
Sequential C C
circuits 0 1 x x x x x 1
FSMD
design
Q1 C Q0 C
VHDL J K J K
C
3/123 D
©
R.Lauwereins
Imec 2001

Q0 Q0 Q0
Digital J0 Q1 K0 Q1 Y Q1
design
0 x x 0 x 0 x x 0 0 x 0
Combina-
torial 0 x x 0 x 0 x x 0 0 x 0
circuits
D D D
0 x x 1 x 1 x x 1 0 x 0
Sequential C C C
circuits 1 x x 0 x 1 x x 0 0 x 1
FSMD
design
Q1 C Q0 C
Y Cost: 26
VHDL J K J K
C
3/124 D
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina- circuits
torial
Sequential
FSMD
design
 Step 6: Timing analysis
circuits
3/125
©
R.Lauwereins
Imec 2001
Step 6: Timing analysis
Digital
• Determine maximum clock frequency
design
 Max. clock frequency = 1/(delay of critical path)
Combina-  Critical path is the path with the longest
torial
circuits
combinatorial delay between two clock edges
 Example:
Sequential
circuits
FSMD
design
Q1 Clr Q0 Clr
VHDL D D Y
C
D
3/126
©
R.Lauwereins
Imec 2001
• Delay of critical path (assume zero

connection delay):
Digital
design  clockQ0 + invertor + 4-input AND + 3-input OR
+ setup Dclock
Combina-
torial  = 5.2 + 1.0 + (2.2+1.0) + (1.8+1.0) + 1.0 = 13.2 ns
circuits
(assuming that our relative times can be
Sequential considered to be nanoseconds)
circuits
 fmax = 76 MHz (same assumption)
FSMD
design
Q1 Clr Q0 Clr
VHDL D D Y
C
D
3/127
©
R.Lauwereins
Imec 2001
Digital
• After designing the combinatorial circuits
design
for next state and output, all traditional
Combina- design steps follow:
torial
circuits  Technology mapping
 Placement and routing
Sequential
circuits  Timing simulation
FSMD • Timing simulation is even more important
design
for sequential circuits than for
VHDL combinatorial circuits
 Determine the maximum clock frequency to
check whether setup and hold times are
satisfied
 Avoid, if necessary because of connected
circuits, glitches when a state transition
involves multiple bit-flips
3/128
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
 Design of asynchronous sequential
Sequential circuits
circuits
FSMD
design
VHDL
3/129
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
 Definitions and Fundamental Mode Restriction
FSMD  Design
design
VHDL
3/130
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
 Definitions and Fundamental Mode Restriction
FSMD  Design
design
VHDL
3/131
©
R.Lauwereins
Imec 2001
Asynchronous Sequential Circuits
Digital
• Definitions:
design
 Sequential circuit: the output is function of the
Combina-
current value of the inputs and of the current
torial state (i.e. also function of the sequence of past
circuits
inputs)
Sequential  Asynchronous sequential circuits: outputs and
circuits
state change as soon as an input changes
FSMD
design
• Fundamental mode restriction:
 only one input may change at a time; the next
VHDL input change may only occur when all effects
to the previous input change died out
• Goal: design of small asynchronous
circuits, e.g. interfaces between two
synchronous islands with not-correlated
clocks or clocks with unpredictable clock
3/132
skew
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
 Definitions and Fundamental Mode Restriction
FSMD  Design
design
VHDL
3/133
©
R.Lauwereins
Imec 2001
Example circuit: requirements
• Design a circuit with two inputs (I and E)
Digital
design and one output Q.
 If E is high, a rising edge on I causes Q to go
Combina-
torial high.
circuits
 Q stays high until E goes low.
Sequential  While E is low, Q is low.
circuits
FSMD
design
VHDL
3/134
©
R.Lauwereins
Imec 2001 Design flow
State table
Digital
design
State transition diagram
Combina-
torial
circuits
Primitive flow table
Sequential
circuits
Minimized flow table
FSMD
design
State assignment
VHDL
Elimination of critical races
Hazard free combinatorial design
Avoidance of input skew

3/135
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/136
©
R.Lauwereins
Imec 2001
State table
Digital
• List all states: each possible combination
design
of inputs and outputs is a state
Combina-
torial Q I E State
circuits
0 0 0 a
Sequential
0 0 1 b
circuits 0 1 0 c
0 1 1 d
FSMD
design 1 0 0 impossible
1 0 1 e
VHDL 1 1 0 impossible
1 1 1 f
3/137
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/138
©
R.Lauwereins
Imec 2001
01 11 11
Digital Q I E State
design
0 0 0 a
Combina-
e/0 f/0 0 0 1 b
torial 0 1 0 c
circuits
01
0 1 1 d
IE 00 11
Sequential 1 0 0 impossible
circuits
01
00 1 0 1 e
01
1 1 0 impossible
FSMD
design a/0 b/0 1 1 1 f
00
VHDL 10
We opted for a
10 00 01
Moore or state
11
10 based design; we
11
could as well have
c/0 d/0 chosen a Mealy
10 approach, with
output per
transition
3/139
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/140
©
R.Lauwereins
Imec 2001
Digital
IE Q I E State
design
S 00 01 11 10 Q 0 0 0 a
Combina- a a b x c 0 0 0 1 b
torial 0 1 0 c
circuits b a b f x 0
c a x d c 0 0 1 1 d
Sequential d x b d c 0 1 0 0 impossible
circuits
e a e f x 1 1 0 1 e
f x e f c 1 1 1 0 impossible
FSMD
design 1 1 1 f
VHDL
3/141
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/142
©
R.Lauwereins
Imec 2001
Digital
• Rule: merge compatible states: states
design
with same next states and outputs or
Combina- don’t cares
torial
circuits • ‘Compatibility’ is not associative!
Sequential
(a compatible b) AND (a compatible c)
circuits
does NOT induce (b compatible c)
FSMD • Note that minimizing the number of states
design
of synchronous circuits requires
VHDL equivalence instead of compatibility.
 States with same outputs and equivalent next
states
 ‘Equivalence’ is associative!
3/143
©
R.Lauwereins
Imec 2001
IE
Digital
S 00 01 11 10 Q Are a and b compatible?
design
a a b x c 0
YES, hence merge them
Combina- b a b f x 0
torial
circuits c a x d c 0
d x b d c 0
Sequential e a e f x 1
circuits
f x e f c 1
FSMD
design
IE
VHDL S 00 01 11 10 Q
   f c 0
c  x d c 0
d x  d c 0
e  e f x 1
f x e f c 1
3/144
©
R.Lauwereins
Imec 2001
Digital IE Are c and d compatible?

design S 00 01 11 10 Q
   f c 0 YES, hence merge them
Combina-
torial c  x d c 0
circuits
d x  d c 0
e  e f x 1
Sequential
circuits f x e f c 1
FSMD
design
IE
VHDL S 00 01 11 10 Q
   f  0
     0
e  e f x 1
f x e f  1
3/145
©
R.Lauwereins
Imec 2001
Digital IE Are e and f compatible?

design S 00 01 11 10 Q

 
 
 ff 
 0
0 YES, hence merge them
Combina-

 
 
 
 
 0
0
torial
circuits e
e 
 e
e ff x
x 1
1
ff x
x e
e ff 
 1
1
Sequential
circuits
FSMD
IE
design
S 00 01 11 10 Q This minimized flow table
VHDL      0 is called the
     0 Transition Table
     1
3/146
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/147
©
R.Lauwereins
Imec 2001
State assignment
Assume we make following
IE
Digital straightforward
design S 00 01 11 10 Q
state assignment:
     0
Combina-
: 00
torial
     0 : 01
circuits      1 : 11
Sequential
circuits IE
S 00 01 11 10 Q
FSMD 00 00 00 11 01 0
design
01 00 00 01 01 0
VHDL 11 00 11 11 01 1
3/148
©
R.Lauwereins
Imec 2001
State assignment
Digital
design
IE
Combina- S 00 01 11 10 Q
torial
circuits 00 00 00 11 01 0
01 00 00 01 01 0
Sequential 11 00 11 11 01 1
circuits
FSMD
design
VHDL
S0 S0
S0n S1 S1n S1
0 0 0 x 0 0 0 x
0 0 1 x 0 0 1 x S0
E E
I 1 1 1 x I 1 0 1 x 0 0
1 1 1 x 0 0 0 x S1 x 1
3/149
©
R.Lauwereins
Imec 2001
State assignment
Digital
design I E S1 S0
Combina-
torial
circuits
Sequential
circuits
Q
FSMD
design
VHDL
S0 S0
S0n S1 S1n S1
0 0 0 x 0 0 0 x
0 0 1 x 0 0 1 x S0
E E
I 1 1 1 x I 1 0 1 x 0 0
1 1 1 x 0 0 0 x S1 x 1
3/150
©
State assignment
R.Lauwereins
Imec 2001
I E S1 S0 IE
Digital
design
S 00 01 11 10 Q
00 00 00 11 01 0
Combina- 01 00 00 01 01 0
torial
circuits 11 00 11 11 01 1
Sequential
circuits Q
FSMD
design Let’s animate behav from state S=00 with inputs IE=01->11
Step 1: Stable state S=00 with inputs IE=01
VHDL
Step 2: Inputs change to IE=11
Step 3: after 2-input gate delay, OR-gate switches,
making S0=1
No Step 4: we are stuck in stable state S=01 because
both state bits did not change at the same time
The fact that 2 or more state variables have to change,
when 1 input-bit changes is called a RACE CONDITION
When this leads to the wrong final state,
3/151 it’s called a CRITICAL RACE
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/152
©
R.Lauwereins
Imec 2001
Digital
• Solution: make the state assignment such
design
that never 2 or more state variables need
Combina- to change following a single input change
torial
circuits
IE 00 01
Sequential
S 00 01 11 10 Q  
circuits
     0
FSMD      0
design
     1 
VHDL 11
No encoding can be found satisfying the above rule!
3/153
©
R.Lauwereins
Imec 2001
Digital
• Do the state assignment as good as you
design
can. Use additional states to solve the
Combina- problems that remain
torial
circuits
IE
S 00 01 11 10 Q Don’t care because both
Sequential
00 00 00 10 01 0
new transitions require
circuits 11
an output change: it
01 00 00 01 01 0
FSMD is not important whether
11 10
00 11 11 01 1
design this already happens in
10 00 x 11 x x
the intermediate state
VHDL
Highlight remaining problems

Route these transitions via an additional state, which
differs in only one state variable
3/154
©
R.Lauwereins
Imec 2001
Digital IE
design S 00 01 11 10 Q
00 00 00 10 01 0
Combina-
torial 01 00 00 01 01 0
circuits
11 10 11 11 01 1
10 00 x 11 x x
Sequential
circuits
FSMD
design
VHDL
S0 S0
S0n S1 S1n S1
0 0 0 0 0 0 1 0
0 0 1 x 0 0 1 x S0
E E
I 0 1 1 1 I 1 0 1 1 0 0
1 1 1 x 0 0 0 x S1 x 1
3/155
©
R.Lauwereins
Imec 2001
I E S1 S0
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
Q
VHDL
S0 S0
S0n S1 S1n S1
0 0 0 0 0 0 1 0
0 0 1 x 0 0 1 x S0
E E
I 0 1 1 1 I 1 0 1 1 0 0
3/156 1 1 1 x 0 0 0 x S1 x 1
©
R.Lauwereins
Imec 2001
Digital IE
design S 00 01 11 10 Q
00 00 00 10 01 0
Combina-
torial 01 00 00 01 01 0
circuits
11 10 11 11 01 1
10 00 00
x 11 01
x x
Sequential
circuits Race, but not critical
FSMD What happens at power-up?
design
The circuit could as well start in state S=10 with an

VHDL input of IE=01
It then depends on the actual values of the don’t cares

what is going to happen; it could even remain stable
in that state...
It would hence be wise to remove the don’t cares and

replace them with an evolution to a stable state with
the same inputs
3/157
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/158
©
R.Lauwereins
Imec 2001
Digital
• The combinatorial circuits of an
design
asynchronous design should be designed
Combina- in a hazard free way
torial
circuits  Static hazard: a status variable that is
supposed not to change, briefly changes; this
Sequential
circuits
could lead to a wrong final state
 Dynamic hazard: a status variable that is
FSMD
design
supposed to change just once, changes three
times; this could lead to a wrong final state
VHDL
• Synchronous designs do not need to be
hazard free, since state variables are only
taken into account on a clock edge
• Our design was hazard free, and hence
should not be changed
3/159
©
R.Lauwereins
State table
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
State assignment
VHDL

3/160
©
R.Lauwereins
Imec 2001
Digital
• Assume that input I is skewed on the
design bottom AND gate with respect to the other
Combina-
inputs IE
torial S 00 01 11 10 Q
circuits
I E S1 S0 00 00 00 10 01 0
Sequential 01 00 00 01 01 0
circuits
11 10 11 11 01 1
10 00 11 11 01 1
FSMD
design
Start in state S=01 with IE=11
VHDL
I becomes 0: S should go to 00
Now the delayed version of I

goes to zero
State however does not change
Q anymore and ends in the
incorrect S=11
Delay State variables may change only after all input
3/161 changes are applied to all gates!
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
 Basic RTL building blocks
FSMD
design
VHDL
3/162
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
Synchronous counters
Asynchronous counters
 Register files
 LIFO queue (push down stack)
 FIFO queue
3/163
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
 Register files
 FIFO queue
3/164
©
R.Lauwereins
Imec 2001
Registers
Digital
• Register
design
I3 I2 I1 I0
Combina-
torial
circuits
D Q D Q D Q D Q
Sequential
circuits
FSMD
design
Clk
VHDL
Q3 Q2 Q1 Q0
I3 I2 I1 I0
Register Symbol
3/165 Q 3 Q 2 Q 1 Q0
©
R.Lauwereins
Imec 2001
Registers
Digital
• Asynchronously presettable and clearable
design Register
Combina- I3 I2 I1 I0
torial
circuits
Preset
Sequential D Q D Q D Q D Q
circuits
FSMD
design Clear
Clk
VHDL Q3 Q2 Q1 Q0
I3 I2 I1 I0
Preset
Register Symbol
Clear
3/166 Q 3 Q 2 Q1 Q 0
©
R.Lauwereins
Imec 2001
Registers
Digital
• Loadable register (without gated clock)
design
I3 I2 I1 I0
Combina-
torial
circuits 1 0 1 0 1 0 1 0
S S S S
Sequential
circuits
Load
FSMD D Q D Q D Q D Q
design
VHDL
Clk
Q3 Q2 Q1 Q0
• Loads only when “Load=1”

• High power dissipation: multiple gates switch
whenever the clock changes
• No clock skew problems since each flip-flop is clocked
3/167
by the master clock
©
R.Lauwereins
Imec 2001
Registers
Digital
• Loadable register (without gated clock)
design
Combina-
torial
circuits I3 I2 I1 I0
Sequential Load
circuits
Register Symbol
FSMD
design
Q3 Q2 Q 1 Q 0
VHDL
3/168
©
R.Lauwereins
Imec 2001
Registers
Digital
• Loadable register (with gated clock)
design
I3 I2 I1 I0
Combina-
torial
circuits D Q D Q D Q D Q
Sequential
circuits CE
FSMD
design Clk
Q3 Q2 Q1 Q0
VHDL
• Clocks only when “CE=1”

• Low power dissipation: gates only switch when a new
value is loaded
• Gated clocks (derived clocks) are sensitive to clock
3/169
skew
©
R.Lauwereins
Imec 2001
Registers
Digital
• Loadable register (with gated clock)
design
Combina-
torial
Sequential CE
circuits
Register Symbol
FSMD
design
Q3 Q2 Q 1 Q 0
VHDL
3/170
©
R.Lauwereins
Imec 2001
Registers
• Clock skew problem for
Digital
design gated clocks:
 Not all clocks of all
Combina- registers change I3 I2 I1 I0
torial
circuits concurrently
 Expected behavior:
Sequential
New I3..0 applied Register 1
circuits
At next clock edge:
FSMD
Clk*11, Clk*21 A3..0
design
CE
Q*3..0A3..0, A*3..0I3..0
Register 2
VHDL  Real behavior:
New I3..0 applied
At next clock edge: Q 3 Q2 Q1 Q 0
Clk*11
A*3..0I3..0, Clk*21
Q*3..0A*3..0
Risk for setup
3/171 violation
©
R.Lauwereins
Imec 2001
Registers
I A Q
Digital
design
D0 Q0 D1 Q1
Combina-
torial
Clk
circuits
CE
Sequential
circuits
Possible setup or hold
violation for 2nd flip-flop
FSMD
design Clk
VHDL I
CE
Gated
Clk
Q
3/172
©
R.Lauwereins
Imec 2001
Registers
Digital
• What causes clock skew?
design
 Gated clocks
Combina-  Different relative routing delay
torial
circuits On PCB and within chip: different
Sequential
wire length
circuits
In FPGA: different number of routing
FSMD switches
design
• Delay depends on many things:
VHDL
 temperature, power supply voltage, fan-out, IC
batch
 under no circumstance clock skew may cause
problems!!!  worst case analysis (e.g. min-
delay for data path and max-delay for clock
path and vice versa)
3/173
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
 Register files
 FIFO queue
3/174
©
R.Lauwereins
Imec 2001
Shift registers
Digital
• Serial-in/parallel-out shift register (SIPO)
design
IL
Combina-
torial
circuits 1 0 1 0 1 0 1 0
S S S S
Sequential
circuits
SE
design
VHDL
Clk
Q3 Q2 Q1 Q0
Example of utilization:
Receive register (Rx) serial port
Delay line for FIR and IIR filters
3/175
©
R.Lauwereins
Imec 2001
Shift registers
Digital
• Serial-in/parallel-out shift register (SIPO)
design
Combina-
torial
circuits
Sequential IL
circuits
Shift Register Symbol
SE
FSMD
design
Q 3 Q 2 Q1 Q 0
VHDL
3/176
©
R.Lauwereins
Imec 2001
Shift registers
Digital
• Parallel-in/serial-out shift register (PISO)
design
IL I3 I2 I1 I0
Combina-
torial
circuits 1 0 1 0 1 0 1 0
S S S S
Sequential
circuits
Sh/Ld
design
Clk
VHDL
CE
Q0
Example of utilization: Transmit register (Tx) serial port
3/177
©
R.Lauwereins
Imec 2001
Shift registers
Digital
• Parallel-in/serial-out shift register (PISO)
design
Combina-
torial
Sequential IL
circuits
Shift Symbol
FSMD CE Register
design Sh/Ld’
VHDL
Q0
3/178
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
Synchronous counters
 Register files
 FIFO queue
3/179
©
R.Lauwereins
Imec 2001
Synchronous counters
Digital
• Synchronous up-counter
design
Combina-
E
torial
circuits
Sequential HA HA HA
circuits
FSMD D Q D Q D Q
design
VHDL Clear
Clk Output Q2 Q1 Q0
carry
Synchronous because all flip-flops are clocked by the

same signal
3/180
©
R.Lauwereins
Imec 2001 Glitch! Synchronous counters
Digital
E
design
Combina-
torial HA HA HA
circuits
Sequential D Q D Q D Q
circuits
FSMD Clear
design
Clk Output
VHDL Q2 Q1 Q0
carry
Clk
Clear
E
Q0
Q1
Q2
3/181
©
R.Lauwereins
Imec 2001
Digital
• Synchronous up/down-counter
design
D
Combina-
E
torial Co Ci
circuits HAS HAS HAS
Sequential
circuits
FSMD D Q D Q D Q
design
VHDL Clear
Clk Output Q2 Q1 Q0
carry
Half
adder/subtractor
3/182
©
R.Lauwereins
Imec 2001
Digital
• Design of the Half adder/subtractor
design
Behavior:
Combina- D When ci=0 then Di=Qi (no counting)
torial co
circuits HAS ci When ci=1 this section should toggle
Qi C0 has to be 1 when the next section
Sequential
circuits has to toggle. When should this happen?
Di
FSMD
design
Up-count Down-count
VHDL
00 00
01 11
10 10
11 01
00 00
01 11
… …
Next section toggles Next section toggles
at 10 of this section at 01 of this section
3/183
©
R.Lauwereins
Imec 2001
Digital
design
ci Dir Qii Dii c
ci+1
i+1 Behavior:
0 0 0 0 0
0 When ci=0 then Di=Qi (no counting)
Combina-
torial 0 0 1 1 0
0 When ci=1 this section should toggle
circuits
0 1 0 0 0
0 C0 has to be 1 when the next section
0 1 1 1 0 has to toggle. When should this happen?
0
Sequential
circuits 1 0 0 1 0
0
1 0 1 0 1
1
FSMD 1 1 0 1 1
1
design
1 1 1 0 0
0 Up-count Down-count
00 00
VHDL
01 11
10 10
11 01
00 00
01 11
… …
Next section Next section
toggles at 10 toggles at 01
3/184 of this section of this section
©
R.Lauwereins
Imec 2001
Digital
design
ci Dir Qi Di ci+1 Qi Qi
Combina- 0 0 0 0 0 Di Dir ci+1 Dir
torial
circuits 0 0 1 1 0
0 1 0 0 0 0 1 1 0 0 0 0 0
Sequential 0 1 1 1 0 ci 1 0 0 1 ci 0 1 0 1
circuits
1 0 0 1 0
FSMD 1 0 1 0 1
design 1 1 0 1 1
ci
1 1 1 0 0
VHDL Dir
Qi
Di ci+1
3/185
©
R.Lauwereins
Imec 2001
Digital
• Parallel loadable up/down-counter
design I2 I1 I0
D
Combina-
torial
circuits E
HAS HAS Co HAS
Sequential Ci
circuits
1 0 1 0 1 0
FSMD
design
Load
VHDL
D Q D Q D Q
Clear
Clk Output Q2 Q1 Q0
carry
3/186
©
R.Lauwereins
Imec 2001
Digital
• BCD up-counter
design
Combina-
torial
circuits 0 0 0 0
Sequential I3 I2 I1 I0
circuits
Up-counter
FSMD E
design Load Q3Q2 Q1 Q0
VHDL
Compares with constant:

When count equals ‘1001’ (i.e.
9), ‘0000’ is loaded at next clock
edge
3/187
©
R.Lauwereins
Imec 2001
Digital
• BCD up/down-counter
design
1 0 0 1 0 0 0 0
Combina-
torial 1 0
circuits
Mux
Sequential
circuits
FSMD
design
D I3 I2 I1 I0
Up/down-
VHDL
E counter
Load Q3Q2 Q1 Q0
3/188
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
Asynchronous counters
 Register files
 FIFO queue
3/189
©
R.Lauwereins
Imec 2001
Asynchronous counters
Digital
E
design T Q T Q T Q T Q
Combina- Q’ Q’ Q’ Q’
torial
circuits
Clear
Sequential
circuits
FSMD Clk Q3 Q2 Q1 Q0
design
VHDL
Clk
Q0
Q1
Q2
Q3
3/190
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
 Register files
 FIFO queue
3/191
©
R.Lauwereins
Imec 2001
Register files
Digital
design
Dout
WE D Q
Combina-
torial Din
circuits
Clk
Sequential RE
circuits
Register File Cell (RFC)
FSMD This implementation dissipates much power due to the
design
active memorization of data, but does not suffer from
VHDL
clock skew problems.
Combining ‘WE’ with ‘Clk’ into a gated clock, we can

reduce the power dissipation
Note that in both cases, Dout

Din D Q
‘writing’ is clocked, but
‘reading’ is not clocked!
WE
Needed for critical-path Clk
3/192
computation... RE
©
R.Lauwereins
Imec 2001
Register files
I3 I2 I1 I0
Digital
design
2-to-4
Combina-
0 read
torial dec
circuits RFC RFC RFC RFC
WA1 RA1
0
Sequential
WA0 1 RA0
circuits
RFC RFC RFC RFC

FSMD
design 1
WE 2 RE
VHDL
RFC RFC RFC RFC
2
3
2-to-4 RFC RFC RFC RFC

write 3
dec
O3 O2 O1 O0
3/193
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
 Register files
 LIFO queue (push down stack)
 FIFO queue
3/194
©
R.Lauwereins
Imec 2001
LIFO queue - stack
Digital
design
Top empty
45
23
12
10 1. Reset
Combina-
torial 2. Push 45
circuits Top-1 empty
45
12
3. Push 12
Top-2 empty
45 4. Push 23
Sequential
circuits 5. Pop -> 23
Top-3 empty
6. Push 10
FSMD
design Top-4 empty
Top-5 empty
VHDL
Top-6 empty
Top-7 empty
3/195
©
R.Lauwereins
Imec 2001
LIFO queue - stack
Enable Push/pop’ Operations
Digital
design 0 0 No change
0 1 No change
Combina- 1 0 Pop
torial
circuits 1 1 Push
Sequential Using left/right’ shift register and counter for indication

circuits
empty/full
FSMD Count Empty Full
design Reset IL IR
L/R’ 0000 1 0
Enable O7 O0 0001 0 0
VHDL
0010 0 0
0011 0 0
0100 0 0
0101 0 0
0110 0 0
0111 0 0
1000 0 1
3/196
©
R.Lauwereins
Imec 2001
LIFO queue - stack
In0
0
Digital
design
Reset IL IR
L/R’
Enable O7 O0
Combina-
torial
circuits
Out0
In7
0
Sequential
circuits Reset IL IR
L/R’
Enable O7 O0
FSMD
design
Out7
VHDL Reset
Up/down’
Enable Q3..0
Reset’ Empty
Push/pop’
Enable Full
3/197
©
R.Lauwereins
Imec 2001
LIFO queue - stack
Digital
Alternative implementation: for large stacks
design
Does not At
0=empty 0=full
shift! ‘Push’
Combina-
torial Write Ptr both
circuits ptrs
0 empty
45 1
2
3
0 count
Sequential
1 up
circuits empty
23
Read Ptr
2 empty
12
17 At ‘Pop’
FSMD
design 0
1
2
3 both
3 empty
52
ptrs
VHDL
count
1. Reset down
2. Push 45
3. Push 23
4. Push 12
5. Pop -> 12
6. Push 17
3/198 7. Push 52
©
R.Lauwereins
Imec 2001
LIFO queue - stack
Note: 10
SET Full/
Digital empty
design
R Up/down
U/D’ counter 1
Combina-
torial E Write ptr 2-to-1
circuits
MUX
S Up/down
Sequential U/D’ counter 0
circuits
E Read ptr S
FSMD Reset’
design
Push/
VHDL Pop’
Enable A 8
1Kx8 Data
CS RAM D in/out
R/W’
Watch timing of the enable: when RAM is not clocked
be careful not to read/write twice since the counters
3/199 count further
©
R.Lauwereins
Imec 2001
Sequential Circuits
Digital
design
Combina-
torial
circuits
circuits
Sequential circuits
circuits
FSMD
design
 Registers
 Shift registers
VHDL
 Counters
 Register files
 FIFO queue
3/200
©
R.Lauwereins
Imec 2001
FIFO queue
Digital
design
1. Reset
Top empty
45
23
12
57
Combina- 2. Write 45
torial
circuits Top-1 empty
45
23
12 3. Write 23
4. Write 12
Top-2 empty
45
23
Sequential 5. Read -> 45
circuits
Top-3 empty 6. Write 57
FSMD
design Top-4 empty
Top-5 empty
VHDL
Top-6 empty
Top-7 empty
3/201
©
R.Lauwereins
Imec 2001
FIFO queue
In0
Digital
Reset IL
design
Enable O7 O0
Combina- 7
torial
circuits In7 Uit0
0 S2..0
Sequential Reset IL
circuits Read
pointer Enable O7 O0
FSMD 7
design
Uit7
0 S2..0
VHDL
Set
Up/down’
Enable Q3..0
Reset’
Read/ Empty
write’
Enable Full
3/202
©
R.Lauwereins
Imec 2001
FIFO queue
Digital
Alternative implementation: for large FIFO’s
design Only write
Does not Wrap-around pointer
Combina- shift!
torial Write Ptr incr. at
circuits write
0 empty
45
16 2
3
0
1
Sequential
circuits 1 empty
23
Read Ptr
2 empty
12
FSMD
0
1 Only read
design
3 empty
57 pointer
VHDL
incr. at
read
1. Reset
2. Write 45
Read and write
3. Write 23
pointer equal:
4. Write 12 empty or full
5. Read -> 45
6. Write 57
3/203 7. Write 16
©
R.Lauwereins
Imec 2001
FIFO queue
Digital
• Previous implementation indicates empty/full
design but does not distinguish between both
Combina- • Solution:
torial
circuits
 assume queue depth equals 2 n
 read and write pointer are hence n-bit up-counters
Sequential
circuits
 select however an (n+1)-bit up-counter:
n-LSB of read and write equal: empty/full
FSMD
design MSB equal: empty
VHDL
MSB different: full
apply only the n-LSB as address for RAM-
queue
• For the stack, we also did not differentiate
between empty and full; how can it be solved
there?
3/204
©
R.Lauwereins
Imec 2001
FIFO queue
MSB Full
Digital
design
10-LSB =? Empty
Combina-
torial
circuits R 11-bit Up
E counter 0
Sequential Write ptr 2-to-1
circuits
MUX
R 11-bit Up
FSMD
design E counter 1
Read ptr S
VHDL
Reset’
Read/ 10
Write’
Enable A 8
1Kx8 Data
CS RAM D in/out
R/W’
3/205

DEPpart 3

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DEPpart 3

Uploaded by

Copyright:

Available Formats

©

DQ delay when C high: L-to-H delay: 2.4+1.4+1.4=5.2

FSMD Analogously, D may not switch “immediately after” H-to-L

The master clocks at the falling clock edge

• The flip-flop as building block

• The flip-flop as building block

Digital Symbol Characteristic table

Negative level triggered Q Q(next) S R

• The flip-flop as building block

Digital Symbol Characteristic table

• The flip-flop as building block

Digital Symbol Characteristic table

• The flip-flop as building block

Digital Symbol Characteristic table

• The flip-flop as building block

CE=0 Count=3 Count=2 CE=0

1. We are in state “Count=0”

CE=0 Q1Q0=11 Q1Q0=10 CE=0

Present state Next state

CE=0 Count=3 Count=2 CE=0

Digital • Be extremely careful about timing issues!!

CE=0 Q1Q0=11 Q1Q0=10 CE=0

Present state Next state Outputs Y is

CE=0/Y=0 Count=3 Count=2 CE=0/Y=0

1. We are in state “Count=2”

Digital • Be extremely careful about timing issues!! Assume

CE=0/Y=0 Q1Q0=11 Q1Q0=10 CE=0/Y=0

Present state Next state/Outputs Y does

Clock Next State S* Current

u2 d2 d2/0 u0/1 d1/0

PRESENT NEXT STATE / OUTPUT

CD=11 This could have been constructed from the begin

s2 s5 s2/0 s4/1 s2/1

s2 s5 s2/0 s4/1 s2/1

PRESENT NEXT STATE / OUTPUT

Digital • n states require at least log2n flip-flops.

3/99 Straightforward Minimum-bit-change

PRESENT NEXT STATE / OUTPUT

FSMD (time-to-market, e.g. exam…)

PRESENT NEXT STATE / OUTPUT

combinatorial logic: D flip-flop

combinatorial logic: D flip-flop

combinatorial logic: T flip-flop

combinatorial logic: T flip-flop

combinatorial logic: SR flip-flop

PRESENT NEXT STATE / OUTPUT

combinatorial logic: SR flip-flop

combinatorial logic: SR flip-flop

combinatorial logic: SR flip-flop

combinatorial logic: SR flip-flop

combinatorial logic: JK flip-flop

PRESENT NEXT STATE / OUTPUT

combinatorial logic: JK flip-flop

combinatorial logic: JK flip-flop

combinatorial logic: JK flip-flop

• Delay of critical path (assume zero

Elimination of critical races

Hazard free combinatorial design

Avoidance of input skew

Elimination of critical races

Hazard free combinatorial design

Avoidance of input skew

Elimination of critical races