Digital Fundamentals

with PLD Programming

Floyd

Chapter 9

Floyd, Digital Fundamentals, 10th ed

Upper
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NJ 07458. All Rights Reserved

Summary
Latches (biestables)
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch
responds to active-HIGH inputs; with NAND gates, it responds to
active-LOW inputs.
S

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
Funcionamiento S-R
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (0). To SET the latch
(Q = 1), a momentary HIGH signal
is applied to the S input while the R
remains LOW.
To RESET the latch (Q = 0), a
momentary HIGH signal is
applied to the R input while the S
remains LOW.

0 R

10

01
0 S
0 R

01

01
0 S

Floyd, Digital Fundamentals, 10th ed

Latch
initially
RESET
Q

Latch
initially
SET
Q

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Summary
Funcionamiento S-R
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (1). To SET the latch
(Q = 1), a momentary LOW signal
is applied to the S input while the R
remains HIGH.

1 S

To RESET the latch a

momentary LOW is applied to the
R input while S is HIGH.

1 S

Never apply an active set and

reset at the same time (invalid).
Floyd, Digital Fundamentals, 10th ed

01

01
1 R
01

Latch
initially
RESET
Q

Latch
initially
01 SET
1R

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Smbolos lgicos

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Tabla de verdad del S-R

Funcionamiento de un S-R

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Otra forma de expresar la tabla de verdad del S-R

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Tabla de verdad del S-R

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Latch S-R con puerta (entrada de habilitacin)

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Tabla de verdad

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Latch D
Memoriza el bit en la entrada D: Q ser igual a D cuando
la entrada EN est activa.

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Otra forma de expresar la tabla de verdad

Funcionamiento en el tiempo

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Summary
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked (sincronizado) device,
in which only the clock edge determines when a new
bit is entered.
The active edge can be positive or negative.
D

Dynamic
input
indicator

Floyd, Digital Fundamentals, 10th ed

C
Q

(a) Positive edge-triggered

Q
(b) Negative edge-triggered

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Flip flops sincronizados por

flanco de subida y de bajada

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Funcionamiento de un flip-flop S-R sincronizado por

flanco de subida

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Un flip-flop D sincronizado por flanco de subida

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Summary
Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In
addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs

Floyd, Digital Fundamentals, 10th ed

0
0
1
1

Outputs

CLK

Comments

0
1
0

Q0
0
1

Q0
1
0

Q0

Q0

No change
RESET
SET
Toggle

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Funcionamiento
J

Q
CLK

Notice that the outputs change on the leading edge of the clock.

Set

Toggle

Set

Latch

CLK

J
K
Q
Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Funcionamiento del flip-flop J-K sincronizado por

flanco de bajada

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Summary
Entradas asncronas
Synchronous inputs are transferred in the triggering edge
of the clock (for example the D or J-K inputs). Most flipflops have other inputs that are asynchronous, meaning
they affect the output independent of the clock.
PRE

Two such inputs are normally labeled

preset (PRE) and clear (CLR). These
inputs are usually active LOW. A J-K
flip flop with active LOW preset and
CLR is shown.

J
CLK

CLR
Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

PRE

Funcionamiento

J
CLK

CLR

Set

Toggle

Set

Reset

Toggle

Latch

CLK
J
K
PRE

Set
Reset

CLR

Q
Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Resumen de los flips-flops

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Summary
Flip-flop Characteristics
The propagation delay time is the time required for an
input to cause a change in the output. It is measured from the
50% levels.

Figure 8--35 Propagation delays, clock to output.

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Retrasos de propagacin de las entradas asncronas

Figure 8--36 Propagation delays, preset input to output and clear input to output.

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Summary
Flip-flop Characteristics
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
Setup time is the minimum
time for the data to be present
before the clock.

D
CLK

Set-up time, ts

Hold time is the minimum time

for the data to remain after the
clock.

D
CLK

Hold time, tH
Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Set-up time

Figure 8--37 Set-up time (ts). The logic level must be present on the D input for a time
equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.

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Hold time

Figure 8--38 Hold time (th). The logic level must remain on the D input for a time equal to
or greater than th after the triggering edge of the clock pulse for reliable data entry.

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Summary
Output
lines
Q0

Flip-flop Applications
D

Principal flip-flop applications are for

temporary data storage, as frequency
dividers, and in counters (which are
covered in detail in Chapter 10).

Q1

D
C

Typically, for data storage applications,

a group of flip-flops are connected to
parallel data lines and clocked together.
Data is stored until the next clock pulse.

Q2

D
C

Parallel data
input lines

Q3

Clock

Clear

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Figure 8--39 Example of flip-flops

used in a basic register for parallel
data storage.

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Summary
Flip-flop Applications
For frequency division, it is simple to use a flip-flop in
the toggle mode or to chain a series of toggle flip flops to
continue to divide by two.
One flip-flop will divide fin by 2, two flip-flops will
divide fin by 4 (and so on). A side benefit of frequency
division is that the output has an exact 50% duty cycle.

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of
CLK.

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Figure 8--41 Example of two J-K flip-flops used to divide the clock frequency by 4. QA is
one-half and QB is one-fourth the frequency of CLK.

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Aplicacin: generar una cuenta

Figure 8--44 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01,
10, 11) are shown.
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Ejemplo: determinar la cuenta generada

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Selected Key Terms

Latch A bistable digital circuit used for storing a bit.
Bistable Having two stable states. Latches and flip-flops are
bistable multivibrators.
Clock A triggering input of a flip-flop.
D flip-flop A type of bistable multivibrator in which the output
assumes the state of the D input on the triggering
edge of a clock pulse.
J-K flip-flop A type of flip-flop that can operate in the SET,
RESET, no-change, and toggle modes.
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Selected Key Terms

Propagation The interval of time required after an input signal
delay time has been applied for the resulting output signal to
change.
Set-up time The time interval required for the input levels to be
on a digital circuit.
Hold time The time interval required for the input levels to
remain steady to a flip-flop after the triggering
edge in order to reliably activate the device.
Timer A circuit that can be used as a one-shot or as an
oscillator.
Registered A CPLD macrocell output configuration where the
output comes from a flip-flop.
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1. The output of a D latch will not change if

a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above

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2. The D flip-flop shown will

D

a. set on the next clock pulse

b. reset on the next clock pulse
c. latch on the next clock pulse

CLK

CLK

d. toggle on the next clock pulse

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3. For the J-K flip-flop shown, the number of inputs that

are asynchronous is
PRE

a. 1
b. 2

c. 3

CLK

d. 4

CLR

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4. Assume the output is initially HIGH on a leading edge

triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
b. 2
c. 3
d. 4

CLK
J
K

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5. The time interval illustrated is called

a. tPHL
b. tPLH

50% point on triggering edge

CLK

c. set-up time
d. hold time

50% point on LOW-toHIGH transition of Q

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6. The time interval illustrated is called

a. tPHL
b. tPLH
c. set-up time
d. hold time

D
CLK

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7. The application illustrated is a

a. astable multivibrator

HIGH

HIGH

b. data storage device

QA

c. frequency multiplier

fin

QB

CLK

fout

CLK

d. frequency divider
K

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Output
lines
Q0

8. The application illustrated is a

a. astable multivibrator

Q1

b. data storage device

c. frequency multiplier

Q2

d. frequency divider

Parallel data
input lines

Q3

Clock

Clear

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9. A retriggerable one-shot with an active HIGH output has

a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH

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Answers:
1. b

6. d

2. d

7. d

3. b

8. b

4. c

9. d

5. b

10. a

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