Paper No. T.12-1.1, pp.

1-5

The 6th PSU-UNS International Conference on Engineering and

Technology (ICET-2013), Novi Sad, Serbia, May 15-17, 2013
University of Novi Sad, Faculty of Technical Sciences

PLL SYNCHRONIZATION IN GRIDCONNECTED CONVERTERS

Evgenije Adzic*, Vlado Porobic, Boris Dumnic, Nikola Celanovic, Vladimir Katic
University of Novi Sad, Faculty of Technical Sciences, Novi Sad, Serbia
*Authors to correspondence should be addressed via email: evgenije@uns.ac.rs

Abstract: Renewable power generation systems utilizing

power electronics converters rely on accurate grid phase
angle determination in order to succesfully close grid
voltage vector oriented control loop usual for this kind of
application. Phase-locked loop (PLL) is the most
common method for determination of the grid voltage
phase angle and frequency. However, there are still
serious limitations of reported PLL algorithms in real
grid voltage conditions (unbalance and distortion). This
paper presents proper PLL parameter selection method
for real grid voltage conditions. The proposed method is
detailed tested and evaluated using real-time hardwarein-the-loop emulator setup dedicated for power
electronics circuits emulation.
Key Words: Power Electronics / Hardware-in-theLoop / Grid-Connected Converters / Synchronization /
Phase-Locked Loop

The quality of the grid synchronization, in addition to

the current control structure, is a key factor which
determines the complete control structure quality. Error
in the phase angle estimation can lead to the significant
errors in the imposed converter output voltage, and thus
the error between the reference and injected power
(current) into the grid [2]. So, it is mandatory to carefully
consider synchronization unit design and test it in
various voltage conditions relevant to the real utility grid.
In the literature related to the grid synchronization,
different methods can be found which are applied in
practice for grid-connected converters [2-4]. The most
common method used today is the phase-locked loop
(PLL) implemented in the dq-synchronous rotating
reference frame, shown in the Fig. 1.

1. INTRODUCTION
The world electrical energy consumption is
continuously
rising. There is significant demand
increase for the electrical power capacities and thier
efficiency. Large centrally controlled conventional
power sources connected to the transmission system are
complemented or replaced with greater number of small
renewable energy sources directly connected to the local
distribution grid. Power electronics represents enabling
technology for this kind of transition [1]. Power
electronics converters serve as an efficient interface
between primary energy sources (wind-turbine
generators, photovoltaic panels, fuel cells) and the utility
grid, with the task to adapt the produced power to the
numerous grid requirements. All efficient distributed
power generation systems use some of the many gridconnected converter (GCC) topologies.
Within grid-connected converter control algorithm it
is necessary to accurately and precisely determine the
grid voltage phase angle () in order to achieve
independent control of active and reactive power flow
between the converter input side and the grid. This task
is performed by grid synchronization unit [2].

Fig. 1. dq-PLL synchronization system block diagram.

It contains a filter in form of proportional-integral
(PI) controller, that determines PLL dynamics.
Especially, it is influenced by presence of unbalance and
distortion in the grid voltage. Therefore, filter bandwidth
is a compromise between filtering undesirable harmonics
that occur in the PLL system due to the measured voltage
distortion, and fast response time necessary for tracking
voltage during a frequency changes or voltage sags in the
grid [5,6].
This paper show detailed test and evaluation of dqPLL synchronization algorithm in distorted grid voltage
conditions: harmonic distortion, unblance, and
measurment offset. It gives comparative study of

obtained results using real-time hardware-in-the-loop

setup for the case of unadjusted and adjusted PLL filter
parameters, and based on obtained results propose proper
filter design.

steady-state the error signal would be zero for the abrupt

changes in the voltage phase angle, but also for abrupt
changes of the voltage frequency (ramp input), which is
expected due to a weak distribution grid where failures
are common. Near the steady-state, where small
difference between the real and estimated phase angle
exist, error signal can be linearized in order to obtain a
suitable model for PLL filter design:

2. PLL OPERATION
A block diagram of the conventional PLL designed in
dq-synchronous rotating reference frame is shown in
Fig.1. PLL operation can be explained through the
following steps:
Three-phase grid voltages uag, ubg, and ucg are
measured. For the first analysis, a balanced three-phase
set of voltages is assumed, where represent actual
phase angle of grid voltage in phase a:

(7)
PI controller (filter) calculates the grid voltage
angular frequency change , which in the continuous
Laplace domain can be represented with following:

s K Ppll Ipll es
s

uag U g cos

ubg U g cos

ucg U g cos

2
3
2

1
uag
2 u
bg
3
ucg

1
s

s s

(2)

3. EFFECTS OF DISTORTED GRID

In practice, distribution grid voltage has not a pure
sinusoidal waveform but it is distorted by various factors
such as load nonlinearities and measurement devices [5].
Resulted three-phase voltage waveforms are unbalanced
and with harmonics. The possible signal offset is often
introduced by the measurement and conversion circuits.
The unbalanced set of three-phase voltages can be
expressed as:

(3)

After applying transformation, grid voltage dqcomponents are:

sin

udg U g cos
uqg U g

uag U g cos

(4)

ubg U g 1 a cos

ucg U g 1 b cos

In PLL steady-state (locked state: = ^), grid

voltage component udg is equal to the amplitude Ug, so it
could be used for grid voltage component uqg
normalization to avoid PLL closed-loop gain loss in the
case of grid voltage sags [8]:

*
qg

uqg
udg

(10)

where a and b are constants indicating unbalance

level. After applying Eqs. (2-5) to find grid voltage dqcomponents and applying Eq. (6) it could be shown that
error caused by unbalanced grid is equal to:

(5)

Error signal e is formed by subtracting the reference

signal uqgref and normalized grid voltage component uqg*,
which is input of PLL filter in proportional-integral (PI)
form. Setting the reference uqgref to 0 is responsible for
tracking the phase angle of grid phase voltage uag. PI
controller will act to reduce the error e to zero:

(9)

The estimated phase angle ^ is used to

calculate grid voltage dq-components, until uqg becomes
zero and udg becomes constant equal to the grid voltage
amplitude Ug, and finally the difference between actual
phase angle of the grid voltage and estimated phase
angle ^ becomes zero.

-voltage components are transformed to dqsynchronous rotating reference frame using Park
transformation with estimated phase angle ^ from the
PLL output. dq-grid voltage components are obtained:

udg cos sin ug

u
qg sin cos ug

(8)

Filter output is added to the reference angular

frequency ref, which is set to the value of the grid
angular frequency (eg. 250 Hz). This result with a
value of estimated grid angular frequency ^.
Integrating the estimated angular frequency ^ in
time, estimated grid voltage phase angle is obtained:

(1)

Measured phase voltages are transformed to a stationary reference frame using Clarke transformation
and obtaining ug and ug:

ug 2 1
u
g 3 0

e sin

ab
ba
sin 2
cos 2
6
2 3

(11)

One can note that second harmonic component would

propagate through the PLL system if three-phase grid
voltage is unbalanced.
Another significant effect which influences PLL
operation is presence of grid voltage harmonics. A
consequence of numerous nonlinear loads in the
distribution grid is distorted grid voltage waveform,

*
e 0 uqg
0 sin 0 (6)

which would lead to equalization of estimated phase

angle and actual grid voltage phase angle in steady-state.
PI controller is selected as the filter type, because in the

which is usually flattened in the region of its maximal

values, and contains dominant 5th and 7th harmonic
components. Therefore, distribution grid voltage with the
dominant harmonics can be represented as follows:

uag U g cos U g 5 cos 5 U g 7 cos 7

2
2

ubg U g cos
U g 5 cos 5

3
3

(12
U g 7 cos 7

(13)

uag U g cos U a 0

U b0

U c0

(14)

Therefore, the error caused by the voltage offset can

be shown as:
(15)
e Edq 0 cos 0
where:

Edq 0

U 2 0 U 2 0
Ug

0 arctg

2
1
1
U 0 U a 0 U b 0 U c 0
3
3
3
1
1
U 0
U b0
U c0
3
3

K Ppll
2 K Ipll

bw n 2 2 1 4 4 2 2

One can note that sixth harmonic component would

propagate through the PLL system if three-phase grid
voltage is distorted with fifth and seventh harmonics.
The voltage offset is often produced by the signal
measurement and conversion circuits. The measured grid
voltages with the offset can be expressed as:

ubg U g cos
3

ucg U g cos
3

where is relative damping factor, and n is system

natural frequency. Values of and n characterize
system performance in the transient-state in the time
domain. From the transfer function form, one could
conclude that the desired character of the PLL response
is achieved by adjusting the parameters of the PI
controller [8]:
(18)

For second order systems, like given Gc(s) (Eq. 17),

bandwidth frequency bw is equal to:

By applying Eqs. (2-6) it could be shown that PLL

error which occurs in grid voltage dq-components,
estimated phase angle and frequency due to the 5th and
7th harmonic can be represented with:

U g5 U g7
sin 6
Ug

sK Ppll K Ipll
s 2n n2
(17

s 2 sK Ppll K Ipll s 2 s 2n n2

n K Ipll

2
2

ucg U g cos
U g 7 cos 7

3
3

U g 7 cos 7

Gc s

U 0
U0
(16)

It is shown in this result that the error caused by the

offset has the same frequency component with that of the
grid voltage (fundamental harmonic).
4. PLL FILTER DESIGN
Based on section 2, three-phase PLL model in
continuous Laplace s-domain can be extracted. The
transfer function of the closed loop normalized dq-PLL
is of second order with one zero and could be rewritten
in general form as:

(19)

In grid-connected converter application it is desirable

that PLL response is without larger overshoot and
oscillations, in order to avoid oscillations of active and
reactive power between the converter and the grid [4, 7].
For aperiodical response =1, and based on Eqs. (18-19)
it yields that PLL parameters should be selected
according to following:

K Ppll 2bw K Ipll

2
bw

(20)

It can be concluded that very slow dynamic of the

PLL filter, determined by its parameters KPpll and KIpll,
would give filtered and relatively stable estimated phase
angle and frequency, but with longer synchronization
time. On the other hand, PLL filter with highly dynamic
filter would give a phase angle that follows the rapid
changes in voltage (necessary in grid failures
conditions), but the grid distortion would reflect in
erroneous estimated phase angle (section 3). This
indicates how important is to design PLL properly,
considering real grid voltage conditions.
5. HARDWARE-IN-THE-LOOP SETUP
In this paper, experimental results have been obtained
using ultra-low-latency high-fidelity hardware-in-theloop (HIL) emulator which provides enough
computational power to execute power electronics circuit
models in only 1-s time steps [9]. HIL environment is
distinguished from the traditional approach where
expensive hardware test equipment like ac power sources
for grid simulation are used. This system simultaneously
eliminates all safety and cost issues with regard to the
laboratory test set. In parallel, it allows to focus on the
evaluation of the software-based functionalities (like
PLL performance in this case), which are provided by
converters controller and which is directly interfaced
with the HIL emulator through its digital and analog
inputs and outputs.
The model of the PWM inverter, dc link and
electrical grid are simulated using the Typhoon HIL600
(Fig. 1, mark 1), while the PLL and grid-connected
converter control algorithm with a sampling loop
frequency of 4 kHz is implemented using a real control
platform based on the Texas Instruments TMS320F2808
digital signal processor (Fig. 1, mark 2).

fundamental, second and sixth harmonic components are

propagated through the PLL producing the oscillating
estimated grid voltage frequency and angle information.
These harmonic components would influence the whole
control algorithm of grid-connected converter which
would result in more distorted currents injected into the
grid. Fig. 5 shows the same recorded controller data in
the case when PLL bandwith was carefully selected and
set to value of 3 Hz. Even in highly distorted grid voltage
conditions, undesirable harmonic components in
estimated frequency and angle are properly attenuatted.

Fig. 2. HIL testing environment.

Corresponding software tools, Schematic Editor (Fig.
1, mark 3) and Script Editor (Fig. 1, mark 4), were used
to define schematic of the emulated grid-connected
converter and to set the parameters of the circuit. Script
Editor tool allows writing test scripts in Python
programming language, for defining different grid
conditions for developed PLL performance evaluation.
Additionally, Script Editor have been used for recording,
plotting and analyzing the results obtained from the HIL
and the DSP controller.

Fig. 4. PLL response with unadjusted filter.

6. EXPERIMENTAL RESULTS
6.1. PLL steady-state response
Fig. 5. PLL response with adjusted/proposed filter.

Fig. 3 shows grid voltage waveforms setup in the HIL

model. Fundamental harmonic with effective value 230
V, is distorted with 5th and 7th harmonics, each with
amplitude 3.5% of fundamental component. In that way,
total harmonic distortion (THD) of the simulated grid
voltage is 5% which represents the limit in the
distribution grid. Phase shift of the harmonics is set in
order to have typical waveform of the grid voltage at
which power converter is connected. Unbalance higher
then 5% is introduced in the voltage waveform, by
setting the constants indicating unbalance level a = 0.05
and b = -0.05. Additional offset of 5% is also introduced
at HIL analog outputs which are interfaced with
controller analog inputs measuring grid phase voltages.

6.2. PLL dynamic response

This section gives PLL dynamic response in the case
of grid voltage phase jumps which can occur in the grid
due to the voltages sags. Sudden voltage phase jump
represents disturbance for the PLL system which can be
used for dynamic performance evaluation. In previous
section we have concluded that PLL bandwidth have to
be reduced in order to properly reject possible harmonics
in the system due to the voltage distortion. This will give
slower dynamic response which can be disastreous in the
case of voltage sags, where synchronization also have to
be maintained. This indicates importance of the PLL
dynamic response evaluation.
Fig. 6 gives simulated grid voltage phase jump of 60
degrees setup in the HIL model. Figs. 7 and 8 shows PLL
dynamic response for two different filter bandwidths
considered before, 50 Hz and 3 Hz.

Fig. 3. Simulated distorted grid voltage conditions.

In relevant literature usually is proposed that PLL
filter response settling time have to be set around 20 ms,
for grid requency of 50 Hz [4,7]. Results given in Fig. 4
confirm that distorted grid voltage conditions are
unjustly neglected in that case. As expected (Eqs. 10-16),

Fig. 6. Simulated grid voltage phase jump.

7. CONCLUSION
Proposed PLL design method is especially suitable
for grid-connected converter control application in
highly unbalanced and distorted grid voltage conditions,
because it is not subject to their influence. It is shown
that PLL filter has to be properly designed in order to
reject possible harmonic components in estimated grid
frequency and angle information, and in the same time to
achieve enough fast dynamic response in the case of
voltage phase jumps during grid voltage sags. HIL
development and testing environment has been proven as
irreplaceable testing tool for grid-connected converter
applications, where grid voltage waveforms could be
defined arbitrarily for the purpose of controller
performance evaluation.

Fig.7.PLL dynamic response for filter bandwidth 50Hz.

8. ACKNOWLEDGMENT
This work was supported by Ministry of Education
and Science of the Republic Serbia within project III
42004.

Fig. 8. PLL dynamic response for filter bandwidth 3Hz.

Frequency (g) response time in the case of filter
bandwidth 50 Hz is 8 ms, and in the case of bandwidth 3
Hz it is equal to 50 ms. Undesirable oscillating estimated
frequency, even in the case of sinusoidal grid voltages
(without distortion), is evident with filter bandwidth
settings 50 Hz. With filter setting 3 Hz, one can note
from Fig. 8 that grid voltage q-component is regulated to
reference zero value only in a 2.5 cycles (for 50 Hz grid
frequency) and more stable frequency response in
steady-state. Settling time of 50 ms represents enough
fast response time to maintain synchronization with the
grid of 50 HZ frequency (period 20 ms), and in the same
time it assures constant and accurate estimated grid
frequency and angle information in the case of highly
distorted grid.
In practice, real phase jumps during the grid voltage
sags depends on grid reactance and resistance ratio at the
point of common coupling, and are less then presented
600 [10]. Used HIL environment and its Script Editor
tool allowed easy automated testing concept where PLL
dynamic response was evaluated for different grid
voltage phase jumps. Final results are summarized in the
Table I. In Table I, Tset represents frequency settling
time, is maximal frequency change relative to
reference frequency (50 Hz = 0.5 p.u.), and udg and uqg
are maximal grid voltage dq-components changes
relative to grid voltage amplitude Ug (325 V = 0.44 p.u.).
Table 1. PLL dynamic response parameters for different
grid voltage phase jumps and filter bandwidth 3 Hz.
Phase jump
300
450
600
150
Parameter
Tset
9 ms
29 ms
36 ms
50 ms

2.5%
6.0%
8.0%
10.3%
udg
2.3%
11.3%
22.7%
43.7%
uqg
28.8%
50.0%
63.6%
81.8%

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