COMPUTER ORGANIZATION.

1. Instruction format contains Op code , address field, Mode field .

2. Op code tells about the operation to be performed.
3. Address field

Designates memory address or process register.

4. Mode field specifies the way the operand or effective address is determined.
5. Instruction cycle contains fetch, encoding , reading the effective address and execute Operatons.
6. Three address instruction
contains Op Code+ Address1 + Address2 + Address3.
7. Two address instruction contains OP code + Address1+ Address2.
8. One address Instruction contains OP code + Address
9. Zero address Instruction contains OP code only.
10. Single accumulator organization uses One address instruction.
11. General Register organization uses Three & Two address instruction.
12. Stack organization uses Zero and One address instruction.
13. Operands are specified implicitely in the definition of instruction in implied addressing Mode.
14. Operand is specified in the instruction and instruction has operand rather than address in
immediate addressing .
15. Operands are in the registers in register addressing mode .
16. Operand is in the memory and the address of the operand is specified in the instruction in
direct addressing mode .
17. Data is stored in memory location and memory location is stored in another register which is
given in the instruction in Indirect addressing mode .
18. In Relative addressing effective address is equal to PC+ Address part of the next
instruction.
19. Relative addressing

uses Branch Type instructions.

20. Base Register addressing uses Relocation of programs in the Memory.

21. Implicit addressing mode example is CMA.
22. Auto increment or decrement mode is used in Branch Type instructions .
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Immediate addressing uses constants.

Indexed addressing uses Pointers.
Auto decrement addressing uses Loops.
Direct addressing uses Local Variables.
Indirect addressing
uses Passing array as parameters.
Indexed addressing uses Array implementation.
Base Register addressing
uses Writing relocatable code.

30. Relative addressing uses Locality of reference.

31. Displacement addressing modes are Relative addressing, Indexed addressing and Base addressing.
32. Mode bit is 0 for direct addressing and 1 for Indirect addressing.
33. Addressing mode used in the instruction PUSH B is Register addressing.
34. STA address is example of Direct address mode.
35. Linker integrates an object code with other required object code.
36. Machine code representing the binary value generated after converting assembly language
instructions to their equivalent machine code instructions.
37. Sign flag specifies the sign of a value computed either by arithmetic or logical instruction.
38. XCHG instruction is used to swap the data of register pair specified by the instruction.
39 Loader copies the executable file into the memory. (linker / loader/ both/ none)
40. data transfer instructions moves data from one memory location to another.
41.In Relative -mode operand is provided is an offset but not the actual address.
42. Instructions are said to be orthogonal if they over lap or perform same function.
43. PSW means Processor status word.
44. Assembly language instructions are Data transfer instructions, Data operation instructions and
Program control instructions .
45. Data Transfer instruction for memory & processor , process register and I/O.
46. Data Operation Instruction for Arithmetic , shift , logical operations.
47. Program control instructions are Jump , Branch , call and return.
48. PSW contains
operation

Status bit of last ALU operation, interrupt information and mode of CPU

49. CPU Operates in Two modes namely Separator mode and user mode.
50. CPU user mode operation operations are CISC and RISC.
51. CISC means Complex instruction set computer.
52. RISC means reduced instruction set computer .
53. Large no of instructions about 100 to 250 , large number of addressing modes 5 to 20 , and
variable length instruction formats are the characteristics of CISC .
54. Few instructions, relatively few addressing modes , Fixed length and easily decodable instruction
set , are the characteristics of RISC .

55. Control logic is implemented through gates , Flip flops , decoders etc and fast in operation is
Hard wired control organization.
56. Microprogarms are stored in control memory and uses micro instructions in Microprogrammed
control.
57. RISC uses Hard wired control organization.
58. In hard wired control for the changes design is to be changed.
59. In Micro programmed control changes can be done by updating microprogram control memory .
60. In static Microprogram control ROM is used for control memory.
61. In Dynamic Microprogram control RAM is used for control memory.
62 . Encoding scheme in which each control signal is represented by a bit in micro instruction is
called Horizontal microprogramming .
63. If there are 42 control signals no of bits required in Horizontal micro programming are 42.
64. Encoding scheme in which compact codes are used to specify only a small number of functions
in each micro instruction is vertical Microprogramming.
65. If there are 42 control signals then no of bits in control word in vertical programming is
about 14.
66. Horizontal microprogramming has Better performance over vertical Microprogramming.
67. MAR and MDR connected to internal bus.
68. MDR is also connected to memory bus and it acts as a bridge between Internal bus and
memory bus .
69. Sequence of operation during fetch operation PCMARmemory MDR IR
70. data path performs all required operations related to ALU , registers and internal bus .
71. Control unit determines the sequence of operations within data path and supervises each
instructions in the CPU.
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Internal Interrupt occurs due to illegal or erroneous use of information.

External Interrupt occurs due to I/O devices and Timing devices.
Software Interrupt Initiated by executing on instructions.
Interrupt that can be temporarily ignored is Maskable Interrupt
Stack over flow is Internal interrupt.
Timer is External interrupt.
Invalid OP code is Machine check interrupt.
Superior call is Soft ware interrupt.
A digital computer has a common bus system for 16 registers of 32 bit each. The bus is
constructed with the MUX. Then no of selection lines in each MUX is 4and No of MUX in
the bus are 32.
80. Shift registers used for Prallel to serial conversion.
81. Multiplexer used for Many to one switch.

82. Decoder is used for generation of memory chip select.

83. WMFC means Wait for memory function Completed .
84. A computer has 128 operation codes and 512 K addresses . No of bits required for single
address instructions are 25 and Two address instructions are 43.
85. Multiplication is not a Microoperation .
86. Pipe line instructions are fetch , decode , execute , write .
87. Pipelining Increases CPU instruction throughput by executing multiple instructions in parallel.
Does not reduce the execution time of an individual instruction. It does not reduce the
instruction latency.
88. Speed up factor by the use of Pipe lining tn/ tp.
89. Difficulties in Instruction pipeline are Resource conflicts , Data dependency conflicts, Branch
difficulties..
90. Any condition that can cause a pipe line to stall is called Hazard .
91. Pipe line hazards are Data hazards, control hazards and structural hazards.
92. In a 5 staged pipe line stage takes 1,2,3,2,1 units of time . Then the through put is 1/3.
93. Instruction pipe line is implemented by FIFO buffer.
94. Speed up factor for n stage pipe line is n .
95. A pipe line is having speed up factor 10 and operating at efficiency 80%. What will be the
number of stages in pipe line is 12. 5
96. Throughput means No of outcomes produced per unit time .
97. IO Interface for Transmitting information between internal storage and external peripheral
device..
98. Asynchronous data transfer modes are Strobe and Handshaking .
99. In synchronous data transfer Global or shared clock is provided between sender and receiver.
100. In Programmed I/O Each data item is transferred by an instruction in the program. CPU stays
in a program loop until I/O indicated that is ready for data transfer.It is a time consuming .
101. Interrupt- initiated I/O Removes draw backs of programmed I/O, CPU can proceed to execute
another program during interrupts.
102. In priority interrupt identification of highest priority is called Polling .
103. Polling is some times known as busy waiting .
104.The ability to temporarily halt the CPU and use this time to send the information on buses is
called cycle stealing .
105. I/O bus contains Data lines , address lines , control lines .
106.Address lines selects the peripherals.
107.Control lines sends the commands to interfaces .
108.DMA means Direct memory access.
109.During DMA transfer CPU is idle and has no control on memory buses.DMA manages the data
transfer between I/O and memory.
110.DMA I/O is Disk.
111. Cache is High speed DMA.
112.Condition code register is ALU.
113. DRAM is used in Cache memory.
114. SRAM is used in main memory.
115.No of address lines and data lines in 128 x 8 RAM are 2, 8.
116.No of 32 K x 1 RAM chips required for memory capacity 256 KB is 64.
117. Cache memory is based on Locality of reference .
118. 90/ 10 rules specifies Spatial locality.
119.As per 90 / 10 rule computer program spends 90% time in 10% of its code .
120. Hit ratio is equal to No of Hits / ( No of Hits + No of Miss ).
121. Consider a memory system with main memory access time is 1000 ns and cache memory
access time is 100 ns. Hit ratio is 0.9 . Average access time of the system is 200 ns.
122.Suppose a cache memory is 10 times faster than main memory. Hit ratio of cache is 90% .
How much speed up does the system gains by using cache memory is 5.7.

123.Method of updating main memory as soon as a word is removed from the cache memory is
Write back .
124.Average time required to reach a storage location in memory and obtain its content is called
Access time.
125. Write through technique is used for updating data in cache memory
126.In direct mapping main memory size is 32K x 8 and cache memory size is 512 x 8 then Tag
field contains 6 bits and index filed contains 9 bits.
127. Virtual memory Used for large computers . Creates illusion that programmers have large
memory at their disposal even though computer has a relatively small memory .
128.In Virtual memory address used by programmers is Logical address and address in main
memory is Physical address .