pn junction isolation is a method used to electrically isolate electronic components, such

as transistors, on an integrated circuit (IC) by surrounding the components with reverse biased
pn junctions.
By surrounding a transistor, resistor, capacitor or other component on an IC with semiconductor
material which is doped using an opposite species of the substrate dopant, and connecting this
surrounding material to a voltage which reverse-biases the pn junction that forms, it is possible
to create a region which forms an electrically isolated "well" around the component.

Operation[edit]
Assume that the semiconductor wafer is p-type material. Also assume a ring of n-type material is
placed around a transistor, and placed beneath the transistor. If the p-type material within the ntype ring is now connected to the negative terminal of the power supply and the n-type ring is
connected to the positive terminal, the 'holes' in the p-type region are pulled away from the pn
junction, causing the width of the nonconducting depletion region to increase. Similarly, because
the n-type region is connected to the positive terminal, the electrons will also be pulled away from
the junction.
This effectively increases the potential barrier and greatly increases the electrical
resistance against the flow of charge carriers. For this reason there will be no (or minimal)
electric current across the junction.
At the middle of the junction of the pn material, a depletion region is created to stand-off the
reverse voltage. The width of the depletion region grows larger with higher voltage. The electric
field grows as the reverse voltage increases. When the electric field increases beyond a critical
level, the junction breaks down and current begins to flow byavalanche breakdown. Therefore,
care must be taken that circuit voltages do not exceed the breakdown voltage or electrical
isolation ceases.

Once all components are fabricated on a single crystal wafer, they must be electrically isolated
from each other. The problem is not encountered indiscrete circuits, because physically all
components are isolated. There are two methods of isolation in Integrated circuits. They are

P-N junction isolation and

Dielectric isolation
In this post we shall discuss p-n junction isolation.
The method of isolation is most compatible with the IC processing, that is, one extra processing
step, other than required to fabricate IC, is required in isolation. Basically the method involves
producing islands of n- type material surrounded by p-type material. Components are then
fabricated in different n-type islands. The p-type material surrounding the islands is given the
most negative p potential with respect to all parts of the wafer, thus each island and hence

component is electrically isolated from the others by back-to-back diodes. The process step for
p-n junction isolation are explained below:
1. One begins with the p-type substrate on which n-epitaxial layer is grown. If the component to
be fabricated is transistor, then buried layer have to be formed before growing epi-layer. Figure
[a] shows epi-layer growth over substrate without buried layer. The epi-layer is then covered with
SiO2layer.
2. A p-type diffusion is now performed from the surface of the wafer. Since this is to be
performed in selected areas, an isolation mask is prepared prior to this diffusion. A long drive-in
time is required for p-type diffusion so that the acceptor concentration is greater than the epilayer donor concentration throughout the region of epi-layer. Thus the portion of wafer at the
location of isolation diffusion is changed to p-type from the surface of wafer to the substrate. This
is shown in the figure [b]. In other words, the substrate is extended toward the surface and acts
as an isolation wall. This isolation wall causes the formation of p-n junction everywhere around
the n-type islands except at the surface. If the substrate is connected to a voltage which is more
negative than any of the n-region voltages, the diodes shown will be reversed biased and
negligible current will flow. Thus isolation is achieved since any reverse biased p-n junction is
associated with a depletion capacitance; this will have parasitic effect associated with junction,
particularly, at high frequencies.

P-N Junction Isolation

The main disadvantage of p-n junction isolations is as below:
1. The time required for such isolation technique is considerably longer due to diffusion time
taken, which is longer than any of other diffusions.
2. Lateral diffusion is significant due to longer time taken by isolation diffusion, hence
considerable clearance must be used for isolation regions.
3. Isolation diffusion takes an area of the wafer surface which is significant portion of the chip
area. From component density consideration, this area is wasted.
4. P-N junction isolation method introduces significant parasitic capacitance which degrades
circuit performance. The parasitic capacitance is introduced by isolation sidewall and
bottom epitaxial substrate junction.

Several methods have been developed by manufacturers to avoid above problems. All of these
methods circumvent the problems of large area and sidewall capacitance, but they suffer from
the parasitic capacitance introduced by bottom epi-substrate junction. Dielectric isolation avoids
this problem too.
Dielectric isolation, as you all know, is the process of electrically isolating various components in
the IC chip from the substrate and from each other by an insulating layer. Its main use is to
eliminate undesirable parasitic junction capacitance or leakage currents associated with certain
applications.
The various methods of dielectric isolation are:

V-Groove Isolation
V-groove isolation is formed with an n-type substrate, on which an n+ diffusion is performed. As
a next step an SiO2 layer is formed, which is then patterned to form a grid of intersecting lines
opening in the oxide. V-groove isolation process is shown in the figure below.

V-Groove Dielectric Isolation

The wafer formed is then exposed to an orientation dependent etching (ODE) process, where the
patterned layer is used as the etching mask; which results in the formation of V-shaped grooves
as shown in the picture (b). In this the <111> plane sidewalls are at an angle of 54.74 degree
with respect to the <100> top surface of the silicon wafer.
As a result the starting material is <111> oriented crystal, which is normally used for p-n junction
isolation. But for dielectric isolation the starting material is <100> oriental silicon.The etchant
used in the above step etches away the exposed silicon anisotropically, this means that the etch
rate is much faster along the <111> planes than along the <100> crystal planes. This kind of
preferential etching is the key reason behind the formation of V-groove. The depth D of the
isolation groove can be determined in the initial oxide cut width W as

D = W/2
Next step is covering the sidewalls of the V-groove with an oxide layer, therefore the wafer is
subjected to a thermal oxidation process. After completing the oxide layer, a very thick layer of
polycrystalline silicon is deposited as shown in picture (c).
The most critical step in the V-groove isolation process is explained in figure (d). Keeping
polycrystalline surface side of the wafer down, silicon wafers are mounted on the lapping plate. In
the next step, n-type silicon substrate is then carefully lapped down to the level at which the
vertices of the V-grooves become exposed.So now we get an array of n-type single crystal
silicon regions that are isolated from the polycrystalline silicon substrate. Polycrystalline silicon
now serves to provide the mechanical support for the IC.This material is ideal for the function
because of its good thermal expansion coefficient, it can withstand high processing
temperatures, and is a good match to single crystal silicon.
The n-type silicon has now moved down to vertices of the V-grooves because of the lapping
operation. If the lapping is recessive, then proper isolation will not be achieved.But if excessive
lapping is done, it may lead to thinner n-type regions. Wafer diameter is approx 100mm and the
V-groove depth is about 10 micro meters, thus precise lapping is necessary.
The n+ diffused layer serves as a buried layer to reduce the collector series resistance of the n-pn transistors The rest of the processing sequence for the dialectically isolated ICs follows along
the same line as for the conventional junction isolated IC.
The dielectric isolation is useful for such applications as high-voltage and radiation-resistant ICs.
This isolation technique is much more expensive than junction isolation technique because it
requires extra processing steps.

Advantage of dielectric isolation:

Excess free electrons and holes created in the silicon as a result of high energy ionisation by
photo radiation causes a large increase in the leakage current of the pn junctions in the IC; which

obviously is undesirable and can cause damage.The dielectric isolation in the IC is resistant and
protects the IC from such large transients.
Below listed are some reasons for the reduced parasitic capacitance:

Permittivity of SiO2 is one reason, which is 1/3rd of Silicon and hence capacitance is
reduced.
Oxide is thicker than the depletion region of the substrate junction and capacitance is
inversely proportional to the thickness of oxide.
No need of applying negetive potential to the substrate.

Silicon-on-lnsulator Technology
Its another process for creating dielectrically isolated devices. In this process, a thin layer of
single-crystal silicon can be produced on top of a thermal SiO2 layer on a silicon wafer. Strips of
oxide are produced by patterning the oxide layer using photolithography. As a next step, a thin
layer of silicon is then deposited on the wafer.It will be polycrystalline in the regions where the
deposited silicon layer overlays the oxide and it will be single crystal in the regions where there is
direct contact with silicon substrate. In the next step we will directionally recrystalise the silicon
layer, which inturn recrystallises the substrate to act as the nucleation centre.As the heated zone
is scanned across the wafer the crystal growth, propagates from these nucleation regions to the
regions of the silicon film on top of the oxide islands or strips.Thus we form a complete single
crystal layer of silicon.

Epitaxial Lateral Overgrowth (ELO)

The Epitaxial Lateral Overgrowth (ELO) is related to Silicon on Insulator process.Like in SOI
process, the starting material is thermally oxidised silicon wafer in which the oxide layer is
patterned to islands or stripes using photolithographic techniques.Next step is a repeated
sequence of carefully controlled CVD silicon deposition, followed vapour phase etching cycles to
produce single crystal silicon film on the silicon substrate.
A preferential removal of polycrystalline silicon (deposited on top of SiO2) happens during the
vapour phase etching process.In the next steps,as successive cycles of the CVD deposition and
vapour-phase etching process continues,the single-crystal silicon that is formed in the oxide
windows starts to extend over the adjoining oxide regions,and at the same time any
polycrystalline silicon that is deposited on top of the oxide is removed by the vapour-phase
etching process.As a result a complete single crystal layer of silicon is formed.

Isolation techniques
Isolation techniques provide electrical isolation between the components and improves frequency
response.

 Isolation simplifies the physical layout of the integrated circuit.

The regions created by isolation are called as isolation regions or isolation islands.

PN junction isolation

Electrical isolation between the different components are accomplished by means of diffusion
which yields back to back pn junctions.

C1 - bottom of n type region to substrate

C2 - sidewalls of isolation islands to the p+ regions

P type substarate must always be held at a negative potential w.r.t. isolation islands so that the pn
junctions be reverse biased.

 If these diodes become forward biased in an operating circuit,then isolation would be lost.

Concentration of acceptor atoms in the region between isolation islands should be higher than in
the p substrate.

Application of bias voltage to the substrate provides adequate dc isolation.

Problems

Base,collector and substrate constitute an unwanted transistor.

This unwanted transistor reduces the coupling.
Capacitance of reverse biased collector substrate pn junction is relatively high,therefore at
higher frequencies,isolation will be poor.

Dielectric isolation

Both physical and electrical isolation is achieved by means of a layer of solid dielectric which
completely surrounds and seperates the components from each other and from the common
substrate.

 Passive layer - SiO2 , silicon monoxide ruby , glazed ceramic substrate.

A silicon crystal is grown on a single crystal sapphire using a technique related to epitaxial growth.

Appropriate portion of silicon is then etched away so that only islands of silicon remain,and
electrical isolation is achieved.

Other isolation techniques

EPIC isolation

Beam lead isolation

Metal Nitride Oxide Silicon (MNOS) isolation

Deep trench isolation