Analog Communication Lab Manual

ANALOG COMMUNICATION LAB MANUAL, V SEM EC
LIST OF EXPERIMENTS
SEM: V EXAM MARKS: 50

BRANCH: EC IA MARKS: 25
SUBJECT: ANALOG COMMUNICATION & LIC LAB
SUB CODE: 06ECL58
1) Active low pass & high pass filters –second order

2) Active band pass & band reject filters –second order
3) Schmitt trigger design and test a Schmitt trigger circuit for the given values of UTP
and LTP
4) Frequency synthesis using PLL
5) Design and test R-2R DAC using OP-AMP.
6) Design and test the following circuits using IC 555
(a) Astable multivibrator for given frequency and duty cycle
(b) Monostable multivibrator for given pulse width W.
7) Class-C single tuned amplifier
8) Amplitude modulation using Transistor/FET (Generation and Detection)
9) Pulse Amplitude modulation and Detection
10) PWM and PPM
11) Frequency modulation using 8038/2206
12) Precision Rectifiers- both Full Wave and Half Wave
DEPARTMENT OF E&C, CMRIT

CYCLE WISE EXPERIMENTS
SEM: V EXAM MARKS: 50

BRANCH: EC IA MARKS: 25
SUBJECT: ANALOG COMMUNICATION & LIC LAB
SUB CODE: 06ECL58
CYCLE - 1
1) Active low pass & high pass filters –second order
2) Active band pass & band reject filters –second order
3) Schmitt trigger design and test a Schmitt trigger circuit for the given values of UTP
and LTP
CYCLE - 2
4) Precision Rectifiers- both Full Wave and Half Wave
5) Design and test R-2R DAC using OP-AMP.
6) Design and test the following circuits using IC 555
(a) Astable multivibrator for given frequency and duty cycle
(b) Monostable multivibrator for given pulse width W.
CYCLE - 3
7) Class-C single tuned amplifier

8) Amplitude modulation using Transistor/FET (Generation and Detection)
9) Pulse Amplitude modulation and Detection
CYCLE - 4
10) PWM and PPM

11) Frequency modulation using 8038/2206
12) Frequency synthesis using PLL

EXPERIMENT N0 1(A)
SECOND ORDER ACTIVE LOW PASS FILTER
Aim: To obtain the frequency response of an active low pass filter for the desired cut off
frequency.
Components required:
Resistors- 33KΩ, 10KΩ, 5.86 KΩ

Capacitors 2200pF, opamp –μA 741
Design
For a 2nd order Filter, F H = 1 / 2RC Hz
Let FH = 2 KHz and R = 33 K
 2  10 3 = 1 / 2   33  10 3  C
 C = 2200 pF
The pass band gain of the filter, AF = (1+R f / R1)
For a second order filter, AF = 1.586, Let R1 = 10K
RF = 5.86 k 

Low pass circuit Diagram
R 1 R f
10k
10K
7
0 2
-
V+
uA741
R R Vo
3
+
V-
33k 33k
4
0
V1
C
C 2200Pf
2200Pf
0
0
Procedure:
1. Before wiring the circuit, check all the components.

2. Design the filter for a gain of 1.586 and make the connections as shown in the
circuit diagram.
3. Set the signal generator amplitude to 10V peak to peak and observe the input voltage
and output voltage on the CRO
4. By varying the frequency of input from Hz range to KHz range, note the frequency
and the corresponding output voltage across pin 6 of the op amp with respect to the
gnd.
5. The output voltage (VO) remains constant at lower frequency range.
6. Tabulate the readings in the tabular column.
7. Plot the graph with ‘f ‘on X-axis and gain in dB on Y axis.
Result:

EXPERIMENT N0 1(B)
SECOND ORDER ACTIVE HIGH PASS FILTER
Aim: To obtain the frequency response of an active high pass filter for the desired cut
off frequency.

Design:
For a 2nd order Filter, FL= 1 / 2RC Hz
Let FL = 2 KHz and R = 33 K
 2  10 3 = 1 / 2   33  10 3  C
 C = 2200 pF
RF = 5.86 k 

High pass circuit Diagram

R 1 R f
10k
10K
7
0 2
-
V+
uA741
C C Vo
3
+
V-
2200Pf 2200Pf
4
0
V1 R
R 33k
33k
0
Procedure:

2. Design the filter for a gain of 1.586 and make the connections as shown in the circuit
diagram.
In addition, output voltage on the CRO.
4. By varying the frequency of input from HZ range to KHA range, note the frequency
And the corresponding output voltage across pin 6 of the op amp with respect to the
gnd.
5-.The output voltage (VO) remains constant at lower frequency range.
Result:

EXPERIMENT N0 2(A)
SECOND ORDER ACTIVE BAND PASS FILTER
Aim: To obtain the frequency response of an active band pass filter for the desired cut
off frequency and to verify the roll off.

Design:
For a 2nd order Filter, F= 1 / 2RC Hz
(i) For High pass section
Let FL = 2 KHz and R = 33 K
 2  10 3 = 1 / 2   33  10 3  C
 C = 2200 pF
(ii) For low pass section
Let FH = 10 KHz And R = 33 k
 10  10 3 = 1 / 2   33  10 3  C
 C = 470 pF
RF = 5.86 k 
The Center frequency FC =  FH  FL
Hence FC = 4.5 KHz
Circuit Diagram:-

B A N D P A S S F IL T E R
R 1 R f R 1 R f
5 .8 k 5 .8 k
10k 10k
7
2
-
V+
7
2 uA741 6
-
V+
0 uA741 6 0 3 Vo
+
V-
3 R Vo R
+
V-
4
C
C C ' C '
V1 0
4
0V R R
0
0 0
Procedure:

2. Design the two filters for the desired cut off frequencies and make the connections as
shown in the circuit diagram.
And output voltage on the CRO.
4. By varying the frequency of input from Hz range to KHz range, note the frequency
gnd.
Result:

EXPERIMENT N0 2(B)
SECOND ORDER ACTIVE BAND REJECT FILTER
Aim: To obtain the frequency response of an active band reject filter for the desired cut
off frequency and to verify the roll off.

Capacitors 2200pF , opamp –μA 741
Design:
For a 2nd order Filter, F= 1 / 2RC Hz
(ii) For High pass section
Let FL = 10 KHz and C = 0.01 F, F L = 1 / 2RC Hz
 10  10 3 = 1 / 2   R  0.01  10 -6
 R = 1.59 k 
(ii) For low pass section
Let FH = 2 KHz And R = 33 k 
 2  10 3 = 1 / 2   33  10 3  C
 C = 2200 pF
For a second order filter, AF = 1.586, Let R1 = 10K 
RF = 5.86 k 
Circuit Diagram:-

BAND REJECT FILTER

R1
Rf
10k 5 .8 K
0 SUMMER
7
2
-
V+
R 2 = 10k R 4 = 10k
HIGH PASS uA741 6
S E C T I O CN C
3
+
V-
7
0 .0 1 u F 0 .0 1 u F 2
-
V+
4
uA741 6
R R
3
+
V-
R 5 = 3 .3 K
0
4
R1
0
10k R f = 5 .8 K
0
7
2
-
V+
LOW PASS SECTION R 3 = 10k

uA741 6
R ' R '
3
+
V-
4
C' C'
Procedure:

2. Design the two filters for the desired cut off frequencies and make the connections as
shown in the circuit diagram.
3. To simplify the design, set R2=R3=R and C2=C3=C then choose a value of C <=1 µF

Calculate the value of R using the equation

R= 1 / (2   fH  C)
R’=1 / (2   fL  C )
4. Because of the equal resistor R2=R3 and C2=C3 values the pass band voltage gain
AF = (1+R f / R1) of the second order low pass and high pass filter has to be equal
To 1.586 i.e. R f =0.586 R1 .This gain is necessary to guarantee Butterworth filter
response. Hence choose the value of R1 <100K and calculate the value for RF
And output voltage on the CRO.
6. By varying the frequency of input from HZ range to KHA range, note the frequency
Ground.
9 .Plot the graph with ‘f ‘on X-axis and gain in dB on Y axis.
Result:

EXPERIMENT NO. 3
DESIGN AND TEST A SCHMITT TRIGGER CIRCUIT FOR THE GIVEN

VALUES OF UTP AND LTP
AIM:
Design a square wave generator for a given UTP and LTP.
COMPONENTS REQUIRED:
Op-Amp - A741 – 1
Resistors – 1k - 1, 2.2k - 1
THEORY:
Schmitt Trigger is also known as Regenerative Comparator. This is a square wave
generator which generate a square based on the positive feedback applied. As shown in
the fig. below, the feedback voltage is Va. The input voltage is applied to the inverting
terminal and the feedback voltage is applied to the non-inverting terminal. In this circuit
the op-amp acts as a comparator. It compares the potentials at two input terminals. Here
the output shifts between
+ Vsat and –Vsat. When the input voltage is greater than V a, the output shifts to – V sat and
when the input voltage is less than Va, the output shifts to + Vsat. Such a comparator
circuit exhibits a curve known as Hysterisis curve which is a plot of Vin vs V0. The input
voltage at which the output changes from + V sat to – Vsat is called Upper Threshold Point
(UTP) and the input voltage at which the output shifts from – V sat to + Vsat is called
Lower Threshold Point (LTP). The feedback voltage Va depends on the output voltage as
well as the reference voltage.
A Zero Cross Detector is also a comparator where op-amp compares the input
voltage with the ground level. The output is a square wave and inverted form of the input.

CIRCUIT DIAGRAM:
Schmitt Trigger
+ Vcc
U 1
7
1
3
+
6 Vo
2
-
U A741 R 1
4
5
2 .2 k
Vin - Vcc
R 2
1k
+ Vref
Zero Cross Detector
+ Vcc
U 2
7
1
3
+ Vo
6
2
-
U A741
Vin
4
5
- Vcc
DESIGN:
Given UTP = + 4V and LTP = - 2V
Let I1 be the current through R1 and I2 be the current through R2.
W.K.T the current into the input terminal of an op-amp is zero.
 I1 + I 2 = 0
I1 = ( V0 – Va ) / R1
I2 = ( Vref – Va ) / R2
 ( V0 – Va ) / R1 + ( Vref – Va ) / R2 = 0
 Va = ( V0 R2 + Vref R1 ) / ( R1 + R2 )

When V0 = + Vsat, Va = UTP

When V0 = - Vsat, Va = LTP
 [ ( Vsat R2 ) / ( R1 + R2) ] + [ ( Vref R1 ) / ( R1 + R2 ) ] = UTP ------- (1)
 [ ( - Vsat R2 ) / ( R1 + R2 ) ] + [ ( Vref R1 / (R1 + R2 ) ] = LTP -------(2)
(1) – (2) 
( 2 Vsat R2 ) / ( R1 + R2 ) = UTP – LTP = 6V
Simplifying this equation we get,
7 R2 = 3 R 1
Assume R2 = 1k
 R1 = 2.2k
(1) + (2)
( 2 Vref R1 ) / ( R1 + R2 ) = UTP + LTP = 2V
Simplifying the above equation, we get
Vref = 1.4V
PROCEDURE:
1. Rig up the connections as shown in the circuit diagram.
2. Give a sinusoidal input of 10V peak to peak and 500 Hz from a signal
generator.
3. Check the output at pin no. 6 (square wave).
4. Coincide the point where the output shifts from + Vsat to – Vsat with any
point on the input wave.
5. Measure the input voltage at this point. This voltage is UTP.
6. Coincide the point where the output shifts from – Vsat to + Vsat with any
point on the input wave.
7. Measure the input voltage at this point. This voltage is LTP.
8. Another method of measuring UTP and LTP is using the Hysterisis Curve.
9. To plot the hysterisis curve give channel 1 of CRO to the output and channel 2
of CRO to the input.
10. Press the XY knob. Adjust the grounds of both the knobs.

11. Measure UTP and LTP as shown in the fig. and check whether it matches with
the designed values.
WAVEFORMS:
Vin
5
4
0 t
-2
-5
Schmitt Trigger
V0
10
0 t
- 10
Zero Cross Detector
V0
10
0 t
- 10

HYSTERISIS CURVE:
V0
+ Vsat
Vin
LTP UTP
- Vsat
NOTE: The same circuit can be designed for different values of UTP and LTP. For UTP
= 4V and LTP = 2V, R1= 10k, R2 = 1k and Vref = 3.3V. Check whether the circuit
works properly for these values.
RESULT:

EXPERIMENT N0 4
CLASS – C - TUNED AMPLIFIER
AIM: To design and test a class c – tuned amplifier to work at f0 = 734 kHz and to find
its max efficiency at optimum load
COMPONENTS REQUIRED
SLNO COMPONENTS RANGE QUANTITY

1. Dc Regulated Power Supply +5V 1
2. Ammeter 0 -10MA 1
3 Inductor 100MH 1
Capacitors 470Pf 1
4. 1000mf 1
0.01mf 1.
5 Resistors 15k 1
22 1
6 Transistor BF194 1
7 CR0 Probe Springs - 1
Springs - 10
THEORY:
Class – C Tuned Amplifier Amplify Large signal at radio frequency with
better frequency response. Efficiency is more than 78% and it increases with decrease in
conduction angle. It is used in radio transmitters and receivers with class – c operation the
collector current flows for less than half a cycle. A parallel resonant circuit can filter the
pulses of collector current and produce a pure sine wave of output voltage. The max
efficiency of a tuned class –c amplifier is 100% the Ac voltage drives the base and an
amplified and inverted signal is then capacitive coupled to the load resistance. Because of
the parallel resonant circuit, the output voltage is max at resonant frequency f0 = 1/2xLC
On either side of the voltage gain drops off shown class – C is always intended to amplify
a narrow ban of frequency.

DESIGN:
F O = 1/2LC
Let L = 100 F and C = 470 pF
 F O = 1 / 2  3.142   100  10 -6  470  10 -12
F O = 734 KHz
T = 1/F O
 T = 1/ 734  10 3
 T = 1.36
S
R B C B  10 T O
Where T O = 1/F O
 R B C B = 10  1/ F O
C B = 10 / F O  R B
Let R B = 15 k 
 C B = 10 / 734  10 3  15  10 3
C B = 908 pF
C B = 1000 Pf
Use Standard Value
CONDUCTION ANGLE  = T e / T  360 0

Where Te = Time period across emitter
T = time period across collector
DUTY CYCLE D =  / T
Or D =  / 360 0

TABULAR COLUMN: ( Vin = 5 volts)
Sl.No RL () V
OUT I dc P ac = V O2/8RL P dc =VCC I dc  = Pac/ Pdc %
(V) (mA)

PROCEDURE
1. Make the connections as shown in circuit diagram set input signal frequency to the
tuned circuit resonant frequency
2. Vary input voltage to get an undistorted approx sine wave by keeping load
resistance to a fixed value by varying load resistance note down the output voltage and
calculate current Iac
3. Tabulate the reading in tabular column\
4. Plot the graph of rl along x – axis and n across y – axis
From the graph, determine optimum load to calculate conduction angle the output is
taken across emitter
RESULT
A class – C tuned amplifier Is designed to work at a reasonable frequency fo 734 kHz
The max optimum load is 400 and conduction angle 0 = 77.
EXPERIMENT N0 5

EXPT. 13 - R-2R DAC USING OP-AMP
AIM:
Demonstrate Digital to Analog conversion for digital (BCD) inputs using R-2R
network.
Op-amp - A741
Resistors – 10k - 4
22k - 6
Dual power supply, Multimeter, bread board, connecting wires.
THEORY:
Nowadays digital systems are used in many applications because of their
increasingly efficient, reliable and economical operation. Since digital systems such as
microcomputers use a binary system of ones and zeros, the data to be put into the
microcomputer have to be converted from analog form to digital form. The circuit that
performs this conversion and reverse conversion are called A/D and D/A converters
respectively.
D/A converter in its simplest form uses an op-amp and resistors either in the
binary weighted form or R-2R form.
The fig. below shows D/A converter with resistors connected in R-2R form. It is
so called as the resistors used here are R and 2R. The binary inputs are simulated by
switches b0 to b3 and the output is proportional to the binary inputs. Binary inputs are
either in high (+5V) or low (0V) state.
The analysis can be carried out with the help of Thevenin’s theorem. The output
voltage corresponding to all possible combinations of binary inputs can be calculated as
below.
V0 = - RF [ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]
Where each inputs b3, b2, b1 and b0 may be high (+5V) or low (0V).

The great advantage of D/A converter of R-2R type is that it requires only two
sets of precision resistance values. In weighted resistor type more resistors are required
and the circuit is complex. As the number of binary inputs is increased beyond 4 even
D/A converter circuits get complex and their accuracy degenerates. Therefore in critical
applications IC D/A converter is used.
Some of the parameters must be known with reference to converters. They re
resolution, linearity error, settling time etc.
Resolution = 0.5V / 28 = 5 / 256 = 0.0195
WAVEFORMS:
R- 2R LADDER NETWORK R F = 2k
1 2
+vcc U 1
7
5
U A741
2 -
6
R R R R 2R
3 + Vo
0
-vcc
2R 2R 2R 2R
4
1
LSB MSB
b0 b1 b2 b3
0
V re f
DESIGN:
The equation for output voltage is given by
V0 = - RF [ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]

V0 = - RF . Vref[ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]

Case (i) If b0 b1 b2 b3 = 1 0 0 0 for 0.5 volts change in output for LSB change
- 0.5 = - 20 x 103.Vref [ (1 / (16 x 1.103)) + 0 + 0 + 0)
Vref = 4V
Case (ii) If Vref = 5V and b0 b1 b2 b3 = 0 1 0 0, then
V0 = - 20.103 . 5 [ (0 + (1/ (8.1.103)) + 0 + 0) ]
V0 = - 1.25V
TABULAR COLUMN:
Inputs Output voltage
b3 b2 b1 b0 Theoretical Practical
0 0 0 0
.
.
.
.
.
1 1 1 1
PROCEDURE:
1. Test the op-amp and other components before rigging up the circuit.
2. Rig up the circuit as shown in the fig.
3. Apply different combination of binary inputs using switches.
4. Observe the output at pin no. 6 of op-amp using multimeter or CRO.

5. Tabulate the readings as shown.

6. Calculate the resolution of the converter.
RESULT:
ASTABLE MULTIVIBRATOR

AIM:
To design and verify the operation of astable multivibrator using 555 Timer for
given frequency and duty cycle.
APPARATUS REQUIRED:
Timer - 555
4.5k - 2
7.25k- 1
Capacitors – 0.01F-1
0.1F-1
Signal Generator, DC power supply, CRO and connecting wires
THEORY:
A 555 timer is a monolithic timing circuit that can produce accurate and highly
stable time delays or oscillations, some of the applications of 555 are square wave
generator, astable and monostable multivibrator.
Astable multivibrator is a free running oscillator has two quasi stable state in one state
o/p voltage remains low for a time interval of Toff and then switches over to other state
in which the o/p remains high for an interval of Ton the time interval Ton and Toff are
determined by the external resistors a capacitor and it does not require an external trigger,
when the power is switched on the timing capacitor begins to charge towards 2/3 Vcc
through RA & RB, when the capacitor voltage has reached this value, the upper
comparator of the timer triggers the flip flop in it and the capacitor begins to discharge
through RB when the capacitor voltage reaches 1/3 Vcc the lower comparator is triggered
and another cycle begins, the charging and discharging cycle repeats between 2/3 Vcc
and 1/3Vcc for the charging and discharging periods t 1and t2 respectively. Since the
capacitor charges through RA and RB and discharges through RB only the charge and
discharge are not equal as a consequence the output is not a symmetrical square wave and
the multivibrator is called an asymmetric astable multivibrator
CIRCUIT DIAGRAM:

ASSYMETRIC MULTIVIBRATOR
Vcc +5V
RA
4
VCC
RE SE T
7
DISCHARGE
RB
6
555 OUTPUT
3 CRO
THRESHOLD
2
TRIGGER
CONTROL
C GND
1
5
0.01uf
0
SYMMETRIC MULTIVIBRATOIR
Vcc+5V
8 4
Ra
VC RE
C SE
T
7
DISCHARGE
Rb
O/P
D1 3
D2 OUTPUT
555D
6
THRESHOLD
CO
2 NT
TRIGGER GN RO
D L
C1
1 5
C2

DESIGN:
ASSYMETRIC: Given f = 1khz

Duty cycle = 60%
T = 0.693(Ra + 2Rb) C
F = 1.45/ [(Ra + 2Rb) C]
Duty cycle = (Ra + Rb)/Ra + 2Rb)
1K = 1.45/ [(Ra + 2Rb) 0.1*10-6]
Ra + 2Rb = 14.5K
Ra + Rb = 8.7K
Assume Ra = 4.7K
Rb = 9.57K  10K
SYMETRIC Given f = 1khz

Duty cycle = 50%
Charging time = Discharging time
T = TON =TOFF
T = 0.693(Ra + Rb) C
F = 1.45/ [(Ra + Rb) C]
Duty cycle = (Ra + Rb)/Ra + Rb)
1K = 1.45/ [(Ra + Rb) 0.1*10-6]
Ra + 2Rb = 14.5K
Since the duty cycle is 50%, Ra = Rb
2Ra = 14.5K
Ra = 7.25K  6.8K
Rb = 7.25K  6.8K

PROCEDURE:
1. Connections are made as shown in the circuit diagram
2. Switch on the DC power supply unit
3. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude
4. Observe the wave form on CRO at pin 6 and measure Vcmax and Vc min
5. Verify that Vcmax=2/3Vcc and Vc min=1/3 Vcc
6. Calculate the duty cycle D, o/p frequency and verify with specified value
TABULAR COLUMN
F(theo) =
Ra Rb C Ton Toff T F DY
1.45/(Ra + Rb)
WAVEFORMS:
Upper threshold
voltage
Vc at pin 6
Lower
2/3VCC
1/3VCC
0V t
Vout 5V
Toff
at pin 3
0V
t
Ton
Result:

MONOSTABLE MULTIVIBRATOR
AIM:
To design and verify the operation of monostable multivibrator using 555 Timer
for given
Pulse width.
APPARATUS REQUIRED:
Timer - 555
Capacitors – 0.01F-1
0.1F-1
Signal Generator, DC power supply, CRO and connecting wires
THEORY:

Monostable multivibrator has a stable state and a quasi stable state, the output of it is
normally low and it corresponds to reset of the flip flop in the timer, on the application of
external negative trigger pulse at pin 2 the circuit is triggered and the flip flop in the timer
is set which in turn releases the short across C and pushes the output high, At the same
time the voltage across C rises exponentially with the time constant RAC and remains in
this state for a period RAC even if it is triggered again during this interval, When the
voltage across the capacitor reaches 2/3 Vcc, the threshold comparator resets the flip flop
in the timer which discharges C and the output is driven low the circuit will remain in this
state until the application of the next trigger pulse
CIRCUIT DIAGRAM
Vcc +5V
8
BY127 Rt RA
VCC
RESET
2 6
TRIGGER THRESHOLD
Input Ct
7
DISCHARGE
555
C
CRO 3
OUTPUT 0
CONTROL
GND
1
DEPARTMENT OF E&C, CMRIT 0.01uf
0
DESIGN:
Given Tp = 1ms
F = 1KHz
T = 1.1R C
Let C = 0.1uF
R = (1*10-3 ) / (1.1*0.1*10-6 )
R = 9.09 K  10K
PROCEDURE:
1. Rig up the circuit as shown in the figure after checking all the components.
2. Apply suitable inputs to the astable multivibrator (DC & Trigger inputs)
3. Observe the waveform across the timing capacitor in one channel and the output in
the other channel..
4. Verify the designed values and the repeat the above procedure for different set of
values.
TABULAR COLUMN
R C Tp = 1.1RC Tp(prac)

WAVEFORMS:
Input trigger pulses

Vcc
T
t
Trigger pulses at pin 2
t
Capacitor voltage Vc at pin 5
Upper
threshold
voltage t
Output pulse at pin 32/3*Vcc
T t
p
T
RESULT:

EXPERIMENT N0 7
COLLECTOR MODULATION
Aim: - To generate AM signal, information signal given the collector. Also, demodulate
it. Measure the modulation index using two different methods.
Components Required:- IFT, AFT, SL 100/BF 194 transistor, resistors, capacitors,

diode 0A79, connecting board, connecting wires and CRO.
Circuit Diagram:-

AFT (GREEN)
VCC
+6v
MESSAGE SIGNAL
OPEN
FM = 2kHz
VAMPL = 5v(p-p)
IFT (RED)
o/p AM
wave
BF 194
0.01microF
2 2
470k 120
0.01microF
1 1
-6v
COLLECTOR AMPLITUDE MODULATION
Theory: -
The modulator is a linear power amplifier that takes the low-level modulating
signal and amplifies it to a high power level. The modulating output signal is coupled
through a modulating transformer to the Class C amplifier. The secondary winding of the
modulation transformer is connected in series with collector supply voltage Vcc of the
Class C amplifier. This means that modulating signal is applied in series with the
collector power supply supply voltage of the Class C amplifier applying collector
modulation.

In the absence of the modulating input signal, there will be zero modulation voltage
across the secondary of the transformer. Therefore, the collector supply voltage will be
applied directly to the Class C amplifier generating current pulses of equal amplitude and
output of the tuned circuit will be a steady sine wave.
When the modulating signal occurs, the a.c. voltage across the secondary of the
modulating transformer will be added to and subtracted from the collector supply voltage.
This varying supply voltage is then applied to the Class C amplifier resulting in variation
in the amplitude of the carrier sine wave in accordance with the modulating signal. The
tuned circuit then converts the current pulses into an amplitude-modulated wave.
Design:-
Let fm= kHz
m=
RC>>tc or RC≤ (1/mωm)
Or RC/3= (1/mωm)
ωm=2πfm
Assuming value of C=0.01μF
Substituting value of C and fm=1 kHz,

we get R=9.5kΩ ≈ 10kΩ
m= (Vmax-Vmin)/ (Vmax+Vmin)
Vm= (Vmax-Vmin)/2
Waveform:-

Procedure:-
1. Design the collector modulator circuit assuming fm=1 kHz and m=0.5 take
C=0.01μF.
2. Before wiring, check all components using multimeter.
3. Make connections as shown in figure.
4. Set the carrier frequency to 2v and 455 kHz.
5. Set the modulating signal to 5v and 1 kHz.
6. Keep carrier amplitude constant and vary the modulating voltage in steps and
measure Vmax and Vmin, and calculate modulation index.
7. Tabulate the reading taken.
8. Feed AM output to Y-plates and modulation signal yo X-plates of CRO. Obtain
trapezoidal pattern.
9. Plot the graph of modulating signal versus modulation index.
Observations:-
Vmax in volts Vmin in volts μ(mod index) Vm in volts

Graph:-
m
Vm
Result:-
EXPERIMENT N0 8
ENVELOPE DETECTOR
Aim: - conduct an experiment to demonstrate envelope detector for an input AM signal.

Plot variation of output signal amplitude versus depth of modulation.
Components required -0A79 diodes, resistors, capacitors, function generator,

connecting board and CRO.

Circuit Diagram:-
0A79
0.6v
AM SIGNAL 2
VAMPL = 2v
FC = 455kHz
0.1microF 6k output
MOD = 0.5 1
FM = 2kHz
ENVELOPE DETECTOR
Theory: -
An envelope detector is a simple and highly effective device that is well suited
for the demodulation of a narrow band AM wave, for which the percentage modulation is
less than 100%. In an envelope detector, the output of the detector follows the envelope
of the modulated signal, hence the name to it.
Figure above shows the circuit of an envelope detector. It consists of a diode and a
resistor-capacitor filter. This circuit is also known as diode detector. In the positive, half
cycle of the AM signal diode conducts and current flows through R whereas in the
negative half cycle, diode is reverse biased and no current flows through R.
As a result, only positive half of the AM wave appears across RC.
During the positive half cycle, the diode is forward biased and the capacitor C
charges up rapidly to the peak value of the input signal. When the input signal falls below
this value, the diode becomes reverse biased and the capacitor C slowly discharges
through the load resistor RL. The discharging process continues until the next positive
half cycle when the input signal becomes greater than the voltage across capacitor, the
diode conducts again and the process is repeated.
Waveforms:-

Design:-
Let fm=1 kHz

m=
fc=455 kHz
C=0.01µf
Let Rc>>fc
Or RC=3/ (mωm)
Substituting value of C and ωm in above equation we get,
Therefore, R=10 kΩ
Procedure:-
1. Before wiring the circuit, check all the components using the multimeter.
2. Make the connections as shown in the figure.
3. From the function generator apply the AM wave to the input.
4. Vary the modulation index knob, note down the Vmax and Vmin simultaneously,
and note down the output voltage the output VO in steps.
5. Modulation index is given by
m= (Vmax-Vmin)/ (Vmax+Vmin)
6. Plot the graph Vo versus modulation index m.
Tabular column:-
Modulation index m Output in volts Vo

Graph:-

Vo

RESULT:-
EXPERIMENT N0 9
FREQUENCY MODULATION USING IC 8038
AIM:To design and conduct an experiment to generate FM wave IC8038 with f= 33 kHz.
SL. NO COMPONENTS RANGE QUANTITY
1. IC 8038 1
2. Signal generator (0-100)MHz 1
3. Resistors 10 k ohms 4
4.7k ohms, 1
22k ohms, 1
82k ohms. 1
4. CRO probes 2
5. Voltage supply 12 V 1
6. Capacitors 0.1 micro F 1
1.00 micro F 1
7. Mother board

DESIGN:
Let R=Ra=Rb Let f=33 kHz

f= 3*(2*Ra-Rb)/10*Rac*Ra
Substituting for R&C in above equation, we get
f=0.3/RC

Let R=10k ohms
Therefore C =0.001*10-6F
Calculation
Frequency deviation =Fmax-Fmin
Modulation index= Frequency deviation / fm
GRAPH:

THEORY:
Frequency modulation:
FM is that form of angle modulation in which the instantaneous frequency is varied

linearly with the message signal.
The IC 8038 waveform generator is a monolithic integrated circuit capable of producing
high accuracy sine square , triangular, saw tooth and pulse waveforms with a minimum
number of external components.
Block diagram of ICL 8038
Basis principle of IC 8038

The operation of IC 8038 is based on charging and discharging of a grounded capacitor
C, whose charging and discharging rates are controlled by programmable current
generators Ia and Ib. When switch is at position A, the capacitor charges at a rate
determined by current source Ia . Once the capacitor voltage reaches Vut, the upper
comparator (CMP 1) triggers and reset the flip-flop out put. This causes a switch position
to change from position A to B. Now, capacitor charge discharging at the rate determined
by the current sink Ib .
Once the capacitor reaches lower threshold voltage, the lower comparator (CMP 2)
triggers and set the flip-flop output. This causes the switch position to change from
position B to A. And this cycle repeats. As a result, we get square wave at the output of
Flip flop and triangular wave across capacitor. The triangular wave is then passed
through the on chip wave shaper to generate sign wave.

To allow automatic frequency controls, currents Ia and Ib are made programmable

through an external control voltage Bi. For equal magnitudes of Ia and Ib, output
waveforms are symmetrical conversely, when two currents are unequal, output
waveforms are asymmetrical. By making, one of the currents much larger than other we
can get saw tooth waveform across capacitor and rectangular waveform at the output of
flip-flop.
Working
The frequency of the waveform generator is direct function of the dc voltage at terminal
8. By altering this voltage, frequency modulation is performed. For small deviations, the
modulating signal can be applied to pins, merely providing dc-dc coupling with a
capacitor. An external resistor between pins 7and 8 is not necessary but it can be used to
increase input impedance from about 8k. The sine wave has relatively high output
impedance. The circuit may use a simple op_amp follower to provide a buffering gain
and amplitude adjustments. The IC 8038 is fabricated with advanced monolithic
technology, using Schottky-barrier diodes and thin film resistors, and the output is stable
over a wide range of temperatures and supply variations.
PROCEDURE:
1. Rig up the circuit as shown in the figure.

2. Apply +12,-12V from the supply.
3. Observe the sinusoidal waveform at pin 2.It should be same as design carrier
frequency.

4. Switch on signal generator and apply the signal amplitude of 0.5V and frequency
of 1 kHz.
5. Observe the output between pin 2 and ground.
6. Sketch the waveforms. Show the graph of message carrier and modulation signal.
RESULT:
The frequency modulation is seen and the transmission bandwidth was found to be
……………kHz.
EXPERIMENT NO 11
PULSE AMPLITUDE MODULATION
AIM: To conduct an experiment to generate PAM signal and design a circuit to

demodulate the PAM signal

1 Transistor SL 100 1
2 Resistor 22 K Ω 3
4.7K Ω 1
10 K Ω 1
680 Ω 1
3 Capacitor Function Generator 0.1  f 1
4 Diode 0A79 1
5 Signal Generator - 2
6 CRO 30MHZ 1
THEORY:
In PAM the amplitude of the pulses are varied in accordance with the modulating signal.
(Denoting the modulating signal as m (t). PAM is achieved simply by multiplying the
carrier with the m (t) signal. The balanced modulators are frequency used as multipliers
for this purpose. The Output is a series of pulses, the amplitude of which vary in
proportion to the modulating signal.
The form of pulse Amplitude modulation shown in the circuit diagram is referred to as
natural PAM because the tops of the pulses follow the shape of the modulating signal. As
shown in fig, the samples are taken at regular interval of time. If enough samples are

taken, a reasonable approximation of the signal being sampled can be constructed at the
receiving end. This is known as PAM.
PULSE AMPLITUDE MODULATION
Vcc +5V
Q 1
C
B SL 100
10K E
22K
4.7K
C(t) Vo
m(t)
DEMODULATION
D 1
OA 79
R C
PAM I/P DEMOD O/P
680 0.1uF

DESIGN
Fc>> 1/RC
i.e., R>1/FcC
Let Fc =15 kHz and C=0.1μF

Therefore R~680Ω
PROCEDURE:
1. Make the Connections as shown in circuit diagram.
2. Set the carrier amplitude to 2 Vpp and in the frequency of 5 kHz to 15 kHz.
3. Set the i/p Signal amplitude to around 1V (p-p) and frequency to 2 kHz.
4. Connect the CRO at the emitter of the transistor and observe the Pam waveform.
5. Now connect the O/p(i.e. PAM) signal to the demodulation circuit and observe
the signal if it matched plot the waveform
RESULT:
The circuit to generate PAM signal and to demodulate the PAM signal were designed
and the waveform were observed.

EXPERIMENT NO 12
PULSE WIDTH MODULATION
AIM : To Conduct an Experiment to generate a PWM Signal for the given analog
signal of frequency less than 1 kHz and to design a demodulation circuit.
COMPONENTS REQUIRED

1 Op- Amp (  A – 741) ± 12 V 3
2 Resistors 10 K Ω 3
15K Ω 1
3 Capacitor Function 0.01  f 2

Generator
4 DC Regulated Power supply ± 12 V 1
5 Signal Generator - 2
6 CRO Probes - 3
7 CRO 30MHZ 1
8 Springs 15 15
THEORY:
Pulse width Modulation (PWM) is also known as Pulse duration

Modulation (PDM). Three variations of PWM are possible. In One variation, the leading
edge of the pulse is held constant and change in the pulse width with signal is measured
with respect to the leading edge. In other Variable, the tail edge is held in constant and
w.r.t to it, the pulse width is measured in the third variation, the centre of the pulse is held
constant and pulse width changes on either side of the centre of the pulse. The PWM has
the disadvantage when compared to ‘PDM’ that its pulses are of varying width and

therefore of varying power content, this means the transmitter must be powerful enough
to handle the max width pulses.
P W M M O D U L A T IO N
m ( t)
1kH z 10k 10K
R 1
7
c ( t) 2
-
V+
7
>1 kH z 10k uA741 6 2
-
3
+
uA741 V+ 6 PW M
V-
O /P
3
+
V-
4
0 0
D E M O D U L A T IO N
R 1
7
2
-
V+
R 2 = 15k
PW M 10k uA741 6 PW M
I/ P C 2 O /P
0 .0 1 u F 3 m ( t)
1n +
V-
C 2
0 .0 1 u F
4
0 0

DESIGN
RC >>T
Time Period Tp=0.1ms
R1C1=Tp
Let R1=10K
C1=0.01µF
Fc=1/2пR2C2
Fc=1KhZ
Let R2=15KΩ
C2=0.01µF
PROCEDURE:
1. Make the connections as shown in the circuit diagram,
2. Set the carrier amplitude to 2vpp and frequency  1 KHz (Say 1 5khz)
3. Set the signal amplitude to 2 Vpp and frequency < 1khz (Say 560 kHz)
4. Observe the o/p signal at pin 6of 2nd op-amp and observe the variation in pulse
width by varying the modulating signal amplitude.
5. Draw PWM Waveform
6. Now connect the output to the demodulate circuit and observe the signal it
matches with m(t)
RESULT:
The circuit to generate a PWM signal is designed and the output waveforms are
observed. In addition, a circuit to demodulate the PWM signal is designed and the
output is observed.

EXPERIMENT NO 13
PULSE POSITION MODULATION
AIM : To conduct an experiment to generate PPM signal of pulse width(between 100 ms

and 200ms) for a given modulating signal.
COMPONENTS REQUIRED

1 Op – amplifier Ma – 741 1
2 555 - Timer - 1
3 Resistors 10 K Ω 1
18 K Ω 1
5 Capacitor 0.01mf 2
6 Dc Regulated Power Supply + 5v 1
7 Function Generator - 2
8 CRO 30mhz 1
THEORY :
In this type of modulation , the amplifier and width of the pulses is kept constant
while the position of each pulse with reference to the position of a reference pulse is
changed according to the instantaneous sampled value of the modulating signal. Pulse
position modulation is observed from pulse width modulation. Any pulse has a leading
edge and trailing edge in this system the leading edge is held in fixed position while the
trailing edge varies towards or away from the leading edge in accordance to the
instantaneous value of sampled signal
Vcc +5V
m ( t)
8
1 kH z 10k 10K BY127 Rt RA

VCC
RESET
R 1
7
2 6
TRIGGER THRESHOLD
c ( t) 2
- Input Ct
V+
7
>2KHz 10k uA741 6 2
- 555
DISCHARGE
V+
C
3 uA741 6 PW M 3
+ CRO
V-
OUTPUT 0
O /P
3
CONTROL
DEPARTMENT OF E&C, CMRIT +

V-
GND
4
5
4
0.01uf
0 0 0
DESIGN
Pulse Width = 200μs
Tp=1.1 RC
Let C=0.01μF
Therefore R=18KΩ
PROCEDURE
1. Make the connections as shown in the circuit diagram.
2. Set the carrier amplitude to around 4v (p-p) and frequency = 1khz.
3. se the signal amplitude to around 2v (p-p) and frequency around (< 1khz)
4. Observe the output signal at pin no : 3 of the 555 timer and also observe the
variation in pulse position by varying the modulating signal amplitude
5. Draw the PPM waveform
RESULT
The circuit to generate a PPM signal of pulse width 200 ms is designed and the
output waveform of PPM was observed.

EXPT. 11 - PRECISION RECTIFIER
AIM:
Design and test the working of Full Wave Precision Rectifier using op-amp.
OP-Amp - A741 -1
Resistors - 10k - 3
22k - 1
3.3k - 1
Diodes - BY127 - 2
THEORY:
Precision Rectifier name itself suggests that it rectifies even lower input voltages
i.e. voltages less than 0.7v (diode drop). A rectifier is a device, which converts AC
voltage to DC voltage. Precision rectifier converts AC to pulsating DC. Normal rectifiers
using transformers cannot rectify voltages below 0.7v, so we go for precision rectifiers.
In this circuit the diodes are placed in such a way that one diode is forward biased in the
positive half cycle and the other in the negative half cycle. Consider the circuit diagram
shown below. Here in the positive half cycle D1 is forward biased and D2 is reverse
biased. The simplified circuit will act as two inverted amplifiers connected in series.
Hence the total gain will be the product of individual gains. During the negative half
cycle, D1 is reverse biased and D 2 is forward biased. Hence the simplified circuit is an
inverting amplifier connected in series with a non-inverting amplifiers. Hence the output

will be inverted and a DC output (unidirectional) is obtained .The precision rectifier we

are using is a full wave rectifier.
CIRCUIT DIAGRAM:
R 1 = 22k R = 10k R = 10k
D 1
+Vcc +Vcc
7
7
2 - 2
Vin -
6 6 Vout
R = 10k 3 + 3 +
U A741 U A741
-Vcc -Vcc
D 2
4
4
GN D
R 2 = 3 .3 K
DESIGN:
Given : Vo = +0.5V in the +ve cycle
= +0.1V in the -ve cycle
During the +ve half cycle the simplified circuit will be as shown below.
 V = (-R1 / R) Vin
V0 = (-R / R)V

= (-R / R) (-R1 / R) Vin

V0 = (R1/R) Vin
As V0 = 0.5V, Vin = 0.25V
 R1 / R = 0.5 / 0.25 = 2
Assume R = 10k , then
R1 = 20k
NOTE: A DRB can be used in the place of R 1 and that resistance can be adjusted to
20K or 22K resistance can be used.
During the negative half cycle, the simplified circuit will be shown below.
V
I1
R 1 R R
I2
+Vcc +Vcc
7
7
2 - 2
Vin -
A 6 6 Vout
R = 10k 3 + 3 +
B U A741 U A741
-Vcc -Vcc
I3
4
4
GN D
R 2
V
Applying KCL at
point A
I1 = I 2 + I 3
From virtual ground concept
VA = 0 ( VB = 0)
 I1 = Vin / R , I2 = -V / ( R1+R ), I3 = -V / R2
Vin / 10k = - V ( (1 / 30k) + (1 / R2) )
As Vin = - 0.25
 - 0.25 / 10k = -V ( (1 / 30k) + (1 / R2) ) --------(1)
As the second Op-Amp works as a non inverting amplifier
V0 = (1 + (R / R1) + R) V
= (1 + (10k / 30k) ) V ---------(2)
From (1) V = - 0.25 / 10k
= - V ( (R2 + 30k) / (30k x R2 ) )

 V = 0.75 R2 / ( R2 + 30k )
Substituting this in the equation (2) we get
V0 = (1 + 1 / 3) (0.75 R2 / (R2 + 30k) )
0.1 R2 + 3k = R2
0.9 R2 = 3k
 R2 = 3.3k
PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Give an input of 0.5V peak to peak (sine wave).
3. Check and verify the designed values.
4. Design the same circuit for a different set of values.
WAVEFORMS:
Vin
0.25
0 t
- 0.25
V0
0.5
0.1
0 t
RESULT:

Viva questions for analog communication lab
1. Define the word communication.

2. What are the basic components of electronic communication.
3. What is Transmitter.
4. What is receiver
5. What is communication channel?
6. State two types of communication?
7. What is baseband signal?
8. What is baseband transmission?
9. What is the need for modulation?
10.Define the carrier signal?
11.What is the classification of modulation?
12.What is frequency deviation?
13.Define noise?
14.Define the basic sources of noise?
15.What is shot noise?
16.Define signal to noise ratio?
17.What is noise factor?
18.State the equation for noise factor for cascade connection?
19.Define amplitude modulation?
20.Define modulation index?
21.State the bandwidth required for amplitude modulation?
22. What is frequency domain display?
23. What is time domain display?
24. What is maximum power of sideband of AM?
25. What is the maximum total power of AM wave?
26. Define a high level modulation?
27. Define a low level modulation?
28.Why amplitude modulation is used for broadcasting?
29.What is the position of the operating point of class-C?
30.What is the advantage of SSB over DSB-SC?
31.What is the function of Transistor mixer?
32.What is the principle of Envelope detector?

33.Where SSB transmission is used?

34.State sampling theorem?
35.What is Nyquist criteria?
36.What is Roll-off factor?
37.Define the order of the filter?
38.What are the classification of filters?
39.Differentiate between butter-worth and cheybeshev filter?
40.Define selectivity?
41.What is quadrature null effect?
42.Define FM?
43.What is percentage modulation?
44.Define pre-emphasis and De-emphasis?
45.What are the advantages of using pre and de-emphasis?
46.List of some advantages of FM over AM?
47.Define wideband FM?
48.What is carson’s rule?
49.State advantages of PWM?
50.State various Pulse modulation methods?

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ANALOG COMMUNICATION LAB MANUAL, V SEM EC

SEM: V EXAM MARKS: 50

1) Active low pass & high pass filters –second order

8) Amplitude modulation using Transistor/FET (Generation and Detection)

9) Pulse Amplitude modulation and Detection

10) PWM and PPM

11) Frequency modulation using 8038/2206

12) Precision Rectifiers- both Full Wave and Half Wave

DEPARTMENT OF E&C, CMRIT

CYCLE WISE EXPERIMENTS

SEM: V EXAM MARKS: 50

7) Class-C single tuned amplifier

10) PWM and PPM

DEPARTMENT OF E&C, CMRIT

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

For a 2nd order Filter, F H = 1 / 2RC Hz

Let FH = 2 KHz and R = 33 K

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K

DEPARTMENT OF E&C, CMRIT

Low pass circuit Diagram

1. Before wiring the circuit, check all the components.

DEPARTMENT OF E&C, CMRIT

SECOND ORDER ACTIVE HIGH PASS FILTER

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

For a 2nd order Filter, FL= 1 / 2RC Hz

Let FL = 2 KHz and R = 33 K

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K

DEPARTMENT OF E&C, CMRIT

High pass circuit Diagram

1. Before wiring the circuit, check all the components.

DEPARTMENT OF E&C, CMRIT

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

For a 2nd order Filter, F= 1 / 2RC Hz

(i) For High pass section

Let FL = 2 KHz and R = 33 K

(ii) For low pass section

Let FH = 10 KHz And R = 33 k

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K

The Center frequency FC =  FH  FL

Hence FC = 4.5 KHz

DEPARTMENT OF E&C, CMRIT

1. Before wiring the circuit, check all the components.

DEPARTMENT OF E&C, CMRIT

Resistors- 33KΩ, 10KΩ, 5.86 KΩ

For a 2nd order Filter, F= 1 / 2RC Hz

(ii) For High pass section

Let FL = 10 KHz and C = 0.01 F, F L = 1 / 2RC Hz

(ii) For low pass section

Let FH = 2 KHz And R = 33 k 

The pass band gain of the filter, AF = (1+R f / R1)

For a second order filter, AF = 1.586, Let R1 = 10K 

DEPARTMENT OF E&C, CMRIT

BAND REJECT FILTER

LOW PASS SECTION R 3 = 10k

1. Before wiring the circuit, check all the components.

DEPARTMENT OF E&C, CMRIT

Calculate the value of R using the equation

DEPARTMENT OF E&C, CMRIT

DESIGN AND TEST A SCHMITT TRIGGER CIRCUIT FOR THE GIVEN

DEPARTMENT OF E&C, CMRIT

Zero Cross Detector