-- This is a 8 Bit Wide 16 Bytes Deep FIFO.

-- I have not synthesized but i feel that there should be no problem

LIbrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity fifo is
Port (
Clk : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
ReadEnable : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
DataOut : out std_logic_vector(7 downto 0);
FifoEmpty : out std_logic;
FifoFull : out std_logic
);
END fifo;-- entity declarations ends
Architecture A_fifo of fifo is
Component Rams
Port (
Writeen : in std_logic;
Wclk : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Addr : in std_logic_vector(3 downto 0);
Dataout : out std_logic_vector(7 downto 0)
);
END Component;
Signal ReadPointer : std_logic_vector(3 downto 0);
Signal WritePointer : std_logic_vector(3 downto 0);
Signal ByteCounter : std_logic_vector(4 downto 0);
Signal WriteEnable_s : std_logic;
Signal Addr_s : std_logic_vector(3 downto 0);
Signal FifoFull_s : std_logic;
Signal FifoEmpty_s : std_logic;
Begin
FifoRam : Rams
Port map (
Writeen => WriteEnable_s,
Wclk => Clk,
Datain => DataIn,
Dataout => DataOut,
Addr => Addr_s
);
ReadWriteFifoOut : Process(Clk,Reset)
Begin
IF ( Reset = '1') then
ReadPointer <= "0000";
WritePointer <= "0000";
ByteCounter <= "00000";
ELSIF(Clk'event and Clk = '1') then
IF ( WriteEnable = '1' and FifoFull_s = '0' and ReadEnab
le = '0')
then
WritePointer <= WritePointer + 1;
ByteCounter <= ByteCounter + 1;
END IF;
IF ( ReadEnable = '1' and FifoEmpty_s = '0' and WriteEna
ble = '0')
then
ReadPointer <= ReadPointer + 1;
ByteCounter <= ByteCounter - 1;
END IF;
END IF;
END process;-- ReadWriteFifo Process ends
-----------------------------------------------------------
-- Combinatorial Logic
-----------------------------------------------------------
FifoEmpty_s <= '1' when ( ByteCounter = "0000") else
'0';
FifoFull_s <= ByteCounter(4);
FifoFull <= FifoFull_s;
FifoEmpty <= FifoEmpty_s;
WriteEnable_s <= '1' when ( WriteEnable = '1' and FifoFull_s = '0') else
'0';
Addr_s <= WritePointer when ( WriteEnable = '1') else
ReadPointer;
------------------------------------------------------------
END A_fifo;--Architecture Ends

The following xnf File was used for Memory

LCANET,6
PROG, MEMGEN, 5.2.0, "14-deep by 8-wide SYNC_RAM macro called 'sramd_s'"
PART, 4013EPQ160
PWR,0,GND
SYM,BANK0-00,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<0>
PIN,O,O,DATAOUT<0>
END
SYM,BANK0-01,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<1>
PIN,O,O,DATAOUT<1>
END
SYM,BANK0-02,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<2>
PIN,O,O,DATAOUT<2>
END
SYM,BANK0-03,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<3>
PIN,O,O,DATAOUT<3>
END
SYM,BANK0-04,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<4>
PIN,O,O,DATAOUT<4>
END
SYM,BANK0-05,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<5>
PIN,O,O,DATAOUT<5>
END
SYM,BANK0-06,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<6>
PIN,O,O,DATAOUT<6>
END
SYM,BANK0-07,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0
PIN,A0,I,ADDR<0>
PIN,A1,I,ADDR<1>
PIN,A2,I,ADDR<2>
PIN,A3,I,ADDR<3>
PIN,WE,I,WRITEEN
PIN,WCLK,I,WCLK
PIN,D,I,DATAIN<7>
PIN,O,O,DATAOUT<7>
END
EOF
-- This entities are not tested
---Behavioral Code For RAM
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Entity Rams is
Port (
Writeen : in std_logic;
Wclk : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0);
Addr : in std_logic_vector(3 downto 0)
);
END Rams;-- Entity Ends
Architecture Behave of Rams is
Type Mem is array ( 15 downto 0) of std_logic_vector( 7 downto 0);
Signal Memory : Mem;
Begin
Write_Process : Process(Wclk)
Begin
if (Wclk'event and Wclk = '1') then
if ( Writeen = '1') then
Memory(Conv_Integer(Addr)) <= Datain;
end if;
end if;
end process; -- Write Process Ends
Dataout <= Memory(Conv_Integer(Addr));
End Behave;-- Architecture Ends