TABLE 1. PIC16F8x FAMILY OF DEVICES ‘Maximum Frequency ‘of Operation (MHz) Flash Program Meriany Bz = K = EEPROM Program Memory = = = = DERE ROM Program Memory = Bia = i Data Memory (bytes) 35 36 8 aa Data EEPROM (bytes) a co ea 4 PREY Timor Module(s) THRO THRO. TWRO TRO Interrupt Sources a + 4 a TO Pine: 3 3 7 cE Verage Range (Waits) 2050 2050 2060 2060 Packages: TBpin DIP, | 1pm IP, 18-pin DIP, | 18 pin DIP, sole. sole sale sole ‘All PiCmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high VO current capa bilty All PICTEF8X Family devices use serial programming with clock pin RBG and data pin REBT. FIGURE 3-1; PIC16F8X BLOCK DIAGRAM 8 Dabs 9 FgshiRoM Foaram Counter cEPROM Data emery Prosar Memory it pictorearenes Ratt eonom eae ta Fie Regetere pictoreaonea Steeisiack | | picropssionss FpL_Eepata_ fey data Memory AK x14 (13-ba) 36x8 4x8 prcterSdiores oe i Program 4 Bus RAM Addr EEADR Instruction reg Aatdr Miae ect Ad Tb inset uo l Dive At ng Ferre aarocks 4 Power vo Fons Insrucon Oocator Beeadee fame] | sh ter antl ‘Power-on = RA3:RAO_ ae Ti Watcnoa Ls] eRe concen ‘ice R67 RS yt ff sone osgycurour «GTR Vo, ves SSeERNFIGURE 4-2: REGISTER FILE MAP - PIC16F84/CR84 File Address File Address 00h | Indirect addr") | Indirect addr | 80h oth TMRO OPTION 8th 02h PCL PCL. 82h 03h STATUS STATUS 83h O4h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB ‘86h o7h 87h 08h EEDATA EECON1 88h 09h EEADR | EECON2(1) 89h OAh PCLATH PCLATH An Bh INTCON INTCON 88h OCh 8Ch 68 General citappes urpose (accesses) reqsters in Bank 0 ¢ ) Fh ‘Fh 50h DOh ~_ 7Fh FFh Bank 0 Bank 1 1 Unimplemented data memory location; read as 0". Note 1: Nota physical register.TABLE 41 REGISTER FILE SUMMARY ‘Value on | Value on all Address | Name an7| ate | ets | site | ots | cz | ant | so | Poneren | otherresets Reset (Notes) Bank 0 ‘00h INDF ‘Uses contents of FSR to address data memory (not a physical register) Tih [THRO rearme cecounter Too seo | uae wa an [Fo Tow oe BIS of be Progam CouTier PS) EE osm [staus@ | ire | rei [Reo TO FO z [oc | c_[ o001 rx | 0000 aun on [FoR Tries dia rion adres pier Toon sooa | uuu wun Eh [PORK =] =) =| SRA] RAS] RDA [RAD] co | cen [PORTS | RAT | ABE [RBS | _ReA_[ _RBF_| REP | RET Te Oh Urimpiemented iocaton, reads 0 Osh [EEDATA_| EEPROM data register (Osh [EEADR | EEPROM address register can [roa | — | = | — | Wite uteri upper us orine po wen [iwrcon | GE | eee | TOE | TE | RBE | TOF | NF Bank 4 80h INDF ‘Uses contents of FSR to address data memory (not a physical register) om [SEROL Yraeo] wens] tocs] ese ] psa | ps2 | par | ro | sae fae ah [Fo Tow order 8 bis of Pagam Counier PO) 7900 0000 | 0060 Guo aan |starus@ | ip | aps | RPO Zz oc | 9002 a0 | 006g qu oh FaR Tred dla wero ade poe O "moa oo | wa ih [TRISA [= PORTA ea Grecion regsier spun [Tn Bh [TRISS__| PORTR daa Gresionreabier man [aaa ah Trimperentedbeaon,readas 0 wn __[eccont | — | — [| — | fe | WRERR[ WAEN| WR | 0 2 x000 | ---0 at0e 89h EECON2 EEPROM control register 2 (not a physical register) oan [POLAT | — |= |__| Wile baer unper is ofthe po = 0000 | —-0 c00e ton [mrcon | GE | EGE | TE | NTE | FOE | Wir | NIF | FIP | coo ocox | coco cow Tegend: c= unknown, a= unchanged. - = unimplemented read as 1, q= value depends on conditon: Note 1: The upper byte of the program counter is not directy accessible. PCLATH is a slave register for PC<12:8>. The contents ‘of PCLATH can be transferred tothe upper byte of he program counter, but the contents of PC<12:8 is never transferred to PCLATH. 2 Tho TO and PD status bits in tho STATUS register are not affocied by a NCLR reset. 3: Other (non power-up) resets include: external reset through NICLR and the Watchdog Timer ResetFIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations B 87 6 OPCODE d (FILE #) d= 0 for destination W d= 1 for destination f f = T-bitfile register address Bit-oriented file register operations 13 19 76 OPCODE [b(@IT#)| _‘F(FILE#) 3-bit bit address T-bit fle register address Literal and control operations General 13 aT OPCODE k (literal) k = 8-bit immediate value CALL and GoTo instructions only B 1110 OPCODE k (literal) k = 11-bit immediate valueTABLE 9-2 [CTEFXX INSTRUCTION SET Mnemonic, Description Cycles ‘TEBit Opcode ‘Status | Notes Operands aS Tsp] Affected EYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF fd ‘Add W end Y [oo oll atte teee[CDCZ ] 12 ANDWF f,d AND W with f + [oo ror eee zee] Z 12 cLAF of Clearf + [oo oor see cece] 2 2 cLRW Clearw + foo 0002 xxx xxx] 2 COMF fd Complement f + [oo 001 eee eee] Zz 12 DECF fd Decrement f + [oo ora geez ceze] 2 12 DECFSz fd Decrement f, Skip if0 1@) [oo 1011 eee tee 12.3 INCF fd. Inerement f 1 Joo 1010 eee eee] Z 12 INCFSZ fd Increment f, Skip if 1@) [oo 1111 atte eee 1.2.3 IORWF fd Inclusive OR W with F + [oo coo geez ceze| 2 12 MOVF fd Movef + [oo 1000 eee sees] Z 12 MOVWF of Move W tof + [oo ooo ite sees NOP. ‘No Operation + }00 0000 oxx0 9000 RLF fd Fotate Left through Carry + [oo i101 ee eee] C 42 RRF fd Rotate Right f through Carry + [oo 00 eee eee] Cc 42 SUBWF fd Subtract W from f + [oo oo10 ate seee}cocz | 12 SWAPF fd. ‘Swap nibbles in f + [oo lo eee eee 12 XORWF fd Exclusive OR W with f + [oo io aes sees] Zz 12 BIT-ORIENTED FILE REGISTER OPERATIONS BCFf,b Bit Clearf T | 0 00bb pete fete 12 BSF fb Bit Set + | 01 olbb bese eeee 12 BTFSC fb Bit Test f, Skip iClear 142) | 01 tobe pees Free 3 BIFSS fb Bit Test f, Ship if Set 1(2) | 02 aibp eee feee 3 LITERAL AND CONTROL OPERATIONS ADDLW ‘Add literaland W 7 [a iiix max won] €DCZ ANDLW Kk AND literal with W + | a2 door wick eee) 2 CALL ok Call subroutine 2 | 10 kkk keke kkkk CLRWDT - Clear Watehcog Timer + | 00 cooo 0110 0100) TOPD GOTO. k Goto address 2 | 10 ikke kkk kk JoRLW ok Inclusive OR literal with W + | a2 tooo wie see] Z MovLW ok Move literal to W 1 | a come ekki kkk RETFIE Retum from interrupt 2 | 00 cooo cooo 1001 RETLW Kk Return with itera in W 2 | an case kkk ke RETURN - Return from Subroutne 2 | 00 coo 000 1000 SLEEP Go into standby mode + | 00 cooo 0110 0011) TOFD SUELW k ‘Subtract W from literal + | a1 tox keke idee] C002 XORLW Exclusive OR literal with W + [a2 toro wre see] |Z Note 1: When an//O register is modified as a function of self (e.g, MOVF PORTS, 1), the value used willbe that value present cn the pins themselves. For example, ifthe data latch is“l'for a pin configured as input and ie driven low by an external device, the data will be written back with 2 ‘0. tothe Timer0 Module. If his instruction is executed on the TMRO resister (and, where applicable, d = 1), the presealer will be cleared if assigned ‘3: If Program Counter (PC) is modified or a conditional tet i rue, the instruction requires two cycles. The second cycle is executed as a NOP.