LAB # 1

Introduction to Basic Syntax of Verilog and Gate-level-Modelling

Using Xilinx ISE tools

Objectives:
1. Identifying the components of a Verilog module definition
2. Understanding how to define the port list for a module and declare it in
3. Verilog
4. Familiarization with the logic gate primitives provided in Verilog
5. Understanding instantiation of gates and construction of a Verilog
6. Description from the logic diagram of the circuit
7. Hierarchical Design in Verilog

Reference:

Chapter 4 and Chapter 5

BOOK : Verilog HDL by Samir Palnitkar

Chapter 4

BOOK : Advanced Digital Design with the Verilog HDL

 Enter the following Verilog Code in half_adder.v file and save the file:
Code:

Input applied:

Output obtained:
 Enter the following Verilog Code in full_adder.v file and save the file:

Code:

Input applied:
 Output obtained:

 Enter the following Verilog Code in full_adder1.v file using half adders and save the
file:

Code:
Input applied:

Output obtained:

 Write the Verilog Code for this 4-Bit Ripple Carry Adder. Now the inputs and
outputs will be handled differently using the concept of “Vectors” in Verilog.
Code:

Input applied:
Output obtained:

 DATA FLOW
 Write down the Boolean Equation for Half Adder:
Code:
 Input applied:

Output applied:

 Write down the Boolean Equations for full adder:

Code:
Input applied:

Output obtained:

LAB # 2

Introduction to Gate level & Dataflow Modelling through implementation of 4

bit Ripple Carry at gate level and its simulation using Xilinx ISE tools.

 MUX 2x1
 Code:

Input Applied:

Output Obtained:

 Mux4x1
 Code:

Input Applied:

Output Obtained:

 Mux8x1
Code:

Input Applied:
 Output Obtained:

 Mux 16x1
Code:

Input applied:
Output Obtained:

LAB#3
Half adder
Carry look ahead generation
Carry look ahead generator
4 bit adder