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CHudNG 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1 TONG QUAN VE VI I)lEU KHIEN PIC

PIC LA GI?? ... ...." ...." ;t ~ " TAl SAO LA PIC MA KHONG LA CAC HO VI DIEU KHIEN KHAC?? KIEN TRUC PIC RISC vA CISC PIPELINING ".... ..." ~ ~ CAC DONG PIC VA CACH Ll,1A CHQN VI DIEU KHIEN PIC NGON NGU LAP TRINH CHO PIC MACH NAP PIC BOOTLOADER vA ICP (In Circuit Programming) CHudNG 2 VI DIEU KHIEN PIC16F877A

2.1 SdDO CHAN VI DIEU KHIEN PIC16F877A ,.? 2.2 MOT VAl THONG SO VE VI DIEU KHIEN PIC16F877A ~,.t ~ ,.? 2.3 so DO KHOI VI DIEU KHIEN PIC16F877 A 2.4 TO CHUC BO NHO 2.4.1 BO NHO CHUdNG TRINH 2.4.2 BO NHO DU LI~U 2.4.2.1 THANH GHI CHUC NANG DA.C BI~T SFR 2.4.2.2 THANH GHI Ml,TC DICH CHUNG GPR 2.4.3 STACK 2.5 cAc CONG XUAT NHAP CVA PIC16F877A 2.5.1 PORTA 2.5.2PORTB 2.5.3 PORTC 2.5.4 PORTD 2.5.5 PORTE 2.6 TIMER 0 2.7 TIMER1 2.8 TIMER2 2.9 ADC 2.10 COMPARATOR 2.10.1 BO TAO DI~N Ap SO sANH 2.11 CCP 2.12 GIAO TIEP NOI TIEP
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1.12.1 USART 2.12.1.1 USART BAT DONG BO .e ,.t ,.t ~ 2.12.1.1.1 TRUYEN DO' Ll~U QUA CHUAN GIAO TIEP USART BAT DONG BO ,.? ,.(' ,.t ~ 2.12.1.1.2 NHAN DO' Ll~U QUA CHUAN GIAO TIEP USART BAT DONG BO 2.12.1.1.2 USART DONG BO 2.12.1.2.1 TRUYEN DU LIeU QUA CHUAN GIAO TIEP USART DONG BO MASTER MODE 2.12.1.2.2 NHAN DU LIeU QUA CHUAN GIAO TIEP USART DONG BO MASTER MODE 2.12.1.2.3 TRUYEN DU LIeU QUA CHUAN GIAO TIEP USART DONG BO SLAVE MODE 2.12.1.2.4 NHAN DU LIeU QUA CHUAN GIAO TIEP USART DONG BO SLAVE MODE
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2.12.2 MSSP 2.12.2.1 SPI 2.12.2.1.1 SPI MASTER MODE 2.12.2.1.2 SPI SLAVE MODE 2.12.2.212C 2.12.2.2.1 12C SLAVE MODE 2.12.2.2.2 12C MASTER MODE ,!l '" 2.13 CONG GIAO TIEP SONG SONG PSP (PARALLEL SLAVE PORT) K.." 2.14 TONG QUAN VE MOT SO DAC TINH CUA CPU. 2.14.1 CONFIGURATION BIT 2.14.2 CAC DAC TINH CUA OSCILLATOR 2.14.3 cAc cHE DORESET 2.14.4 NGAT (INTERRUPT) 2.14.4.1 NGAT INT 2.14.4.2 NGAT DO su THAY DOl TRANG THAI cAc PIN TRONG PORTB 2.14.5 WATCHDOG TIMER (WDT) 2.14.6 CHE DO SLEEP 2.14.6.1 "DANH THUC" VI DIEU KHIEN
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4.1 IHEU KHIEN CAC PORT 110 4.1.1 CHudNG TRINH DELAY 4.1.2 MOT SO UNG Dl,TNG VE DA.C TINH 1/0 CVA cAc PORT DIEU KHIEN ~,.? , 4.2 VI DIEU KHIEN PIC16F877 A VA IC GHI DJCH 74HC595 4.3 PIC 16F877A vA LED 7 DOAN 4.4 NGAT V A cAu TRUC CV A MOT CHudNG TRINH NGAT 4.5 TIMER V A UNG Dl,TNG 4.5.1 TIMER vA HOA T DONG DJNH THO I PHl,TLl,TC 1 so DO KHOI cAc PORT CVA VI DIEU KHIEN PIC16F877A PHl,TLl,TC 2 THANH GHI SFR (SPECIAL FUNCTION REGISTER)

CHu'(jNG 1 TONG QUAN VE VI DIEU KHIEN PIC

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PIC Ia vie't t~t cua "Programable Intelligent Computer", c6 th€ tam dich la "may tinh thong minh kha trmh" do hang Genenral Instrument dcJ.tten cho vi di€u khien dffu tien cua ho: PIC1650 du'<_1C ke' d€ dung lam cac thie't bi ngoai vi cho vi di€u khi€n CP1600. Vi di€u thie't khicn nay sau d6 diroc nghien cuu phat tri€n them va til d6 hlnh thanh nen dong vi di€u khicn PIC ngay nay. 1.2 T~I SAO LA PIC MA KHONG LA CAC HQ VI DIEU KHIEN KHAC?? Hien nay tren thi tnrcng c6 r(t nhieu ho vi di€u khicn nhu 8051, Motorola 68HC, AVR, ARM, ... Ngoai ho 8051 diroc hudng dfin mot each can ban a moi tnrong dai hoc, ban than ngu'Cfiviet da chon ho vi di€u khi€n PIC d€ rna rQng vO'n kien thiic va phat tri€n cac irng dung tren cong cu nay VI cac nguyen nhan sau: HQ vi di€u khien nay c6 th€ tim mua d€ dang tai thi tnrong Vi~t Nam. Gia thanh khong qua d~t. C6 dffy du cac tinh nang ciia mot vi di€u khien khi hoat dQng dQc l~p. La mQt su b6 sung r(t to't v€ kie'n thirc ciing nhu v€ tmg dung cho ho vi di€u khien mang tinh truyen thong: ho vi di€u khien 8051. SO'lu'<_1ngguoi sti' dung ho vi di€u khi€n PIC. Hien nay tai Vi~t Nam ciing nhu tren n the' gidi, ho vi di€u khien nay diroc sti' dung kha rong rai. Di€u nay tao nhieu thuan loi trong qua trmh tim hi€u va phat tri€n cac irng dung nhu: sO'lu'<_1ng lieu, sO'lu'<_1ngac irng dung tai c rna da diroc phat tri€n thanh cong, d€ dang trao d6i, hoc t~p, d€ dang tim diroc st;J'chi dfin khi gap kh6 khan, ... St;J'h6 tro cua nha san xuft v€ trmh bien dich, cac cong cu l~p trlnh, nap chuong trmh til don gian de'n phirc ta p, ... Cac tinh nang da dang cua vi di€u khien PIC, va cac tinh nang nay khong ngirng dircc phat tri€n. 1.3 KlEN TRUC PIC C(u tnic phdn cimg ciia mot vi dieu khi€n diroc thie't ke' theo hai dang kien tnic: kien tnic Von Neuman va kien tnic Havard.
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Hlnh 1.1: Kitn tnic Havard va kien tnic Von-Neuman T6 clnrc phdn cimg cua PIC dtroc thiet kt theo kien tnic Havard. Di€m khac biet gitta kien true Havard va kitn tnic Von-Neuman la c(u tnic bQ nhd dii' lieu va bQ nhd chtrong trmh. Do'i vdi kien tnic Von-Neuman, bQ nhd dii' lieu va bQ nhd chtrong trmh n~m chung trong mot bQ nhd, do d6 ta c6 th€ t6 chtrc, din do'i mQt each linh hoat bQ nhd chtrong trmh va bQ nhd dii' lieu. Tuy nhien dieu nay chi c6 y nghla khi to'c dQ xir li ciia CPU phai r(t cao, VI vdi c(u tnic d6, trong cung mot thCfi di€m CPU chi c6 th€ nrong tac vdi bQ nhd dii' lieu hoac bQ nhd chirong trinh. Nhu v~y c6 th€ n6i kien tnic Von-Neuman khong thich hop vdi c(u tnic ciia mot vi dieu khidn. Do'i vdi kien tnic Havard, bQ nhd dii' lieu va bQ nhd chuong trmh tach ra thanh hai bQ nhd rieng biet. Do d6 trong cung mot thoi di€m CPU c6 th€ nrong tac vdi ca hai bQ nhd, nhu v~y to'c dQ xU'Ii cua vi dieu khi€n diroc cai thien dang k€. MQt di€m cffn chii y mra la t~p lenh trong kien tnic Havard c6 th€ du'<;lC u'u tuy theo yeu to'i cffu kitn tnic cua vi dieu khien rna khong phu thuoc vao c(u tnic dii' lieu. Vi du, do'i vdi vi dieu khi€n dong 16F, dQ dai l~nh luon la 14 bit (trong khi dii' lieu diroc t6 chiic thanh tung byte), con do'i vdi kien tnic Von-Neuman, dQ dai l~nh lucn la bQi so' cua 1 byte (do dii' lieu dircc t6 clnrc thanh tung byte). D~c di€m nay diroc minh hoa cu th€ trong hlnh 1.1.

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Nhu dll trinh bay (j tren, kitn tnic Havard la khai niern mdi hon so vdi kien tnic VonNeuman. Khai niern nay diroc hlnh thanh nham cai titn to'c dQ thuc thi ciia mot vi dieu khi€n. Qua viec tach rCfibQ nhd chuong trmh va bQ nhd dii' lieu, bus chuong trlnh va bus dii' lieu, CPU c6 th€ cung mQt hie truy xudt ca bQ nhd chuong trlnh va bQ nhd dii' lieu, giiip tang to'c dQ xU'Ii ciia vi dieu khi€n len g(p dOi. Dang thoi c(u tnic lenh khong con phu thuoc vao c(u true dii' lieu ntta rna c6 th€ linh dQng dieu chinh tuy theo kha nang va to'c dQ cua tung vi dieu

khien. Vii d€ tie'p tuc cai tie'n to'c d(l thuc thi l~nh, t~p l~nh cua ho vi di€u khi€n PIC diroc thie't ke' sao cho chieu dai rna l~nh luon cd dinh (vi du dO'ivdi ho 16Fxxxx chien dai rna l~nh Iuon Iii 14 bit) vii cho phep thuc thi lenh trong mot chu kl cua xung clock ( ngoai trir met sO' tnrong hop d~c biet nhu lenh nhdy, lenh goi chuong trmh con ... dn hai chu kl xung dang ha). Di€u nay co nghia t~p l~nh cua vi di€u khien thuoc ca'u tnic Havard se it l~nh hen, ngdn hon, don gian hen d€ dap irng yeu du rna hoa l~nh bang mot sO'Iu'<jngbit nha't dinh. Vi di€u khien diroc t6 chtrc theo kien tnic Havard con diroc goi Iii vi di€u khien RISC (Reduced Instruction Set Computer) hay vi di€u khi€n co t~p lenh rut gon. Vi di€u khi€n dircc thie't ke' theo kien tnic Von-Neuman con diroc goi Iii vi di€u khicn CISC (Complex Instruction Set Computer) hay vi di€u khien co t~p lenh phiic tap VI rna l~nh cua no khong phai Iii mot sO'cO'dinh rna Iuon Iii b(li sO'cua 8 bit (1 byte).
1.5

PIPE LINING

Day chinh Iii co che' xii' li l~nh cua cac vi di€u khien PIC. M(lt chu kl lenh cua vi di€u khi€n se bao gam 4 xung clock. Vi du ta sii' dung oscillator co t~n sO'4 MHZ, thl xung lenh se co t~n sO'1 MHz (chu kl lenh se Iii 1 us). Gid sir ta co m(lt doan chirong trmh nhu sau: 1. MOVLW 55h 2. MOVWF PORTB SUB_l 3. CALL PORTA,BIT3 4. BSF 5. instruction @ address SUB_l day ta chi ban de'n qui trmh vi di€u khien xii' li doan chirong trinh tren thong qua tung chu kl lenh. Qua trmh tren se duoc thuc thi nhir sau:

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Ail i~rtnK:tiQrlsere sngie cicie e:<er!t for env P'QQH!r1 o!'?nciles. These t~ke br.,.'ocvces snce ihe feic~ im:truC!.ions is "flusMu" nm "ltle ppetm \Nt-liteme nev'!' ~Istr·uction is tieing felcfleC! ana men e):ecIJteii.

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TCYO: doc l~nh 1 TCYl: thuc thi l~nh 1, doc l~nh 2 TCY2: thirc thi l~nh 2, doc l~nh 3 TCY3: thirc thi l~nh 3, doc l~nh 4. TCY 4: vl lenh 4 khong phai la lenh se du'<;lc thuc thi theo qui trmh thirc thi cua chirong trlnh (lenh tie'p theo diroc thuc thi phai la lenh d~u tien tai label SUB_I) nen chu kl thuc thi l~nh nay chi diroc dung d~ doc l~nh d~u tien tai label SUB_I. Nhu v~y co th~ xem lenh 3 dn 2 chu kl xung clock d~ thuc thi. TCY5: thirc thi l~nh d~u tien ciia SUB_l va dQClenh tie'p theo ciia SUB_I. Qua trinh nay diroc thuc hien tirong tu cho cac l~nh tie'p theo cua chirong trmh. Thong thuong, d~ thuc thi mot lenh, ta dn mot chu kl lenh d~ goi l~nh do, va mot chu kl xung clock ntta d~ giai rna va thuc thi l~nh. Vdi co che' pipe lining du'<;lc trlnh bay (j tren, mc3i l~nh xem nhu chi diroc thuc thi trong mQt chu kl lenh, Do'i vdi cac lenh rna qua trlnh thuc thi no lam thay ddi gia tri thanh ghi PC (Program Counter) dn hai chu kl lenh d~ thuc thi VI phai thuc hien viec goi l~nh (j dia chi thanh ghi PC chi tdi. Sau khi da xac dinh dung vi tri lenh trong thanh ghi PC, mc3il~nh chi dn mot chu kl lenh d~ thuc thi xong. 1.6 CAC DONG PIC vA CACH LljA CHQN VI BlEU KHlEN PIC Cac ki hieu cua vi PICl2xxxx: PICl6xxxx: PICl8xxxx: di€u khien PIC: dQ dai l~nh 12 bit dQ dai l~nh 14 bit dQ dai l~nh 16 bit

C: PIC co bQ nhd EPROM (chi co 16C84la EEPROM) F: PIC co bQ nhd flash LF: PIC co bQ nhd flash hoat dQng (j dien ap thdp LV: tirong tu nhu LF, day la ki hieu Cll Ben canh do mot so' vi dieu khi~n co ki hieu xxFxxx la EEPROM, ne'u co them chtr A (j cudi la flash (vi du PIC16F877la EEPROM, con PIC16F877A la flash). Ngoai ra con co them mot dong vi di€u khi~n PIC mdi la dsPIC. d Vi~t Nam phd bien nha't la cac ho vi di€u khi~n PIC do hang Microchip san xuft, Cach lira chon mot vi di€u khi~n PIC phu hop: Tnrdc he't dn chii y de'n so' chan cua vi di€u khien dn thie't cho ling dung, Co nhieu vi di€u khi~n PIC vdi so' hrong chan khac nhau, tham chi co vi di€u khien chi co 8 chan, ngoai ra con co cac vi di€u khien 28, 40, 44, ... chan.

Cffn chon vi di€u khi€n PIC co b(l nhd flash d€ co th€ nap xoa chirong trlnh diroc nhieu lffn hen, Tie'p theo cffn chii y de'n cac khdi chirc nang diroc tich hop san trong vi dieu khi€n, cac chudn giao tie'p ben trong. Sau cung cffn chii y de'n b(l nhd chirong trmh rna vi di€u khi€n cho phep. Ngoai ra moi thong tin v€ each hra chon vi di€u khi€n PIC co th€ diroc tim tha'y trong cudn sach "Select PIC guide" do nha san xua't Microchip cung ca'p.

1.7 NGON NGU L!P TRINH CHO PIC

Ngon ngii' l~p trmh cho PIC ra't da dang. Ngon ngii' l~p trlnh ca'p thap co MPLAB (duoc cung ca'p mi~n phi bdi nha san xua't Microchip), cac ngon ngii' l~p trinh ca'p cao hon bao gam C, Basic, Pascal, ... Ngoai ra con co mot so' ngon ngii' l~p trmh du'<;lC phat tri€n danh rieng cho PIC nhu PICBasic, MikroBasic, ...

1.8 M~CH N~P PIC

Day ding la mot dong san ph5m ra't da dang danh cho vi di€u khien PIC. Co th€ sa dung cac mach nap diroc cung ca'p bdi nha san xua't la hang Microchip nhir: PICSTART plus, MPLAB ICD 2, MPLAB PM 3, PRO MATE II. Co th€ dung cac san ph5m nay d€ nap cho vi di€u khicn khac thong qua chtrong trlnh MPLAB. Dong san ph5m chinh thong nay co u'u the'la nap diroc cho ta't cac vi di€u khi€n PIC, tuy nhien gia thanh ra't cao va thuong g~p ra't nhieu kho khan trong qua trlnh mua san phdrn.

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Ngoai ra do tinh nang cho phep nhieu che' d(l nap khac nhau, con co ra't nhieu mach nap diroc thie't ke' danh cho vi di€u khien PIC. Co th€ so hroc mot so' mach nap cho PIC nhir sau: JDM programmer: mach nap nay dung chuong trlnh nap Icprog cho phep nap cac vi di€u khicn PIC co hc3 tro tinh nang nap chuong trlnh di~n ap thap ICSP (In Circuit Serial Programming). Hffu he't cac mach nap d€u hc3tro tinh nang nap chuong trlnh nay. WARP-13A va MCP-USB: hai mach nap nay gidng vdi mach nap PICSTART PLUS do nha san xudt Microchip cung ca'p, tirong thich vdi trmh bien dich MPLAB, nghla la ta co th€ true tie'p dung chuong trinh MPLAB d€ nap cho vi di€u khi€n PIC rna khong cffn sa dung m(lt chtrong trlnh nap khac, chang han nhu'ICprog. P16PR040: mach nap nay do Nigel thiet ke' va cung kha n6i tieng. Ong con thie't ke' chircng trmh nap, tuy nhien ta cflng co th€ sa dung chirong trmh nap Icprog.

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Mach nap Universal cua Williem: day khong phai la mach nap chuyen dung danh cho PIC nhu P16PR040. Cac mach nap k~ tren co u'u di~m ra't ldn la don gian, re ti~n, hoan toan co th~ t11Mp rap mQt each d€ dang, va moi thong tin v~ so d6 mach nap, each thie't ke', thi cong, ki~m tra va chirong trlnh nap d~u d€ dang tim diroc va download mien phi thong qua mang Internet. Tuy nhien cac mach nap tren co nhiroc di~m la han che' v~ s6 vi di~u khi~n diroc h6 tro, ben canh do m6i mach nap cffn diroc sti' dung vdi mQt chirong trlnh nap thich hop. 1.9 BOOTLOADER vA ICP (In Circuit Programming)

CHu'(jNG 2 VI DIEU KHIEN PIC16F877A

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'............ 1R~..5WiNi!_ts=fC2O!l.Jlil"' .........., 1;;o~A"'iIJ):ct;;JfC,1 CO.

Hlnh 2.1 Vi di€u khien PIC 16F877AJPIC 16F874A va cac dang so d6 chan

2.2 MQT VAl THONG SO VE VI DIEU KHIEN PIC16F877A Day Hi vi di€u khien thuoc ho PIC16Fxxx vdi t~p l~nh g6m 35 lenh c6 d(l dai 14 bit. M6i l~nh d€u diroc thuc thi trong mot chu ld xung clock. T6c d(l hoat d(lng t6i da cho phep la 20 MHz vdi mot chu kl lenh Ia 200ns. B(l nhd chuong trinh 8Kx14 bit, b(l nhd dii' lieu 368x8 byte RAM va b(l nhd dii' lieu EEPROM vdi dung hrong 256x8 byte. se' PORT I/O la 5 vdi 33 pin 110. Cac d~c tinh ngoai vi bao g6mcac khdi chiic nang sau: TimerO: b(l de'm 8 bit vdi b(l chi a t~n s6 8 bit. Timer1: b(l de'm 16 bit vdi b(l chi a t~n s6, c6 th€ thuc hien clnrc nang de'm dira vao xung clock ngoai vi ngay khi vi di€u khicn hoat d(lng (j che'd(l sleep. Timer2: b(l de'm 8 bit vdi b(l chi a t~n s6, b(l postcaler. Hai b(l Capture/so sanh/di€u che'd(l rong xung. Cac chuan giao tie'p n6i tiep SSP (Synchronous Serial Port), SPI va 12C. Chuan giao tie'p n6i tie'p USART vdi 9 bit dia chi. C5ng giao tie'p song song PSP (Parallel Slave Port) vdi cac chan di€u khi€n RD, WR, CS (j ben ngoai, Cac d~c tinh Analog: 8 kenh chuyen d5i ADC 10 bit. Hai b(l so sanh. Ben canh d6 la mot vai dac tinh khac cua vi di€u khien nhir: B(l nhd flash vdi kha nang ghi x6a dircc 100.000 l~n. B(l nhd EEPROM vdi kha nang ghi x6a diroc 1.000.000 l~n. Dii' lieu b(l nhd EEPROM c6 th€ hill trii' tren 40 nam, Kha nang ttf nap chirong trlnh vdi su di€u khicn cua phdn memo Nap diroc chuong trmh ngay tren mach dien ICSP (In Circuit Serial Programming) thong qua 2 chan. Watchdog Timer vdi b(l dao d(lng trong. Clute nang bao mat rna chuong trmh. Che'd(l Sleep. C6 th€ hoat d(lng vdi nhieu dang Oscillator khac nhau.

A.

....

A.

~~

,:?

2.3 SO DO KHOI VI DIEU KHIEN PIC16F877A

0",.1" 18u5 Ifl~st. IPfllg~lT;l
MEIllOl'{

iRAM F
R.;;gis~el\S

IRAeJANO RA'ifANI IRA2IAN.2Nll.EF-ICVREF

RA:!JM'.J3N~ E F-.

IRA'lfHlCKlfG10Uif IRA&ANo;lI8S~C~OlJi

!Prog'''1Tl Bus·

rr=~~~JVI

P 0.'1 il"B

R81J.11MT R81 Rtl2 R82.fp.G~~ R84 Rtl5 R8fi11F\GC R87f1PGD IRGOIf~QSonrKiJ{1 RG'lfT'iQSlrCCp~ RG2ICCE'1 RG~ISDKtSOl ROIISDIISDA IRG51S00 RC6ff)),CK IRC7!RXMif RDOiPS:?D RDlIPS:P1 RD:2iPSn ROaJPSP3 RD'lIPSP4 RD!jJPS."5 RDfllPSP,EI RD7IPS:?7

!POi'~rcup
Tinter

11\(,'tciJell.~
Tirr.er

O<SG'fGLKI C15G21GLKO

Brm'm-oui
lRe9r.i In~Cirou] O",buggosr Arllgr~.mml~g

LIlI~'·\i'O:;ta~e

Hlnh 2.2 So d6 kh6i vi dieu khi~n PIC16F877 A.

2.4 TO CHUC

BO NHO
bao g6m bQ nhd chtrong trmh (Program

Cau tnic bQ nhd cua vi di€u khi€n PIC16F877A memory) va bQ nhd dii' lieu (Data Memory). 2.4.1

BO NHO

CHUONG TRiNH

BQ nhd chirong trmh cua vi di€u khien PIC 16F877 A la bQ nhd flash, dung hrong bQ nhd 8K word (1 word = 14 bit) va du'<;lC phan thanh nhieu trang (til pageO den page 3) . Nhu vay bQ nhd chtrong trlnh co kha nang chua diroc 8*1024 = 8192 l~nh (vl mot lenh sau khi rna hoa se co dung hrong 1 word (14 bit). D€ rna hca du'<;lc chi cua 8K word dia bQ nhd chuong trmh, bQ d€m chuong trlnh co dung hrong 13 bit (PC<12:0». Khi vi di€u khi€n dircc reset, bQ d€m chirong trmh se chi den dia chi OOOOh (Reset vector). Khi co ng~t xay ra, bQ d€m chtrong trlnh se chi den dia chi 0004h (Interrupt vector). BQ nhd chuong trmh khong bao g6m bQ nhd stack va khong diroc dia chi hoa bdi bQ d€m chtrong trinh, BQ nhd stack se diroc d€ c~p cu th€ trong phdn sau. 2.4.2

CALL, RETURN RETFIE, RETL'I'!

i[_~=n:::::;;' V

t:::===::::;r

31" ak Le'l.fe1 1 :al~ d. L.ewe I .2

Rese-t Veetol
,~

OOt~~h
A

• ~

~
OO~~h OO~5h

On·CiIi;i p c.:;g ram

r=:
In1.;;rru;~t Ve dCI
Page

il1FH, OODDh ilHTti

'ill'~Oh

Page 1

1------------1
Page 2

t~efll~f"l'

Page)

11FH" 'i8DDh

1lFfFh ~~-------~

BO NHO DU

Hlnh 2.3 BQ nhd chuong trlnh PIC16F877 A

LltU

BQ nhd dii' lieu cua PIC la bQ nhd EEPROM diroc chi a ra lam nhieu bank. Do'i vdi PIC16F877A bQ nhd dii' lieu diroc chia ra lam 4 bank. M6i bank co dung hrong 128 byte, bao g6m cac thanh ghi co clnrc nang d~c biet SFG (Special Function Register) nam i'1 cac vung dia chi thfip va cac thanh ghi muc dich chung GPR (General Purpose Register) n~m i'1 vung dia chi con lai trong bank. Cac thanh ghi SFR thuong xuyen du'<;lC dung (vi du nhu thanh sil' ghi STATUS) se diroc d~t i'1 ta't ca cac bank cua bQ nhd dii' lieu giup thuan tien trong qua trinh truy xua't va lam giam bdt l~nh cua chirong trinh, So d6 cu th€ cua bQ nhd dii' lieu PIC16F877A nhu sau:

Frle AdI'dress Ino irect ac:r.dr_(~) oot.

file Ad'~[ress, Ilndic'aDt addr_Ir'1 <SOh OPlfION REG ,s1h PCt STATUS fSR TIRISA TIRISB TIRISC TRISD(!I TRIISE(11 PCIL.4THl INITCONI PIE'n IPIE2 peON >S2h S3h 84h <S5h S6h S7h SBh S9h 3M SBh SCIh .8DIh SEh SRh 90h SSPCON,2 PR:2: SS P;l.![)0 SSPSTAT £l1h 92h 93h 94h 9Sh £l6h 97h 9Bh 99h 9M 9Bh gCIh 9DIh 9Eh 9Rh AGh Gener .. 1 Purpose RegiS'~er 80 Byles EFh FOIh IFFh General Purpose Register 80 Byles Ind ire et addrJ')

Fir-e' ,Address

lFile Ad,[Iress, I ndlreet ,add,r.l('l OPTl:ON REG pet STATUS IFSR llRISEJ. 180h 18'ih 182h 1B3h 1[J;4h 185h 1S6h mlh 1SSh 189h lBAIh 1SBIh,

nitRO
PCl STATUS f.'SR IPORTA IPORm PORTe. PORTI[)111~ PORTE'II~' PClATHI INrTCONI PIIR~ PIIR2 llMRTIIL lrMR1 HI T1CON

mh 02h [Hh []'4h 05h [J6h

'Th:1RO
pel STATUS FSR PORTH

[Un ruh
09h OAhi [JiB hi

WOh 1011h 102h W3h 104h 105h 106h 107h 10Bh 109h 10M 10Bh

PCLA.1H INITCON IEIEIDATA EEA.IDR EEDATIH EE!l;.DR!H

OCh ODh OEhi OFh 10h 1111

men
10:Dh 10:Eh WHn 1WIhi 111h 1121h1 1131h1 1141hi 1151hi 1161hi 11l1h1 11B1h1 1191hi 11A'hi 118'hI 11Ch 11Dh 11Elhi 11Fh 120h

PCLA.1H INfTCON IEIECONI IEIECONi2 ResBrve d,l21 Reserved,!l]

tscn
mOh lSEIh UtFh 190h 19'ih 192h 193h 19.4h 195h 196h 191h 198h 199h 19A1h 19BIh 19Ch 190h 19EIh 19Fh lA,DIh

lM,R]
T2eON SSPBUF SSPCON CCPRiL CCPR,11H1 CCP'jCON RCST.A. TXREG RCIREG CCIF'1R2L CCPR2H CCP2CO~ ADIRESH A,DCONO

12h
1311

14h
15t.

Un

16h
TX8TA 8PBIR.G

Geneml

1St. 19h 1AhI 1Bhi 1Ch 1Dh

Reliisler 16 Bytes

Purpose

General IPmposH IRegister 168Vles

c r.;1 ON C CYRCON
ACDRESL ADCON1

irn
1Fh 2Dh

General IF'ulfiDDse Register 96 Bytes

Geneml Purpose Re~iS'~eIT' 80 Byles 16Fh HGh 1lIRhi TIHIhI TIHlh lFIFIh

IBan'k 0

7Fh

accesses 7mn-7FIh IElllll~ 11

<lccess:es 10 1h1-7FIh, IBanil:2

ao:esses 70h -TRhi l6:,mil: 3

D
t

Note 1: 2:

Unimpl:ement:ed data mel'il1OJYIOCl11iiOTIIS, "'Rad 118 '!J'_ Not .. IPhy.sics IIreg iste. Thsse registers :are nell nmplelJllented, Gill tlhe PIC16FBl6.4._. Tlhese registers are rese:rved; ma~ntain Ifle'Se lreg.islers clear,

Hlnh 2.4 So d6 bQ nhd dii' lieu PIC16F877A

2.4.2.1 THANH GHI CHUC NANG D~C BItT

SFR

Day la cac thanh ghi dircc sti' dung bdi CPU hoac du'<;ledung d€ thie't l~p va di€u khien cac khdi clnrc nang du'<;letich hop ben trong vi di€u khien, C6 th€ phan thanh ghi SFR lam hai loai: thanh ghi SFR lien quan de'n cac chuc nang ben trong (CPU) va thanh ghi SRF dung d€ thie't l~p va di€u khi€n cac khdi chuc nang ben ngoai (vi du nhu ADC, PWM, ...). Ph~n nay se d€ e~p de'n cac thanh ghi lien quan de'n cac chiic nang ben trong. Cac thanh ghi dung d€ thie't l~p va di€u khidn cac khdi chuc nang se diroc nhac de'n khi ta d€ e~p de'n cac khdi chirc nang d6. Chi tie't v€ cac thanh ghi SFR se diroc li~t ke cu th€ trong bang phu luc 2. Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi chua ke't qua thirc hien phep toan ella khdi ALU, trang thai reset va cac bit chon bank dn truy xua't trong bQ nhd dfi' lieu,
IRfiA!-O ~RP ~i17 IRfIN-'O RP1 RJW-O RIPO I R-1 TO R-'I PO fi:JIN-x RMI-x GC RNII-x C

z:

Thanh ghi OPTION_REG (81h, 181h): thanh ghi nay eho phep doc va ghi, eho phep di€u khicn chtrc nang pull-up ella cac chan trong PORTB, xac l~p cac tham sO'v€ xung tac dQng, canh tac dQng ella ng~t ngoai vi va bQ de'm TimerO.

RfiN-,lI

RfiII!'-1

RlW-,1

RfW-'~ I '"f08E I

RiVi/-1

PJ'lIrI-lI
PS2

IRNIJ-l IPS1
PS[l

RBlPU bit 7

IIINTIEIDG I llDCS

P'SA

lJ.;it(]I

Thanh ghi INTCON (OBh, 8Bh,10Bh, 18Bh):thanh ghi eho phep doc va ghi, chua cac bit di€u khien va cac bit eCl hieu khi timerO bi tran, ngdt ngoai vi RBOIINT va ngdt interrputon-change tai cac chan ella PORTB.
R{I;I\!'-iQ

GillE
~it 7

RfW-O

PIEIE

IlfMRlJlE I

R{W-{J

R/1iIt..,o INilE RB~IE

I TMROHF I

INTF

RtII"i!'-x RB'IIF ~it [l

Thanh ghi PIEI nang ngoai vi.

(8Ch): chua cac bit di€u khi€n chi tie't cac ngdt ella cac khdi chiic
RJVV-D RCIIE RfW-O TXIIE RiW-O SSPIE

I PSPIEI11] lADlE
bit 7

RiV\,r-o

R/W,-O

I CCPUE I irMR21E I TMR11E I

bit 0

Thanh ghi PIRI (OCh) chua eCl ngat ella cac khdi chirc nang ngoai vi, cac ngat nay dircc eho phep bdi cac bit di€u khien chua trong thanh ghi PIEl.

RM'-iJ
tl'jt 7

lPS!PIFI111

RfW"O A[!IIF

R-O IRCIF

1R-iJ lXIF

RAIV-O SSPIF

RiW-O CC!PlIIF

IRMt-O

Rf'W-O

TMR21F

lMRHIF bit 0

Thanh ghi PIE2 (8Dh): chua cac bit di€u khi€n cac ng~t ella cac khdi clnrc nang CCP2, SSP bus, ng~t ella bQ so sanh va ng~t ghi vao bQ nhd EEPROM.

u-o
CMIE tD'it7

RlW-O EEIIE

RlW-O BeLIE

U-O

LI-O

IR1W-'O I OCP21E I bit 0

Thanh ghi PIR2 (ODh): chua cac cClngdt cua cac khdi chtrc nang ngoai vi, cac ng~t nay diroc cho phep bdi cac bit di€u khi€n chua trong thanh ghi PIE2_
U-Iil beill

IR1W"O GMI'F

un

RlW-O IEEIF

RJW-[1 BCUf

Ul{J

u-o

I CCP'1lf I
blt [)

Thanh ghi PCON (8Eh): chua cac cClhieu cho biet trang thai cac che'dQ reset cua vi di€u khien. IRfiM-{l u-tJ u-o u-o u-o
IPUR BOH bit 0

2.4.2.2 THANH GHI MVC

ntcn

CHUNG GPR

Cac thanh ghi nay co th€ diroc truy xudt tnrc tiep hoac gian tiep thong qua thanh ghi FSG (File Select Register). Day la cac thanh ghi dii' lieu thong thuong, nguai sii' dung co th€ tuy theo muc dich chtrong trmh rna co th€ dung cac thanh ghi nay d€ chua cac bien so', h~ng so', ke't qua hoac cac tharn so' phuc vu cho chuong trmh. 2.4.3 STACK Stack khong n~rn trong bQ nhd chirong trmh hay bQ nhd dii' lieu rna la mot vung nhd d~c biet khong cho phep doc hay ghi. Khi lenh CALL diroc thuc hien hay khi mot ngdt xay ra lam chuong trinh bi re nhanh, gia tri cua bQ de'rn chuong trinh PC t\f dQng diroc vi di€u khi€n c(t vao trong stack. Khi mot trong cac l~nh RETURN, RETLW hat RETFIE dircc thuc thi, gia tri PC se t\f dQng diroc l(y ra tu trong stack, vi di€u khi€n se thuc hien tie'p chuong trinh theo dung qui trinh dinh tnrdc. BQ nhd Stack trong vi di€u khi€n PIC ho l6F87xA co kha nang chua du'Qc 8 dia chi va hoat dQng theo co che' xoay vong. Nghia la gia tri c(t vao bQ nhd Stack lffn thti 9 se ghi de len gid tri c(t vao Stack lffn dffu tien va gia tri c(t vao bQ nhd Stack lffn thti 10 se ghi de len gia tri6 c(t vao Stack lffn thti 2. Cffn chti y la khong co cClhieu nao cho biet trang thai stack, do do ta khong bie't diroc khi nao stack tran. Ben canh do t~p l~nh ciia vi di€u khi€n dong PIC cting khong co l~nh POP hay PUSH, cac thao tac vdi bQ nhd stack se hoan toan diroc di€u khi€n bdi CPU.

2.5 CAC CONG XUAT NH~P CUA PIC16F877A C5ng xudt nhap (I/O port) chinh la phirong tien rna vi di€u khien dung d€ tirong tac vdi the' gidi ben ngoai. Su nrong tac nay r(t da dang va thong qua qua trmh tirong tac d6, clnrc nang cua vi di€u khien diroc th€ hien mot each ro rang. MQt c5ng xu(t nhap cua vi di€u khi€n bao g6m nhieu chan (I/O pin), tuy theo each bo' tri va chirc nang ciia vi di€u khi€n rna so'lu'<_1ng c5ng xuft nhap va so' hrong chan trong m6i c5ng c6 th€ khac nhau. Ben canh d6, do vi di€u khien diroc tich hop san ben trong cac dac tinh giao tie'p ngoai vi nen ben canh chiic nang la c5ng xudt nhap thong thtrong, mot so' chan xu(t nhap con c6 them cac chuc nang khac d€ th€ hien stf tac dQng ciia cac d~c tinh ngoai vi neu tren do'i vdi the' gidi ben ngoai. Chiic nang cua tung chan xudt nhap trong m6i c5ng hoan toan c6 th€ diroc xac l~p va di€u khicn diroc thong qua cac thanh ghi SFR lien quan de'n chan xu(t nhap d6. Vi di€u khien PIC16F877A c6 5 c5ng xudt nhap, bao g6m PORTA, PORTB, PORTC, PORTD va PORTE. Cau tnic va chiic nang cua tung c5ng xu(t nhdp se diroc d€ c~p cu th€ trong phdn sau. 2.5.1 PORTA PORTA (RPA) bao g6m 6 I/O pin. Day la cac chan "hai chieu" (bidirectional pin), nghia la c6 th€ xudt va nhap diroc. Clnrc nang I/O nay diroc di€u khien bdi thanh ghi TRISA (dia chi 85h). Mudn xac l~p clnrc nang cua mQt chan trong PORTA la input, ta "set" bit di€u khi€n nrong irng vdi chan d6 trong thanh ghi TRISA va ngiroc lai, mudn xac l~p chirc nang cua mot chan trong PORTA la output, ta "clear" bit di€u khi€n nrong irng vdi chan d6 trong thanh ghi TRISA. Thao tac nay hoan toan tirong ttf do'i vdi cac PORT va cac thanh ghi di€u khi€n nrong irng TRIS (do'i vdi PORTA la TRISA, do'i vdi PORTB la TRISB, do'i vdi PORTC la TRISC, do'i vdi PORTD la TRISD vado'i vdi PORTE la TRISE). Ben canh d6 PORTA con la ngo ra ciia bQ ADC, bQ so sanh, ngo vao analog ngo vao xung clock cua TimerO va ngo vao ciia bQ giao tie'p MSSP (Master Synchronous Serial Port). D~c tinh nay se diroc trmh bay cu th€ trong phan sau.
Cau tnic ben trong va chirc nang cu th€ cua tung chan trong PORTA se diroc trlnh bay

,,Q

,..,

A.

cu th€ trong Phu luc 1. Cac thanh ghi SFR lien quan de'n PORTA bao g6m: PORTA (dia chi 05h) TRISA (dia chi 85h) CMCON (dia chi 9Ch) CVRCON (dia chi 9Dh) : chua gid tri cac pin trong PORTA. : di€u khien xuft nhap. : thanh ghi di€u khien bQ so sanh. : thanh ghi di€u khi€n bQ so sanh dien ap,

ADCON1 (dia chi 9Fh) : thanh ghi dieu khi~n bQ ADC. Chi titt ve cac thanh ghi se diroc trmh bay cu th~ trong phu luc 2. 2.5.2 PORTB PORTB (RPB) gam 8 pin 1/0. Thanh ghi dieu khien xuft nhap nrong irng la TRISB. Ben canh d6 mot scschan cua PORTB con dtroc sii' dung trong qua trmh nap chirong trlnh cho vi dieu khien vdi cac cht dQ nap khac nhau. PORTB con lien quan dtn ngat ngoai vi va bQ TimerO. PORTB con diroc tich hop chiic nang dien trd keo len diroc dieu khien bdi chirong trinh. Ca'u tnic ben trong va chirc nang cu th~ cua tung chan trong PORTB se du'<;lC trmh bay cu th~ trong Phu luc 1. Cac thanh ghi SFR lien quan dtn PORTB bao gam: PORTB (dia chi 06h,106h) : chua gia tri cac pin trong PORTB TRISB (dia chi 86h,186h) : dieu khien xua't nhap OPTION_REG (dia chi 81h,181h) : dieu khien ngdt ngoai vi va bQ TimerO. Chi titt ve cac thanh ghi se diroc trmh bay cu th~ trong phu luc 2. 2.5.3 PORTC PORTC (RPC) gam 8 pin 1/0. Thanh ghi dieu khien xuft nhap nrong irng la TRISC. Ben canh d6 PORTC con chua cac chan chiic nang cua bQ so sanh, bQ Timed, bQ PWM va cac chudn giao titp ncSitiep 12C, SPI, SSP, USART. ca'u tnic ben trong va chirc nang cu th~ cua tung chan trong PORTC se du'<;lC trmh bay cu th~ trong Phu luc 1. Cac thanh ghi dieu khien lien quan dtn PORTC: PORTC (dia chi 07h) : chua gia tri cac pin trong PORTC TRISC (dia chi 87h) : dieu khien xua't nhap. Chi titt ve cac thanh ghi se diroc trmh bay cu th~ trong phu luc 2. 2.5.4PORTD PORTD (RPD) gam 8 chan 110, thanh ghi dieu khien xua't nhap tircng tmg la TRISD. PORTD con la c6ng xua't dii' lieu ciia chuan giao titp PSP (Parallel Slave Port). Cau tnic ben trong va chtrc nang cu th~ cua tung chan trong PORTD se diroc trmh bay cu th~ trong Phu luc 1. Cac thanh ghi lien quan dtn PORTD bao gam: Thanh ghi PORTD : chua gia tri cac pin trong PORTD. Thanh ghi TRISD : dieu khien xua't nh~ p. Thanh ghi TRISE : dieu khien xuft nhap PORTE va chuan giao titp PSP. Chi titt ve cac thanh ghi se diroc trmh bay cu th~ trong phu luc 2.

2.5.5 PORTE PORTE (RPE) g6m 3 chan 1/0. Thanh ghi di€u khien xua't nhap tuong irng la TRISE. Cac chan ella PORTE co ngo vao analog. Ben canh do PORTE con 1a cac chan di€u khicn ella chudn giao tie'p PSP. Ca'u true ben trong va chiic nang cu th€ ella tung chan trong PORTE se du'<;1e trinh bay cu th€ trong Phu luc 1. Cac thanh ghi lien quan de'n PORTE bao g6m: PORTE : chua gia tri cac chan trong PORTE. TRISE : di€u khicn xudt nhap va xac l~p cac thong scseho chudn giao tiep PSP. ADCON1 : thanh ghi di€u khien khdi ADC. Chi tie't v€ cac thanh ghi se diroc trmh bay cu th€ trong phu luc 2. 2.6 TIMER 0 Day la mot trong ba bQ de'm hoac bQ dinh thoi ella vi di€u khi€n PIC16F877A. TimerO la bQ de'm 8 bit diroc ke't ncSivdi bQ chi a t~n scs (presea1er) 8 bit. Ca'u tnic ella TimerO eho phep ta lua chon xung clock tac dQng va canh tich cue ella xung clock. Ngat TimerO se xua't hien khi TimerO bi tran, Bit TMROIE (INTCON<5» la bit di€u khien ella TimerO. TMROIE=l eho phep ngdt TimerO tac dQng, TMROIF= 0 khong eho phep ngdt TimerO tac dQng. Sd d6 khcSiella TimerO nhu' sau:
CI!.~OI=lFo~4)-_--------------,

RA4ff.c~DKI tnn ~

f\/1
il"OSE

I
PSA

Sync 2
CJl~Ie.!l

SB~ A~ hitTMROUf
on OIo'MOO!

,-----------,

PRES CALER

PS2PS(]
PSA
L

I
-1

PSA
WDT

liillle-'oLJi
II-Io-te::rues, HISlE, PSA, PS2:P.SO are [OPTION_REG~:O>jc

Hlnh 2.5 Sd d6 khdi ella TimerO.

Mudn TimerO hoat dQng d che'dQ Timer ta clear bit TOSC (OPTION_REG<5», khi do gitl tri thanh ghi TMRO se tang theo tung chu kl xung d6ng h6 (tffn so' vao TimerO bang 1A tffn so' oscillator). Khi gia tri thanh ghi TMRO tu FFh trd ve OOh, ngdt TimerO se xuft hien. Thanh ghi TMRO cho phep ghi va xoa diroc giiip ta a'n dinh thci di€m ngdt TimerO xua't hien mQt each linh dQng. Khi do xung tac dQng len bQ de'm du'<jcla'y tu chan RA4/TOCKl. Bit TOSE (OPTION_REG<4» cho phep lua chon canh tac dQng vao bQt de'm. Canh tac dQng se la canh len neu TOSE=O va canh tac dQng se la canh xuong ntu TOSE=l. Khi thanh ghi TMRO bi tran, bit TMROIF (INTCON<2» se diroc set. Day chinh la cCf ngat cua TimerO. CCfng~t nay phai diroc xoa bang chtrong trmh tnrdc khi bQ de'm b~t dffu thuc hien lai qua trlnh de'm. Ng~t TimerO khong th€ "danh thiic" vi dieu khi€n tu che' dQ sleep. BQ chi a tffn so' (prescaler) dtroc chi a se gifta TimerO va WDT (Watchdog Timer). Dieu do co nghfa la neu prescaler diroc sil' dung cho TimerO thl WDT se khong co diroc h6 tro cua prescaler va nguoc lai. Prescaler dircc dieu khien bdi thanh ghi OPTION_REG. Bit PSA (OPTION_REG<3» xac dinh do'i tuong tac dQng cua prescaler. Cac bit PS2:PSO (OPTION_REG<2:0» xac dinh ti so' chia tffn so' cua prescaler. Xem lai thanh ghi OPTION_REG d€ xac dinh lai mot each chi tie't ve cac bit dieu khien tren, Cac l~nh tac dQng len gia tri thanh ghi TMRO se xoa che' dQ hoat dQng ciia prescaler. Khi do'i urong tac dQng la TimerO, tac dQng len gia tri thanh ghi TMRO se xca prescaler nhimg khong lam thay d6i do'i tuong tac dQng cua prescaler. Khi do'i tuong tac dQng la WDT, l~nh CLRWDT se xoa prescaler, d6ng thCfiprescaler se ngung tac vu h6 tro cho WDT. Cac thanh ghi dieu khien lien quan de'n TimerO bao g6m: TMRO (dia chi Olh, lOlh) : chua gia tri de'm cua TimerO. INTCON (dia chi OBh, 8Bh, lOBh, l8Bh): cho phep ng~t hoat dQng (GIE va PEIE). OPTION_REG (dia chi 81h, l8lh): dieu khien prescaler. Chi titt ve cac thanh ghi se diroc trmh bay cu th€ trong phu luc 2.
Mudn TimerO hoat dQng d che'dQ counter ta set bit TOSC (OPTION_REG<5».

2.7TIMERI
Timerl la bQ dinh thoi 16 bit, gia tri cua Timerl se diroc hill trong hai thanh ghi (TMRIH:TMRIL). CCf ngdt ciia Timerl la bit TMRlIF (PIRI<O». Bit dieu khien cua Timerl se la TMRlIE (PIE<O». Tuong tu nhu Timerf), Timerl ding co hai che' dQ hoat dQng: che'dQ dinh thoi (timer) vdi xung kich la xung clock cua oscillator (tffn so' cua timer bang 1Atffn so' cua oscillator) va cht dQ dtm (counter) vdi xung kich la xung phan anh cac su kien dn dtm la'y tir ben ngoai

thong qua chan RCO/TIOSO/TICKI (canh tac dQng la canh len). Viec lua chon xung tac dQng (nrong irng vdi viec hra chon che' dQ hoat dQng la timer hay counter) diroc di€u khien bdi bit TMRICS (TICON<l». Sau day la so d6 khdi cua Timerl:
SE'i FI<lg bi. llMR'IIF [In
Qv.,.rfl);wl .~

. TMR1H

--,TMRi__

--,

Clock l"pul

TMR'll

~ lTMR'ION
On!Off

RDomosom

OKJ

:<
RC'I{f,aSIfCcP2t~1 ~

..
TIC«PSI llMR'ICS :nCK~S1J

Note 1: !/IJhpnilw T 103CEN b"l is oleillJE;d. he im,'eriE'ri5 i~m6d ffif i

his eI.nin,.tes pcwe. drain.

Hlnh 2.6 Sd d6 khdi ciia Timerl. Ngoai ra Timer! con co chiic nang reset input ben trong diroc di€u khien bdi mQt trong hai khdi CCP (Capture/Compare/PWM). Khi bit TIOSCEN (TICON<3» dircc set, Timer! se la'y xung clock til hai chan RCIITIOSIICCP2 va RCO/TIOSOITICKI lam xung de'm. Timer! se b~t dffu de'm sau canh xuong dffu tien cua xung ngd vao, Khi do PORTC se bi) qua su tac dQng cua hai bit TRISC<l:O> va PORTC<2:1> dtroc gan gia tri o. Khi clear bit TIOSCEN Timer! se la'y xung de'm til oscillator hoac til chan RCO/TIOSO/TICKI. Timer! co hai che' dQ de'm la d6ng bQ (Synchronous) va ba't d6ng bQ (Asynchronous). Che'dQ de'm du'<;lc quyet dinh bdi bit di€u khien i~SYNC (TICON<2». Khi lflSYNC =1 xung de'm la'y til ben ngoai se khong diroc d6ng bQ hoa vdi xung clock ben trong, Timer! se tie'p tuc qua trmh de'm khi vi di€u khien dang d che'dQ sleep va ngat do Timer! tao ra khi bi tran co kha nang "danh thiic" vi di€u khi€n. d che'dQ de'm ba't d6ng bQ, Timer! khong th€ dircc sa dung d€ lam ngudn xung clock cho khdi CCP (Capture/Compare/Pulse width modulation). Khi i~SYNC =0 xung de'm vao Timerl se diroc d6ng bQ hoa vdi xung clock ben trong. d che'dQ nay Timer! se khong hoat dQng khi vi di€u khien dang d che'dQ sleep. Cac thanh ghi lien quan de'n Timerl bao g6m: INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): cho phep ngdt hoat dQng (GIE va PEIE). PIRI (dia chi OCh): chua cClng~t Timer! (TMRlIF). PIE1( dia chi 8Ch): cho phep ngdt Timerl (TMRlIE). TMRIL (dia chi OEh): chua gia tri 8 bit tha'p cua bQ de'm Timerl. TMRIH (dia chi OEh): chua gia tri 8 bit cao cua bQ de'm Timerl. TICON (dia chi 10h): xac l~p cac thong s6 cho Timerl. Chi tie't v€ cac thanh ghi se diroc trmh bay C1:l th€ trong phu luc 2.

2.8 TIMER2 Timer2 la bQ dinh thci 8 bit va diroc h6 tro bdi hai bQ chi a tffn s6 prescaler va postscaler. Thanh ghi chua gia tri de'm cua Timer2 la TMR2. Bit cho phep ng~t Timer2 tac dQng la TMR20N (T2CON<2». C~ ngat cua Timer2 la bit TMR21F (PIR1<1». Xung ngo vao (tffn s6 bang JA tffn s6 oscillator) diroc dira qua bQ chia tffn s6 prescaler 4 bit (vdi cac ti s6 chia tffn s6 la 1:1, 1:4 hoac 1:16 va diroc di€u khien bdi cac bit T2CKPS1:T2CKPSO (T2CON<1 :0>)).
Sets !Fle.;;!1
blt TMR211!F

lfMR2

OlJ..lrtpu~,~11}

lf2DlJJIlPS3.: 1I:20UTIPSO
N;;JI~:e'ill: TMR2 ue;giSt'811 10lU~put, C<I11I[tile sOJjj:~-'!.!'aIF8':S8~8C~OO IIJ:Ytitle. SSP mooIJ.J1e ,as BI ~1J.J:d dClck_

Hlnh 2.7 Sci d6 khdi Timer2. Timer2 con diroc h6 tro bdi thanh ghi PR2. Gia tri de'm trong thanh ghi TMR2 se tang tu OOh de'n gia tri chua trong thanh ghi PR2, sau do du'<;lc reset v€ OOh. Kh I reset thanh ghi PR2 du'<;lC nhan gia tri mac dinh FFh. Ng5 ra cua Timer2 diroc dira qua bQ chia tffn s6 postscaler vdi cac rmic chia tu 1:1 de'n 1:16. Postscaler ducc di€u khien bdi 4 bit T20UTPS3:T20UTPSO. Ng5 ra ciia postscaler dong vai tro quyet dinh trong viec di€u khien c~ ngdt, Ngoai ra ngo ra ciia Timer2 con diroc ke't n6i vdi khdi SSP, do do Timer2 con dong vai tro t40 ra xung clock d6ng bQ cho khdi giao tie'p SSP. Cac thanh ghi lien quan de'n Timer2 bao g6m: INTCON (dia chi OBh, 8Bh, lOBh, 18Bh): cho phep toan bQ cac ngdt (GIE va PEIE). PIRI (dia chi OCh): chua c~ ngdt Timer2 (TMR2IF). PIEI (dia chi 8Ch): chua bit di€u khien Timer2 (TMR2IE). TMR2 (dia chi l l h): chua gia tri de'm cua Timer2. T2CON (dia chi 12h): xac l~p cac thong s6 cho Timer2.

PR2 (dia chi 92h): thanh ghi h6 tro cho Timer2. Chi tie't ve cac thanh ghi se diroc trmh bay C1:l thS trong phu luc 2. Ta co mot vai nhan xet ve TimerO, Timerl va Timer2 nhu sau: TimerO va Timer2 la bQ de'm 8 bit (gia tri de'm to'i da la FFh), trong khi Timer l la bQ de'm 16 bit (gia tri de'm to'i da la FFFFh). TimerO, Timerl va Timer2 deu co hai che' dQ hoat dQng la timer va counter. Xung clock co tffn so' bang JA tffn so' ciia oscillator. Xung tac dQng len TimerO diroc h6 tro bdi prescaler va co thS diroc thiet l~p i'1 nhieu che'dQ khac nhau (tffn so' tac dQng, canh tac dQng) trong khi cac thong so' cua xung tac dQng len Timerl la co' dinh. Timer2 diroc h6 tro bdi hai bQ chia tffn so' prescaler va postcaler dQc l~p, tuy nhien canh tac dQng v~n diroc co' dinh la canh len. Timerl co quan ht%vdi khdi CCP, trong khi Timer2 diroc ke't no'i vdi khdi SSP. MQt vai so sanh se giiip ta d€ dang Iva chon diroc Timer thich hop cho ling dung,

2.9ADC
ADC (Analog to Digital Converter) la bQ chuyen d6i tin hieu giii'a hai dang tu'dng tv va so'. PIC16F877A co 8 ngo vao analog (RA4:RAO va RE2:REO). Hieu dit%nthe' chuan VREF co thS diroc Iva chon la VDD, Vss hay hieu dien thS chuan diroc xac l~p tren hai chan RA2 va RA3. Ke't qua chuyen d6i tll' tin tieu nrong tv sang tin hieu so'la 10 bit so' nrong ling va diroc hill trong hai thanh ghi ADRESH:ADRESL. Khi khong sti' dung bQ chuyen d6i ADC, cac thanh ghi nay co thS diroc sti' dung nhu cac thanh ghi thong thuong khac. Khi qua trlnh chuyen d6i hoan ta't, ke't qua se diroc hill vao hai thanh ghi ADRESH:ADRESL, bit
SO/DONE

(ADCONO<2»

diroc xoa ve 0 va cC1 ngdt ADIF diroc set.

Qui trlnh chuyen d6i tll' nrong tv sang so' bao gam cac birdc sau: 1. Thie't l~p cac thong so' cho bQ chuyen d6i ADC: Chon ngo vao analog, chon dien ap m~u (dua tren cac thong so' cua thanh ghi ADCONl) Chonh kenh chuyen d6i AD (thanh ghi ADCONO). Chonh xung clock cho kenh chuyen d6i AD (thanh ghi ADCONO). Cho phep bQ chuyen d6i AD hoat dQng (thanh ghi ADCONO). 2. Thie't l~p cac cC1 ng~t cho bQ AD Clear bit ADIF. Set bit ADIE. Set bit PEIE. Set bit GIE.

3. Doi cho tdi khi qua trmh Ia'y mfiu hoan ta't. 4. B~t dffu qua trinh chuyen d6i (set bit GOfDONE). 5. Dei cho tdi khi qua trmh chuyen d6i hoan ta't bang each: ------Ki€m tra bit GOJ[lONE . Ne'u GOmONE: =0, qua trlnh chuyen d6i dff hoan ta't. Ki€m tra cClngat. 6. DQc ke't qua chuyen d6i va x6a cClngat, set bit GOmONE, (neu dn tiep tuc chuyen d6i). 7. Tie'p tuc thuc hien cac birdc 1 va 2 cho qua trlnh chuyen d6i tie'p theo.

CIH!S2:CHSD

LL l
~

.
RE2I;\,N[.i1'1 RE1IANB,II} REOJANSI1],

,~

V.~.IN

'~RA5lAN4 I~AN3f"REF+

[lf1J!oIJiVollal}e) AID Converter

RA,:21ANQNREFRA1!AN1

{Ref6!f.moo

'\k.I~:;ge)

. -11 rl- ,
IF'CFG:]JPCFGO

PCfG3:PCFGO

Hlnh 2.8 So d6 khdi bQ chuyen d6i ADC. Cffn chii y la c6 hai each hill ke't qua chuyen d6i AD, viec lua chon each hill diroc di~u khien bdi bit ADFM va diroc minh hoa cu th€ trong hlnh sau:

PiDfM

=:1.

---__.-"--_',"

2107

'1]765,

I ~mmHDO
ADRESH

I
ADRESL

I ADRIESH
"yr'"". _-'

IDODO 00

'--~

1O-bil Re stilt R:igll1,Ju~1ffied

TIO-bi~ ResUillit

Hinh 2.9 Cac each hru ke't qua chuyen d6i AD. Cac thanh ghi lien quan de'n bQ chuyen d6i ADC bao gam: INTCON PIR1 (dia PIE1 (dia ADRESH d6iAD. ADCONO (dia chi 1Fh) va ADCON1 (dia chi 9Fh): xac l~p cac thong sa cho bQ chuyen d6i AD. PORTA (dia chi 05h) va TRISA (dia chi 85h): lien quan de'n cac ngo vao analog a PORTA. PORTE (dia chi 09h) va TRISE (dia chi 89h): lien quan de'n cac ngo vao analog a PORTE. Chi tie't v€ cac thanh ghi se diroc trmh bay cu th€ 2.10 COMPARATOR BQ so sanh bao gam hai bQ so so sanh tin hieu analog va diroc d~t a PORTA. Ng5 vao bQ so sanh la cac chan RA3:RAO, ngo ra la hai chan RA4 va RA5. Thanh ghi di€u khi€n bQ so sanh la CMCON. Cac bit CM2:CMO trong thanh ghi CMCON dong vai tro chon lua cac che' dQ hoat dQng cho bQ Comparator (hlnh 2.10). Co che' hoat dQng cua bQ Comparator nhu sau: (dia chi OBh, 8Bh, lOBh, 18Bh): cho phep cac ng~t (cac bit GIE, PEIE). chi OCh): chua cCfngdt AD (bit ADIF). chi 8Ch): chua bit di€u khien AD (ADIE). (dia chi 1Eh) va ADRESL (dia chi 9Eh): cac thanh ghi chua ke't qua chuyen

a phu

luc 2.

Tin hieu analog (j chan VIN + se diroc so sanh vdi dien ap chuan (j chan VIN- va tin hieu (j ngfi fa bQ so sanh se thay d6i nrong ling nhir hmh vc. Khi di~n ap (j chan VIN+ldn hen di~n ap (j chan VIN+ngo fa se (j mire 1 va nguoc 19-i. Dua vao hmh ve ta th(y dap ling tai ngo fa khong phai la nrc thCfiso vdi thay d6i tai ngo vao rna dn co mQt khoang thoi gian nh(t dinh dS ngo fa thay d6i trang thai (t6i da la 10 us). C~n chii y den khoang thoi gian dap ling nay khi sti' dung bQ so sanh. Cue tinh cua cac bQ so sanh co thS thay d6i dua vao cac gia tri d~t vao cac bit C2INV va CUNY (CMCON<4:5».

VUN+

---

;..~

.,

..

. .. .......

outP~.lt:

V~N- ---I v--'

/"

Oulp~.lt

Hlnh 2.10 Nguyen li hoat dQng cua mot bQ so sanh don gian.

G()mP.J~reIIJrs Off CM2:CMO ,= J! l1.l..

[~POR[Ieilmii

Varll'J:e~

RAWANO

.i:-__;,,;~

RAOIANO

.s,

RA31AN3 _:"_:_'. -------i

RA.3iAN3I __!gi_

Off (Read 1]"" '0')

RA.'IIAN1

.s,

RA.2lAN2 .J;L
11"wo, In depe\l"ldlent 'CM2:iCM® = D'U

Off (Rearl

8$ •

o')

T I'ii'D' In de pen de nt C 0:1'11 PI'U1l.I.oI',s: 'CM2::CIMO = OlLO RAotANO A

VI~- ~ ..

COJlllpar<lto:r.s: wi1l1li OutPllIts,

RA3tAN3 _:~-,---- ' _"'T_, __

"I'~ + C1·.·.·
1

ClOUT

C10lLnr

RATIlAN1 RA2lAN2

_:k_:_" __
---,'_o_"
I".

V..:..:I:..:.."-_'I'~~,. ".!_.·H----1I .,,,

__

!+..'-C.Y V 2.'

C"2:0UT R.l\.5-1AN4/SSi'C:20Ui

C20lLnr

TWI:l' Com IlrilOllil1 ererll,mce B

1))Dm;plllfmOf'O'

'CM2~CIMO =

UI)

Two Comrnen Reference C,"'l:2:CMi!I= ;!!O;!! A

COJ'llpaHltO:F!3: .....th Ouipl!llis, i

RAOlANO _:...._ __;,,;'v'I"-"-_, _:_. .. 'v'1~~

C1

ClOUT

RA.3fAN3

Vl'-l+ ~

..

ClOUT

RAAfTClCKl{ClI
RA UAN~ -"-'. -l---'-'~ RA2lAN2 C"2:0UT

--+------1
A

our

_Q_

IRA1JAN1

1RA21AN.2

C2DUT

Fou:r 1.lIiijllltS. Mu1itilPi e;.;e;ci '~ClI 'l'wo Comp:;mlm,s CM2:CMO ,= l! lL~'

RAWANO
RA3tAN3

VI~~ ~ VI~"+

1+ C1
l

\In· I"

ClOUT
\{M,

,+/'

C~

C10Ulf

Rl!!MlITIOKlfCl0UT

--------'
_Q_
__!L_ VI~-

RATIlANl
RA2lAN2

1 by-t:~
VI~"+

RA.1fAN1

---(J

RA2fAN2 ~ A
Oifi [Read as '0')

CIS'=

1.

C20Ulf

Hinh 2.11 Cac ehe' d(l hoat d(lng cua b(l comparator. Cac bit C20UT va ClOUT (CMCON<7:6» dong vai tro ghi nhan sl! thay d6i tin hieu analog so vdi dien ap d~t tnrdc. Cac bit nay dn diroc xii' li thich hop bang chuong trinh dS ghi nhan sl! thay d6i ciia tin hieu ngo vao. CC1ngat cua b(l so sanh 130 CMIF (thanh ghi PIRl). CC1 bit ngdt nay phai diroc reset v~ O. Bit di~u khiSn b(l so sanh 130 CMIE (Tranh ghi PIE). bit

Cac thanh ghi lien quan de'n bQ so sanh bao g6m: CMCON (dia chi 9Ch) va CVRCON (dia chi 9Dh): xac l~p cac thong s6 cho bQ so sanh. Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): chua cac bit cho phep cac ngat (GIE va PEIE). Thanh ghi PIR2 (dia chi ODh): chua cCl ngat ciia bQ so sanh (CMIF). Thanh ghi PIE2 (dia chi 8Dh): chua bit cho phep bQ so sanh (CNIE). Thanh ghi PORTA (dia chi 05h) va TRISA (dia chi 85h): cac thanh ghi di~u khien PORTA. Chi tie't v~ cac thanh ghi se diroc trlnh bay cu thS trong phu luc 2. 2.10.1

BO T~O

DltN

AP SO SANH

BQ so sanh Khi d6 cac CIS = 1) se va C2 (xem bQ t9-0 dien sau:

nay chi hoat dQng khi bQ Comparator duoc dinh dang hoat dQng d che'dQ '110'. pin RAO/ANO va RAI/ANI (khi CIS = 0) hoac pin RA3/AN3 va RA2/AN2 (khi la ngo vao analog cua dien ap cffn so sanh dira vao ngo Vrw cua 2 bQ so sanh Cl chi tie't d hlnh 2.10). Trong khi d6 dien ap dua vao ngo VIN+ se diroc la'y tu mot ap so sanh, So d6 khdi cua bQ t9-0 dit$n ap so sanh duoc trmh bay trong hlnh ve

16 smge;a eVREN-[:>v-q
8R R

''I/VI,-V
r-CVRR

RA2IAN2iVil.Ef·{CV",u

Ilnp!Jlj

C1J.'t1:F

C ornp ..ralor

to __

--------''-----t

CVR3 CVR2

CVR1

CVRO

Hlnh 2.12 So d6 khdi bQ t9-0 dien ap so sanh. BQ t9-0 dit$n ap so sanh nay bao g6m mot thang dien trd 16 rmrc d6ng vai tro la cffu phan ap chia nho dit$n ap VDD thanh nhieu mire khac nhau (16 rmrc). M6i mire c6 gia tri dit$n ap khac nhau tuy thuoc vao bit di~u khien CVRR (CVRCON<5». Ne'u CVRR d rmrc logic 1, dien trd 8R se khong c6 tac dung nhu mot thanh phdn ciia cffu phan ap (BJT d~n manh va dong dien

khong di qua dien trd 8R), khi do 1 rmrc dien ap co gia tri VDDI24. Ngu'(_1C khi CVRR d lai rmrc logic 0, dong dien se qua di~n trd 8R val mire dien ap co gia tri VDD/32. Cac rmrc dien ap nay diroc dira qua bQ MUX cho phep ta chon du'(_1C dien ap dira ra pin RA2/AN2NREFjCVREF dS dira vao ngo VIN+ ciia bQ so sanh bang each dira cac gia tri thich hop vao cac bit CVR3:CVRO. BQ tao dien ap so sanh nay co thS xem nhu met bQ chuyen d6i D/A don gian, Gia tri dien ap dn so sanh d ngo vao Analog se du'(_1C sanh vdi cac mire dien ap do bQ tao dien ap so tao ra cho tdi khi hai di~n ap nay dat diroc gia tri xa'p xi bang nhau. Khi do k€t qua chuyen d6i xem nhu diroc chua trong cac bit CVR3:CVRO. Cac thanh ghi lien quan den bQ tao dien ap so sanh nay bao g6m: Thanh ghi CVRCON (dia chi 9Dh): thanh ghi tnrc ti€p di€u khien bQ so sanh dien ap. Thanh ghi CMCON (dia chi 9Ch): thanh ghi di€u khien bQ Comparator. Chi ti€t v€ cac thanh ghi se du'(_1c trmh bay ClJthS d phu luc 2. 2.11 CCP CCP (Capture/Compare/PWM) bao g6m cac thao tac tren cac xung d€m cung ca'p bdi cac bQ d€m Timer! va Timer2. PIC16F877A diroc tich hop san hai khdi CCP : CCPl va CCP2.M6i CCP co mot thanh ghi 16 bit (CCPR1H:CCPR1L va CCPR2H:CCPR2L), pin di€u khiSn dung cho khdi CCPx la RC2/CCPl va RC1IT10SIICCP2. Cac chiic nang cua CCP bao g6m: Capture. So sanh (Compare). Di€u ch€ dQ rQng xung PWM (Pulse Width Modulation). Ca CCPl va CCP2 v€ nguyen t~c hoat dQng d€u gidng nhau va chuc nang cua tung khdi la kha dQc l~p. Tuy nhien trong met so' tnrong hop ngoai l~ CCPl va CCP2 co kha nang phdi hop vdi nhau dS dS tao ra cac hien tuong d~c biet (Special event trigger) hoac cac tac dQng len Timerl va Timer2. Cac tnrong hop nay diroc liet ke trong bang sau: CCPx Capture Capture Compare PWM PWM PWM CCPy Capture Compare Compare PWM Capture Compare Tac dQng chung ngudn xung clock tu TMRI hien tuong dac biet lam xoa TMRI hien nrong dac biet lam xca TMRI so' xung clock vacung chiu tac dQng cua ng~t TMR2. Hoat dQng dQc l~p Hoat dQng dQc l~p

Dung Tao ra Tao ra Dung chung tffn

Khi hoat dQng d che'dQ Capture thl khi co mQt "hien nrong " xay ra tai pin RC2/CCP1 (hoac RC1ff10SI/CCP2), gia tri cua thanh ghi TMR1 se diroc dua vao thanh ghi CCPR1 (CCPR2). Cac "hien nrong " diroc dinh nghia bdi cac bit CCPxM3:CCPxMO (CCPxCON<3:0» va co th~ la mot trong cac hien nrong sau: M6i khi co canh xudng tai cac pin CCP. M6i khi co canh len. M6i canh len thti 4. M6i canh len thti 16.

,-------,

SE.i FI~g Ibi~. CP'll F C (PIR 1«2:»

pin

Q~.

Htnh 2.13 So d6 khdi CCP (Capture mode).

Sau khi gia tri cua thanh ghi TMR1 diroc dira vao thanh ghi CCPRx, cCl ngdt CCPIF diroc set va phai diroc xoa bang chirong trmh. Neu hien tuong tie'p thea xay ra rna gia tri trong thanh ghi CCPRx chua diroc xii' li, gia tri tie'p thea nhan diroc se tu dQng duoc ghi de len gia tri cu. MQt so' di~m dn chti y khi sii' dung CCP nhu sau: Cac pin dung cho khdi CCP phai du'<;lC dinh la input (set cac bit nrong ling trong a'n thanh ghi TRISC). Khi a'n dinh cac pin dung cho khdi CCP la output, viec dua gia tri vao PORTC cung co th~ gay ra cac "hien tuong " tac dQng len khdi CCP do trang thai cua pin thay d6i. Timer1 phai diroc hoat dQng d che'dQ Timer hoac che'dQ de'm d6ng bQ. Tranh sii' dung ng~t CCP bang each clear bit CCPxIE (thanh ghi PIE1), cCl ng~t CCPIF nen du'<;lcxoa bang phdn mem m6i khi dtroc set d~ tie'p tuc nhan dinh diroc trang thai hoat dQng ciia CCP. CCP con du'<;lctich hop bQ chia tffn so' prescaler diroc dieu khicn bdi cac bit CCPxM3:CCPxMO. Viec thay d6i do'i nrong tac dQng cua prescaler co th~ tao ra hoat dQng ngdt, Prescaler duoc xca khi CCP khong hoat dQng hoac khi reset. Xem cac thanh ghi dieu khi~n khdi CCP (phu luc 2 d~ bie't them chi tiet),

Khi hoat dQng d che'dQ Compare, gid tri trong thanh ghi CCPRx se thuong xuyen diroc so sanh vdi gia tri trong thanh ghi TMRI. Khi hai thanh ghi chua gia tri bang nhau, cac pin cua CCP du'<,1C thay d6i trang thai (dircc dira len mire cao, dira xudng mire thfp hoac giu nguyen trang thai), d6ng thoi cC1 ngat CCPIF cting se diroc set. Sl! thay d6i trang thai cua pin co th~ dircc di€u khien bdi cac bit CCPxM3:CCPxMO (CCPxCON <3:0».
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Hlnh 2.14 So d6 khdi CCP (Compare mode). Tuong tl! nhu d che'dQ Capture, Timerl phai diroc a'n dinh che' dQ hoat dQng la timer hoac de'm d6ng bQ. Ngoai ra, khi d che' dQ Compare, CCP co khd nang tao ra hien nrong d~c biet (Special Event trigger) lam reset gia tri thanh ghi TMRI va khdi dQng bQ chuyen d6i ADC. Di€u nay cho phep ta di€u khidn gia tri thanh ghi TMRI mot each linh dQng hen,

Khi hoat dQng d che' dQ PWM (Pulse Width Modulation _ khdi di€u che' dQ rQng xung), tin hieu sau khi di€u che' se diroc dua ra cac pin ciia khdi CCP (dn fin dinh cac pin nay la output). E>€ sii' dung chiic nang di€u che' nay tnrdc tien ta dn tie'n hanh cac birdc cai d~t sau: 1. Thie't l~p thci gian cua 1 chu kl ciia xung di€u che' cho PWM (period) bang each dira gia tri thich hop VaGthanh ghi PR2. 2. Thie't l~p dQ rong xung dn di€u che' (duty cycle) bang each dira gia tri VaG thanh ghi CCPRxL va cac bit CCP1CON<5:4>. 3. E>i€u khien cac pin cua CCP la output bang each clear cac bit nrong irng trong thanh ghi TRISC. 4. Thie't l~p gia tri bQ chia tffn so' prescaler ciia Timer2 va cho phep Timer2 hoa t dQng bang each dira gia tri thich hop VaG thanh ghi T2CON. 5. Cho phep CCP hoat dQng d che' dQ PWM. Trong do gia

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Hlnh 2.15 So d6 khdi CCP (PWM mode).

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TMR2 = PR2

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Hlnh 2.16 Cac tham so' ciia PWM

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PWM period

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tri bQ chia tffn so' cua TMR2).

BQ chia tffn so' prescaler ciia Timer2 chi co th€ nhan cac gid tri 1,4 hoac 16 (xem lai Timer2 d€ bie't them chi tie't). Khi gid tri thanh ghi PR2 bang vdi gia tri thanh ghi TMR2 thl qua trinh sau xay ra: Thanh ghi TMR2 tlj dQng du'<,1C xoa. Pin ciia khdi CCP diroc set. Gia tri thanh ghi CCPR1L (chua gia tri fin dinh dQ rQng xung di€u che' duty cycle) diroc dira VaGthanh ghi CCPRxH. E>Q rQng cua xung di€u che' (duty cycle) du'<,1c thea cong thuc: tinh PWM duty cycle

= (CCPRxL:CCPxCON<5:4»*Tosc*(gia

tri bQ chia tffn so'TMR2)

Nhu v~y 2 bit CCPxCON<5:4> se chua 2 bit LSB. Thanh ghi CCPRxL chua byte cao ciia gid tri quyet dinh dQ rQng xung. Thanh ghi CCPRxH dong vai tro la buffer cho khdi PWM. Khi gia tri trong thanh ghi CCPRxH bang vdi gia tri trong thanh ghi TMR2 va hai bit CCPxCON<5:4> bang vdi gia tri 2 bit cua bQ chia t~n so' prescaler, pin ciia khdi CCP lai dircc dira v€ rmrc thap, nhu vay ta co diroc hlnh anh cua xung di€u che' tai ngo ra cua khdi PWM nhu hlnh 2.14. MQt so'di€m cffn chti y khi sil' dung khdi PWM: Timer2 co hai bQ chi a t~n so' prescaler va posts caler. Tuy nhien bQ postscaler khong dircc sil' dung trong qua trinh di€u che'dQ rQng xung cua khdi PWM. Neu thCfigian duty cycle dai hen thoi gian chu kl xung period thl xung ngd ra tie'p tuc diroc gili d rmrc cao sau khi gia tri PR2 bang vdi gia tri TMR2. 2.12 GIAO TlEP NOI TlEP 1.12.1 USART USART (Universal Synchronous Asynchronous Receiver Transmitter) la mot trong hai chudn giao tiep no'i tie'p.USART con dircc goi la giao dien giao tie'p no'i tie'p no'i tie'p SCI (Serial Communication Interface). Co th€ sil' dung giao dien nay cho cac giao tie'p vdi cac thie't bi ngoai vi, vdi cac vi di€u khi€n khac hay vdi may tinh. Cac dang ciia giao dien USART ngoai vi bao g6m: Ba't dQng bQ (Asynchronous). D6ng bQ_ Master mode. D6ng bQ_ Slave mode. Hai pin dung cho giao dien nay la RC6ffX/CK va RC7/RXIDT, trong do RC6ffX/CK dung d€ truyen xung clock (baud rate) va RC7/RXlDT dung d€ truyen data. Trong tnrcng hop nay ta phai set bit TRISC<7:6> va SPEN (RCSTA<7» cOd€ cho phep giao dien USART. PIC16F877A diroc tich hop san bQ tao to'c dQ baud BRG (Baud Rate Genetator) 8 bit dung cho giao dien USART. BRG thirc cha't la mot bQ de'm co th€ diroc sil' dung cho cii hai dang d6ng bQ va ba't d6ng bQ va dUQCdi€u khien bdi thanh ghi PSBRG. d dang ba't d6ng bQ, BRG con dircc di€u khien bdi bit BRGH ( TXST A<2». d dang d6ng bQ tac dQng cua bit BRGH diroc bo qua. To'c dQ baud do BRG tao ra diroc tinh thea cong thirc sau:
SYNC IBR,GH = 1 (H[gh Speetl)

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(As~nchroITliJus)Baud Ralie =, Foscil64 {X ... ~H (Synchcooous) Baudi Rate :=: FosJCi(4 (X + 'I))

Baud Rate, ,= Foscl( 16< IX, +- 1})

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Trong do X la gid tri ciia thanh ghi RSBRG (X la so' nguyen va O<X<255).

Cac thanh ghi lien quan de'n BRG bao g6m: TXSTA (dia chi 98h): chon che' dQ dong bQ hay ba't d6ng bQ (bit SYNC) va chon mire t6c dQ baud (bit BRGH). RCSTA (dia chi 18h): cho phep hoat dQng c6ng n6i tie'p (bit SPEN). RSBRG (dia chi 99h): quyet dinh t6c dQ baud. Chi tie't v~ cac thanh ghi se diroc trinh bat cu th~ trong phu luc 2.

2.12.1.1 USART BAT DONG BO

che' dQ truyen nay USART hoat dQng theo chuan NRZ (None-Return-to-Zero), nghla la cac bit truyen di se bao g6m 1 bit Start, 8 hay 9 bit dii' lieu (thong thuong la 8 bit) va 1 bit Stop. Bit LSB se diroc truyen di tnrdc. Cac kh6i truyen va nhan data dQc I~p vdi nhau se dung chung tffn s6 nrong ling vdi t6c dQ baud cho qua trlnh dich dii' lieu (t6c dQ baud ga'p 16 hay 64 Iffn t6c dQ dich dii' lieu tuy theo gia tri cua bit BRGH), va d~ dam bao tinh hieu qua ciia dii' lieu thl hai khdi truyen va nhan phai dung chung mot dinh dang dir Iieu.

2.12.1.1.1 TRUYEN

DU LIEU
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QUA CHUAN GIAO TIEP USART BAT DONG BO

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Thanh phdn quan trong nha't ciia khdi truyen dii' lieu la thanh ghi dich dii' lieu TSR (Transmit Shift Register). Thanh ghi TSR se Ia'y dii' lieu tu thanh ghi dt$m dung cho qua trlnh truyen dii' lieu TXREG. Du lieu cffn truyen phai duoc dira tnrdc vao thanh ghi TXREG. Ngay sau khi bit Stop ciia dii' lieu cffn truyen tnrdc do du'<_1C truyen xong, dii' lieu tu thanh ghi TXREG se diroc dua vao thanh ghi TSR, thanh ghi TXREG bi rang, ngdt xay ra va cC1 hieu TXIF (PIR1<4» dircc set. Ngat nay diroc di~u khi~n bdi bit TXIE (PIE1<4». CC1 hieu TXIF v~n diroc set ba't chap trang thai cua bit TXIE hay tac dQng ciia chuong trlnh (khong th~ xoa TXIF bang chirong trlnh) rna chi reset v~ 0 khi co dii' lit$u mdi du'<_1C vao thanhh ghi TXREG. du'a

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Hlnh 2.17 So d6 kh6i cua khdi truyen dii' lieu USART.

Trong khi cCfhieu TXIF dong vai tro chi thi trang thai thanh ghi TXREG thl cCfhieu TRMT (TXSTA<I» co nhiern V1:l th~ hien trang thai thanh ghi TSR. Khi thanh ghi TSR rling, bit TRMT se du'(_1C Bit nay chi doc va khong co ngat nao dircc g~n vdi trang thai ciia no. set. MQt di~m cffn chu y nil'a la thanh ghi TSR khong co trong b6 nhd dil' lieu va chi diroc di€u khi~n bdi cpu. Kh6i truyen dil' lieu diroc cho phep hoat dQng khi bit TXEN (TXSTA<5» duoc set. Qua trlnh truyen dil' lieu chi thuc su b~t dffu khi dff co dil' lieu trong thanh ghi TXREG va xung truyen baud dircc tao ra. Khi khdi truyen dil' lieu diroc khdi dQng lffn dffu tien, thanh ghi TSR rling. Tai thci di~m do, dil' lieu dira vao thanh ghi TXREG ngay l~p nrc diroc load vao thanh ghi TSR va thanh ghi TXREG bi rling. Liic nay ta co th~ hlnh thanh mot chulii dil' lieu lien tuc cho qua trinh truyen dil' lieu. Trong qua trmh truyen dil' lieu ne'u bit TXEN bi reset v€ 0, qua trmh truyen ke't thtic, khdi truyen dil' lieu diroc reset va pin RC6ITx/CK chuyen de'n trang thai high-impedance. Trong tnrcng hop dil' lieu cffn truyen la 9 bit, bit TX9 (TXSTA<6» diroc set va bit dil' lieu thti 9 se diroc hru trong bit TX9D (TXSTA<O». Nen ghi bit dil' lieu thti 9 vao tnrdc, VI khi ghi 8 bit dil' lieu vao thanh ghi TXREG tnrdc co th~ xay ra tnrong hop nQi dung thanh ghi TXREG se du'(_1C load vao thanh ghi TSG tnrdc, nhu v~y dil' lieu truyen di se bi sai khac so vdi yeu cffu. Tom lai, d~ truyen dil' lieu thea giao dien USART b(t d6ng bQ, ta cffn thuc hien tudn tlJ' cac birdc sau: 1. Tao xung truyen baud bang each dira cac gia tri cffn thie't vao thanh ghi RSBRG va bit di€u khien rmrc t6c dQ baud BRGH. 2. Cho phep c6ng giao dien n6i tiep n6i tie'p b(t d6ng bQ bang each clear bit SYNC va set bit PSEN. 3. Set bit TXIE ne'u cffn sil' dung ngdt truyen. 4. Set bit TX9 ne'u dinh dang dil' lieu cffn truyen la 9 bit. 5. Set bit TXEN d~ cho phep truyen dil' lieu (hie nay bit TXIF cung se ducc set). 6. Ne'u dinh dang dil' lieu la 9 bit, dira bit dil' lieu thti 9 vao bit TX9D. 7. Dira 8 bit dil' lieu cffn truyen vao thanh ghi TXREG. 8. Ne'u sil' dung ngat truyen, cffn ki~m tra lai cac bit GIE va PEIE (thanh ghi INTCON). Cac thanh ghi lien quan de'n qua trinh truyen dil' lieu bang giao dien USART b(t d6ng bQ: Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): cho phep t(t Thanh ghi PIRI (dia chi OCh): chua cCfhieu TXIF.

ca cac ngdt.

Thanh ghi PIE1 (dia chi 8Ch): chua bit cho phep ngdt truyen TXIE. Thanh ghi RCSTA (dia chi 18h): chua bit cho phep c6ng truyen dii' lieu (hai pin RC6ffX/CK va RC7/RXIDT). Thanh ghi TXREG (dia chi 19h): thanh ghi chua dii' lieu dn truyen. Thanh ghi TXSTA (dia chi 98h): xac l~p cac thong scscho giao dien. Thanh ghi SPBRG (dia chi 99h): quyet dinh tcScdQ baud. Chi tie't ve cac thanh ghi se diroc trmh bay cu th€ (j phu luc 2.
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2.12.1.1.2 NH~N DU LI~U QUA CHUAN GIAO TIEP USART BAT DONG BO Du lieu du'<jcdira vao tll' chan RC7IRX/DT se kich hoat khdi phuc h6i dii' lieu. KhcSiphuc h6i dii' lieu thuc cha't la mot bQ dich dii' lieu ctdc dQ cao va co t~n scshoat dQng ga'p 16 l~n hoac 641~n t~n scsbaud. Trong khi do tcScdQ dich cua thanh thanh ghi nhan dii' lieu se bang vdi t~n scsbaud hoac t~n scscua oscillator.

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Interrupt

Hlnh 2.18 So d6 khdi cua khdi nhan dii' lieu USART. Bit dieu khi€n cho phep khdi nhan dii' lieu Ia bit RCEN (RCST A<4». Thanh phdn quan trong nhdt cua khdi nhan dii' lieu la thsnh ghi nhan dii' lieu RSR (Receive Shift Register). Sau khi nhan dien bit Stop ciia dii' lieu truyen tdi, dii' lieu nhan du'<jctrong thanh ghi RSR se diroc dira vao thanh ghi RCGER, sau do cCl hieu RCIF (PIR1<5» se diroc set va ngdt nhan diroc kich hoat, Ng~t nay duoc dieu khi€n bdi bit RCIE (PIE1<5». Bit cCl hieu RCIF la bit chi doc va khong th€ du'<jctac dQng bdi chuong trlnh, RCIF chi reset ve 0 khi dii' lieu nhan vao (j thanh ghi RCREG dff diroc doc va khi do thanh ghi RCREG r6ng. Thanh ghi RCREG la thanh ghi

co bQ d~rn kep (double-buffered register) va hoat dQng theo co che' FIFO (First In First Out) cho phep nhan 2 byte va byte thu 3 tie'p tuc diroc dira vao thanh ghi RSR. Ne'u sau khi nhan diroc bit Stop cua byte dii' lieu thii 3 rna thanh ghi RCREG v~n con d~y, cCl hieu bao tran dii' lieu (Overrun Error bit) OERR(RCSTA<l» se duoc set, dii' lieu trong thanh ghi RSR se bi rna't di va qua trlnh dira dii' lieu til thanh ghi RSR vao thanh ghi RCREG se bi gian doan. Trong tnrong hop nay dn la'y he't dii' lieu a thanh ghi RSREG vao tnrdc khi tie'p tuc nhan byte dii' lieu tie'p theo. Bit OERR phai ducc xoa bang phdn mern va thirc hien bang each clear bit RCEN r6i set lai. Bit FERR (RCSTA<2» se dtroc set khi phat hien bit Stop dua dii' lieu dircc nhan vao. Bit dii' lieu thti 9 se du'<,1c ira vao bit RX9D (RCST A<O». Khi doc dii' d lieu til thanh ghi RCREG, hai bit FERR va RX9D se nhan cac gia tri mdi. Do do dn doc dii' lieu til thanh ghi RCST A tnrdc khi doc dii' lieu til thanh ghi RCREG d€ tranh bi rna't dii' lieu, Tom lai, khi sa dung giao dien nhan dii' lieu USART ba't d6ng bQ dn tie'n hanh tudn tu cac birdc sau: 1. Thie't l~p to'c dQ baud (dira gid tri thich hop vao thanh ghi SPBRG va bit BRGH. 2. Cho phep c6ng giao tie'p USART ba't d6ng bQ (clear bit SYNC va set bit SPEN). 3. Neu dn sa dung ngdt nhan dii' lieu, set bit RCIE. 4. Ne'u dii' lieu truyen nhan co dinh dang la 9 bit, set bit RX9. 5. Cho phep nhan dii' lieu bang each set bit CREN. 6. Sau khi dii' lieu diroc nhan, bit RCIF se du'<,1Cet va ngdt diroc kich hoat (neu bit s RCIE diroc set). 7. DQc gia tri thanh ghi RCST A d€ doc bit dii' lieu thti 9 va ki€rn tra xern qua trmh nhan dii' lieu co bi Ic3ikhong. 8. DQc 8 bit dii' lieu til thanh ghi RCREG. 9. Neu qua trlnh truyen nhan co Ic3ixay ra, xoa Ic3ibang each xoa bit CREN. 10. Ne'u sa dung ngdt nhan dn set bit GIE va PEIE (thanh ghi INTCON). Cac thanh ghi lien quan de'n qua trlnh nhan dii' lieu bang giao dien USART ba't d6ng bQ: Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, l8Bh): chua cac bit cho phep toan bQ cac ng~t (bit GIER va PEIE). Thanh ghi PIRI (dia chi OCh): chua cCl hieu RCIE. Thanh ghi PIEI (dia chi 8Ch): chua bit cho phep ngdt RCIE. Thanh ghi RCSTA (dia chi l8h): xac dinh cac trang thai trong qua trmh nhan dii' lieu, Thanh ghi RCREG (dia chi lAh): chua dii' lieu nhan diroc, Thanh ghi TXSTA (dia chi 98h): chua cac bit di~u khicn SYNC va BRGH. Thanh ghi SPBRG (dia chi 99h): di~u khien to'c dQ baud. Chi tie't v~ cac thanh ghi se diroc trmh bay C1:lh€ t

a phu

luc 2.

2.12.1.1.2 USART DONG

BO

Giao dien USART d6ng b(l du'<;lc kich hoat bang each set bit SYNC. C6ng giao tie'p no'i tiep v~n Ia hai chan RC7IRX/DT, RC6ITX/CK va diroc cho phep bang each set bit SPENo USART cho phep hai che' d(l truyen nhan dli lieu la Master mode va Slave mode. Master mode diroc kich hoat bang each set bit CSRC (TXSTA<7», Slave mode diroc kich hoat b~ng each clear bit CSRC. Di€m khac biet duy nh(t gifta hai che'd(l nay la Master mode se l(y xung clock d6ng b(l til b(l tao xung baud BRG con Slave mode l(y xung clock d6ng b(l til ben ngoai qua chan RC6ITX/CK. Di~u nay cho phep Slave mode hoat d(lng ngay ca khi vi di~u khicn dang d che'd(l sleep.

2.12.1.2.1 TRUYEN DU LIEU QUA CHUAN GIAO TlEP USART DONG MODE

BO MASTER

Tirong tv nhu giao dien USART bat d6ng b(l, thanh phdn quan trong nh(t cua ho'i truyen dli lieu la thanh ghi dich TSR (Transmit Shift Register). Thanh ghi nay chi diroc di~u khi€n bdi cpu. Dli lieu dira vao thanh ghi TSR diroc chua trong thanh ghi TXREG. CC1hieu cua khdi truyen dli lieu la bit TXIF (chi thi trang thai thanh ghi TXREG), cC1hieu nay diroc gan vdi mot ngdt va bit di~u khi€n ngdt nay la TXIE. CC1hieu chi thi trang thai thanh ghi TSR la bit TRMT. Bit TXEN cho phep hay khong cho phep truyen dli lieu. Cac birdc cffn tie'n hanh khi truyen dli lieu qua giao dien USART d6ng b(l Master mode: 1. Tao xung truyen baud bang each dira cac gid tri cffn thie't vao thanh ghi RSBRG va bit di~u khien rmrc to'c d(l baud BRGH. 2. Cho phep c6ng giao dien no'i tiep no'i tiep d6ng b(l bang each set bit SYNC, PSEN va CSRC. 3. Set bit TXIE ne'u cffn dung ngdt truyen. 4. Set bit TX9 ne'u dinh dang dli lieu cffn truyen la 9 bit. 5. Set bit TXEN d€ cho phep truyen dli lieu. 6. Ne'u dinh dang dli lieu la 9 bit, dira bit dli lieu thti 9 vao bit TX9D. 7. Dira 8 bit dli lieu cffn truyen vao thanh ghi TXREG. 8. Ne'u d1:111g gat truyen, cffn ki€m tra lai cac bit GIE va PEIE (thanh ghi n INTCON).

sa

sa

Cac thanh ghi lien quan de'n qua trinh truyen dli lieu bang giao dien USART d6ng b(l Master mode: Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): cho phep t(t cii cac ngdt. Thanh ghi PIRI (dia chi OCh): chua cC1 hieu TXIF.

Thanh ghi PIE1 (dia chi 8Ch): chua bit cho phep ngdt truyen TXIE. Thanh ghi RCSTA (dia chi 18h): chua bit cho phep c6ng truyen dii' lieu (hai pin RC6ffX/CK va RC7/RXIDT). Thanh ghi TXREG (dia chi 19h): thanh ghi chua dii' lieu dn truyen. Thanh ghi TXSTA (dia chi 98h): xac l~p cac thong scscho giao dien. Thanh ghi SPBRG (dia chi 99h): quyet dinh tcScdQ baud. Chi tie't ve cac thanh ghi se diroc trmh bay cu th€ (j phu luc 2.
A _
A.

2.12.1.2.2 NH~N DU LI~U QUA CHUAN GIAO TIEP USART DONG BO MASTER MODE Cau tnic khdi truyen dii' lieu la khong d6i so vdi giao dien b(t dang bQ, k€ cii cac cClhieu, ngdt nhan va cac thao tac tren cac thanh phdn d6. Di€m khac biet duy nhdt la giao dien nay cho phep hai che' dQ nhan sii' lieu, d6 la chi nhan 1 word dii' lieu (set bit SCEN) hay nhan mot chu6i dii' lieu (set bit CREN) cho tdi khi ta clear bit CREN. Neu cii hai bit deu diroc set, bit dieu khien CREN se diroc uu tien, Cac birdc dn tie'n hanh khi nhan dii' lieu bang giao dien USART dang bQ Master mode: 1. 2. 3. 4. 5. 6. Thie't l~p tcScdQ baud (dira gid tri thich hop vao thanh ghi SPBRG va bit BRGH). Cho phep c6ng giao tie'p USART b(t dang bQ (set bit SYNC, SPEN va CSRC). Clear bit CREN va SREN. Ne'u dn sii' dung ngat nhan dii' lieu, set bit RCIE. Neu dii' lieu truyen nhan c6 dinh dang la 9 bit, set bit RX9. Ne'u chi nhan 1 word dii' lieu, set bit SREN, neu nhan 1 chudi word dii' lieu, set bit CREN. 7. Sau khi dii' lieu diroc nhan, bit RCIF se duoc set va ng~t diroc kich hoat (neu bit RCIE diroc set). 8. DQc gia tri thanh ghi RCST A d€ doc bit dii' lieu thti 9 va ki€m tra xem qua trmh nhan dii' lieu c6 bi l6i khong. 9. DQc 8 bit dii' lieu tll' thanh ghi RCREG. 10. Neu qua trlnh truyen nhan c6 l6i xay ra, x6a l6i bang each x6a bit CREN. 11. Neu sii' dung ng~t nhan dn set bit GIE va PEIE (thanh ghi INTCON).

,:?

,..,

A.

Cac thanh ghi lien quan de'n qua trinh nhan dii' lieu bang giao dien USART dang bQ Master mode: Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): chua cac bit cho phep toan bQ cac ngdt (bit GIER va PEIE). Thanh ghi PIR1 (dia chi OCh): chua cClhieu RCIE.

Thanh Thanh Thanh Thanh Thanh

ghi ghi ghi ghi ghi

PIE1 (dia chi 8Ch): chua bit cho phep ngdt RCIE. RCSTA (dia chi 18h): xac dinh cac trang thai trong qua trmh nhan dii' lieu. RCREG (dia chi 1Ah): chua dii' lieu nhan diroc, TXSTA (dia chi 98h): chua cac bit dieu khi~n SYNC va BRGH. SPBRG (dia chi 99h): dieu khien to'c d(l baud.

Chi titt ve cac thanh ghi se diroc trinh bay C1:lh~ d phu luc 2. t 2.12.1.2.3 TRUYEN MODE

DU LIEU

QUA CHUAN GIAO TlEP USART DONG

BO SLAVE

Qua trlnh nay khong co slj khac biet so vdi Master mode khi vi dieu khi~n hoat d(lng d cht d(l bmh thuong. Tuy nhien khi vi dieu khien dang d trang thai sleep, su khac biet du'<_1c th~ hien ro rang. Neu co hai word dii' lieu diroc dira vao thanh ghi TXREG tnrdc khi lenh sleep diroc thirc thi thl qua trmh sau se xay ra: 1. 2. 3. 4. Word dii' lieu dffu tien se ngay l~p nrc diroc dira vao thanh ghi TSR d~ truyen di. Word dii' lieu thti hai v~n nam trong thanh ghi TXREG. CCfhieu TXIF se khong diroc set. Sau khi word dii' lieu dffu tien dff dich ra khoi thanh ghi TSR, thanh ghi TXREG titp tuc truyen word thu hai vao thanh ghi TSR va cCfhieu TXIF diroc set. 5. Ntu ngdt truyen diroc cho phep hoat d(lng, ngdt nay se danh thirc vi dieu khien va ntu toan b(l cac ngdt diroc cho phep hoat d(lng, b(l de'm chirong trlnh se chi tdi dia chi chua chirong trinh ngat (0004h).

Cac birdc cffn titn hanh khi truyen dii' lieu bang giao dien USART dang b(l Slave mode: 1. 2. 3. 4. 5. 6. 7. 8. Set bit SYNC, SPEN va clear bit CSRC. Clear bit CREN va SREN. Neu cffn sa dung ngat, set bit TXIE. Neu dinh dang dii' lieu la 9 bit, set bit TX9. Set bit TXEN. Dira bit dii' lieu thti 9 vao bit TX9D tnrdc (ntu dinh dang dii' lieu la 9 bit). Dira 8 bit dii' lieu vao thanh ghi TXREG. Ntu ngat truyen du'<_1C dung, set bit GIE va PEIE (thanh ghi INTCON). sa

Cac thanh ghi lien quan dtn qua trlnh truyen dii' lieu bang giao dien USART dang b(l Slave mode: Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): cho phep ta't Thanh ghi PIR1 (dia chi OCh): chua cCfhieu TXIF.

ca cac ngdt.

Thanh ghi PIE1 (dia chi 8Ch): chua bit cho phep ngdt truyen TXIE. Thanh ghi RCSTA (dia chi 18h): chua bit cho phep c6ng truyen dii' lieu (hai pin RC6ffX/CK va RC7/RXIDT). Thanh ghi TXREG (dia chi 19h): thanh ghi chua dii' lieu dn truyen. Thanh ghi TXSTA (dia chi 98h): xac l~p cac thong sa cho giao dien. Thanh ghi SPBRG (dia chi 99h): quyet dinh tac dQ baud. Chi tie't ve cac thanh ghi se diroc trmh bay cu th€ (j phu luc 2. 2.12.1.2.4 NH~N MODE
A

DU LI~U

A.

QUA CHUAN

,Q

GIAO TIEP USART DONG

BO
A.

SLAVE

S1.fkhac biet cua Slave mode so vdi Master mode chi th€ hien ro rang khi vi dieu khien hoat dQng (j che'dQ sleep. Ngoai ra che'dQ Slave mode khong quan tam tdi bit SREN. Khi bit CREN (cho phep nhan chudi dii' lieu) diroc set tnrdc khi l~nh sleep diroc thuc thi, 1 word dii' lieu v~n diroc tie'p tuc nhan, sau khi nhan xong bit thanh ghi RSR se chuyen dii' lieu vao thanh ghi RCREG va bit RCIF du'<jcset. Ne'u bit RCIE (cho phep ngat nhan) dff diroc set tnrdc do, ngdt se diroc thuc thi va vi dieu khien diroc "danh thuc, bQ de'm chirong trmh se chi de'n dia chi 0004h va chuong trinh ng~ t se diroc thuc thi. Cac birdc dn tie'n hanh khi nhan dii' lieu bang giao dien USART d6ng bQ Slave mode: 1. Cho phep c6ng giao tie'p USART ba't d6ng bQ (set bit CSRC). 2. Ne'u dn sii' dung ngat nhan dii' lieu, set bit RCIE. 3. Ne'u dii' lieu truyen nhan co dinh dang la 9 bit, set bit RX9. 4. Set bit CREN d€ cho phep qua trlnh nhan dii' li~u b~t dffu. 5. Sau khi dii' lieu diroc nhan, bit RCIF se duoc set va ng~t RCIE diroc set). 6. DQc gia tri thanh ghi RCST A d€ doc bit dii' lieu thti 9 va nhan dii' lieu co bi 16i khong. 7. DQc 8 bit dii' lieu til thanh ghi RCREG. 8. Neu qua trlnh truyen nhan co 16i xay ra, xoa 16i bang each 9. Ne'u sii' dung ngdt nhan dn set bit GIE va PEIE (thanh ghi SYNC, SPEN clear bit

diroc kich hoat (neu bit ki€m tra xem qua trmh

xoa bit CREN. INTCON).

Cac thanh ghi lien quan de'n qua trlnh nhan dii' lieu bang giao dien USART d6ng bQ Slave mode: Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, 18Bh): chua cac bit cho phep toan bQ cac ngdt (bit GIER va PEIE).

Thanh Thanh Thanh Thanh Thanh Thanh

ghi ghi ghi ghi ghi ghi

PIR1 (dia chi DCh): chua cCl hieu RCIE. PIE1 (dia chi 8Ch): chua bit cho phep ngdt RCIE. RCSTA (dia chi 18h): xac dinh cac trang thai trong qua trmh nhan dii' lieu. RCREG (dia chi 1Ah): chua dii' lieu nhan diroc, TXSTA (dia chi 98h): chua cac bit di€u khicn SYNC va BRGH. SPBRG (dia chi 99h): di€u khi€n to'c dQ baud.

Chi tie't v€ cac thanh ghi se diroc trmh bay cu th€ (j phu luc 2. 2.12.2 MSSP MSSP ( Master Synchronous Serial Port) la giao dien d6ng bQ no'i tie'p dung d€ giao tiep vdi cac thie't bi ngoai vi (EEPROM, ghi dich, chuyen d6i ADC, ...) hay cac vi di€u khi€n khac, MSSP co th€ hoat dQng dirdi hai dang giao tiep: SPI (Serial Pheripheral Interface). I2C (Inter-Intergrated Circuit). Cac thanh ghi di€u khicn giao chudn giao tiep nay bao g6m thanh ghi trang thai SSPST AT va hai thanh ghi di€u khien SSPSON va SSPSON2. Tuy thea chudn giao tiep dircc sti' dung (SPI hay I2C) rna chtrc nang cac thanh ghi nay diroc th€ hien khac nhau. 2.12.2.1 SPI Chudn giao tie'p SPI cho phep truyen nhan d6ng bQ. Ta cffn sii' dung 4 pin cho chuan giao tie'p nay: ffinh 2.19 Sci d6 khdi MSSP (giao dien SPI) RCS/SDO: ngo ra dii' lieu dang no'i tiep (Serial Data output). RC4/SDIISDA: ngo vao dii' lieu dang no'i tie'p (Serial Data Input). RC3/SCKlSCL: xung d6ng bQ no'i tie'p (Serial Clock). RAS/AN4/SS/C20UT: chon do'i nrong giao tie'p (Serial Select) khi giao tie'p (j che'dQ Slave mode. Cac thanh ghi lien quan de'n MSSP khi hoat dQng (j chuan giao tie'p SPI bao g6m:

M'5JAN4J SSiC20m

Thanh ghi di~u khien SSPCON, thanh ghi nay cho phep doc va ghi. Thanh ghi trang thai SSPSTAT, thanh ghi nay chi cho phep doc va ghi d 2 bit tren, 6 bit con lai chi cho phep doc, Thanh ghi d6ng vai tro la buffer truyen nhan SSPBUF, dii' lieu truyen di hoac nhan dircc se dUQcdira vao tranh ghi nay. SSPBUF khong c6 ca'u tnic d~m hai ldp (doubledbuffer), do d6 dii' lieu ghi vao thanh ghi SSPBUF se l~p tilc diroc ghi vao thanh ghi SSPSR. Thanh ghi dich dii' lieu SSPSR dung dS dich dii' lieu vao hoac ra. Khi 1 byte dii' lieu dircc nhan hoan chinh, dii' lieu se til thanh ghi SSPSR chuyen qua thanh ghi SSPBUF va cCl hieu diroc set, d6ng thCling~t se xay ra. Chi tie't v~ cac thanh ghi se diroc trmh bay cu thS d phu luc 2. Khi sti' dung chudn giao tie'p SPI tnrdc tien ta cffn thiet l~p cac che'd(l cho giao dien bang each dira cac gia tri thich hop vao hai thanh ghi SSPCON va SSPSTAT. Cac thong scs cffn thie't l~p bao gdm: Master mode hay Slave mode. DcSivdi Master mode, xung clock d6ng b(l se di ra til chan RC3/SCKlSCL. DcSivdi Slave mode, xung clock d6ng b(l se dircc nhan til ben ngoai qua chan RC3/SCKlSCL. Cac che'd(l cua Slave mode. Mifc logic cua xung clock khi d trang thai tam ngirng qua trmh truyen nhan (Idle). Canh tac d(lng cua xung clock d6ng b(l (canh len hay canh xudng). TcScd(l xung clock (khi hoat d(lng d Master mode). Thoi diSm xac dinh rmrc logic cua dii' lieu (d giii'a hay d cudi thCli gian 1 bit dii' lieu diroc dira vao). Master mode, Slave mode va cac che' d(l cua Slave mode diroc di~u khiSn bdi cac bit SSPM3:SSPMO (SSPCON<3:0». Xem chi tie't d phu luc 2. MSSP bao g6m mot thanh ghi dich dii' lieu SSPSR va thanh ghi d~m dii' lieu SSPBUF. Hai thanh ghi nay tao thanh b(l d~m dii' lieu kep (doubled-buffer). Dii' lieu se diroc dich vao hoac ra qua thanh ghi SSPSR, bit MSB diroc dich tnrdc, Day la m(lt trong nhtrng diSm khac biet giii' hai giao dien MSSP va USART (USART dich bit LSB tnrdc). Trong qua trlnh nhan dii' lieu, khi dii' lieu dira vao til chan RC4/SDI/SDA trong thanh ghi SSPSR dff san sang (dff nhan du 8 bit), dii' lieu se diroc dira vao thanh ghi SSPBUF, bit chi thi trang thai b(l d~m BF (SSPSTAT<O» se diroc set dS bao hieu b(l d~m dff d~y, d6ng thoi cClngdt SSPIF (PIRl<3» ciing diroc set. Bit BF se tv d(lng reset v~ 0 khi dii' lieu trong thanh ghi SSPBUF diroc doc vao. B(l d~m kep cho phep doc tie'p byte tiep thea tnrdc khi byte dii' lieu tnrdc d6 diroc doc vao, Tuy nhien ta nen doc tnrdc dii' lieu til thanh ghi SSPBUF tnrdc khi nh~n byte dii' lieu tie'p theo. Qua trmh truyen dii' lieu cung hoan toan nrong tv nhung nguoc lai. Dii' lieu cffn truyen se dUQc dua vao thanh ghi SSPBUF d6ng thoi dira vao thanh ghi SSPSR, khi d6 cClhieu BF

diroc set. Dfi' lieu diroc dich til thanh ghi SSPSR va dira ra ngoai qua chan RC5/SDO. Ng~t se xay ra khi qua trlnh dich dfi' lieu hoan ta't. Tuy nhien dfi' lieu tnrdc khi diroc dira ra ngoai phai dircc cho phep bdi tin hieu til chan IRA5JAN4!lS8IC20UT . Chan nay dong vai tro chon d6i tuong giao titp khi SPI i'1 cht dQ Slave mode. Khi qua trlnh truyen nhan dfi' lieu dang di€n ra, ta khong diroc phep ghi dfi' lieu vao thanh ghi SSPBUF. Thao tac ghi dfi' lieu nay se set bit WCON (SSPCON<7». MQt di€u cffn chti y nfi'a la thanh ghi SSPSR khong cho phep truy xua't tnrc tiep rna phai thong qua thanh ghi SSPBUF. C6ng giao titp cua giao dien SPI diroc di€u khi€n bdi bit SSPEN (SSPSON<5». Ben canh do cffn di€u khi€n chieu xua't nhap cua PORTC thong qua thanh ghi TRISC sao cho phil hop vdi chieu cua giao dien SPI. Cu th€ nhir sau: RC4/SDI/SDA se ttf dQng diroc di€u khien bdi khdi giao itep SPI. RS5/SDO la ngo ra dfi' lieu, do do cffn clear bit TRISC<5>. Khi SPI i'1 dang Master mode, cffn clear bit TRISC<3> d€ cho phep dira xung clock d6ng bQ ra chan RC3/SCKlSCL. Khi SPI i'1 dang Slave mode, cffn set bit TRISC<3> d€ cho phep nhan xung clock d6ng bQ til ben ngoai qua chan RC3/SCKlSCL. Set bit TRISC<4> d€ cho phep chan RJi51A!N4JSSlC20UT nhan tin hieu di€u khicn truy xudt dfi' lieu khi SPI i'1 cht dQ Slave mode. So d6 ktt n6i cua chudn giao tiep SPI nhu sau:

~----------------------~
SP,I MUl~\eISSPM~:SSPMO

~----------------------~
SPI Sme
SSP~"'3:SSPMO

QQ:X.U.

= OW7.b

soo
Serialll}p!Jl! BlJI'Ier ~Ss!Pf'UF)

SD:I

Serriiallinpu! Bl!lifer
(SSPBUF)

:Shift lR:egjilfle rr
(SSPSR~

SiDI

Stlii!] Reg'i~teu (SSIPSR) MSb ILSb

SCK ,_:

Seri:!lJ ICI 0 ck

___,.....: SCK ':

----------------------~

PROOESSORlI

~----------------------

IPROOESSOR :2

Hlnh 2.20 So d6 ktt n6i ciia chuan giao titp SPI. Theo so d6 ktt n6i nay, khdi Master se b~t dffu qua trmh truyen nhan dfi' lieu bang each gii'i tin hieu xung d6ng bQ SCK. Dfi' lieu se dich til hai thanh ghi SSPSR dira ra ngoai neu co met canh ciia xung d6ng bQ tac dQng va ngung dich khi co tac dQng cua canh con 19-i.

ca

Ca hai khdi Master va Slave nen diroc fin dinh chung cac qui t~c tac dQng cua xung clock d6ng bQ dS dil lieu co thS dich chuyen d6ng thoi. 2.12.2.1.1 SPI MASTER MODE. Master mode, vi dieu khiSn co quyen fin dinh thoi diSm trao d6i dil lieu (va ddi nrong trao d6i dil lieu ne'u cffn) VI no dieu khiSn xung clock d6ng bQ. Dil lieu se diroc truyen nhan ngay thoi diSm dil lieu diroc dira vao thanh ghi SSPBUF. Ne'u chi cffn nhan dil lieu, ta co thS fin dinh chan SDO la ngo vao (set bit TRISC<5». Dil lieu se diroc dich vao thanh ghi SSPSR thea mQt tdc dQ dtroc dinh san cho xung clock d6ng bQ. Sau khi nhan diroc mot byte dil lieu hoan chinh, byte dil lieu se diroc dira dao thanh ghi SSPBUF, bit BF diroc set va ngat xay ra. Khi lenh SLEEP diroc thuc thi trong qua trmh truyen nhan, trang thai cua qua trmh se diroc giil nguyen va tie'p tuc sau khi vi dieu khiSn diroc danh thiic. Gian d6 xung cua Master mode va cac tac dQng cua cac bit dieu khiSn dircc trlnh bay trong hinh ve sau:

d che'dQ

seE(
eKE

(CKP

=0 0;""----;.------"

'u--D-1
I
I

'
'

seE(

{OKP = 1 eKE = oj

.Jl-l1_J
I
----'__ ---'-__ --'-__ -'---__ -'---__
L___----'__ ----;-_

WITfllE to =--_-;-_-.----_L___----' __ SSPBUF

soo
S'DI

:'5--~v~
I

(SMP·= InplJll~

0,

C>-+-@>k ,t
b~11
, 'I

'

SIJlITlple,
(SMP'= Dl' SSPIF Inlerl1!lp~

1
--'.',.,..afIa_'

Flag

~---------------------------",_\-----~
Ne:w:t 4 Cycle ' Q _=_rQ_2_:1_----II--_

SSPSRIo SSPBUF

Hlnh 2.21 Gian d6 xung SPI d che'dQ Master mode.

2.12.2.1.2 SPI SLAVE MODE dQ nay SPI se truyen va nhan dil' lieu khi co xung d6ng bQ xuat hien (j chan SCK. Khi truyen nhan xong bit dil' lieu cudi cung, cClngdt SSPIF se diroc set. Slave mode hoat dQng ngay khi vi di€u khien dang (j cht dQ sleep, va ngat truyen nhan cho phep "danh thiic" vi di€u khicn. Khi chi cffn nhan dil' lieu, ta co thS (n dinh RC5/SDO la ngd vao (set bit TRISC<5». Slave mode cho phep s11tac dQng cua chan di€u khiSn R!\51A!M4JSSlC20UT (SSPCON<3:0> =

d cht

ca

0100). Khi chan IRA'5IAN4JSSlC20UT

(j mire

thap, chan RC5/SDO

diroc cho phep xuft dil' lieu va bi khoa, d6ng thoi SPI diroc

khi 1Rfi.51A.N.4JSSlC20UT (j mire cao, dil' lieu ra (j chan RC5/SDO reset (bQ dtm bit dil' lieu diroc gan gia tri 0).

sell: sell:

(CKB" =, ,)::_: ";'_ (lKE =·0" (CKB" = 1 DKE =, 01

__

....J

'1___n_h

'f,JiJiJ
I ,) I :

'

'l/lf.itE!~ ,....-----i---.-----'---7-----'------''-----'-----7---.L.----'------I.--+---

SSP~UF

51)0

SI];I (8 dl?'= 0)

l1'ipui.
S~JT1~)e

, , , , ,
"

Ibit 1

(S~Ii"=

0)

t
4'-:;~

SSPIF
1F1il9

IIlIErIfUP~' SSPSR ~:~

SSPBUF_'

~r---~-Hlnh 2.22 Gian d6 xung chuan giao titp SPI (Slave mode).

Cac thanh ghi lien quan dtn chuan giao titp SPI bao g6m: Thanh ngdt (GIE va Thanh Thanh ghi INTCON (dia chi OBh, 8Bh, 10Bh, l8Bh): chua bit cho phep toan bQ cac PEIE). ghi PIRI (dia chi OCh): chua ngdt SSPIE. ghi PIEI (dia chi 8Ch): chua bit cho phep ngdt SSPIE.

Thanh Thanh Thanh Thanh Thanh

ghi ghi ghi ghi ghi

TRISC (dia chi 87h): di~u khien xua't nhap PORTe. SSPBUF (dia chi 13h): thanh ghi dt$m dir Iieu. SSPCON (dia chi 14h): dieu khidn chuan giao tie'p SPI. SSPSTAT (dia chi 94h): chua cac bit chi thi trang thai chuan giao tie'p SPI. TRISA (dia chi 85h):di~u khien xua't nhap chan ~A!r>l4lSSJC2DUl'.

Chi tie't v~ cac thanh ghi se diroc trmh bay cu thS (j phu luc 2. 2.12.2.212C Day la mot dang khac ciia MSSP. Chudn giao tie'p I2C cung co hai che' dQ Master, Slave va cflng dtroc ke't n6i vdi ng~t. I2C se sa dung 2 pin dS truyen nhan dii' lieu: RC3/SCKlSCL: chan truyen d~n xung clock. RC4/SDI/SDA: chan truyen d~n dii' lieu. Cac khdi co ban trong so d5 khdi cua I2C khong co nhieu khac biet so vdi SPI. Tuy nhien I2C con co them khdi phat hien bit Start va bit Stop cua dii' lieu (Start and Stop bit detect) va khdi xac dinh dia chi Si<lI1 d1Id St~p [bit Qoe,te:lt (Match detect). Cac thanh ghi lien quan de'n I2C bao g5m: Thanh ghi SSPCON va SSPCON2: Hlnh 2.23 Sd d5 khdi MSSP (l2Cslave di~u khiSn MSSP. mode). Thanh ghi SSPSTAT: thanh ghi chua cac trang thai hoat dQng ciia MSSP. Thanh ghi SSPBUF: buffer truyen nhan n6i tiep. Thanh ghi SSPSR: thanh ghi dich dung dS truyen nhan dii' lieu. Thanh ghi SSPADD: thanh ghi chua dia chi ciia giao dien MSSP. Cac thanh ghi SSPCON, SSPCON2 cho phep dQCva ghi. Thanh phep doc va ghi (j 2 bit dffu, 6 bit con lai chi cho phep doc. Thanh ghi SSPBUF chua dii' lieu se dircc truyen di hoac nhan nhu mot thanh ghi dt$m cho thanh ghi dich dii' lieu SSPSR. Thanh ghi SSPADD chua dia chi cua thie't bi ngoai vi cffn truy khi hoat dQng (j Slave mode. Khi hoat dQng (j Master mode, thanh ghi tao ra t6c dQ baud cho xung clock dung dS truyen nhan dtr lieu. ghi SSPSTAT chi cho dircc va dong vai tro xudt dii' lieu cua I2C SSPADD chua gia tri

Trong qua trlnh nhan dii' lieu, sau khi nhan du'<_1Cbyte dii' lieu hoan chinh, thanh ghi 1 SSPSR se chuyen dii' lieu vao thanh ghi SSPBUF. Thanh ghi SSPSR khong dQCva ghi diroc, qua trlnh truy xua't thanh ghi nay phai thong qua thanh ghi SSPBUF. Trong qua trmh truyen dii' lieu, dii' lieu cffn truyen khi diroc dira vao thanh ghi SSPBUF cfing se d6ng thCfidira vao thanh ghi SSPSR. Chi titt v~ cac thanh ghi se diroc trinh bay C1:lhS d phu luc 2. t 12C c6 nhieu cht dQ hoat dQng va diroc di~u khien bdi cac bit SSPCON<3:0>, bao g6m: 12C Master mode, xung clock = fosJ4*(SSPADD+l). 12C Slave mode, 7 bit dia chi. 12C Slave mode, 10 bit dia chi. 12C Slvae mode, 7 bit dia chi, cho phep ngdt khi phat hien bit Start va bit Stop. 12C Slave mode, 10 bit dia chi, cho phep ngdt khi phat hien bit Start va bit Stop. 12C Firmware Control Master mode. Dia chi truyen di se bao g6m cac bit dia chi va mot bit RJW dS xac dinh thao tac (doc hay ghi dii' lieu) vdi d6i tuong cffn truy xudt dii' lieu, Khi lua chon giao dien 12C va khi set bit SSPEN, cac pin SCL va SDA se d trang thai cue thu hd. Do do trong tnrcng hop cffn thitt ta phai sa dung dit$n trd keo len d ben ngoai vi di~u khiSn, ben canh d6 cffn a'n dinh cac gia tri phil hop cho cac bit TRISC<4:3> (bit di~u khiSn xudt nhap cac chan SCL va SDA). 2.12.2.2.1 12C SLAVE MODE. Viec tnrdc tien la phai set cac pin SCL va SDA la input (set bit TRISC<4:3». 12C ciia vi di~u khicn se diroc di~u khien bdi mot vi di~u khien hoac mot thitt bi ngoai vi khac thong qua cac dia chi. Khi dia chi nay chi dtn vi di~u khien, thl tai thoi diSm nay va tai thoi diSm dii' lieu dff diroc truyen nhan xong sau d6, vi di~u khien se tao ra xung ACK dS bao hieu ktt thiic dii' lieu, gia tri trong thanh ghi SSPSR se dircc dira vao thanh ghi SSPBUF. Tuy nhien xung ACK se khong diroc tao ra ntu mot trong cac tnrcng hop sau xay ra: Bit BF (SSPSTAT<O» bao hieu buffer d~y dff diroc set tnrdc khi qua trlnh truyen nhan xay ra. Bit SSPOV (SSPCON<6» diroc set tnrdc khi qua trlnh truyen nhan xay ra (SSPOV dircc set trong tnrcng hop khi mQt byte khac diroc nhan vao trong khi dii' lieu trong thanh ghi SSPBUF tnrdc d6 v~n chua diroc la'y ra). Trong cac tnrcng hop tren, thanh ghi SSPSR se khong dira gia tri vao thanh ghi SSPBUF, nhimg bit SSPIF (PIRl<3»se diroc set. DS qua trlnh truyen nhan dii' lieu dircc tiep tuc, cffn doc dii' lieu tu thanh ghi SSPBUF vao tnrdc, khi d6 bit BF se t11dQng du'<_1C x6a, con bit SSPOV phai diroc x6a bang chirong trmh.

Khi MSSP diroc kich heat, no se cho tin hieu d~ b~t d~u hoat dQng. Sau khi nhan diroc tin hieu b~t d~u hoat dQng (canh xudng d~u tien cua pin SDA), dli lieu 8 bit se diroc dich vao thanh ghi SSPSR. Cac bit dira vao se diroc la'y mfiu tai canh len ciia xung clock. Gia tri nhan diroc tll' thanh ghi SSPSR se diroc so sanh vdi gia tri trong thanh ghi SSPADD tai canh xudng cua xung clock thti 8. Neu k€t qua so sanh bang nhau, nrc la I2C Master chi dinh do'i nrong giao ti€p la vi di~u khien dang d ch€ dQ Slave mode (ta goi hien nrong nay la address match), bit BF va SSPOV se diroc xca v~ 0 va gay ra cac tac dQng sau: 1. 2. 3. 4. Gia tri trong thanh ghi SSPSR dircc dira vao thanh ghi SSPBVF. Bit BF tt! dQng diroc set. MQt xung ACK diroc tao ra. CC1 ng~t SSPIF dtroc set (ngdt diroc kich hoat n€u diroc cho phep tnrdc do) tai canh xuong ciia xung clock thii 9.

Khi MSSP d ch€ dQ I2C Slave mode 10 bit dia chi, vi di~u khi~n dn phai nhan vao 10 bit dia chi d~ so sanh. Bit R'W (SSPSTAT<2» phai ducc xca v~ 0 d~ cho phep nhan 2 byte dia chi. Byte d~u tien co dinh dang la '11110 A9 A8 0' trong do A9, A8 la hai bit MSB ciia 10 bit dia chi. Byte thti 2la 8 bit dia chi con lai. Quatrmh nhan dang dia chi cua MSSP d ch€ dQ I2C Slave mode 10 bit dia chi nhir sau: 1. D~u tien 2 bit MSB cua 10 bit dia chi du'<jc nhan tnrdc, bit SSPIF, BF va VA (SSPSTAT<I» diroc set (byte dia chi d~u tien co dinh dang la '11110 A9 A8 0'). 2. Cap nhat vao 8 bit dia chi thap ciia thanh ghi SSPADD, bit VA se du'<jcxoa bdi vi di~u khi~n d~ khdi tao xung clock d pin SCL sau khi qua trlnh c~p nhat hoan ta't. 3. DQc gia tri thanh ghi SSPBVF (bit BF se diroc xoa v~ 0) va xoa cC1 ngdt SSPIF. 4. Nhan 8 bit dia chi cao, bit SSPIF, BF va VA diroc set. 5. C~p nh~t 8 bit dia chi dff nhan diroc vao 8 bit dia chi cao cua thanh ghi SSPADD, n€u dia chi nhan diroc la dung (address match), xung clock d chan SCL dircc khdi tao va bit VA diroc set. 6. DQc gia tri thanh ghi SSPBVF (bit BF se diroc xoa v~ 0) va xoa cC1 ngdt SSPIF. 7. Nhan tin hieu Start. 8. Nhan byte dia chi cao (bit SSPIF va BF diroc set). 9. DQc gia tri thanh ghi SSPBVF (bit BF diroc xoa v~ 0) va xoa cC1 ng~t SSPIF. Trong do cac buoc 7,8,9 xay ra trong qua trlnh truyen dli lieu d ch€ dQ Slave mode. Xem gian d6 xung cua I2C d~ co diroc hmh anh cu th~ hon v~ cac birdc tien hanh trong qua trmh nhan dang dia chi.

Xet qua trinh nhan dii' lieu d che'dQ Slave mode, cac bit dia chi se diroc I2C Master dira vao tnrdc. Khi bit RM' trong cac bit dia chi c6 gia tri bang 0 (bit nay diroc nhan dang sau khi cac bit dia chi dff diroc nhan xong) va dia chi diroc chi dinh dung (address match), bit RJW ciia thanh ghi SSPSTAT dircc x6a ve 0 va du'~ng dii' lieu SDI duoc dira ve rmrc logic thfp (xung ACK). Khi bit SEN (SSPCON<O» diroc set, sau khi 1 byte dii' lieu dircc nhan, xung clock tu chan RC3/SCKlSCL se diroc dira xudng mire thap, mudn khdi tao lai xung clock ta set bit CKP (SSPCON<4». Dieu nay se lam cho hien nrong tran dii' lieu khong xay ra vi bit SEN cho phep ta dieu khien diroc xung clock dich dii' lieu thong qua bit CKP (tham khao gian d6 xung d€ bie't them chi tie't). Khi hien tuong tran dii' lieu xay ra, bit BF hoac bit SSPOV se diroc set. Ng~t se xay ra khi mot byte dii' lieu diroc nhan xong, c~ ngdt SSPIF se diroc set va phai dircc x6a bang chtrong trinh,

SWlf

ll'IR1<~!

~--------------------~

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t= Cl2iJ"ed I

H1J~lIiIre

8SPBU F Ii r<il~

ls~pc\~Ii!rcl te:au~,SSFW; [0 i~lIfUll.llo..~ l,r~t'~J11.

Hinh 2.24 Gian d6 xung cua I2C Slave mode 7 bit dia chi trong qua trlnh nhan dii' lieu (bit SEN = 0).

Ill' !i~er SSP/iDQ ~li

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Hinh 2.25 Gian d6 xung cua I2C Slave mode 10 bit dia chi trong qua trmh nhan dii' lieu (bit SEN = 0).
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Hinh 2.26 Gian d6 xung cua I2C Slave mode 7 bit dia chi trong qua trmh nhan dii' lieu (bit SEN = 1).

Iim.jJ I." ,n[1 "r<I'-" M3BR!.~D 1M

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Hinh 2.27 Gian d6 xung cua I2C Slave mode 10 bit dia chi trong qua trmh nhan dii' lieu (bit SEN = 1). Xet qua trmh truyen dii' lieu, khi bi!_Rl'W trong cac bit dii' lieu mang gia tri 1 va dia chi diroc chi dinh dung (address match), bit P.NI cua thanh ghi SSPSTAT se diroc set. Cac bit dia chi dtrcc nhan tnrdc va dira vao thanh ghi SSPBUF. Sau d6 xung i\CIK diroc tao ra, xung clock (j chan RC3/SCKlSCL diroc dira xuong mac thap b(t chap trang thai cua bit SEN. Khi d6 I2C Master se khong diroc dira xung clock vao I2C Slave cho de'n khi dii' lieu (j thanh ghi SSPSR (j trang thai wsdn sang cho qua trlnh truyen dii' lieu (dii' lieu dira vao thanh ghi SSPBUF se d6ng thoi duoc dira vao thanh ghi SSPSR). Tie'p thea cho phep xung (j pin RC3/SCKlSCL bang each set bit CKP (SSPCON<4». Tung bit cua byte dii' lieu se diroc dich ra ngoai tai mlii canh xuong cua xung clock. Nhu v~y dii' lieu se san sang (j ngd ra khi xung clock (j mire logic cao, giup cho I2C Master nhan dircc dii' lieu tai mlii canh len cua xung clock. Nhu vay trong qua trlnh truyen dii' lieu bit SEN khong d6ng vai tro quan trong nhu trong qua trlnh nhan dii' lieu. Tai canh len xung clock thti 9, dii' lieu dff duoc dich hoan toan vao I2C Master, xung ,1\CIK se dl1Qc tao ra (j I2C Master, d6ng thCfi pin SDA se diroc giii' (j rmrc logic cao. Trong tnrong hop xung ACK diroc chdt bdi I2C Slave, thanh ghi SSPSTAT se diroc reset. I2C Slave

se cho tin hieu ciia bit Start d~ tie'p tuc truyen byte dii' lieu tie'p theo (dua byte dii' lieu tie'p theo vao thanh ghi SSPBUF va set bit CKP. Ng~t MSSP xay ra khi mot byte dii' lieu ke't thiic qua trmh truyen, bit SSPIF diroc set tai canh xudng cua xung clock thti 9 va phai diroc xoa bang chuong trmh d~ dam bao se du'<_1C set khi byte dii' lieu tiep theo truyen xong.

Hinh 2.28 Gian d6 xung cua I2C Slave mode 7 bit dia chi trong qua trlnh truyen dii' lieu,
~I(¢] IS~iKd ~w un II

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Hlnh 2.29 Gian d6 xung cua I2C Slave mode 10 bit dia chi trong qua trmh truyen dii' lieu.

Qua trlnh truyen nhan cac bit dia chi cho phep 12C Master chon hra do'i tuong 12C Slave dn truy xua't dii' lieu. Ben canh d6 12C con cung ca'p them met dia chi GCA (General Call Address) cho phep chon ta't cac 12C Slave. Day la mQ~rong 8 dia chi dac biet ciia protocol 12C. Dia chi nay diroc dinh dang la mQt chudi '0' vdi RJIA' =0 va diroc cho phep bang each set bit GCEN (SSPCON2<7». Khi d6 dia chi nhan vao se diroc so sanh vdi thanh ghi SSPADD va vdi dia chi GCA.

ca

SDA
SCL. .1··

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34

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BIF (S5PSTAT_'!:Il_.~",---)

--/

b
'0'

SSPOV

~$SPDON<6::»

-------------------------------

.1'

Hinh 2.30 Gian d6 xung cua 12C Slave khi nhan dia chi GCA. Qua trlnh nhan dang dia chi GCA ding tuong tt;l'nhu khi nhan dang cac dia chi khac va khong c6 su khac biet ro rang khi 12C hoat dQng d cht dQ dia chi 7 bit hay 10 bit. 2.12.2.2.2 12C MASTER MODE 12C Master mode diroc xac l~p bang each dira cac gia tri thich hop vao cac bit SSPM ciia thanh ghi SSPCON va set bit SSPEN. d cht dQ Master, cac pin SCK va SDA se diroc di€u khi€n bdi phdn ctrng ciia MSSP.

SSPM3,:SSPMO SSIP:IIHD<:6:0>

SkJrrli, biiij,SlqJ' bit,

AdknDlt/~e~e GelllS'm~e,
-'"

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Q

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smr'li: b itlD elect Slop bl~[!\erect. SiCL In \Nir,i!e ("-!]'lli'!lian DeI'ed Clock p.,rf)i'jl"<I!iall Bu,," Co li~'iol'l' SV;]'e' Counlef'Ior end ofXMlrlifRCV

. Sefl'Resei, S, IP, Ii'll'COL ~SSIPSTAT} Se1iSSPllf, BCUF Reset AC:KSTAT, PEN (SSPDON2)

Hlnh 2.31

se d6 khdi MSSP

(I2C Master mode).

I2C Master dong vai tro tich cue trong qua trmh giao tie'p va dieu khi~n cac I2C Slave thong qua viec chii dQng tao ra xung giao tiep va cac dieu kien Start, Stop khi truyen nhan dfi' lieu. MQt byte dfi' lieu co th~ diroc b~t d~u bang dieu kien Start, ke't thiic bang dieu kien Stop hoac b~t d~u va ke't thiic vdi cung met dieu kien khdi dQng lap lai (Repeated Start Condition). Xung giao tie'p n6i tie'p se duoc tao ra tu BRG (Baud Rate Generator), gia tri a'n dinh t~n sO' xung clock n6i tie'p diroc la'y tu 7 bit tha'p cua thanh ghi SSPADD. Khi dfi' lieu diroc dira vao thanh ghi SSPBUF, bit BF diroc set va BRG t11dQng de'm ngiroc ve 0 va dung lai, pin SCL diroc gifi' nguyen trang thai tnrdc do.Khi dfi' lieu tie'p theo diroc dira vao, BRG se dn mot khoang thoi gian T BRG t11dQng reset lai gia tri d~ tie'p tuc qua trlnh de'm ngiroc, M6i vong l~nh (co thoi gian Tcv ) BRG se giam gia tri 21~n.

SSPM3:SSPMO

Reloald
COf1lJol

SCL

CLI<O

Hlnh 2.32 So d6 khdi BRG (Baud Rate Benerator) cua I2C Master mode. Cac gia tri cu th~ cua t~n sO'xung n6i tiep do BRG tao ra diroc liet ke trong bang sau:

Fe..
!O IMHz:

iFc:y'2 201 MHiz 201 MHiz 201 MHiz

,ffi

HIRG Valu&.
~'91hl

(2 R.ol~over.s omIBRGj 400 f.;Hz1i 312:.5 kHz 10.01kHz: 400 f.;Hi!l)1 3D-8.kHz 1[]!0I kHz: 333 f.;Hi[I)1 10.01kHz 11MHz(1j
,

FSCL

'TID1MHz: 'TIDIMHz:
4 MHz 4 MHz. 4 MHz.

2D:hI
3'Flh,

Mf--Dz

OAh ODh 2I!JJhI [1J!l'n O}\h ~ml'n

s 1i111f1lz a Mh'lz
2 MHz ]' MHz 2 Mf-9z

11MHz. 11MHz 11MHz

Trong d6 gia tri BRG la gia tri diroc Iffy til 7 bit thap cua thanh ghi SSPADD. Do I2C ache'dQ Master mode, thanh ghi SSPADD se khong du'<jcsii' dung d~ chua dia chi, thay vao d6 clnrc nang cua SSPADD la thanh ghi chua gia tri cua BRG. t9-0 diroc di~u kien Start, tnrdc he't dn dira hai pin SCL va SDA len mire logic cao va bit SEN (SSPCON2<O» phai diroc set. Khi do BRG se t11dQng doc gia tri 7 bit thffp cua thanh ghi SSPADD va b~t dffu de'm. Sau khoang thoi gian TBRG, pin SDA dircc dira xudng rmrc logic thap. Trang thai pin SDA a rmrc logic thffp va pin SCL a rmrc logic cao chinh la di~u kien Start cua I2C Master mode. Khi d6 bit S (SSPSTAT<3» se dircc set. Tie'p theo BRG tie'p tuc Iffy gia tri til thanh ghi SSPADD d~ tiep tuc qua trlnh de'm, bit SEN diroc t11 dQng x6a va cC1 ngdt SSPIF diroc set.
f)~

Trong tnrong hop pin SCL va SDA a trang thai logic thap, hoac la trong qua trinh t9-0 di~u kien Start, pin SCL diroc dira v~ trang thai logic thffp tnrdc khi pin SDA diroc dira v~ trang thai logic thffp, di~u kien Start se khong diroc hlnh thanh, cC1 ngdt BCLIF se diroc set va I2C se a trang thai tam ngirng hoat dQng (Idle).

\!'iI'Jii~eo SEN ib'iliocCUI!lltielie t

,I

seL

"

Hlnh 2.33 Gian d6 xung I2C Master mode trong qua trlnh t9-0 di~u kien Start.

Tin hieu Stop se diroc dira ra pin SDA khi ke't thiic du lieu bang each set bit PEN (SSPCON2<2». Sau canh xudng cua xung clock thir 9 va vdi tac dQng cua bit di€u khien PEN, pin SDA cling ducc dira xuong mire thap, BRG lai b~t dffu qua trinh de'm. Sau mot khoang thoi gian TBRG,pin SCL diroc dira len rmrc logic cao va sau mot khoang thoi gian TBRGnfta pin SDA cling diroc dira len mire cao. Ngay tai thoi di€m d6 bit P (SSPSTAT<4» diroc set, nghla la di€u kien Stop dff diroc tao ra. Sau mot khoang thoi gian TBRG mra, bit PEN tv dQng du'<_1C va cCfngat SSPIF diroc set. x6a

J
.

seL =, .1 "few T ElR5. foll-ol'iBd by S []A ,= 1.for T 81ill ~f[eJ' 5D~ samPIE..j] h~:~. p bit (SSP~TAJ-(4i~) it::sel.
I

sci,

il:~'iG

.lf~---:-I

-""7

"'___1--_..J}1

1 1 .----L__I--+I .. '
L.EJ
-J;-llBoo

--+----

PEW !bIt (SSPD[lN2~2:>J ~ ~B;ilred b~ h~rd...are m!l tlle' SS, ·I~·'lin IS set !

fI

TEl~~G -r-if8,~G;

L :!3JCL1lm~9hl

--+I

RtghiiHerr T=';;:G

.sDA i;.s,'Ser.ed low befure rls~Iijj E<tl[lf' of GI-oo~ 10 "ei I!IJi SiD 11OO:~diiiDn

Hinh 2.34 Gian d6 xung I2C Master mode trong qua trmh tao di€u kien Stop. D€ tao diroc dieu kien Start lap lai lien tuc trong qua trlnh truyen du lieu, tnrdc he't dn set bit RSEN (SSPCON2<1». Sau khi set bit RSEN, pin SCL diroc dua xuong rmrc logic thap, pin SDA diroc dira len mire logic cao, BRG la'y gia tri til' thanh ghi SSPADD vao d€ baty dffu qua trmh de'm. Sau khoang thoi gian TBRG,pin SCL cling diroc dira len rmrc logic cao trong khoang thCfigian TBRG tie'p theo. Trong khoang thoi gian TBRG tiep, pin SDA lai diroc ke' dua xudng mire logic thap trong khi SCL vfin diroc giu d rmrc logic cao. Ngay thci di€m d6 bit S (SSPSTAT<3» dircc set d€ bao hieu di€u kien Start diroc hinh thanh, bit RSEN tv dQng diroc x6a va cCfngat SSPIF se diroc set sau mot khoang thoi gian TBRGnita. Liic nay dia chi cua I2C Slave c6 th€ diroc dira vao thanh ghi SSPBUF, sau d6 ta chi viec dira tie'p dia chi hoac du lieu tiep thea vao thanh ghi SSPBUF mlii khi nhan duoc tin hieu ACK til' I2C Slave, I2C Master se tv dQng tao tin hieu Start lap lai lien tuc cho qua trlnh truyen du lieu lien tuc, Cffn chii y la ba't cu mot trmh tv nao sai trong qua trmh tao di€u kien Start lap lai se lam cho bit BCLIF diroc set va I2C diroc dira v€ trang thai "Idle".

'Iltrn:e bo SSPOOM2
'Q;:;~

.3[>11- 1..

h,- liE" 'i;!

SiD)!. = 1" SOL

=J
'_

r:
.., II ",,-,-----'II '\---.-

SEll S (SSPST.AT4:>~

At QDmp l,e::~D,' oUf-,Start Ibi ~• m

SOL (oo cIilange)

1 and S'E'1s SSPIF

i3iidWilj'€ clei31S,

R;SiBN b:;t

1""-E'_'<G-T-'iI"8R::l,·q_·o'ir"'J;.;a

SOA~----------~
Fi3Il~ €oll1ge' >Df ninih ;:ro~). ernd of ,Xmil+

_~L__ ~ 1:sll"l:i1

v-,'--',

I\..__

I
I=---------

so,

I
L

I
..J Sr = Repearted Starl

Hinh 2.35 Gian d6 xung I2C Master mode trong qua trlnh tao di€u kien Start lien tuc. Xet qua trmh truyen dfi' lieu, xung clock se diroc dira ra tu pin SCL va dfi' lieu diroc dira ra tu pin SDA. Byte dfi' lieu dffu_!ien phai la byte dia chi xac dinh I2C Slave cffn giao tiep va bit RillIJ (trong tnrong hop nay Rl'i/I! = 0). Dffu tien cac gia tri dia chi se diroc dira vao thanh ghi SSPBUF, bit BF tv dQng diroc set len 1 va bQ d€m tao xung clock nO'i ti€p BRG (Baud Rate Generator) b~t dffu hoat dQng. Khi d6 tung bit dfi' lieu (hoac dia chi va bit R/Vii) se diroc dich ra ngoai theo tung canh xuting cua xung clock sau khi canh xudng dffu tien ciia pin SCL dircc nhan dien (dieu kien Start), BRG b~t dffu d€m nguoc v€ O. Khi ta't ca cac bit cua byte dfi' lieu dircc dff dircc dira ra ngoai, bQ d€m BRG mang gia tri O. Sau do, tai canh xuong cua xung clock thll' 8, I2C Master se ngung tac dQng len pin SDA d~ cho d<;jitin hieu tu I2C Slave (tin hieu xung ,ACK). Tai canh xuong cua xung clock thll' 9, I2C Master se la'y mfiu tin hieu tu pin SDA d~ ki~m tra xem dia chi dff diroc I2C Slave nhan dang chua, trang thai ii.CK diroc dira vao bit ACKST AT (SSPCON2<6». Cling tai thoi di~m canh xudng cua xung clock thrr 9, bit BF diroc tv dQng clear, cC1 ng~t SSPIF diroc set va BRG tam ngirng hoat dQng cho tdi khi dfi' lieu hoac dia chi tiep theo diroc dira vao thanh ghi SSPBUF, dfi' lieu hoac dia chi se ti€p tuc dU<;jc truyen di tai canh xuong ciia xung clock ti€p theo.

I~'n SSPG ON 2 <iJ~ SEN = 1 le' &~ri, CiD ~d!liQII Q eg'rn~

I'!iCl{STAli' "m

I
I I

From SI,3.~e, cle:;: ACKSTATb~ SS!'(;Oj\l2-:::6} ir;;n~mltiin; Da'l.aJ Qf Se<;and H>3J" _,.

SSPOOM2= 1 /'

IIOK, :

-•

'.,__V:
I I

SCL CPU ~ 'l'€!sPQn~:s to SS~~IF

\'!hll'

Sel held low

SSFIF __

--In!L
,

____,l
C Ieared in 5cih'ror,e

"

,,;-1

'L Cleiil'€!d

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~Du1i~e : CI~aJ;e d in iafl'l1iile

in !>ofti'l'iil'€! :5~ 'flam SSP i lltelli~i

i" ~,

~ SSPBUF !wiitero SEM

PEM

--~------------------~~------------~' ~

Hlnh 2.36 Gian d6 xung I2C Master mode trong qua trinh truyen dii' lieu. Xet qua trlnh nhan dii' lieu (j ch€ dQ I2C Master mode. Trude tien ta cffn set bit cho phep nhan dii' lieu RCEN (SSPCON2<3». Khi do BRG b~t dffu qua trinh d€m, dii' lieu se diroc dich vao I2C Master qua pin SDA tai canh xudng cua pin SCL. Tai canh xuting ciia xung clock thti 8, bit cClhieu cho phep nhan RCEN t11dQng dircc xoa, dii' lieu trong thanh ghi SSPSR duqc dira vao thanh ghi SSPBUF, cClhieu BF diroc set, cClngdt SSPIF diroc set, BRG ngimg d€m va pin SCL diroc dira v~ rmic logic thap. Khi do MSSP (j trang thai tam ngirng hoat dQng d€ cho dci lt$nh ti€p theo. Sau khi doc gia tri thanh ghi SSPBUF, cClhieu BF t11 dQng duqc xoa, Ta con co th€ gii'i tin hieu PICK bang each set bit ACKEN (SSPCON2<4».

'lirit, 10 SSPCIJN2:<4? 'I~ s,l~rt ~clmo!\'ledg~ s eque:no.,

'1Iliie to SSPC()~1~~
be,;i" 31.rt 'Dndilion

ISitt.J"

11

SDA ' ACK[)u (SSPCOI'l2<;;» , o AOK flem rn.s.!el SDA ' AOICDT'' 0
Se~ACKEN, !!.rt Acloowledge seq~e_,

1..
• 1 SDA 1 "-.1--'--'-''''-1,,,-~,,,,.,,,-,,,,=,,,,-=
I 1

SC!A 'ACIWT '

I,

PiEN bit:,1 wrimEn ItEriE'

1C:'.'7""C<r--=-o-_':~ .,_ I I
r1

ACK is nul ;en! I I

SCl

Sus rnai:el
,~rJIII,~at es

.
i:
I

r. J"'I M "" ,.-l-.-L- ,rJnm I 'jV6ViU~L_j~l_jIpl__j

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Q

Dac" 'hille', ,i1oo'ollin9 edge..tO . n ~ ~SPI'~ , al end ~'Acknowled ge

rS!1

L.J

SSPIF.I of recei'.~

end

Set SSPIF ~J1U pi. at e nd ~i'('.IlM\j/ [e~ e' ~e~uence'

SSPIF

I~q~:nc~

SDA'

0,

SOL':J

tSel1P b:l 1<4> ) [SS~SIA

and SSPIF

I\!hileCPl! I res pends !D as PiF I

Sf
ISSPS TAi co.)

~~li 'l: iosh in:ed i n,o 5S PSR .and b

I

ooni, rt;; "re unlcaded i"to SSP BUF

SSPO\! --------------------

.......

----------:1i

SSPDV is !!1 ~~us .. SSPS UF i!'J.iilll~

I

.ACKEN

___J

Hlnh 2.37 Gian d6 xung I2C Master mode trong qua trinh nhan dfi' lieu. 2.13 CONG GIAO TIEP SONG SONG PSP (PARALLEL SLAVE PORT) Ngoai cac c6ng n6i tie'p va cac giao dien n6i tie'p diroc trinh bay d phdn tren, vi di~u khi€n PIC16F877 A con diroc h6 tro mot c6ng giao tie'p song song va chuan giao tie'p song song thong qua PORTD va PORTE. Do c6ng song song chi hoat dQng d che'dQ Slave mode nen vi di~u khien khi giao tiep qua giao dien nay se chiu stf di~u khien cua thie't bi ben ngoai thong qua cac pin cua PORTE, trong khi dfi' lieu se diroc doc hoac ghi thea dang ba't d6ng bQ thong qua 8 pin cua PORTD. Bit di~u khien PSP la PSPMODE (TRISE<4». PSPMODE diroc set se thiet l~p chuc nang cac pin cua PORTE la cac pin cho phep doc dfi' lieu RD (REWRD/AN5), cho phep ghi dfi' lieu WR (RE 1tWRl.~N5) va pin chon vi di~u khicn cs '( RE2fCSfANii') phuc vu cho viec truyen nhan dfi' lieu song song thong qua bus dfi' lieu 8 bit cua PORTD. PORTD hie nay dong vai tro la thanh ghi chdt dfi' lieu 8 bit, d6ng thoi tac dQng cua thanh ghi TRISD ciing se dtroc bi) qua do PORTD hie nay chin su di~u khien cua cac thiet bi ben ngoai, PORTE v~n chiu stf tac dQng ciia thanh ghi TRISE, do do dn xac l~p trang thai cac pin PORTE la input bang each set cac bit TRISE<2:0>. Ngoai ra dn dira gia tri thich hop cac bit PCFG3:PCFGO (thanh ghi
,!! ~

ADCONl<3:0» dS a'n dinh cac pin ciia PORTE la cac pin 110 dang digital (PORTE con la cac pin clnrc nang cua khdi ADC). Khi cac pin es va 'WR cung d rmrc
I

r-------------...,
............ ------1 WR
Pori

thap, dii' lieu til ben ngoai se diroc ghi len PORTD. Khi met trong hai pin tren chuyen len rmrc logic cao, cCfhieu bao dii' lieu trong buffer dff dffy BIF (TRISE<7» diroc set va cCf ng~i:tPSPIF (PIRl <7» diroc set dS bao hieu ktt thiic ghi dii' lieu. Bit BIF chi dircc xoa v€ 0 khi dii' lieu vira nhan diroc d PORTD diroc doc vao, Bit bao hieu dii' lieu nhan du'<;lc trong buffer bi tran IBOV (TRISE<S» se du'<;lcset khi vi di€u khien nhan titp dii' lieu titp theo trong khi chua doc vao dii' lieu dff nhan diroc tnrdc do. Khi cac pin cs va RID cung d mire logic thap, bit bao hieu buffer truyen dii' lieu dff dffy BOF (TRISE<6» se diroc xoa ngay l~p tuc dS bao hieu PORTD dff san sang cho qua trinh doc dii' lieu, Khi mQt trong hai pin tren chuyen sang rmrc logic cao, cCfng~ t PSPIF
I

I I
lTlTL.

RDxpin

I I I I

RD P>IJ:rt
L _

(1 n e· bii d' P.D R'TiD

RD

cs

Hlnh 2.38 So d6 khdi cua PORTD va PORTE khi hoat dQng d cht dQ PSP Slave mode. se dircc set dS bao hieu qua trinh dQCdii' lieu hoan ta't. Bit BOF vfin duoc giii' d rmic logic 0 cho dtn khi dii' lieu tiep theo du'<;lc dira vao PORTD. va phai du'<;lC xoa

Cffn chii y la ngdt SSPIF diroc di€u khien bdi bit PSPIE (PIEl<7» bang chircng trmh. Cac thanh ghi lien quan dtn PSP bao g6m: Thanh Thanh Thanh Thanh Thanh Thanh ghi ghi ghi ghi ghi ghi

PORTD (dia chi 08h): chua dii' lieu cffn doc hoac ghi. PORTE (dia chi 09h): chua gia tri cac pin PORTE. TRISE (dia chi 89h): chua cac bit di€u khien PORTE va PSP. PIRl (dia chi OCh): chua cCfng~t PSPIF. PIEl (dia chi 8Ch): chua bit cho phep ngdt PSP. ADCONl (dia chi 9Fh): di€u khiSn khdi ADC tai PORTE.

Chi titt v€ cac thanh ghi se diroc trmh bay C1:lhS d phu luc 2. t

2.14 TONG QUAN VE MOT SO D~C TINH CUA CPU. 2.14.1 CONFIGURATION BIT
Day la cac bit dung dS hra chon cac d~c tinh ciia Cpu. Cac bit nay diroc chua trong bQ nhd chirong trlnh tai dia chi 2007h va chi co thS dircc truy xua't trong qua trmh l~p trinh cho vi di€u khicn. Chi tie't v€ cac bit nay nhir sau:

,Q

A.

"..,....

lRilP-1

cp

I - I DEBLIG I WtRT ~ I VIftRTO I C PD I LVP I BO REN I

lI-O

RitP-1

RfP'-1

RIP'-1

R1P-]

RlP-1

R(p-'i

lI-O

u-n

IPVrJiRTEN IWDllEN I

RtP-1

RlP-1

RtP-11
f09Cl

IIFOsd] I
bltO

lRiP-11

1]1:1: 13

Bit 13 CP: (Code Protection) 1: t~t che' dQ bao v~ rna chuong trlnh. 0: b~t che' dQ bao v~ rna chuong trmh, Bit 12, 5, 4: khong quan tam va du'<_1c dinh mang gia tri O. mac Bit 11 DEBUG (In-circuit debug mode bit) 1.khong cho phep, RB7 va RB6 diroc xem nhu cac pin xuft nhap blnh tlnrong. O:cho phep, RB7 va RB6la cac pin diroc sil' dung cho qua trinh debug. Bit 10-9 WRTl:WRTO Flash Program Memory Write Enable bit 11: T~t chiic nang chong ghi, EECON se di€u khiSn qua trlnh ghi len toan bQ nhd chirong trinh, 10: chi chdng til' dia chi OOOOh:OOFFh. 01: chi chdng ghi til' dia chi 0000h:07FFh. 00: chi chdng ghi til' dia chi OOOOh:OFFFh. Bit 8 CPD Data EEPROM Memory Write Protection bit 1: T~t chiic nang bao v~ rna cua EEPROM. 0: B~t chrrc nang bao v~ rna. Bit 7 LVP Low- Voltage (Single supply) In-Circuit Serial Programming Enable bit 1: Cho phep che' dQ nap dien ap tha'p, pin RB3/PGM diroc sil' dung cho che' dQ nay. 0: Khong cho phep che' dQ nap dien ap thap, dien ap cao diroc dira vao til' pin MCLR, pin RB3 la pin 1/0 blnh tlnrong. Bit 6 BODEN Brown-out Reset Enable bit 1: cho phep BaR (Brown-out Reset) 0: khong cho phep BaR. Bit 3 PWR1EN Power-up Timer Enable bit 1: khong cho phep PWR. 0: cho phep PWR. Bit 2 WDTEN Watchdog Timer Enable bit 1: cho phep WDT. 0: khong cho phep WDT.

Bit 1-0 Fosc1 :FoscO lua chon loai oscillator 11: sa dung RC oscillator. 10: sa dung HS oscillator. 01: sa dung XT oscillator. 00: sa dung LP oscillator. Chi tie't v~ cac d~c tinh se diroc d~ cap cu thS trong cac phdn tie'p theo. 2.14.2 CAC D~C TINH CVA OSCILLATOR PIC16F877 A c6 khd nang sa dung mot trong 4lo~i oscillator, d6 la: LP: (Low Power Crystal). XT: Thach anh blnh thuong, HS: (High-Speed Crystal). RC: (Resistor/Capacitor) dao dQng do mach RC tao ra. D6i vdi cac loai oscillator LP, HS, XT, oscillator diroc g~n vao vi di~u khien thong qua cac pin OSCl/CLKI va OSC2/CLKO.
VvD D6i vdi cac ling dung khong cffn cac T loai oscillator t6c dQ cao, ta c6 thS sa dung lnternel mach dao dQng RC lam ngudn cung ca'p ~___,..... Glock xung hoat dQng cho vi vi di~u khicn. T~n sO" PIIC16U7XA tao ra phu thuoc vao cac gia tri dien ap, gia ...... ---1 OSC2!OLKO tri dien trd va tv dien, ben canh d6 la s1;l'anh foro'4L__-------~ hudng ciia cac ye'u to" nhir nhiet dQ, cha't Hlnh 2.39 RC oscillator. hrong cua cac linh kien, Cac linh kien sa dung cho mach RC oscillator phai bao dam cac gia tri sau: 3 K < REXT < 100 K CEXT >20 pF
~ ... , ?

2.14.3 CAC CUE DORESET C6 nhieu che' dQ reset vi di~u khien, bao gdm: Power-on Reset POR (Reset khi ca'p ngudn hoat dQng cho vi di~u khien). MCLR reset trong qua trlnh hoat dQng. MGLR til che' dQ sleep. WDT reset (reset do khdi WDT tao ra trong qua trmh hoat dQng). WDT wake up til che' dQ sleep. Brown-out reset (BOR).

Ngoai tnr reset POR trang thai cac thanh ghi la khong xac dinh va WDT wake up khong anh hirdng de'n trang thai cac thanh ghi, cac che' dQ reset con 19-ideu dira gid tri cac thanh ghi ve gia tri ban d~u du'<_1C dinh san. Cac bit irO va PD chi thi trang thai hoat dQng, a'n trang thai reset cua vi dieu khi€n va diroc dieu khi€n bdi cpu. reset: Khi pin MCLR d rmic logic thap, vi dieu khicn se diroc reset. Tin hieu reset du'<_1C cung ca'p bdi mot mach ngoai vi vdi cac yeu cffu cu th€ sau: Khong no'i pin MCLR tnrc tiep len ngudn VDD• R1 phai nho hen 40 K d€ dam bao cac d~c tinh dien cua vi dieu khien, R2 phai ldn hon 1 K d€ han dong di vao vi dieu khicn.
MCLR MCLR

Htnh
ill

2 40
•

Mach

reset

qua pm

MCiLR

reset con dircc chong nhieu bdi mot bQ IQc d€ tranh cac tin hieu nho tac dQng

len pin MCiLR. Power-on reset (POR): Day la xung reset do vi dieu khi€n t9-0 ra khi phat hien ngudn cung ca'p VDD. Khi hoat dQng d che'dQ blnh thuong, vi dieu khidn cffn diroc dam bao cac thong so've dong dien, dien ap d€ hoat dQng blnh tlnrong. Nhung ne'u cac tham so' nay khong dircc dam bao, xung reset do POR t9-0 ra se dira vi dieu khien ve trang thai reset va chi tie'p tuc hoat dQng khi nao cac tham so' tren duoc dam bao. Power-up Timer (PWRT): day la bQ dinh thoi hoat dQng dua vao mach RC ben trong vi dieu khi€n. Khi PWRT diroc kich heat, vi dieu khien se diroc dira ve trang thai reset. PWRT se t9-0 ra mot khoang thoi gian delay (khoang 72 ms) d€ VDD tang de'n gia tri thich hop. Oscillator Start-up Timer (OST): OST cung ca'p mot khoang thci gian delay bang 1024 chu kl xung cua oscillator sau khi PWRT ngung tac dQng (vi dieu khien dii du dieu kien hoat dQng) d€ dam bao stf6n dinh cua xung do oscillator phat ra. Tac dQng ciia OST con xay ra do'i vdi paR reset va khi vi dieu khien diroc danh thirc til che' d<_1leep. OST chi tac dQng do'i s vdi cac loai oscillator la XT, HS va LP. Brown-out reset (BaR): Neu VDD ha xudng thap hen gia tri VBOR (khoang 4V) va keo dai trong khoang thoi gian ldn hen TBOR (khoang 100 us), BaR diroc kich hoat va vi dieu khien dircc dira ve trang thai BaR reset. Neu dien ap cung ca'p cho vi dieu khi€n ha xudng thap hon VBOR trong khoang thoi gian ngan hen TBOR, vi dieu khi€n se khong diroc reset. Khi di~n ap cung ca'p du cho vi dieu khi€n hoat dQng, PWRT diroc kich hoat d€ t9-0 ra mot khoang thoi gian delay (khoang 72ms). Neu trong khoang thC1igian nay di~n ap cung ca'p cho

vi di~u khi~n lai tie'p tuc ha xuong dirdi rmrc dien ap VBOR,BOR reset se 19-idiroc kich hoat khi vi di~u khien du di~n ap hoat dQng. MQt di~m cffn chti y la khi BOR reset diroc cho phep, PWRT cling se hoat dQng ba't chap trang thai ciia bit PWRT. Tom 19-id~ vi di~u khicn hoat dQng diroc til khi ca'p ngudn cffn tnli qua cac birdc sau: POR tac dQng. PWRT (ne'u dircc cho phep hoat dQng) t9-0 ra khoang thoi gian delay TpWRTd~6n dinh ngudn cung ca'p. OST (neu diroc cho phep) t9-0 ra khoang thoi gian delay bang 1024 chu kl xung cua oscillator d~ 6n dinh t~n so' ciia oscillator. De'n thC1idi~m nay vi di~u khicn mdi b~t d~u hoat dQng blnh thirong. Thanh ghi di~u khien va chi thi trang thai ngudn cung ca'p cho vi di~u khicn la thanh ghi PC ON (xem phu luc 2 d~ bie't them chi tie't).
IExI:em,aJ

._

~s

I®-<bitRipp~ C~~ater

>

'm~t RilPple C~unter

En"hle PWR1T

EBilbl80ST

Hlnh 2.41 So d6 cac che'dQ reset cua PIC16F877 A. 2.14.4 NGAT (INTERRUPT) PIC16F877A co de'n 15 ngudn t9-0 ra hoat dQng ngdt diroc di~u khien bdi thanh ghi INTCON (bit GIE). Ben canh do m6i ngat con co mot bit di~u khien va cC1 ngdt rieng, Cac cC1 ngdt vftn diroc set blnh thirong khi thea man di~u kien ngat xay ra ba't chfp trang thai cua bit GIE, tuy nhien hoat dQng ng~t vftn phu thuoc van bit GIE va cac bit di~u khicn khac. Bit di~u khi~n ngat RBO/INT va TMRO narn trong thanh ghi INTCON, thanh ghi nay con chua bit cho

phep cac ngat ngoai vi PEIE. Bit di~u khien cac ngat nam trong thanh ghi PIEl va PIE2. CC1 ngdt cua cac ng~t n~m trong thanh ghi PIRl va PIR2. Trong mot thoi diSm chi co mot chuong trinh ngat diroc thuc thi, chuong trlnh ngat diroc ke"t thiic bang lt$nh RETFIE. Khi chuong trmh ngat diroc thirc thi, bit GIE tlj dQng du'<_1C xoa, dia chi lenh tie"p theo cua chuong trinh chinh diroc ca't vao trong bQ nhd Stack va bQ de"m chirong trinh se chi de"n dia chi 0004h. Lenh RETFIE diroc dung dS thoat khoi chuong trinh ngdt va quay trd v~ chirong trlnh chinh, d6ng thC1ibit GIE ding se dircc set dS cho phep cac ngdt hoat dQng trd 19-i.Cac cC1 hieu diroc dung dS kiern tra ngat nao dang xay ra va phai diroc xoa bang chirong trlnh tnrdc khi cho phep ngat tie"p tuc hoat dQng trd 19-idS ta co thS phat hien dircc thoi diSm tie"p theo rna ng~t xay ra. DO'i vdi cac ng~t ngoai vi nhu ngdt til chan INT hay ng~t til slj thay d6i trang thai cac pin cua PORTB (PORTB Interrupt on change), viec xac dinh ng~t nao xay ra cffn 3 hoac 4 chu kl lenh tuy thuoc vao thoi diSm xay ra ngdt. Cffn chri y la trong qua trlnh thuc thi ngat, chi co gia tri cua bQ de"m chtrong trmh du'<_1c ca't vao trong Stack, trong khi mot sO'thanh ghi quan trong se khong diroc ca't va co thS bi thay d6i gia tri trong qua trlnh thirc thi chuong trmh ngft, Di~u nay nen diroc xii' li bang chirong trinh dS tranh hien nrong tren xay ra.
E:EIF EEIE

----r---\

-LJ..... ---------...,

f'SPIFi1} -I) f'SPIE'1~ -LJ;------------,

TMRGIF ...,---TM~:;:GIE-{_, :

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n.1R1I n.IR1I

~g~:~:O,-----------J
CMIF

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Hlnh 2.42 So d6 logic cua ta't

ca cac

ngdt trong vi di~u khiSn PICl6F877 A.

2.14.4.1 NGA TINT Ng~t nay dua tren slj thay d6i trang thai cua pin RBO/INT. Canh tac dQng gay ra ngat co th€ la canh len hay canh xuong va dircc di€u khi€n bdi bit INTEDG (thanh ghi OPTION_ REG <6». Khi co canh tac dQng thich hop xua't hien tai pin RBO/INT, cClng~ t INTF diroc set ba't chap trang thai cac bit di€u khien GIE va PEIE. Ng~t nay co khd nang danh thuc vi di€u khicn til che' dQ sleep ne'u bit cho phep ng~t diroc set tnrdc khi l~nh SLEEP diroc thuc thi. 2.14.4.2 NGAT DO

str THAY Dch

TR~NG

THAI CAC PIN TRONG PORTB

Cac pin PORTB<7:4> diroc dung cho ngdt nay va diroc di€u khien bdi bit RBIE (thanh ghi INTCON<4». CClngdt cua ng~t nay la bit RBIF (INTCON<O». 2.14.5 WATCHDOG TIMER (WDT)

Watchdog timer (WDT) la bQ de'm dQc l~p dung ngudn xung de'm til bQ tao xung diroc tich hop san trong vi di€u khien va khong phu thuoc vao ba't kl ngudn xung clock ngoai vi nao, Di€u do co nghia la WDT vfin hoat dQng ngay khi xung clock du'<jc la'y til pin OSCl/CLKI va pin OSC2/CLKO cua vi di€u khien ngung hoat dQng (chang han nhir do tac dQng ciia l~nh sleep). Bit di€u khi€n ciia WDT Ia bit WDTE nam trong bQ nhd chuong trmh a dia chi 2007h (Configuration bit).

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WDT se tlj dQng reset vi di€u khien (Watchdog Timer Reset) khi bQ de'm cua WDT bi tran (neu WDT diroc cho phep hoat dQng), d6ng thoi bit TO tlj dQng diroc xoa. Ne'u vi di€u khicn dang ache' dQ sleep thl WDT se danh thirc vi di€u khien (Watchdog Timer Wake-up) khi bQ de'm bi tran. Nhu v~y WDT co tac dung reset vi di€u khien a thoi di€m dn thie't rna khong dn de'n slj tac dQng til ben ngoai, chang han nhu trong qua trmh thuc thi lenh, vi di€u khicn bi "ket" a met ch6 nao do rna khong thoat ra dtroc, khi do vi di€u khi€n se tlj dQng diroc reset khi WDT bi tran € chuong trlnh hoat dQng dung tra lai. Tuy nhien khi sii' dung WDT cfing co su phien toai VI vi di€u khicn se thirong xuyen diroc reset sau met thoi gian nha't dinh, do doi dn tinh toan thCli gian thich hop d€ xoa WDT (dung lenh CLRWDT). Va d€ viec a'n dinh thoi gian reset diroc linh dQng, WDT con diroc h6 tro mot bQ chia t~n sO' prescaler diroc di€u khien bai thanh ghi OPTION_REG (prescaler nay diroc chia xe vdi TimerO). MQt di€m dn chti Y mla la lenh sleep se xoa bQ de'm WDT va prescaler. Ngoai ra l~nh xoa CLRWDT chi xoa bQ de'm chii khong lam thay d6i dO'i nrcng tac dQng cua prescaler (WDT hay TimerO). Xem lai TimerO va thanh ghi OPTION_REG (phu luc 2) d€ bie't them chi tie't.

2.14.6 CHE

""

DO
A

SLEEP

Day Hi che' dQ hoat dQng cua vi di€u khien khi l~nh SLEEP dircc thuc thi. Khi d6 ne'u dircc cho phep hoat dQng, bQ de'm cua WDT se bi x6a nhirng WDT v~n tiep tuc hoat dQng, bit PD (ST ATUS<3» diroc reset v€ 0, bit TO diroc set, oscillator ngirng tac dQng va cac PORT giii' nguyen trang thai nhu tnrdc khi l~nh SLEEP du'<jcthuc thi. Do khi d che'dQ SLEEP, dong cung ca'p cho vi di€u khien la ra't nho nen ta dn thuc hien cac birdc sau tnrdc khi vi di€u khicn thuc thi l~nh SLEEP: Dira ta't cac pin v€ trang thai VDD hoac Vss C~n bao dam r~ng khong co mach ngoai vi nao diroc di€u khi€n bdi dong dien ciia vi di€u khi€n VI dong dien nho khong du kha nang cung ca'p cho cac mach ngoai vi hoat dQng. Tam ngirng hoat dQng cu khdi AID va khong cho phep cac xung clock til ben ngoai tac dQng vao vi di€u khi€n. D€ y de'n chirc nang keo len di~n trd d PORTB. Pin MCLR phai d rmrc logic cao.

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2.14.6.1 "DANH THUC" VI DlEU KHIEN Vi di€u khi€n c6 th€ diroc "danh thiic" dudi tac dQng cua mot trong so' cac hien nrong sau: 1. Tac dQng ciia reset ngoai vi thong qua pin MCLR . 2. Tac dQng ciia WDT khi bi tran, 3. Tac dQng til cac ngdt ngoai vi til PORTB (PORTB Interrupt on change hoac pin INT). Cac bit PQ va TO diroc dung d€ th€ hien trang thai ciia vi di€u khien va d€ phat hien ngudn tac dQng lam reset vi di€u khien, Bit PD diroc set khi vi di€u khi€n diroc ca'p ngudn va diroc reset v€ 0 khi vi di€u khien d che' dQ sleep. Bit irO diroc reset v€ 0 khi WDT tac dQng do bQ de'm bi tran, Ngoai ra con c6 mQt so' ngudn tac dQng khac til cac chtrc nang ngoai vi bao g6m: 1. DQc hay ghi dii' lieu thong qua PSP (Parallel Slave Port). 2. Ng~t Timer1 khi hoat dQng d che'dQ de'm ba't d6ng bQ. 3. Ngat CCP khi heat dQng d che'dQ Capture. 4. Cac hien nrong d~c biet lam reset Timer1 khi hoat dQng d che'dQ de'm ba't d6ng bQ dung ngudn xung clock d ben ngoai), 5. Ngat SSP khi bit Start/Stop diroc phat hien. 6. SSP hoat dQng d che'dQ Slave mode khi truyen hoac nhan dii' lieu. 7. Tac dQng cua USART til cac pin RX hay TX khi hoat dQng d che'dQ Slave mode d6ng bQ. 8. Kho'i chuyen d6i AID khi ngudn xung clock hoat dQng d dang RC. 9. Roan ta't qua trmh ghi vao EEPROM. 10. Ngo ra bQ so sanh thay d6i trang thai.

Cac tac dQng ngoai vi khac khong c6 tac dung danh thiic vi dieu khi~n vi khi d che'dQ sleep cac xung clock cung ca'p cho vi dieu khi~n ngirng hoat dQng. Ben canh d6 dn cho phep cac ngat hoat dQng tnrdc khi lt$nh SLEEP dircc thuc thi d~ bao dam tac dQng cua cac ngft, Vit$c danh tlnrc vi dieu khi~n til cac ng~t v~n diroc thuc thi ba't chap trang thai cua bit GIE. Ne'u bit GIE mang gid tri 0, vi dieu khi~n se thuc thi lenh tie'p thea sau lenh SLEEP cua chirong trinh (vi chuong trlnh ngat khong diroc cho phep thuc thi). Ne'u bit GIE diroc set tnrdc khi lt$nh SLEEP dtroc thuc thi, vi dieu khien se thuc thi lt$nh tie'p thea cua chtrong trmh va sau d6 nhay tdi dia chi chua chuong trmh ngdt (0004h). Trong tnrong hop lenh tie'p thea khong d6ng vai tro quan trong trong chuong trtnh, ta dn d~t them lt$nh NOP sau lenh SLEEP d~ bo qua tac dQng ciia lenh nay, d6ng thoi giiip ta d~ dang hen trong viec kiern soat hoat dQng ciia chuong trinh ngat. Tuy nhien ding c6 mot s6 di~m dn hill y nhir sau: Ne'u ngdt xay ra tnrdc khi lenh SLEEP diroc thirc thi, lenh SLEEP se khong diroc thirc thi va thay vao d6 la lt$nh NOP, d6ng thoi cac tac dQng cua lenh SLEEP cting se diroc bo qua. Ne'u ngdt xay ra trong khi hay sau khi lt$nh SLEEP diroc thirc thi, vi dieu khi~n l~p tuc du'<_1c danh thirc til che' dQ sleep, va lenh SLEEP se diroc thuc thi ngay sau khi vi dieu khicn du'<_1C danh thiic, ki~m tra xem lt$nh SLEEP dff diroc thuc thi hay chua, ta kiern tra bit PD. Ne'u bit P'D v~n mang gia tri 1 nrc la lt$nh SLEEP dff khong diroc thuc thi va thay vao d6 la lt$nh NOP. Ben canh do ta dn x6a WDT d~ chao chan dng WDT dff diroc x6a tnrdc khi thuc thi lt$nh SLEEP, qua do cho phep ta xac dinh diroc thoi di~m vi dieu khi~n dircc danh thiic do tac dQng ciia WDT.
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CHu'(jNG 3 T!P LtNH CUA VI BlEU KHIEN PIC

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CVA VI DIEU KHIEN PIC

Nhir da trlnh bay d chirong 1, PIC la vi di€u khi€n c6 t~p lenh rut gon RISC (Reduced Instruction Set Computer), bao gam 35 lenh va c6 th€ du'<;fC phan ra thanh 3 nh6m cd ban: Nh6m l~nh thao tac tren bit. ByfieLo rle nted f'i le reg:i:s,ier ooperali'o IlS 13 8 7' 0' Nh6m l~nh thao tac tren byte. j'~FILE";!) I OPDOIDE I dI Nh6m l~nh di€u khien, Ddi vdi dong vi di€u khidn PICI6Fxxx, m6i l~nh diroc rna h6a thanh 14 bit word, bao gam cac bit opcode (dung d€ xac dinh l~nh nao diroc rna h6a) va cac bit rna ta met hay vai tham sd ciia Ienh, Ddi vdi nh6m l~nh thao tac tren byte, ta c6 2 tham sd f (xac dinh dia chi byte dn thao tac) va d (xac dinh noi chua ke't qua thuc thi l~nh). Neu d = 0, ke't qua se diroc dua vao thanh ghi W. Ne'u d = 1, ke't qua dircc dira vao thanh ghi dircc rna ta bdi tham sdf. Ddi vdi nh6m lenh thao tac tren bit, ta c6 hai tham sd b (xac dinh bit dn thao tac) va f (xac dinh dia chi byte dii' lieu dn thao tac).
III " 0 For deOl'b]li'Iatio 1'1 '\!'I! dl " :L For de~'b] netio n I j' '" 7 - ~ it 'fl.1 re.gIsler add res ~ e Bil-o:rhoTlred ~1iE:'regi,s;rer operatiens

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Hlnh 3.1 Co che' rna h6a lenh cua PIC 16Fxxx. Ddi vdi nh6m l~nh di€u khien chi c6 mQt tham sd duy nhdt la k (k c6 th€ la 8 bit trong tnrcng hop cac l~nh blnh thirong hay 11 bit trong tnrong hop la lenh CALL va l~nh GOTO) dung d€ rna ta ddi tuong tac dQng cua vi di€u khi€n (mQt label, mQt hang sd nao d6). M6i lenh se diroc vi di€u khicn thuc thi xong trong vong mQt chu kl l~nh, ngoai tru cac l~nh lam thay d6i gia tri bQ de'm chtrong trmh PC dn 2 chu kl lenh. MQt chu ki lenh gam 4 xung clock ciia oscillator. Vi du ta sii' dung oscillator c6 tffn sd 4 MHz thl tffn sd thirc thi l~nh se la 4MHz/4 = 1 MHz, nhir vay mQt chu ki lenh c6 thCfigian 1 uS. Cac l~nh thao tac tren mot thanh ghi b(t kl d€u thirc hien co che' Read-Modify-Write, tuc la thanh ghi se diroc doc, dii' lieu diroc thao tac va ke't qua diroc dira vao thanh ghi chua ke't qua (noi chua ke't qua tuy thuoc vao lenh thuc thi va tham sd d). Vi du nhu khi thirc thi l~nh "CLRF PORTB", vi di€u khien se doc gia tri thanh ghi PORTB, x6a t(t cac bit va ghi ke't qua trd lai thanh ghi PORTB. Sau day ta se di sau vao c(u tnic, cu phap va tac dQng cu th€ cua tung l~nh.

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3.2 T~P L~NH CVA VI DIEV KHIEN PIC 3.2.1 L~nh ADDLW phap: ADDLW k (0 s k~255) Tac dung: cQng gia tri k vao thanh ghi W, ke"t qua du'<_1C trong thanh ghi W. chua Bit trang thai: C, DC, Z 3.2.2 L~nh ADDWF Cu phap: ADDWF f,d 3.2.5 L~nh BCF

A.

A.

,Q

cc

ce phap: BCF f,b (0~f~127, 0~b~7) Tac dung: x6a bit b trong thanh ghi f v€ gid tri O. Bit trang thai: khong c6.
3.2.6 L~nh BSF BSF f,b «isrs 127, 0~b~7) Tac dung: set bit b trong trnh ghi f. Bit trang thai: khong c6 3.2.7 Lenh BTFSS BTFSS f,b «isrs 127, 0~b~7) Tac dung: kiSm tra bit b trong thanh ghi f. Ne"u bit b bang 0, lenh tie"p theo du'<_1C thirc thi. Neu bit b bang 1, lenh tie"p theo diroc bo qua va thay vao do Ia lenh NOP. Bit trang thai: khong c6 3.2.S Lenh BTFSC

cc phap:

(0~f~255, dE[O,I]). Tac dung: cQng gia tri hai thanh ghi W va thanh ghi f. Ke"t qua diroc chua trong thanh ghi W neu d = 0 hoac thanh ghi f ne"u d =1. Bit trang thai: C, DC, Z 3.2.3 L~nh ANDLW ANDL W k (0~k~255) Tac dung: thuc hien phep toan AND gifta thanh ghi : va gid tri k, ke"t qua diroc chua trong thanh ghi W. Bit trang thai: Z 3.2.4 L~nh ANDWF Cu phap: ANDWF f,d

cc phap:

cc phap:

127, d E[O,I]). Tac dung: thuc hien phep toan AND giira cac gia tri chua trong hai thanh ghi W va f. Ke"t qua du'<_1cira vao thanh ghi W ne"u d d=O hoac thanh ghi f ne"u d = 1. Bit trang thai: Z

rosrs

Cu phap: BTFSC f,b «isrs 127, 0~b~7) Tac dung: kiSm tra bit b trong thanh ghi f. Neu bit b bang 1, lenh tie"p theo du'<_1c thuc thi. Neu bit b bang 0, lenh tie"p theo diroc bo qua va thay vao do la lenh NOP. Bit trang thai: khong c6

3.2.9 L~nh CALL CALL k (0~k~2047) Tac dung: goi mot chtrong trmh con. Tnrdc he"t dia chi quay trd ve, tu chuong trinh con (PC+ 1) dlt<_1c a't vao trong Stack, gid tri c dia chi mdi diroc dira vao b(l de"m gam 11 bit ciia bien k va 2 bit PCLATH<4:3>. Bit trang thai: khong co 3.2.10 Lenh CLRF 3.2.15 Lenh DECFSZ Cu phap CLRF f (O~f~ 127) Tac dung: xoa thanh ghi f va bit Z diroc set. Bit trang thai: Z 3.2.11 Lenh CLRW Cu phap CLRW Tac dung: xoa thanh ghi W va bit Z diroc set. Bit trang thai: Z 3.2.12 L~nh CLRWDT Cu phap: CLRWDT Tac dung: reset Watchdog Timer, dang thoi prescaler cling diroc reset, cac bit PO va IrO dircc set len 1. Bit trang thai: IrO, PD 3.2.13 L~nh COMF Cu phap: COMF f,d (0~f~127, dE[O,I]). Tac dung: dao cac bit trong thanh ghi f. Ke"t qua dlt<_1c ira vao thanh ghi W ne"u d d=O hoa c thanh ghi f ne"u d= 1. Bit trang thai: Z

cc phap:

3.2.14 L~nh DECF Cu phap: DECF f,d (0~f~127, dE[O,I]). Tac dung: gia tri thanh ghi f dircc giam di 1 don vi. Ke"t qua diroc dira vao thanh ghi W ne"u d = 0 hoac thanh ghi f ne"u d = 1. Bit trang thai: Z

cc phap:

DECFSZ f,d

(0~f~127, dE[O,I]) Tac dung: gta tri thanh ghi f diroc giam 1 don vi. Neu ke"t qua sau khi giam khac 0, lenh tie"p theo diroc thuc thi, ne"u ke"t qua bang 0, l~nh tie"p theo khong diroc thuc thi va thay vao do la lenh NOP. Ke"t qua diroc dira vao thanh ghi W neu d = 0 hoac thanh ghi f ne"u d = 1. Bit trang thai: khong co 3.2.16 L~nh GOTO GOTO k (0~k~2047) Tac dung: nhay tdi mot label diroc dinh nghla bdi tham s6 k va 2 bit PCLA TH <4:3>. Bit trang thai: khong co. 3.2.17 Lenh INCF

ce phap:

cc phap:

INCF f,d

E[O,I]) Tac dung: tang gia tri thanh ghi f len 1 don vi. Ke"t qua diroc dira vao thanh ghi W ne"u d = 0 hoac thanh ghi f ne"u d = 1. Bit trang thai: Z

«isrs 127, d

3.2.18 L~nh INCFSZ 3.2.22 L~nh RETURN Cu phap: INCFSZ f,d (0::::;f::::;127, dE[0,1]) Tac dung: tang gia tri thanh ghi f len 1 don vi. Neu ktt qua khac 0, lenh tiep theo diroc thirc thi, ntu ktt qua bang 0, l~nh tiep theo diroc thay bang l~nh NOP. Ktt qua se dUQc dira vao thanh ghi f ntu d=1 hoac thanh ghi W ntu d = O. Bit trang thai: khong co. RETURN Tac dung: quay trd ve chirong trmh chinh til mot chuong trlnh con Bit trang thai.khong co 3.2.23 L~nh RRF Cu phap: RRF f,d (0::::;f::::;127, dE[0,1]) Tac dung: dich phai cac bit trong thanh ghi f qua cCf carry. Ktt qua dUQC htu trong thanh ghi W ntu d=O hoac thanh ghi f ntu d=l.

ce phap:

3.2.19 L~nh IORL W IORLW k (0::::;k::::;255) Tac dung: thirc hien phep toan OR giii'a thanh ghi W va gia tri k. Ktt qua diroc chua trong thanh ghi W. Bit trang thai: Z 3.2.20 Lenh IORWF Cu phap: IORWF f,d (0::::;f::::;127, dE[0,1]) Tac dung: thirc hien phep toan OR giii'a hai thanh ghi W va f. Ktt qua dUQCdira vao thanh ghi W ntu d=O hoac thanh ghi f neu d= I. Bit trang thai: Z 3.2.21 L~nh RLF Cu phap: RLF f,d (0::::;f::::;127, dE[0,1]) Tac dung: dich trai cac bit trong thanh ghi f qua cCfcarry. Ktt qua dUQChtu trong thanh ghi W ntu d=O ho~c thanh ghi f ntu d=l.
~ Register I

cc phap:

C~I

Regi"lterf

Bit trang thai: C

3.2.24 L~nh SLEEP SLEEP Tac dung: dira vi dieu khi~n ve cht dQ sleep. Khi do WDT bi xoa ve 0, bit PD diroc xo ve 0, bit IrO diroc set len 1 va oscillator khong dircc cho phep hoat dQng. Bit trang thai: IrO, PD.

ce phap:

3.2.25 L~nh SUBL W Cu phap: SUBLW k Tac dung: la'y gia tri k trir gia tri trong thanh ghi W. Ktt qua diroc chua trong thanh ghi W. Bit trang thai: C, DC, Z

1::1

Bit trang thai: C

3.2.26 Lenh SUBWF 3.2.28 Lenh XORLW Cu phap: SUBWF f,d (O~f~127, dE[O,l]) Tac dung: la'y gia tri trong thanh ghi f dem tnr cho thanh ghi W. K€t qua du'<;lchill trong thanh ghiaW n€u d=O hoac thanh ghi
f neu d= l .

XORLW k (O~k~255) Tac dung: thuc hien phep toan XOR gifta gid tri k va gid tri trong thanh ghi W. K€t qua dircc hill trong thanh ghi W. Bit trang thai: Z 3.2.29 L~nh XORWF

cc phap:

Bit trang thai: C, DC, Z 3.2.27 Lenh SWAP Cu phap: SWAP f,d (O~f~127, dE[O,l]) Tac dung: dao 4 bit tha'p vdi 4 bit cao trong thanh ghi f. K€t qua diroc chua trong thanh ghiaW n€u d=O hoac thanh ghi f neu d=l. Bit trang thai: khong c6

Cu phap: XORWF f,d Tac dung: thuc hien phep toan XOR gitta hai gia tri chua trong thanh ghi W va thanh ghi f. K€t qua diroc hill vao trong thanh ghi W n€u d=O hoac thanh ghi f n€u d= I. Bit trang thai: Z

Ngoai cac lenh tren con c6 mot s61~nh dung trong chuong trlnh nhir: 3.2.30 Lenh #DIFINE Cu phap: #DEFINE -ctextl » <text2> Tac dung: thay the mQt chu6i ki t11nay bang mQt chu6i ki t11khac, c6 nghia la m6i khi chuei ki t11textl xua't hien trong chuong trtnh, trmh bien dich se t11dQng thay the chudi ki t11 d6 bang chudi ki t11<text2>. 3.2.31 L~nh INCLUDE Cu phap: #INCLUDE <filename> hoac #INCLUDE "filename" Tac dung: dinh kern mQt file khac vao chirong trmh, tirong t11nhu viec ta copy file d6 vao vi tri xudt hien lenh INCLUDE. Neu dung cu phap <filename> thl file dlnh kern la file h~ thong (sitem file), n€u dung cii pha p "filename" thl file dinh kern la file cua ngu'Cfisa dung. Thong thuong chirong trinh diroc dinh kern thea mot "header file" chua cac thong tin dinh nghia cac bien (thanh ghi W, thanh ghi F, ..) va cac dia chi cau cac thanh ghi clnrc nang d~c biet trong bQ nhd dfi' lieu, Neu khong c6 header file, chuong trmh se kh6 dQCva kh6 hi€u hen,

3.2.32 L~nh CONSTANT Cu phap: CONSTANT <nameo=-cvalue> Tac dung: khai bao mQt h~ng sa, c6 nghia la khi pha t hien chuc3i ki t11"name" trong chtrong trinh, trmh bien dich se t11dQng thay bang chuc3i ki t11bang gia tri "value" dii diroc dinh nghfa tnrdc d6. 3.2.33 L~nh VARIABLE Cu phap: VARIABLE <name>=<value> Tac dung: tu'dng t11nhir l~nh CONSTANT, chi c6 di€m khac biet duy nhdt la gia tri "value" khi dung lenh VARIABLE c6 th€ thay d6i diroc trong qua trinh thirc thi chuong trmh con lenh CONSTANT thl khong. 3.2.34 L~nh SET Cu phap: <name variable> SET <value> Tac dung: gan gia tri cho mot ten bien. Ten cua bien c6 th€ thay d6i du'<;lc trong qua trinh thuc thi chirong trlnh. 3.2.35 L~nh EQU Cu phap: <name constant> EQU <value> Tac dung: gan gia tri cho ten cua ten cua hang sa. Ten cua h~ng sa khong thay d6i trong qua trlnh thuc thi chuong trlnh. 3.2.36 Lenh ORG Cu phap: ORG <value> Tac dung: dinh nghia mot dia chi chua chuong trmh trong bQ nhd chuong trinh cua vi dieu khi€n. 3.2.37 L~nh END cc phap: END Tac dung: danh dau ktt thuc chirong trinh. 3.2.38 Lenh _CONFIG Cu phap: Tac dung: thitt l~p cac bit dieu khi€n cac khdi chuc nang cua vi dieu khien diroc chua trong bQ nhd chtrong trlnh (Configuration bit). 3.2.39 L~nh PROCESSOR Cu phap: PROCESSOR <processor type> Tac dung: dinh nghla vi dieu khi€n nao sii' dung chuong trmh,

3.3 CAU TRUC CVA MOT CHUONG TRiNH ASSEMBLY VIET CHO VI DlEU .:! KHIENPIC MQt chuong trmh Assembly bao gam nhieu thanh phan nhu chirong trmh chinh, chirong trinh ngdt, chucng trmh eon, ...d day chi trinh bay ea'u true mot chuong trlnh don gidn nha't khi mdi b~t dffu lam quen vdi viec l~p trlnh eho vi dieu khien PIC.
Inform,atiCirn 'On ltlle'
1=1

B·.:.s~t

ro.;) ram

-----t :lJers:i()rl

J Prourarn

for initielizetion

of port Band

S'l:lttilfllg

pins to status
Written

of louie ems
bv: John Smith

1.01 Date ~ 1101 ,10,,1 !)I,')i19" MCiIJ: flIClL6f~'4

; De'ciar,ationand

eonfiqureticn off a processor PROCESSOR'1I6FII:4. ifil1l!:l:ude "F,11iifS4Jiuc" ; P'rocess:or title

DirectivE

---+----~OONFIG ..
Dr!!) goto orlll goto

_CP _OF'F
l(b,iJilli [Mllin 10,:<04 [Ml'lin

s _)NIH _O:FF: & _If!I"WRJE~O~

; Start of proqrern ; R'e;:,et ...ector
; Go to the be:Qlinning of

8. _)(1 _O,SC

Main

; Interrupt vector
j j

lntiilrrupt Inti3rrupt

vector

reutin ..' doesn't exist

'------Comment.---~------------

#i!1!!:!:u:de '''b:1lnk,jm:;:''
B,AN~1

Mclin
label tnstruotion
Operand
iI-----+-...J

._---+--

mlINl:w 1(i;.,iJillI mouwf lilRlSB

Eli\NliU) mmv1:w ill:w:FF mmvwf [PGnnl

,_---+--------,

~ ~mt 8, ~ins sre IJblItPlJt : Sel,ect,memory bank ~

lJ()@P

goto

LooJl'

end
Hlnh 3.2 Cau true mot chirong trmh Asembly vie't eho vi di€u khien PIC. Ta nhan tha'y r~ng khong e6 su khac biet Ion trong ea'u true cua mQt chuong trlnh Assembly vie't eho vi dieu khien PIC so vdi vi dieu khien khac, chi e6 slJ'khac biet ve cac l~nh sti' dung trong chtrong trmh. Da'u ";" diroc dung d€ dira mot ghi chti vao chirong trmh va chi e6 hieu hrc tren mot hang cua chuong trmh. Hlnh tren la vi du ve mot chuong trlnh don gian vdi cac birdc khdi t9-0 co ban ban dffu, ngoai ra ne'u dn thiet ta v~n e6 th€ khai bao them cac bien, h~ng va cac tham sa khac tnrdc chuong trlnh chinh (label "Main "). Trong tnrong hop dn sti' dung de'n chuong trmh ngdt, ta dn mot ea'u tnic chuong trtnh phirc t9-P hon vdi nhieu birdc khdi t9-0 phirc t9-P va phai tuan thea mot thti tlJ' l~nh nha't dinh. Tuy nhien neu sti' dung trlnh bien dich MPLAB, ea'u true cua chtrong trlnh danh eho mQt vi dieu khi€n PIC nha't dinh dff ducc vie't san, ta chi viec vie't doan chuong trmh dieu khien vao cac vi tri thich hop tren m~u chuong trlnh diroc vie't tnrdc d6. Day la mot lei the' ra't Ion khi sti' dung MPLAB d€ soan thao cac chirong trlnh vie't eho vi dieu khien PIC.

CHu'(jNG 4

MOT SO UNG DlJNG ClJ THE CUA PIC16F877A

,.."

Trong chuong nay ta se di sau vao mot s6 irng d1:111g1:l th~ ciia vi di~u khi~n C PIC16F877A. Cac irng dung nay diroc xay dung dua tren cac chiic nang ngoai vi dircc tich hop san ben trong vi di~u khi~n, qua do giiip ta ndm ro hon va dieu khien diroc cac khdi clnrc nang do. Tuy nhien tnrdc tien se la mot s6 irng dung don gian giiip ta birdc d~u lam quen vdi t~p l~nh va each vie't chuong trlnh cho vi di~u khien PIC. 4.1 DIEU KHIEN

cAc

PORT 1/0.

Day la met trong nhtrng irng dung don gian nhft giiip ta lam quen vdi vi di~u khi~n. Trong tmg dung nay ta se xudt mot gia tri nao do ra mQt PORT cua vi di~u khien, ch~ng han nhu PORTB. Gia tri nay se diroc ki~m tra bang each g~n vao cac pin cua PORTB cac LED. Khi do pin mang gid tri mire logic 1 se lam cho LED sang va pin mang gia tri rmrc logic 0 se lam cho LED t~t. Sau day la mot vai di~m dn chii D~ LED Volt tuy thea mau s~c rmrc logic 1 thuong la dong (co th~ dung dien

y cho irng dung

nay:

sang blnh thirong thl dien ap d~t len LED vao khoang 1.8 de'n 2.2 cua LED, trong khi dien ap tai ngo ra ciia 1 pin trong PORTB ne'u d 5 volt. Do do ta dn co them dien trd mdc n6i tiep vdi LED d~ han trd 0.33 K).

D~ xua't dircc gia tri ra PORTB, tnrdc he't ta dn khdi tao cac pin cua PORTB la output. Di~u nay diroc thuc hien bang each clear cac bit trong thanh ghi TRISB. Tuy nhien hai thanh ghi PORTB va TRISB n~m d hai bank khac nhau trong bQ nhd dfi' lieu. Do do tnrdc khi mudn truy xua't gia tri trong mQt thanh ghi nao do dn chon bank dfi' lieu chua thanh ghi do bang each dira cac gid tri thich hop vao 2 bit RP1:RPO cua thanh ghi STATUS (xem phu luc 2 va so d6 bQ nhd dfi' lieu). Do trong t~p l~nh ciia vi di~u khien PIC khong co lenh nao cho phep dira mot byte vao met thanh ghi cho tnrdc, do do dn sii' dung met thanh ghi trung gian (thanh ghi W) va dung hai lenh MOVLW (dtra byte vao thanh ghi W) va l~nh MOVWF (dtra gia tri trong thanh ghi W vao thanh ghi f nao do rna ta muon). Ngoai ra dn dung lenh ORG d~ chi ra dia chi b~t d~u chirong trlnh khi vi di~u khi€n du'<;jc reset. Thong thirong dia chi b~t d~u chuong trlnh se la dia chi OOOOh. Trong tnrong hop dn dung de'n che' dQ reset cua pin MCLR, ta co th~ thie't ke' them mot mach reset ngoai vi (vi di~u khi~n se diroc reset khi pin MCLR chuyen tll' mire logic 1 xuong rmrc logic 0).

Sau day la so d6 mach cua ling d1:111g tren:

R1 R U1 1 0.33 K 40 39 38 37 36 35 34 33
5V

-MClRNPP

1'1' 1'1' 1'1'

SW1~
5V

RB7/PGD RB6/PGC RAO/ANO RB5 RA1/AN1 RB4 RA2/AN2NREF-/CVREFRB3/PGM RA3/AN3NREF+ RB2 RB1 RA4fTOClliLC10UT RA51 AN4/SS/C20UT RBO/INT REOI.8.QLAN5 RE1IWR/AN6 RE2/CS/AN7 VDD GND RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4

0.33 K

0.33 K 0.33 K 0.33 K

1'1' 1'1' 1'1' 1'1'

32 31

11 12 13 14

VDD GND OSC1/ClK OSC2/ClKOUT

-=-0
0.33 K

aco/rr oso/ri

ClK RC7/RXlDT RC1 fT1 OSI/CCP2 RC6fTXlCK RC2/CCP1 RC5/SDO RC3/SCKlSCl RC4/SDI/SDA RDO/PSPO RD1/PSP1 PIC16F877A RD3/PSP3 RD2/PSP2

Hinh 4.1 Mach nguyen 11cua ling d1:111g dieu khi~n cac PORT ciia vi dieu khidn, MQt di~m dn chti Y la vi dieu khi~n PIC16F877A co de'n 2 pin VDD va 2 pin GND. Trong tnrong hop nay ta phai ca'p ngudn vao ta't cac pin tren, khi do vi dieu khi~n mdi co du di~n ap d~ hoat dQng.

ca

Chuong trinh vie't cho ling d1:111g nhu sau: tren .clnrong trinh 4.1.1 ;PORTBTEST.ASM processor include 16fS77a <pI6fS77a.inc> ; khai bao vi di€u khien ; header file dinh kern

_CONFIG _CP _OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ; khai bao cac "Configuration bits" ORG GOTO Start BCF BCF CLRF BSF MOVLW MOVWF BCF MOVLW MOVWF loop END GO TO STATUS,RPI STATUS,RPO PORTB STATUS,RPO OxOO TRISB STATUS,RPO OxSF PORTB loop OxOOO start ; dia chi b~t d~u chuong trmh ; chirong trmh chinh b~t d~u tai day ; chon BANKO
; xca PORTB

; chon BANKI

; PORTB <- outputs ; chon BANKO ; gia tri cffn dira ra PORTB ; PORTB <- SFh ; vong lap vo han ; ke't thiic chuong trinh

Cac birdc tiep theo d€ hoan ta't ling dung tren la bien dich chirong trmh tren bang mQt trinh bien dich Assembly danh cho vi dieu khien PIC (trlnh bien dich MPLAB chang han), sau do dung mach nap d€ nap chuong trmh vao vi di€u khi€n PIC va kiern tra ke't qua, Ne'u khong co UH nao xay ra, LED g~n vao cac pin RB7, RB3, RB2, RBI, RBO se sang, LED g~n vao cac pin con lai se t~t (do gid tri ta dira ra PORTB la SFh). Roan toan tirong tt! ta co th€ vie't chirong trinh dira mot gia tri ba't kl vao cac PORT cua vi di€u khi€n PICI6FS77A. Tuy nhien co mot di€u cffn chii y la do'i vdi PORTA, do pin

RA4 co cue thu d~ hd (xem phu luc 1) nen mudn PORTA hi~n thi ke't qua mQt each chinh xac ta cffn dung mot dien trd keo len g~n them vao ben ngoai pin RA4. 4.1.1 CHUdNG TRINH DELAY Chuong trmh tren giup ta dira gia tri ra cac PORT ciia vi dieu khi~n va cac LED se sang hay t~t tuy thea rmrc logic dua ra cac PORT. Bay giC1ta lai mudn cac LED se chdp t~t sau mot khoang thci gian dinh tnrdc, Mudn vay ta dung them mQt dean chirong trmh DELAY. Thirc cha't cua chirong trmh DELAY la cho vi dieu khien lam mot cong viec vo nghia nao do trong mot khoang thoi gian dinh tnrdc, Khoang thC1igian nay dircc tinh toan dua tren qua trmh thuc thi It%nh,hay C1:l th~ hon la dua vao thoi gian cua mQt chu ki lenh. Co th~ vie't chuong trlnh DELA Y dua tren dean chirong trlnh sau: MOVLW MOVWL DECFSZ GOTO
.....................

loop

OX20 delay-reg delay-reg loop

; gia tri 20h ; dira vao thanh ghi delay ; gidrn gia tri thanh ghi delay-reg 1 don vi ; nha y tdi label "loop" ne'u thanh ghi delay-reg ;sau khi giam 1 don vi chua gia tri khac O. ; lenh nay diroc thirc thi khi delay-reg bang 0

ti = 4/fo Vdi fo la t~n so' cua oscillator. Sd dI co cong thirc nay la VI mQt chu kl lenh bao g6m 4 xung clock. Cong thiic nay chi g~n dung VI ta dff bo qua thoi gian thuc thi cac lenh tnrdc label "loop" va mQt chu kl lenh phat sinh khi thanh ghi delay-reg mang gia tri 0 (tnrong hop nay cffn hai chu kl lenh d~ thuc thi lenh DECFSZ). Do thanh ghi delay-reg chi mang gid tri ldn nha't la FFh nen thoi gian delay chi gidi han d mot khoang thoi gian nha't dinh tuy thuoc vao xung clock sil' dung d~ ca'p cho vi dieu khien. Mudn tang thC1igian delay ta co th~ goi chtrong trmh delay nhieu l~n hoac tang so' hrong vong lap ciia chuong trmh delay nhu sau: MOVLW OXff MOVWF delay-reg 1 loop DECFSZ delay-reg 1 GOTO loopl ; thirc thi ding It%nhnay ne'u delay-reg khac 0 GOTO exit ; thirc thi dlng It%nhnay ne'u delay-reg bang 0 Loopl MOVLW OXff MOVWF delay-reg2 DECFSZ delay-reg2

Ne'u dung doan chuong trinh nay thl thoi gian delay diroc tinh g~n dung nhu sau: 1d = 3(1 +tv)ti Trong do td la thoi gian delay, tv la gia tri dira vao thanh ghi delay-reg va ti la thoi gian cua mQt chu ki lenh va diroc tinh thea cong thtrc:

MOVWF GOTO Exit

loopl loop

; thirc thi dlng lenh nay ne'u delay-reg khac 0 ; thirc thi dlng lenh nay ne'u delay-reg bang 0 ; l~nh tie'p theo sau thoi gian delay

Vdi dean chtrong trlnh tren thC1igian delay chi ke't thiic khi cii hai thanh ghi delay-reg 1 va delay-reg2 d~u rnang gid tri O. Sau day la mot vi du C1:l thS. Yeu cffu d~t ra la cho cac LED trong chuong trinh 4.1 chdp t~t sau rn6i 100 miligiay. Gia sir ta nang sli' dung oscillator 4MHz. Khi d6 thoi gian cua mot chu kl lenh la: ti = 4/4 MHz = 1 uS. Vdi thoi gian cffn delay la td bang 1s thl gia tri cffn dira vao thanh ghi delay-reg la: tv = (td/3tj) _ 1 = 33332. Nhu v~y ta dira vao thanh ghi delay-reg2 gid tri 255 (FFh) va thanh ghi delay-reg 1 gid tri 33332/255 = 131 (83h). Chuong trlnh diroc vie't nhir sau: .chuong trlnh 4.1.2 ;PORTBTESTANDDELA ;Version 1.1 processor include

Y.ASM

16f877a <p16f877a.inc>

; khai bao vi di~u khiSn ; header file dinh kern

__ CONFIG CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ; khai bao cac "Configuration bits" delay_reg1 delay_reg2 ORG GOTO start BCF BCF CLRF BSF MOVLW STATUS,RP1 STATUS,RPO PORTB STATUS,RPO OxOO EQU EQU Ox20 Ox21 OxOOO start ; khai bao dia chi cac 0 nhd chua cac thanh ghi ; delay-reg 1 va delay-reg2 ; dia chi b~t dffu chirong trlnh ; chuong trinh chinh b~t dffu tai day ; chQnBANKO ; x6a PORTB ; chQnBANKl

MOVWF BCF loop MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF loop1 DECFSZ GOTO GOTO loop2 DECFSZ GOTO GOTO exit! CLRF MOVLW MOVWF MOVLW MOVWF

TRISB STATUS,RPO Ox8F PORTB Ox83 delay_reg1 OxFF delay_reg2 delay_reg1 loop2 exit! delay_reg2 loop2 loop1 PORTB Ox83 delay_reg1 OxFF delay_reg2

; PORTB <- outputs ; chQnBANKO ; gia tri cffn dira ra PORTB ; PORTB <- 8Fh

; delay 100 ms ; x6a PORTB

loop3 DECFSZ GOTO GOTO loop4 DECFSZ GOTO GOTO exit2 GOTO END

delay_reg1 loop4 exit2 delay_reg2 loop4 loop3 loop

; delay 100 ms ; vong l~p

vo han

; ktt thuc chirong trlnh

Vdi chuong trlnh nay cac pin ciia PORTB se thay d6i trang thai sau mlii khoang thoi gian delay la 100 ms. Di€u nay cho phep ta nhan tha'y bang m~t thuong vi trong mot giay cac pin ciia PORTB se thay d6i trang thai 10 l~n.

Tuy nhien ta d~ dang nhan tha'y mot nhiroc diSm ciia chuong trmh tren la dn tdi hai doan chirong trlnh delay vdi ca'u tnic chirong trlnh, thuat toan va chirc nang hoan toan gidng nhau. Di~u nay lam cho chuong trmh trd nen phiic tap va to'n nhieu dung luong bQ nhd ciia vi di~u khidn, Di~u nay dn diroc chii trong VI dung hrong bQ nhd chuong trinh ciia mot vi di~u khiSn thtrong nho (do'i vdi PIC 16F877 A dung hrong bQ nhd chtrong trlnh la 8K word vdi mQt word la 14 bit). MQt phirong phap dS khac phuc nhiroc diSm nay la sil' dung chuong trinh con va dung l~nh "CALL" dS goi chuong trmh con do. Chuong trinh con co thS duoc d~t tai ba't cli vi tri nao trong chuong trlnh chinh. Chirong trlnh 4.2 khi do dircc vitt lai nhir sau: .chuong trinh 4.1.3 ;PORTBTESTANDDELA ;Version 1.2 processor include

Y.ASM

16f877a <p16f877a.inc>

; khai bao vi di~u khien ; header file dinh kern

CONFIG CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ; khai bao cac "Configuration bits" delay_reg1 delay_reg2 ORG GOTO start BCF BCF CLRF BSF MOVLW MOVWF BCF loop MOVLW MOVWF CALL STATUS,RP1 STATUS,RPO PORTB STATUS,RPO OxOO TRISB STATUS,RPO Ox8F PORTB delay100ms EQU EQU Ox20 Ox21 OxOOO start ; khai bao dia chi cac 0 nhd chua cac thanh ghi ; delay-reg1 va delay-reg2 ; dia chi b~t d~u chuong trlnh ; chuong trlnh chinh b~t d~u tai day ; chQnBANKO ; xoa PORTB ; chQnBANK1

; PORTB <- outputs ; chQnBANKO ; gia tri ba't kl dn dira ra PORTB ; PORTB <- 8Fh ; goi chuong trmh con delay100ms

CLRF CALL GOTO DelaylOOms MOVLW MOVWF MOVLW MOVWF DECFSZ GOTO GOTO 100p2 DECFSZ GOTO GOTO Exit RETURN END loopl

PORTB delaylOOms loop

; xoa PORTB ; vong l~p vo han

Ox83 delay_regl OxFF delay_reg2 delay_regl 100p2 exit delay_reg2 100p2 loopl

; delay 100 ms ; trd

ve chuong

trinh chinh

; ke't thiic chuong trinh

Vdi each vie't chtrong trmh sti' dung chirong trlnh con, c(u tnic chtrong trmh se trd nen gon gang d~ hiSu hen, linh hoat hon va tie't kiern diroc nhieu dung hrong bQ nhd chuong trlnh. Bay giCfta se ban de'n mot thuat toan khac dS vie't chtrong trlnh delay. nguyen t~c thl thuat toan mdi nay khong co nhieu khac biet so vdi thuat toan cti, tuy nhien l~nh sti' dung trong chircng trlnh va each tinh toan thoi gian delay thl khac nhau. Chirong trlnh con delay lOOms vdi oscillator 4 MHz co thS diroc vie't 19-inhir sau: delaylOOms MOVLW MOVWF dl MOVLW MOVWF MOVLW MOVWF delay_O DECFSZ GOTO d'lOO' count! OxC7 counta OxOl countb counta,l $+2

ve

DECFSZ GOTO DECFSZ GOTO RETLW END

countb,l delay_O countl,l d1 OxOO

Tnrdc tien ta xet doan chtrong trmh k€ til label "delay_O". Lenh DECFSZ ma't mQt chu kl l~nh (tnr tnrong hop thanh ghi counta mang gitl tri thl dn 2 chu kl lenh), lenh GOTO $+2 ma't hai chu kl lenh. Lenh nay co tac dung cong vao bQ de'm chirong trlnh gia tri 2, khi do chirong trinh se nhay tdi l~nh co dia chi (PC+2), nrc la l~nh GOTO delay_O, l~nh nay ciing to'n hai chu kl lenh. Nhir v~y ta dn t6ng cQng 5 chu ki lenh d€ giam gia tri trong thanh ghi counta 1 don vi. Thanh ghi counta mang gia tri 199 (C7h), do do doan chuong trinh nay se tao ra mot khoang thoi gian delay: 1d= 5(counta+1)*ti

= 5(199+1)*1

uS

= 1 mS

Mudn tao ra thoi gian delay 100 mS, ta chi viec dua gia tri 100 vao thanh ghi count 1.

Vdi giai thuat nay thoi gian delay tao ra se dai hen so vdi giai thuat rna ta sli' dung d chirong trlnh 4.2. Ben canh do ta co th€ vie't mot chuong trinh con co tac dung delay mot khoang thoi gian ba't ki la bQi so' cua 1 mS mot each d€ dang. Trong chucng trinh tren ta con sli' dung them mot lenh kha la la l~nh RETL W. Lenh na y co tac dung trd v€ vi tri rna chirong trlnh con diroc goi va thanh ghi W khi do mang gia tri la tham so' ciia lenh RETLW (OOh). Trong tnrong hop nay thanh ghi W khong dn mang mot gia tri cu th€ khi quay trd v€ chtrong trmh chinh nen l~nh RETL W chi co tac dung nhir l~nh RETURN. 4.1.2 MOT SO UNG DllNG VE DA.C TINH 1/0 CVA

cAc

PORT DIEU KHIEN

D1/a vao chuong trinh delay va thao tac dua dfi' I i~u ra cac PORT, ta phat tri€n them mdt so' chircng trlnh nho vdi muc dich lam quen vdi each vie't chirong trlnh cho vi di€u khien PIC 16F877A.

(jng dung 4.1:

D1/a vao mach nguyen Ii hlnh 4.1 vie't chuong trinh dieu khi€n LED chay. Cu th€ la sau thoi gian delay 250 ms, LED tie'p thea se sang mot each tudn t1/ til tren xuong dudi.

Chtrong trlnh nay diroc viet dua vao chuong trlnh 4.3 vdi mdt vai thay d6i nho. Thay vi dira rnQt gia tri ba't kl ra PORT, ta dira ra PORB gia tri 80h, sau d6 dich phai gia tri 80h sau rnlii khoang thoi gian delay (dung lenh RRF). ; Chuong trinh 4.1.4 ; Chuong trinh di~u khien LED chay processor l6f877a ; khai bao vi di~u khiSn include <p16f877a.inc> ; header file dinh kern CONFIG CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ; khai bao cac "Configuration bits" ;Khai bao bien countl counta countb ORG GOTO start BCF BCF CLRF BSF MOVLW MOVWF BCF MOVLW MOVWF CALL RRF GOTO STATUS,RPI STATUS,RPO PORTB STATUS,RPO OxOO TRISB STATUS,RPO Ox8F PORTB delay 1OOrns PORTB,1 loop EQU EQU EQU Ox20 Ox2l Ox22 OxOOO start ; dung cho chtrong trmh delay ; dung cho chtrong trmh delay ; dung cho chuong trinh delay ; dia chi b~ t d~u chuong trinh ; chuong trlnh chinh b~t d~u tai day ; chQnBANKO ; x6a PORTB ; chQnBANKl ; PORTB <- outputs ; chQnBANKO ; gia tri ba't kl cffn dira ra PORTB ; PORTB <- 8Fh ; goi chuong trmh con delaylOOrns ; dich phai PORTB ; vong lap vo han

loop

delaylOOrns MOVLW MOVWF dl MOVLW MOVWF MOVLW

d'lOO' countl OxC7 counta OxOl

MOVWF delay_O DECFSZ GOTO DECFSZ GOTO DECFSZ GOTO RETLW END

countb counta,l $+2 countb,l delay_O countl,l dl OxOO

; delay lOOms ; trd ve chuong trtnh chinh ; ket thuc chirong trlnh

Nhu v~y dua tren mot sa chuong trinh cd ban, ta chi dn thay d6i met sa chi tiet la co th€ tao ra mot ling dung mdi. MQt phirong phap khac d€ viet chuong trlnh tren la dung bang dii' lieu. Phuong phap bang dii' lieu diroc dira ra d day khong mang tinh chat tai u'u hoa giai thuat chtrong trlnh rna chi mang tinh ch(t lam quen vdi mQt giai thuat mdi, qua do tao dieu kien thuan loi hon trong viec viet cac chtrong trlnh ling dung plnrc tap hen sau nay. Ta co th€ viet lai chirong trlnh tren theo phuong pha p bang dii' lieu nhu sau: ; Chuong trinh 4.1.5 ; Chuong trinh dieu khien LED chay dung bang dir lieu processor l6f877a ; khai bao vi dieu khi€n include <p16f877a.inc> ; header file dinh kern CONFIG CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ; khai bao cac "Configuration bits" countl EQU Ox20 dung cho chtrong trmh delay counta EQU Ox2l dung cho chuong trmh delay countb EQU Ox22 dung cho chtrong trmh delay count EQU Ox23 dung d€ tra bang dii' lieu ORG GOTO start BCF BCF CLRF BSF MOVLW MOVWF STATUS,RPI STATUS,RPO PORTB STATUS,RPO OxOO TRISB OxOOO start ; dia chi b~t dffu chirong trlnh ; chuong trinh chinh b~t dffu tai day ; chQnBANKO ; xoa PORTB ; chQnBANKl ; PORTB <- outputs

BCF Loopl CLRF Loop2 MOVF CALL MOVWF CALL INCF XORLW BTFSC GOTO INCF GOTO Table ADDWF RETLW RETLW RETLW RETLW RETLW RETLW RETLW RETLW delaylOOms MOVLW MOVWF dl MOVLW MOVWF MOVLW MOVWF delay_O DECFSZ GOTO DECFSZ GOTO DECFSZ GOTO

STATUS,RPO count count, 0 Table PORTB delaylOOms count, 0 d'8' STATUS,Z Loopl count, I Loop2

; chQnBANKO ; reset thanh ghi chua gitl tri de'm ; dira gia tri de'm vao thanh ghi W ; goi chuong trmh con Table ; xua't gia tri chua trong thanh ghi W ra POR TB ; goi chuong trinh con delaylOOms ; tang gia tri than ghi count va chua ke't qua trong ; thanh ghi W ; so sanh thanh ghi W vdi gia tri 8 ; kiern tra bit Z (Zero) ; nhay v€ label Loopl ne'u W = 0 ; thirc thi lenh nay ne'u W khac 0

PCL,1 b' 10000000' b'OIOOOOOO' b'OOIOOOOO' b'OOOIOOOO' b'OOOOIOOO' b' 00000 100' b'OOOOOOIO' b' 0000000 I' d'IOO' countl OxC? counta OxOI countb counta,l $+2 countb,l delay_O countl,1 dl

; cong gi tri thanh ghi W vao thanh ghi PCL, ke't ; qua chua trong thanh ghi PCL

; delay lOOms

RETURN END

; trd v€ chtrong trmh chinh ; ket thuc chirong trlnh

d phdn tnrdc ta dff tung d€ c~p den l~nh RETLW nhung khi d6 l~nh nay chi c6 tac dung nhu l~nh RETURN. Tuy nhien trong tnrcng hop nay l~nh RETLW c6 mot vai tro cu th€ hon la mang dii' lieu tu bang dii' lieu trd v€ chuong trlnh chinh va xua't ra PORTB dii' lieu vira mang v€ d6. Sau m6i lffn mang dii' lieu v€ bien count se tang gia tri dem len. Gia tri dem du'<;lC vao thanh ghi W d€ cong vao thanh ghi PCL. Thanh ghi PCL la thanh ghi chua gid dira tri b(l dem chuong trlnh, gid tri tu bien count ducc cong vao thanh ghi PCL thong qua thanh ghi W se di€u khien chtrong trlnh nhay tdi dung dia chi cffn la'y dii' lieu tu bang dii' lieu vao thanh ghi W va thanh ghi W mang dii' lieu d6 trd v€ chuong trinh chinh trong qua l~nh RETLW.
D€ d€ phong tnrong hop gia tri bien count cong vao thanh ghi PCL se di€u khi€n chirong trmh den vi tri virct qua vi tri cua bang dii' lieu (tnrong hop nay xay ra khi bien count mang gia tri ldn hon 8, khi d6 vi tri l~nh cffn thuc thi do b(l dem chtrong trlnh chi den khong con dung mra), ta so sanh bien count vdi gia tri 8. Neu bien count mang gia tri 8 thl phep toan XOR giira bien cao va gid tri se c6 ket qua bang 0 va cCfZ trong thanh ghi STATUS se diroc set. Liic nay ta cffn reset lai bien count bang each nhay v€ label Loopl. Viec dung bang dii' lieu trong tnrong hop nay lam cho chuong trmh trd nen dai hon, qua trinh thuc thi chtrong trmh lau hen VI b(l dem chirong trlnh lien tuc bi thay d6i gia tri, tuy nhien ta cling tha'y ducc mot uu di€m cua viec dung bang dii' lieu la cho phep ta s~p xep b6 tri dii' lieu mot each linh heat. Di€u nay th€ hien qua viec chi cffn thay d6i dii' lieu trong bang dii' lieu, ta se c6 diroc nhieu each di€u khien cac LED sang hay t~t theo nhieu qui lu~t khac nhau chii khong chi don thudn la dich LED sang sang trai hoac sang phai. U'ng dung sau day cho ta tha'y ro hen hieu qua cua bang dii' lieu.

Un: dun:4 2: Tuong tu nhu irng dung 1, nhirng lffn nay ta cho LED chay tu vi tri gitta
sang hai phia sau m6i khoang thoi gian delay 100 ms. Chtrong trlnh cho tmg dung nay hoan toan nrong ttf nhir trong tmg dung, ta chi cffn thay d6i bang dii' lieu mot each thich hop. ; Chuong trinh 4.1.6 ; Chuong trinh di€u khi€n hi€n thi LED processor 16f877a ; khai bao vi di€u khien include <p16f877a.inc> ; header file dinh kern CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _CONFIG _WRT_OFF & _LVP _OFF & _CPD_OFF

; khai bao cac "Configuration bits" ;Khai bao bien countl counta countb count ORG GOTO start BCF BCF CLRF BSF MOVLW MOVWF BCF Loopl CLRF Loop2 MOVF CALL MOVWF CALL INCF XORLW BTFSC GOTO INCF GOTO Table ADDWF RETLW RETLW RETLW PCL,l b'OOOllOOO' b'OOlOOlOO' b'OlOOOOlO' ; cong gi tri thanh ghi W vao thanh ghi PCL, ke't ; qua chua trong thanh ghi PCL count, 0 Table PORTB delaylOOms count, 0 d'8' STATUS,Z Loopl count, 1 Loop2 ; dira gia tri de'm vao thanh ghi W ; goi chuong trmh con Table ; xua't gia tri chua trong thanh ghi W ra POR TB ; goi chuong trinh con delaylOOms ; tang gia tri than ghi count va chua ke't qua trong ; thanh ghi W ; so sanh thanh ghi W vdi gia tri 8 ; ki~m tra bit Z (Zero) ; nhay v€ label Loopl ne'u W = 0 ; thirc thi lenh nay ne'u W khac 0 count ; reset thanh ghi chua gia tri de'm STATUS,RPl STATUS,RPO PORTB STATUS,RPO OxOO TRISB STATUS,RPO EQU EQU EQU EQU Ox20 Ox2l Ox22 Ox23 OxOOO start ; ; ; ; dung dung dung dung cho chtrong cho chuong cho chtrong d~ tra bang trmh delay trmh delay trmh delay dii' lieu

; dia chi b~t dffu chirong trlnh ; chuong trinh chinh b~t dffu tai day ; chQnBANKO ; x6a PORTB ; chQnBANKl ; PORTB <- outputs ; chQnBANKO

RETLW RETLW RETLW RETLW RETLW delaylOOms MOVLW MOVWF dl MOVLW MOVWF MOVLW MOVWF delay_O DECFSZ GOTO DECFSZ GOTO DECFSZ GOTO RETURN END

b' 10000001' b'OlOOOOlO' b'OOlOOlOO' b'OOOllOOO' b'OOlOOlOO'

d'lOO' countl OxC? counta OxOl countb counta,l

$+2
countb,l delay_O countl,l dl

; delay lOOms ; trd ve chuong trtnh chinh ; ke't thiic chuong trinh

(jng dung 4.3: Test clnrc nang Input/Output cua cac pin cua vi dieu khi~n.
cac ling dung tnrdc ta chi lam mQt viec la xua't tin hieu dieu khicn ra cac PORT thea met s6 qui t~c dinh san nao d6. Trong ling dung nay ta se phat tri~n them mot chirc nang nii'a cua cac PORT la kha nang nhan tin hieu dieu khien til ben ngoai, Vi dieu khien se doc tin hieu 0 (dien ap 0 V) va 1 (dien ap 5 V) diroc tao ra bang each sa dung cac cong t~c a'n til cac pin RBO:RB3 ciia PORTB , sau d6 ki~m tra xem cong t~c nao diroc a'n va b~t LED tirong ling vdi cong t~c d6 (cac LED nay diroc b6 tri d cac pin RB?:RB4) sang len. f)~ ki~m tra du'<;lc ling dung nay ta cffn xay dung so d6 mach nhir sau:

R8 R7 R9 U1 RB7/PGD RB6/PGC RAO/ANO RBS RA1/AN1 RB4 RA2/AN2IVREF-/CVREFRB3/PGM RAS/AN4/SS/C20UT REO/8.QLANS RE1/llllB/AN6 RE2/CS/AN7 11 12 13 14 VDD GND OSC1/ClK OSC2/ClKOUT ~40~ __ 1--7.39~ __ 1--*'38;..__ ~37<---__ ~36~ __

R6

RS

-+_1---+--+ __ -+_I---+--+_---,

--"/"v""_

R1

D1

J'J' +'-'-__ J'J' J'J'

----,

-+_t-+--+---, -+_t-+--+-,

=~~~~Jcr:=i~UT I-*-~~:-----+----' =~~

RBO/INT 1-3~3~ __ VDD GND RD7/PSP7 RD6/PSP6 RDS/PSPS RD4/PSP4 32 31 ....

-+-+_+- ....

-=-0

D4

J'J'

-=-0

~ ~ ~ ~
SW4 SW3 SW2

SW1

o--------____.

RCO/T1OSO/T1 ClK RC7/RX/DT RC11T10SI/CCP2 RC6ITX/CK RC2/CCP1 RCS/SDO RC3/SCKlSCl RC4/SDI/SDA RDO/PSPO RD1/PSP1 RD3/PSP3 RD2/PSP2

0------------__.
-=-0

PIC16F877A

Hinh 4.2 Mach test chiic nang 110 cho tmg dung 3. Chuong trtnh vie't cho irng dung nay nhu sau: .Chuong trlnh 4.1.7 processor l6f877a include <pl6f877a.inc> _CONFIG _CP _OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ;Khai bao hang SWl SW2 SW3 SW4 LEDl LED2 EQU EQU EQU EQU EQU EQU 0 1 2 3 4

LED3 LED4 ORG GOTO start

EQU EQU

7 OxOOO start

STATUS,RPl BCF BCF STATUS,RPO CLRF PORTB BSF STATUS,RPO MOVLW b'OOOOl1l1 ' MOVWF BCF loop BTFSS CALL BTFSS CALL BTFSS CALL BTFSS CALL GOTO switchl CLRF BSF RETURN switch2 CLRF BSF RETURN switch3 CLRF BSF RETURN switch4 CLRF PORTB PORTB PORTB,LED3 PORTB PORTB,LED2 PORTB PORTB,LEDl PORTB,SWl switchl PORTB,SW2 switch2 PORTB,SW3 switch3 PORTB,SW4 switch4 loop TRISB STATUS,RPO

; thi€t l~p chtrc nang 1/0 cho tung pin trong ;PORTB

; ki€m tra cong t~c 1 ; thirc thi l~nh nay n€u cong t~c 1 diroc tn ; n€u cong t~c ; 1 khong diroc tn, kiern tra cong ; t~c 2 ; ti€p tuc qua trinh do'i vdi cac cong t~c con lai

BSF RETURN END

PORTB,LED4

Trong chirong trmh tren ta tmg dung thuat toan hoi vong thong qua vong lap loop trong phdn chuong trlnh chinh, Khi cong t~c khong ducc nhan, mire logic tai cac pin n6i vdi cong t~c la rmrc 1. Khi cong t~c diroc a'n, cac pin tren sem nhu n6i da't va mang mire logic O. Ta chi viec ki€m tra lien tuc trang thai logic cua cac pin do va b~t LED tirong tmg vdi cong t~c thong qua cac chuong trlnh con switchl, switch2, switch3 va swtich4 khi phat hien mot cong t~c nao do diroc a'n. Tuy nhien cffn chii y la phai thie't l~p trang thai 110 thich hop cho tung pin trong PORTB (thiet l~p RB3:RBO la input, RB7:RB4Ia output). MQt di€m quan trong cffn hill y la cac cong t~c a'n thirong bi "dQi", nrc la khi a'n xudng hoac tha ra, di~n ap tai cac cong t~c se phdi trai qua mQt giai doan qua dQ, di~n ap se dao dQng khong 6n dinh trong mot khoang thoi gian nao do, ngoai ra trang thai logic ciia pin ciing se thay d6i do mot tac dQng nrc thoi tu mQt tnrcng ben ngoai rna khong phai do ta a'n cong t~c. Cac ye'u to' tren se lam anh hirdng tdi hoat dQng cua vi di€u khien, D€ khac phuc nhtroc di€m tren ta co hai phuong phap: Phuong phap chong "dQi" bang phdn cung: ta them cac tu dien vao cac cong t~c d€ IQc bdt cac tin hieu nho gay nhieu va cac tin hieu khong 6n dinh trong thoi gian qua dQ. Phuong phap nay ciing hieu qua nhirng gay t6n kern v€ linh kien va mach nguyen li trd nen phuc tap, Phuong phap chong "dQi" bang phdn mem: ta cho vi di€u khicn delay trong mot thoi gian ngan va ki€m tra xem cong t~c con diroc a'n khong, ne'u cong t~c thuc su con dircc a'n thi mdi tie'n hanh cac thao tac nrong irng vdi cong t~c do. Chuong trmh cai tie'n d€ khac phuc nhuoc di€m tren co th€ du<;fcvie't nhu sau: .Clnrong trinh 4.1.8 processor 16f877a include <p16f877a.inc> _CONFIG _CP _OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP_OFF & _CPD_OFF ;Khai bao hang SWI SW2 SW3 SW4 EQU EQU EQU EQU

o
1 2 3

LEDl LED2 LED3 LED4

EQU EQU EQU EQU

5
6

;Khai bao bien countl counta countb EQU EQU EQU Ox20 Ox2l Ox22

.Cac khai bao khac SWdel .Clnrong trinh ORG GOTO start BCF BCF CLRF BSF MOVLW MOVWF BCF loop BTFSS CALL BTFSS CALL BTFSS CALL BTFSS CALL GOTO switchl PORTB,SWl switchl PORTB,SW2 switch2 PORTB,SW3 switch3 PORTB,SW4 switch4 loop STATUS,RPl STATUS,RPO PORTB STATUS,RPO b'OOOOl1l1 ' TRISB STATUS,RPO OxOOO start ; vi tri b~ t dff u chuong trmh chinh ; chQnBANKO ; chQnBANKl SET de1150 ; gan SWdel vdi label de1150

; chQnBANKO ; vong lap ki€m tra cong tac nao diroc (n ; ki€m tra SWl ; nhay tdi chuong trlnh con switchl ne'u ; SWl diroc (n ; ne'u SWl khong du'<jc(n tiep tuc ki€m tra ;SW2 ; thao tac nrong nhir SW 1

tv

CLRF CALL BTFSC RETURN ledl _ ON BSF BTFSC RETURN GOTO switch2 CLRF CALL BTFSC RETURN led2_ON BSF BTFSC RETURN GOTO switch3 CLRF CALL BTFSC RETURN led3_ON BSF BTFSC RETURN GOTO switch4 CLRF CALL BTFSC RETURN led4_ON BSF

PORTB SWdel PORTB,SWl

; xca PORTB ; goi chtrong trlnh delay de1150 ; kiSm tra cong t~c 1 con nhan hay khong ; ne'u khong con nhan thl trd chuong ; trlnh chinh

ve

PORTB,LEDl PORTB,SWl

ledl_ON

; b~t LEDl sang ; xac nhan lai trang thai cong t~c 1 ; trd chuong trinh chinh neu cong t~c ; khong con a'n ; tiep tuc gifi' LEDl sang ne'u cong t~c con ; diroc a'n ; thao tac nrong tu vdi cac cong t~c con lai

ve

PORTB SWdel PORTB,SW2

PORTB,LED2 PORTB,SW2 led2_ON

PORTB SWdel PORTB,SW3

PORTB,LED3 PORTB,SW3 led3_ON

PORTB SWdel PORTB,SW4

PORTB,LED4

BTFSC RETURN GOTO

PORTB,SW4 led4_ON

.Clnrong trinh delay cai tien cho phep nhieu khoang thoi gian delay khac nhau delO RETURN dell MOVLW GOTO del5 MOVLW GOTO dell 0 MOVLW GOTO del20 MOVLW GOTO del50 MOVLW GOTO dell 00 MOVLW GOTO dell 50 MOVLW GOTO del200 MOVLW GOTO delay MOVWF dl MOVLW MOVWF MOVLW MOVWF delay_O DECFSZ OxC7 counta OxOI countb counta,l countl ; t9-0 thoi gian delay I mS d'200' delay d'150' delay d'IOO' delay d'50' delay d'20' delay d'IO' delay d'5' delay d'l' delay

GOTO$+2 DECFSZ GOTO DECFSZ GOTO RETURN END

countb,l delay_O countl,1 dl

Vdi chuong trinh tren, thoi gian a'n cong t~c phai lau hen thci gian delay diroc chi dinh bdi h~ng s6 SWdel do cong t~c se diroc ki€m tra lai trang thai sau thoi gian delay. Neu thoi gian a'n cong t~c khong dat yeu du, thao tac b~t LED tirong ling vdi cong t~c d6 sang len se khong du'<;fC thuc hien va vi dieu khien se titp tuc qua trlnh kiern tra trang thai cac cong t~c con lai. Thci gian delay dn dircc ki€m dinh bang thuc nghiern va du'<;fc dinh mot each thich a'n hop d€ chdng "doi" met each hieu qua, dang thoi cting khong diroc lau qua, nhu v~y se gay su kh6 chiu trong viec sti' dung cong t~c do phai a'n cong t~c trong m(lt khoang thoi gian dii lau. Viec thay d6i thoi gian delay trong chuong trinh c6 th€ dircc thirc hien don gian bang each thay d6i label cua chirong trlnh delay gan cho tham s6 SW del. Thuc ra ta c6 th€ tnrc titp dua tham s6 thoi gian delay true titp vao thanh ghi countl rna khong dn thong qua tham s6 SWdel, dieu d6 lam cho chirong trinh tri'1 nen dai va phirc tap hen, Tuy nhien chuong trmh tren cfing dff cho ta tha'y dircc mot di€m khac biet gifta lenh "EQU" va lenh "SET", giiip ta hi€u ro hen va sti' dung mot each thich hop cac lenh tren trong cac ling dung khac .
ung dung 4.4: ling dung tong hop.
.,., ,:?

Trong ling dung nay ta se t~p hop lai ta't cac ki nang diroc sti' dung trong cac ling dung tnrdc. Yeu du d~t ra ciing nhu irng dung 3, tuy nhien ben canh viec b~t LED tucng ling vdi cong t~c sang len, ta phai titp tuc thuc hien mot thao tac ntta la ra lenh cho vi dieu khien hi€n thi 8 LED diroc g~n vao PORTD theo mot thti tlf nrong ling. C1:lth€ nhir sau: An An An An SWl: SW2: SW3: SW4: LEDl LED2 LED3 LED4 sang, sang, sang, sang, 8 LED 8 LED 8 LED 8 LED PORTD PORTD PORTD PORTD chay chay chay chay til til til til trai trai trai trai sang sang sang sang phai phai phai phai (LED sang chay). (LED t~t chay). (2 LED sang chay), (2 LED t~t chay),

ca

D€ test diroc ling dung nay, ta dn phat tri€n them mach test cua ling dung 3 bang each them vao 8 LED i'1 PORTD thong qua cac dien trd, C1:lth€ nhu sau:

R9 U1 1

-MClRNPP

SW~

1
-=-0
11 12 13 14

RB7/PGD RBS/PGC RAO/ANO RB5 RA1/AN1 RB4 RA2/AN2IVREF-/CVREFRB3/PGM RA3/AN3/vREF+ RB2 RB1 RA4fTOCbM:10UT RA5/AN4/SS/C20UT RBO/INT REO/RD/AN5 RE1IWR/ANS RE2/CS/AN7

40 39 38 37 3S 35 34 33 32 31 SW2 c:::::C!:::= SW3 c:::::C!:::=

JIJI JIJI JIJI JIJI

SW1 c:::::C!:::=
IH

VDD GND RD7/PSP7 RDS/PSPS RD5/PSP5 RD4/PSP4

VDD GND OSC1/ClK OSC2/ClKOUT

-=-0
4MHzD

30 29 28 27

-=-0

JIJI JIJI JIJI

RCOfT1OSOfT1 ClK RC7/RXIDT RC1fT10SI/CCP2 RCSfTX/CK RC2/CCP1 RC5/SDO RC3/SCK/SCl RC4/SDI/SDA RDO/PSPO RD1/PSP1 RD3/PSP3 RD2/PSP2 22 21

JIJI JIJI JIJI JIJI JIJI -=-0

PIC1SF877A

Hlnh 4.3 Mach test ling dung 4. Chuong trmh vie't cho mach test nay cung nrong t\1'nhu irng dung 3 nhung diroc them vao phdn hien thi LED d PORTD. Ta sli' dung thuat toan bang dii' lieu d~ hi~n thi LED. Chuong trinh cu th~ nhir sau: .Chuong trlnh 4.1.9 processor 16f877a include <p16f877a.inc> _CONFIG _CP _OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP _OFF & _CPD_OFF ;Khai bao cac hang sa SW1 SW2 SW3 EQU EQU EQU

o
1 2

SW4 LEDl LED2 LED3 LED4

EQU EQU EQU EQU EQU

3
4

5
6

;Khai bao bien count count! counta countb .Clnrong trinh ORG GOTO start BCF BCF CLRF CLRF BSF MOVLW MOVWF MOVLW MOVWF BCF loopl CLRF CALL loop2 MOVF BTFSC CALL BTFSC CALL BTFSC CALL count,W PORTB,LEDl tablel PORTB,LED2 table2 PORTB,LED3 table3 ; dira gia tri bien count vao thanh ghi W ; ki€m tra trang thai bit LEDl ; goi chuong trinh con "table 1" ne'u bit ; "LED 1" mang gia tri bang 1 ; tie'p tuc ki€m tra bit LED2 ne'u bit LEDl bang 0 ; thao tac nrong t\1'vdi cac bit chi thi trang thai cac ; SW con lai count check_key ; reset bien count ; goi chirong trlnh con check_key STATUS,RPl STATUS,RPO PORTB PORTD STATUS,RPO b'OOOOl1l1 ' TRISB OxOO TRISD STATUS,RPO OxOOO start ; vi tri b~ t d~u chuong trmh chinh ; chQnBANKO EQU EQU EQU EQU Ox20 Ox2l Ox22 Ox23 ; bien dung cho qua trmh dich LED ; cac bien dung cho chtrong trlnh delay

; chQnBANKl

; chQnBANKO