DatapathAndControl (20%)

Chng 5: B x l: ng truyn d liu v iu khin
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Translater: huahongquan2007
5.1: Li gii thiu 5.2: Quy c thit k logic 5.3: Xy dng mt ng truyn d liu (datapath) 5.4: S h thng x l n gin 5.5: H thng x l nhiu vng 5.6: Cc trng hp ngoi l 5.7: Lp trnh vi x l: Thit k iu khin n gin ho 5.8: Gii thiu thit k k thut s s dng ngn ng thit k phn cng 5.9: Vn thc t: Cu to ca h thng x l Pentium 5.10: Cc vn sai lm v cm by 5.11: Kt lun 5.12: Quan im lch s v m rng 5.13: Bi tp
Nm thnh phn cu to c bn ca mt my tnh
5.1
Li gii thiu
Trong chng 4, chng ta bit c hiu sut ca mt c my th c xc nh bng 3 yu t quyt nh: s lng tp lnh (instruction count), thi gian mt clock cycle(clock cycle time) v s clock cycle mi tp lnh (CPI). Trnh bin dch v kin trc tp lnh (ISA) quyt nh s lng tp lnh (instruction count) cn thit cho chng trnh. Tuy nhin, c hai thi gian mt clock cycle(clock cycle time) v s clock cycle mi tp lnh (CPI) th c quyt nh bi h thng x l ca b x l. Trong chng ny, chng ta xy dng ng truyn d liu(datapath) v b phn iu khin (control unit) cho hai h thng x l khc nhau ca mt b tp lnh MIPS (MIPS instruction set). Chng ny gii thch cc nguyn l v k thut c dng trong vic thi hnh trong mt b x l, bt u vi mt s miu t chung kh tru tng trong mc ny v theo sau bi mc xy dng ng truyn d liu v mt phin bn n gin ca b x l v cui cng pht trin mt khi nim cn thit to ra nhng b tp lnh (instructions set) phc tp, nh IA-32. Dnh cho cc c gi a thch vic tm hiu sau v tp lnh (instruction) v nhng tc ng ca n ti hiu sut ca my tnh, mc ny s cung cp kin thc hiu cc khi nim cng nh nhng khi nim c bn ca x l lin lnh (pipelining) c gii thch trong mc 6.1 chng sau. i vi cc c gi ham mun hiu phn cng thi hnh cch lnh nh th no th mc 5.3 v 5.4 c tt c ti liu cn thit. Hn na, hai mc ny l hiu tt c t liu chng 6. Ch cc c gi a thch thit k phn cng nn i xa nh vy. Cc mc cn li ca chng ny bao qut v cch cc phn cng hin i thi hnh cc lnh. Nguyn l c bn ca iu khin trng thi hu hn c gii thch, cc cch thc khc nhau ca h thng x l, bao gm lp trnh vi x l, c nu ra. i vi cc c gi a thch hiu su hn v b x l v hiu sut ca n, mc 5.4 v 5.5 th hu ch. Mc 5.7 s ni v lp trnh vi x l. Mc 5.8 gii thch lm th no ngn ng thit k phn cng v cc cng c CAD c dng thc thi phn cng.
H thng x l MIPS c bn:

Chng ta ang xem xt mt h thng x l m bao gm tp hp cc b tp lnh trung tm ca MIPS: Cc tp lnh truy xut b nh load word (lw) and store word (sw) Cc tp lnh ton hc- logic add, sub, and, or, v slt Cc tp lnh r nhnh: beq v jump. Cc tp hp ny cha bao gm tt c cc tp lnh vi bin nguyn (shift, nhn, chia th cha c), cng nh cha c cc tp lnh vi du chm ng. Tuy nhin, tt c cc nguyn l c dng trong vic xy dng cc ng truyn d liu(datapath) v thit k iu khin s c lm sng t. H thng x l ca cc tp lnh cn li th cng tng t. Trong khi xem xt h thng x l, chng ta s c c hi xem lm sao cc kin trc tp lnh (ISA) quyt nh nhiu kha cnh ca h thng x l, v cch la chn cc chin lc thc thi khc nhau nh hng ti clock cycle v CPI ca my. Nhiu nguyn l thit k quan trng c gii thiu trong chng 4 c th c lm sng t bng cch xem h thng x l, nh nguyn l Make the common case fast v Simplicity favors regularity. Thm vo , nhng nguyn l c dng thc thi cc lnh MIPS trong chng ny v chng ti c cng quan im v ra hnh nh rng v my tnh, t cc server hiu sut cao ti cc b vi x l thng thng.
Miu t chung v h thng x l

Trong chng 2 v 3, chng ta nhn vo cc tp lnh tng tm ca MIPS, bao gm cc tp lnh ton hc-logic vi bin nguyn, cc tp lnh truy xut b nh v cc tp lnh r nhnh. Nhiu iu cn thit thc thi cc tp lnh ny th ging nhau, khng ph thuc vo chnh xc lp ca tp lnh. i vi nhiu tp lnh, hai bc sau th vn ging nhau: 1/ Gi b m chng trnh (program counter) ti b nho m cha m ngun v ly tp lnh t b nh 2/ c mt hoc hai register, dng cc trng ca tp lnh la chn register cn c. i vi tp lnh load word, chng ta ch cn c mt register, nhng hu ht cc tp lnh khc th cn c hai register. Sau hai bc ny, cc hot ng cn hon thnh tp lnh phuc thuc vo lp tp lnh. May mn l, i vi mi lp ca ba lp tp lnh (truy xut b nh, s hc logic v r nhnh), cc hot ng phn ln l ging nhau, khng ph thuc vo chnh xc loi opcode. Ngay c cc lp tp lnh khc nhau cng c im ging nhau. V d, tt c cc lp tp lnh, ngoi tr jump, dng mt n v tnh ton s hc-logic (ALU) sau khi c cc register. Tp lnh truy xut b nh dng ALU cho vic tnh ton cc a ch, cc tp lnh tnh ton s hc- logic cho vic tnh ton v r nhnh cho vic so snh. Nh chng ta c th thy, tnh n gin v thng dng ca cc b tp lnh n gin ha cc thc thi bng cch khi ng nhiu lp tp lnh tng t. Sau khi dng ALU, cc hot ng hon thnh cc tp lnh th khc nhau. Cc tp lnh truy xut b nh s cn truy cp vo b nh hoc ghi d liu hoc lu d liu. Tp lnh tnh ton s hc- logic phi ghi d liu t ALU vo mt register. Cui cng, tp lnh r nhnh, chng ta cn phi thay i a ch ca tp lnh da trn php so snh mc d PC s tng ln 4 ly a ch ca tp lnh tip theo. Hnh 5.1 th hin quan im cp cao ca mt h thng x l MIPS, tp trung vo nhiu n v chc nng khc nhau v quan h ni lin gia chng. Mc du hnh ny th hin hu ht cc ng d liu qua b x l, chng vn b i hai kha cnh quan trng ca thc thi tp lnh.
u tin, hnh 5.1 cho thy d liu i n mt n v c th qua hai ngun khc nhau. V d, gi tr c ghi trong PC c th n t mt trong hai b cng v d liu c ghi vo d liu register m c th n t ALU hoc l b nh. Trong thc t, nhng ng d liu khng th ch n gin c ni dy vi nhau; chng phi c thm vo mt thnh phn chn t nhiu ngun v li mt trong cc ngun ti ch. S la chn ny thng hon thnh bi mt thit b gi l b dn knh (multiplexor), thit b ny thng c gi l b chn d liu (data selector). B dn knh ni k hn trong Ph lc B - chn t nhiu ngun khc nhau da trn s b tr ca cc ng iu khin. Cc ng iu khin th c t da trn thng tin c t tp lnh c thc thi. Th hai, nhiu n v phi c iu khin da trn loi tp lnh. V d, b nh phi c c khi load v ghi khi store. Cc register phi c ghi load v cc ALU. Tt nhin, ALU phi thc hin mt trong nhiu lnh, nh trong chng 3. Ging nh trong cc muxes (multiplexor), nhng lnh ca ALU c iu khin bi mt ng iu khin m c thit t da trn cc trng trong mt tp lnh.
Hnh 5.2 th hin cc ng truyn d liu ca Hnh 5.1 vi ba b dn knh (multiplexor) cn thit, cng nh cc ng iu khin cho cc b phn chc nng chnh. Mt b iu khin m c cc tp lnh nh mt u vo th c dng xc nh lm th no b tr cc ng iu khin cho cc n v chc nng v hai b dn knh (multiplexor). B dn knh th ba ci m quyt nh liu PC + 4 hay a ch lnh r nhnh c ghi vo PC th c b tr da trn gi tr ra 0 ca ALU ci m c dng thc hin lnh so snh cho tp lnh beq. Tnh thng xuyn v n gin ca b tp lnh MIPS ngha l mt qu trnh gii m n gin c th c dng xc nh cch b tr cc ng iu khin. // b qua mt on y //
Cch tip cn ny th khng thc tin, khi n s chm hn mt h thng x l m cho php nhng lp tp lnh khc nhau nhn s lng clock cycle khc nhau, mi ci c th ngn hn. Sau khi thit k b iu khin cho b my n gin ny, chng ta s nhn vo h thng x l m dng nhiu clock cycle cho mt tp lnh. Thit k nhiu vng (multicycle) ny th c dng khi chng ta bn v nhng khi nim iu khin phc tp, gii quyt trng hp ngoi l, v cch dng ngn ng thit k phn cng trong mc 5.5 ti 5.8 Cc ng truyn d liu n vng (single-cycle) c miu t trong mc ny phi c cc tp lnh v b nh ring l v: 1. Cu trc ca d liu v tp lnh th khc nhau trong MIPS do b nh khc nhau th cn thit 2. C cc b nh ring l th tit kim chi ph hn 3. Cc b x l hot ng mt vng v khng th dng mt b nh cho vic truy xut hai ni khc nhau trong cng mt vng.
5.2
Quy c thit k logic
bn v thit k ca mt c my, chng ta phi quyt nh cch cc my thc hin logic s hot ng v cch my tnh thi gian (?). Mc ny xem li mt vi quan im quan trng trong logic s m chng ta s dng rng khp trong chng ny. Nu bn c mt t hoc khng c khi nim v logic s, bn nn c ph lc B trc khi i tip. Cc n v chc nng trong h thng MIPS bao gm hai loi khc nhau ca yu t logic: cc yu t x l trn gi tr d liu v cc yu t cha trng thi. Cc yu t x l gi tr d liu th u mang tnh kt hp(combinational), ngha l u ra ca chng ch ph thuc vo u vo hin ti. a vo cng mt u vo, mt yu t mang tnh kt hp lun cho ra mt u ra nh nhau. ALU th hin trong hnh 5.1 v c tho lun trong chng 3 v ph lc B l mt yu t mang tnh kt hp. Nhng yu t khc trong thit k th khng mang tnh kt hp, nhng thay vo cha trng thi (state). Mt yu t cha trng thi nu n c ch lu tr. Chng ta gi chng l yu t trng thi bi v, nu chng ta tt ngun ca my, chng ta c th phc hi li n bng cch load cc yu t trng thi vi gi tr m chng lu. Hn na, nu chng ta lu v phc hi li yu t trng thi, n s tr li nh l my cha bao gi mt ngun. Do , nhng yu t trng thi hon ton nh r c im ca my. Trong hnh 5.1, ch th v b nh cng nh cc register l cc yu t trng thi. Mt yu t trng thi c t nht hai u vo m mt u ra. u vo l cc gi tr d liu c ghi trong mt yu t v mt clock, ci m quyt nh khi no d liu c ghi. u ra ca mt yu t trng thi cung cp gi tr m chng c ghi trong clock cycle trc . V d, mt yu t trng thi n gin nht l mt mch lt loi D (D-type ip-op) (Xem ph lc B) - c chnh xc hai u vo ( mt gi tr v mt clock) v mt u ra. Ngoi flip-flops, h thng x l MIPS cng dng hai loi yu t trng thi khc: b nh v register. Clock th dng xc nh khi no yu t trng thi c ghi; mt yu t trng thi c th c c bt k lc no. Nhng thnh phn logic m cha trng thi th cng c gi l mang tnh lin tc(sequential), bi v ng ra ca chng ph thuc vo c u vo v ni dung ca trng thi bn trong (internal state). V d, ng ra t mt n v chc nng tng ng(functional unit) l register ph thuc vo c s lng register c cung cp v trn nhng g c ghi trong register. Hot ng ca c yu t mang tnh kt hp (combinational) v yu t mang tnh lin tc( sequential) v cu trc ca chng th c ni r trong ph lc B.
Chng ta s dng t asserted m ch rng mt tn hiu (signals)th ang trng thi cao v assert l ch nh tn hiu (signals)vo trng thi cao v deasserted hay deassert th i din cho trng thi thp.
Clocking Methodology
Mt Clocking Methodology nh r khi no tn hiu (signals)c th c c v khi no chng c th c ghi. N th quan
trng xc nh thi gian c v ghi bi v nu mt tn hiu (signals) c ghi cng thi im c, gi tr ca c c th tng ng vi gi tr c hoc l gi tr va c ghi hoc l s pha trn ca c hai. Tuy nhin, thit k ca my tnh khng th cho php mt s khng on trc c nh vy. Clocking Methodology c thit k ngn chn trng hp ny.
n gin, chng ta gi s mt phng php xung nhp theo gc cnh (edge-triggered clocking methodology ).(?) ## Cha dch chun c An edge-triggered clocking methodology means that any values stored in a sequential logic element are updated only on a clock edge. Because only state elements can store a data value, any collection of combinational logic must have its inputs coming from a set of state elements and its outputs written into a set of state elements. The inputs are values that were written in a previous clock cycle, while the outputs are values that can be used in a following clock cycle. ## Hnh 5.3 cho thy hai yu t trng thi quanh mt khi lun l mang tnh kt hp, ci m hot ng trong n chu k (single clock cycle): tt c tn hiu (signals) phi c truyn i t yu t trng thi 1, qua mt l n v logic t hp , n yu t trng thi 2 trong mt chu k ( clock cycle). Thi gian cn thit cho tn hiu ti yu t trng thi 2 quyt nh chiu di ca mt chu k (clock cycle). cho n gin, chng ti khng th hin mt tn hiu iu khin ghi( write control signal) khi mt yu t trng thi c ghi trong mi gc chu k (clock edge). Ngc li, nu mt yu t trng thi m khng c cp nht trong mi chu k, mt tn hiu iu khin s c xut hin. C hai tn hiu iu khin ghi v tn hiu chu k (clock signal) u l u vo, yu t trng thi th ch thay i khi tn hiu iu khin ghi c asserted v khi mt clock edge xut hin.
phng php xung nhp theo gc cnh (edge-triggered clocking methodology )(?) cho php chng ta c ni dung ca mt register v gi gi tr qua mt n v logic t hp v ghi thnh ghi trong cng mt chu k, nh trong hnh 5.4. Khng c vn g nu chng ta gi s rng vic ghi d liu thc hin trong cnh tng (rising clock cycle) hay cnh gim ( falling clock cycle), v nhng u vo ca n v logic t hp khng th thay i ngoi tr trong cnh c chn (chosen clock cycle). Vi phng php trn, khng h c mt s hi tip no trong mt chu k n nn logic trong hnh 5.4 hon ton ng. ## B qua mt on nh y.
##
5.3
Xy dng mt ng truyn d liu
Mt cch tt nht bt u thit k mt ng truyn d liu l xc nh kin trc ca cc phn t cn thit cho cu lnh MIPS. Hy bt u cch nhn vo cc yu t ca ng truyn d liu (datapath element) m mi tp lnh cn. Khi chng ti a ra cc yu t ca datapath, chng ti cng a ra cc tn hiu iu khin ca chng. Hnh 5.5 th hin yu t u tin m chng ta cn : mt n v b nh lu tr tp lnh ca chng trnh v cung cp cho tp lnh mt a ch. Hnh 5.5 cng a ra mt register gi l program counter (PC), m dng cha a ch ca tp lnh hin ti. Cui cng, chng ta s cn mt b cng tng PC ti a ch ca tp lnh tip theo. B cng ny, mang tnh kt hp, c th xy dng vi ALU bng cch ni cch ng iu khin iu khin lun xc nh mt php ton cng. Chng ta s v ALU nh vy mi tn l ADD, nh trong hnh 5.5 m ch rng n l mt b cng v khng th thc hin php ton khc. chy bt c tp lnh no, chng ta phi bt u bng vic chp tp lnh t b nh. chun b cho vic chy tp lnh tip theo, chng ta phi tng PC ln 4 . Hnh 5.6 ch ra cch 3 yu t t hnh 5.5 c th ni li vi nhau to thnh mt ng truyn d liu m chp tp lnh v tng PC ln 4.
By gi hy xem xt cc b tp lnh kiu R. Chng u c hai register, thc hin php tnh vi ALU i vi d liu trong register v vit ra kt qu. Chng ta gi cc tp lnh ny l tp lnh kiu R hay cc tp lnh tnh ton s hc lun l. B tp lnh ny bao gm add, sub, and, or v slt (chng ta ni r chng 2). Hy th nh li v d in hnh nht ca b lnh ny l add $t1,$t2,$t3 - ci m c $t2 , $t3 v ghi $t1. B x l 32 register th lu cc register vo trong mt cu trc gi l register file. Mt register file l mt tp hp cc register m trogn bt c register no c th c c hay ghi bng vic a ra s tng ng ca register trong file. Trong php cng, chng ta cn mt ALU tnh ton cc gi tr c c t register. Bi v cc tp lnh kiu R c ba ton t register, chng ta s cn c hai d liu word t register file v ghi mt d liu word v register file trong mi tp lnh. mi d liu word c c t register, chng ta cn mt truyn vo register file mt input cha s tng ng ca register cn c v mt output lu gi tr c c. ghi mt d liu word, chng ta s cn hai input: mt ch nh register number v mt cung cp d liu ghi vo register. Register Translater: huahongquan2007 10
file lun lun xut ra (output) d liu ca register ng vi bt k register number no c truyn vo qu trnh c (READ). Nhng i vi vic ghi (WRITE), n c iu khin bi mt tn hiu iu khin ghi, ci m c asserted (bt) cho php ghi. Do , chng ta cn tt c l bn input (3 cho register number v 1 cho d liu) v hai output (u cho d liu), nh trong hnh 5.7. Register number th u rng 5 bits xc nh 32 register (32 = 2 5), cn i vi d liu vo v ra th rng 32 bits. Hnh 5.7 th hin mt ALU, n s nhp vo hai 32-bit input v to ra mt kt qu 32 bit, v cng c mt tn hiu 1-bit nu kt qu l 0. Tn hiu iu khin 4-bit ca ALU th c m t r trong PH LC B(Appendix B). Tip theo hy xem xt ti tp lnh MIPS load word v store word - lw $t1,offset_value($t2) or sw t1,offset_value ($t2) . Nu tp lnh l STORE, d liu lu tr phi c c t register file m n c tr ti trong $t1. Nu tp lnh l LOAD, d liu c c t b nh phi c ghi vo register file register xc nh ($t1). Do chng ta s cn c hai register file v ALU t hnh 5.7.
Trong php cng, chng ta s cn mt n v m rng du (sign-extend) trng offset 16bit trong cu lnh thnh d liu c du 32-bit v mt n v b nh d liu c hoc ghi. B nh d liu phi c ghi trong tp lnh store; do , n c c hai tn hiu c v ghi, mt address input cng nh mt data input. Hnh 5.8 th hin hai n v ny. Tp lnh beq cng c ba ton hng- beq $t1,$t2,offset- hai register cn c so snh vi nhau v mt offset 16-bit tnh ton a ch cn nhy ti (branch target address) lin quan (relative) ti a ch ca tp lnh branch. thi hnh cu lnh ny, chng ta phi tnh ton branch target address bng cch thm trng offset c sign-extend vo PC. Chng ta cn phi ch vo hai chi tit trong nh ngha v tp lnh branch (trong chng 2): ISA
The instruction set architecture species that the base for the branch address calculation is the address of the instruction following the branch. Since we compute
PC + 4 (the address of the next instruction) in the instruction fetch datapath, it is

easy to use this value as the base for computing the branch target address.
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Do , ng truyn r nhnh phi lm hai vic sau: tnh ton a ch n ca r nhnh v so snh ni dung ca register. Bi v s phc tp ca vic x l r nhnh, chng ti s a ra cu trc ca cc phn on ng truyn m x l r nhnh trong hnh 5.9. tnh ton a ch n ca r nhnh, ng truyn r nhnh bao gm mt n v m rng du (sign extension unit) v mt n v cng(adder). thc hin vic so snh, chng ta cn dng register file nh trong hnh 5.7 cung cp hai ton hng(operand) register (mc d chng ta s khng cn phi ghi vo register file). Thm vo , vic so snh c th c thc hin bng vic s dng ALU. V ALU cung cp tn hiu ra (output) m ch rng liu kt qu c bng 0 hay khng, chng ta c th gi hai ton hng(operands) n ALU vi lnh iu khin l tr. Nu tn hiu ZERO ra khi ALU l tn hiu cao (asserted), th chng ta bit rng hai gi tr bng nhau. Chng ti s th hin chnh xc cch kt ni nhng tn hiu iu khin ca ALU c dng trong ng truyn d liu. Tp lnh JUMP hot ng bng cch thay th 28 bits thp ca PC vi 26 bits thp ca tp lnh c shift left 2 bits.(?). Ln shift th c hon thnh n gin bi vic rang buc 00 l jump offset (nh trong chng 2).
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To mt ng truyn d liu n (Creating a Single Datapath)

Cho ti by gi, chng ta xem xt qua cc thnh phn ca ng truyn d liu cn thit cho nhng class tp lnh ring bic, chng ta c th kt hp chng vo mt ng truyn d liu n v thm tn hiu iu khin hot thnh tp lnh. ng truyn d liu n gin nht c th c chy tt c cc tp lnh (instructions) trong mt clock cycle. iu ny ngha l khng c ti nguyn ng truyn( data path resource) c th c s dng nhiu hn mt trong mi tp lnh, do bt c thnh phn no m cn nhiu hn mt s PHI b lp li. Do chng ta cn b nh cho nhng tp lnh tch bit ring vi d liu. Mc d vi trong nhng n v chc nng ( functional units) s cn phi b lp li, hu ht cc thnh phn khc c th chia s gia cc tp lnh vi nhau. chia s mt thnh phn ng truyn d liu gia hai class tp lnh khc nhau, chng ta cn cho php nhiu kt ni ti mt u vo ca mt phn t, bng vic dng cc multiplexor v tn hiu iu khin chn gia cc u vo.
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V d
Xy dng mt ng truyn d liu

Cc bc ca ng truyn d liu v cc tp lnh tnh ton lun l (hay R type) v cc tp lnh b nh th kh n gin. Tuy nhin c mt vi s khc bit sau: Cc tp lnh tnh ton lun l dng ALU vi u vo n t hai register. Cc tp lnh b nh c th dng ALU tnh ton a ch, mc d u vo th hai l mt trng 16 bit offset c m rng du t tp lnh (instruction). Gi tr c lu trong register ch n t ALU (i vi tp lnh kiu R) hoc t b nh ( i vi load).
Hy cho bit cch xy dng mt ng truyn d liu cho ( the operational portion of the memory reference and arithmetic-logical instructions) m dng mt register file n v mt ALU x l c hai loi tp lnh, thm cc multiplexor nu cn thit
Gii
to mt ng truyn d liu vi ch mt register file n v mt ALU, chng ta PHI h tr (support) hai ngun khc nhau (sources) cho u vo th hai ca ALU, cng nh hai loi ngun khc nhau cho d liu c lu trong register file. Do , mt multiplexor th c t u vo ca ALU v mt ci khc c t d liu vo register file. Hnh 5.10 th hin iu ny.
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By gi chng ta c th kt hp tt c phn li vi nhau to thnh mt ng truyn d liu c bn cho MIPS. Hnh 5.11 cho thy ng truyn d liu m chng ta thu thp c bng vic kt hp cc phn ring l. Tp lnh r nhnh dng ALU chnh cho vic so snh cc ton hng register, nn chng ta phi gi mt b cng (adder) trong hnh 5.9 tnh ton a cha r nhnh. Mt multiplexor thm vo chn rng PC+4 hay l a ch r nhnh c ghi ln PC. By gi chng ta hon thnh mt ng truyn d liu c bn, chng ta c th thm vo cc n v iu khin. Cc n v iu khin phi c th nhn u vo (input) v to ra mt tn hiu ghi cho mi thnh phn trng thi (state element), mt b chn iu khin cho mi multiplexor, mt b iu khin ALU. B iu khin ALU th kh khc bit, v n s thng c thit k u tin.
Check yourself
iu no sau y th ng cho mt tp lnh LOAD? a/ MemtoReg nn c set lm cho d liu t b nh c th c truyn ti register file b/ MemtoReg nn c set lm cho ch n ng register(correct register destination) c gi ti register file c/ Khng quan tm v MemtoReg.
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5.4
A Simple Implementation Scheme
Trong mc ny, chng ta s xy dng mt h thng x l n gin s dng ng truyn d liu. H thng n gin ny s bao hm load word(lw), store word (sw), r nhnh bng (beq) v tp lnh tnh ton lun l add, sub, or v set on less than. Chng ta s pht trin thit k vi tp lnh jump sau. The ALU Control Nh chng ta c th xem ph lc B, ALU c bn u vo iu khin. Nhng bits ny th khng c m ha; do , ch c 6 trong s 16 la chn u vo c th c dng trong tp hp con ny (subset). MIPS ALU trong ph lc B c:
Da trn loi class ca tp lnh, ALU s cn phi thc hin mt trogn 5 chc nng. i vi load word v store word, chng ta dng ALU tnh ton a ch b nh bng php cng. i vi tp lnh loi R, ALU cn thc hin mt trong chc nng (AND, OR, sub, add hoc set on less than), ph thuc vo gi tr ca 6 bit chc nng. i vi r nhnh bng, ALU phi thc hin php tr. Chng ta c th to ra c u vo iu khin ALU 4 bit bng vic s dng cc n v iu khin nh ci m nh l trng chc nng ca tp lnh v c 2 bit, ci m chng ta gi l ALUOp. ALUOp m ch rng liu thao tc cn thc th l cng (00) cho load v store, tr (01) cho beq hay cc lnh thuc loi R(10). u ra ca n v iu khin ALU l mt tn hiu 4 bit m n iu khin trc tip ALU bng vic mt trong nhng b 4 bit trn. Trong hnh 5.12, chng ta th hin cch set u vo iu khin ALU da trn 2bit ALUOp iu khin v m chc nng 6 bit. y , mi lin h gia cc bit ALUOp v opcode ca tp lnh cng c th hin.
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/* B 1 on y.
*/ Designing the Main Control Unit Chng ta m t cch m mt ALU dng cc m chc nng v mt tn hiu 2 bit iu khin, chng ta c th quay tr li xem xt phn cn li. bt u, hy th xem cc trng ca mt tp lnh v cc ng iu khin m cn thit cho ng truyn d liu c xy dng trong hnh 5.11. hiu cch lin kt cc trng ca mt instruction vi datapath, ta cn phi xem li cu trc ca 3 class tp lnh: R type, branch v load/ store. Hnh 5.14 th hin cu trc ny. C nhiu iu trong vic quan st cc yu t ca cu trc tp lnh m bn cn da vo: Op field, cn gi l opcode, th lun lun cha cc bit trong vng 31:26. Chng ti s xem trng ny l Op[5:0]. Hai register c th lun lun c ch nh l rs v rt, v tr 25:21 v 20:16. iu ny th ng cho tp lnh loi R, r nhnh bng v store. Register cho tp lnh load v store th lun trong v tr 25:21 (rs). 16-bit offset cho r nhnh bng, load v store th lun c lu v tr 15:0 Register ch th mt trong hai ni. i vi mt load, n lu v tr 20:16 (rt). Trong khi tp lnh loi R th lu v tr 15:11(rd). Do chng ta s cn phi thm mt multiplexor la chn trng no ca tp lnh c dng m ch register ch ghi .
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Dng thng tin ny, chng ta c th thm tiu tp lnh v nhng multiplexor ph vo ng truyn d liu n. Hnh 5.15 th hin y nhng g cn cn thit xy dng mt h thng x l n gin. // rt gn 1 on y. Hnh 5.16 miu t cc chc nng cho 7 ng iu khin.
By gi chng ta bit chc nng ca mi tn hiu iu khin, chng ta c th nhn vo cc chng c set. n v iu khin c th c set ln tt c nhng mt trong nhng tn hiu iu khin th duy nht da vo trng opcode ca tp lnh (?). ng iu khin PCSrc l ngoi l. ng iu khin s c set ln nu tp lnh l r nhnh bng v
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ng ra ZERO ca ALU l true. to c tn hin PCSrc, chng ta s cn phi AND mt tn hiu t n v iu khin v mt tn hiu ra ZERO ca ALU. Chn ng iu khin ny ( 7 t hnh 5.16 v 2 t ALUOp) c th c set ln trn c s ca 6 tn hiu vo n n v iu khin, ci m l nhng bit opcode. Hnh 5.17 cho thy ng truyn d liu vi n v iu khin v tn hiu iu khin. /* B 1 on khng cn thit. */ Hot ng ca ng truyn d liu (Operation of the Datapath) Vi thng tin c cha trong hnh 5.16 v 5.18, chng ta c th thit kt n v iu khin logic, nhng trc khi chng ta lm iu , hy nhn xem lm th no mi tp lnh dng ng truyn d liu. Trong vi hnh nh tip theo, chng ti th hin dng chy ca ba b tp lnh khc thng qua datapath. Hnh 5.19 cho thy cc hot ng ca ng truyn d liu i vi tp lnh loi R, nhng l add $t1,$t2,$t3. Mc d mi th xy ra trong 1 clock cycle, chng ta c th ngh v bn bc thc thi tp lnh; nhng bc ny th c sp xp theo th t nh sau:
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1) Tp lnh c ly ra (fetch) v PC c tang ln 2) Hai register $t2 v $t3 th c c t register file v thit lp cc control line vo cng lc ny. 3) ALU tnh ton trn d liu c t register file, s dng function code (bits :5 :0) to ra chc nng tng ng cho ALU 4) Kt qu t ALU th c ghi ln register file s dng cc bit 15:11 ca tp lnh chn register ch($t1)
Cc bc tng t cho load word nh: Translater: huahongquan2007 20
Lw $t1, offset($t2) Chng ta c th chia loadword thnh 5 bc 1) Mt tp lch th c ly ra(fetch) v PC th tng ln 2) Gi tr ca Register $t2 th c c t register file 3) ALU tnh ton tng gi tr c t register v 16bits thp ( c m rng du) ca tp lnh (offset) 4) Tng ca ALU th c dng cho a ch ca b nh d liu 5) D liu t n v b nh th c ghi vo register file, register ch th c ly t bit 20:16 ca tp lnh ($t1)
Cui cng chng ti s gii thiu v tp lnh r nhnh bng beq $t1,$t2,offset. N hot ng kh ging vi tp lnh loi R, nhng ng ra ALU th c dng xc nh liu PC c c ghi vi PC + 4 hay l a ch cn r nhnh. Hnh 5.21 th hin 4 bc ca tp lnh ny 1) Mt tp lnh c ly ra (fetch), PC c tng ln 2) Hai register $t1,$t2 c c t register file 3) ALU thc hin php tr ln d liu c c t register file. Gi tr ca PC + 4 th c cng vi 16 bit thp( c m rng du) ca tp lnh , sau shift left qua 2, kt qu l a ch r nhnh. 4) Kt qu ZERO t ALU th quyt nh tng no c ghi vo PC..
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Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Nm thnh phn cu to c bn ca mt my tnh

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

H thng x l MIPS c bn:

Miu t chung v h thng x l

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Quy c thit k logic

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Xy dng mt ng truyn d liu

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

PC + 4 (the address of the next instruction) in the instruction fetch datapath, it is

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

To mt ng truyn d liu n (Creating a Single Datapath)

Chng 5: B x l: ng truyn d liu v iu khin

Xy dng mt ng truyn d liu

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

A Simple Implementation Scheme

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

Cc bc tng t cho load word nh: Translater: huahongquan2007 20

Chng 5: B x l: ng truyn d liu v iu khin

Chng 5: B x l: ng truyn d liu v iu khin

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