HC VIN K THUT QUN S

KHOA V TUYN IN T

BI TP LN
MN THIT K MCH LOGIC S

GVHD : TRNH QUANG KIN

SVTH : NGUYN TRUNG KIN (B)
DNG MINH TR
PHM HUY TNG
NGUYN TH VN
LP : TVT 7B

H Ni 19/06/2011

 Bi
Thit k v kim tra khi nhn c du 4x4 = 8bit dng m ha Booth c s 2
I C s l thuyt:
Gi s c chui bit sau:
2s complemnt 1 1 1 0 0 1 0 1 1 0 1 0 0 1(0)
Radix-2 booth 0 0-1 0 1-1 1 0-1 1-1 0 1-1
thc hin php nhn s c du u tin s m ha s nhn di dng m Booth, khi thc hin
php nhn nu bit nhn l 0, 1 ta vn lm bnh thng, nu bit nhn l -1 th kt qu nhn bng
s b hai ca s b nhn. C th p dng m ha Booth cho c s cng dch tri v cng dch
phi v h tr thao tc m rng c du.
S trn c th sa i mt cht n vn ng vi c php nhn vi s khng du, khi ta
b xung thm bit 0 vo bn tri ca s b nhn v chui Booth s di hn mt bit.
2s complemnt (0) 1 1 1 0 0 1 0 1 1 0 1 0 0 1(0)
Radix-2 Booth (1) 0 0-1 0 1-1 1 0-1 1-1 0 1-1
V d y v php nhn c du s dng m ha Booth c s 2 nh sau:
---------------------a1101

B 2 a = 0 0 1 1 (a = -3)

x0111x=+7
b 1 0 0-1 Radix 2 booth encoding of x
---------------------P(0) 0 0 0 0
+b0.a 0 0 1 1
---------------------2p(1) 0 0 0 1 1
P(1) 0 0 0 1 1
+b1.a 0 0 0 0
---------------------2p(2) 0 0 0 0 1 1
P(2) 0 0 0 0 1 1

+x2.a 0 0 0 0
---------------------2p(2) 0 0 0 0 0 1 1
P(3) 0 0 0 0 0 1 1
+x3.a 1 1 0 1
---------------------2p(3) 1 1 0 1 0 1 1
P 1 1 1 0 1 0 1 1 = -21
II.Kt cu n:
S khi ca khi m ha Booth2 gm c cc khi sau:
Multiplicand: S b nhn 4bit
-Multiplicand(2s complement):s b hai ca s b nhn
Multiplier& 0: s nhn hp vi 1 bit 0 thc hin m ha Booth c s 2.
Shift_Reg : thanh ghi dch phi 1 bit
Mux3_1: B chn tn hiu vo cho khi cng c 3 u vo l s b nhn,s b hai ca s b nhn
v 0.
AdderK+1: Khi cng K+1 bit.
Thanh ghi kt qu ca php nhn.
Thanh ghp tn hiu.

III.Chng trnh ngun ca khi nhn dng m ha Booth2:

--Khoi nhan ma hoa Booth2---------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------entity radixbooth2 is

port (in1,in2

: in std_logic_vector(3 downto 0);

reset,clk,we,reset_reg,sel : in std_logic;
product

: out std_logic_vector(7 downto 0)

);
end radixbooth2;
--------------------------------------------------------------------------architecture behavioral of radixbooth2 is
signal shift_reg_ra : std_logic_vector(1 downto 0);
signal in1_bu2

: std_logic_vector(3 downto 0);

signal B_vao

: std_logic_vector(4 downto 0);

signal bit_k_2

: std_logic_vector(1 downto 0);

signal Din3

: std_logic_vector(3 downto 0):="0000";

signal D_vao_gom
signal Vao_shift
signal in1_ra

: std_logic_vector(7 downto 0);

: std_logic_vector(4 downto 0);

: std_logic_vector(3 downto 0);

signal Qb

: std_logic_vector(7 downto 0);

signal Qa

: std_logic_vector(7 downto 0);

signal Cout

: std_logic;

signal Q

: std_logic_vector(4 downto 0);

signal Sum
signal product1

: std_logic_vector(4 downto 0);

: std_logic_vector(7 downto 0);

signal Dout

: std_logic_vector(3 downto 0);

signal Dout1

: std_logic_vector(4 downto 0);

component regis_shift is
port ( clk,reset_reg,we,sel
shift_in2
Q
);

: in std_logic;

: in std_logic_vector(4 downto 0);

: out std_logic_vector(4 downto 0)

end component;
--------------------------------------------------------------------------component mux3_1 is
port(
sel_mux

: in std_logic_vector(1 downto 0);

Din1

: in std_logic_vector(3 downto 0);

Din2

: in std_logic_vector(3 downto 0);

Din3

: in std_logic_vector(3 downto 0);

Dout

: out std_logic_vector(3 downto 0)

);
end component;
--------------------------------------------------------------------------component adder is
port ( A
B

: in std_logic_vector(4 downto 0);

: in std_logic_vector(4 downto 0);
Sum : out std_logic_vector(4 downto 0);
Cout : out std_logic
);
end component;

--------------------------------------------------------------------------component gom is
port (
Da

: in std_logic_vector(7 downto 0);

Qa

: out std_logic_vector(7 downto 0)

);
end component;
--------------------------------------------------------------------------component regB is
port (

Db

: in std_logic_vector(7 downto 0);

reset : in std_logic;
clk

: in std_logic;

Qb

: out std_logic_vector(7 downto 0)

);
end component;
BEGIN
shift_reg_ra<=Q(1 downto 0);
in1_bu2 <=not(in1)+1;
in1_ra <=in1;
D_vao_gom <=cout & Sum & bit_k_2;
process(sel)
begin
if sel='1' then
B_vao<="00000";
else
B_vao<=Qb(6 downto 2);
end if;
end process;
process(sel)
begin
if sel='1' then
bit_k_2<="00";
else
bit_k_2<=Qb(2 downto 1);
end if;
end process;
Vao_shift<=in2&'0';
product1<=Qb;
process(Dout,reset)
begin
if reset='1' then
Dout1<="00000";
else

Dout1<='0'&Dout;
end if;
end process;
shift_reg : component regis_shift
port map(shift_in2=>Vao_shift,we=>we,sel=>sel,clk=>clk,reset_reg=>reset_reg,Q=>Q);
mux5 : component mux3_1
port map(sel_mux=>shift_reg_ra,Din1=>in1_bu2,Din2=>in1_ra,Din3=>Din3,Dout=>Dout);
adder5 : component adder
port map(A=>Dout1,B=>B_vao,Cout=>Cout,Sum=>Sum);
gom8 : component gom
port map(Da=> D_vao_gom,Qa => Qa);
regB8 : component regB
port map(Db=>Qa,reset=>reset,clk=>clk,Qb=>Qb);
end behavioral;
--------Khoi test_Radixbooth2--------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test_radixbooth2 is
end test_radixbooth2;
architecture test of test_radixbooth2 is
component radixbooth2 is
port (
in1,in2

: in std_logic_vector(3 downto 0);

reset,reset_reg,clk,we,sel : in std_logic;
product

: out std_logic_vector(7 downto 0)

);
end component;
signal product1 : std_logic_vector(7 downto 0);
signal in1

: std_logic_vector(3 downto 0);

signal in2

: std_logic_vector(3 downto 0);

signal clk

: std_logic:='0';

signal reset,reset_reg,sel: std_logic;

signal we

: std_logic;

signal B_vao

: std_logic_vector(4 downto 0);

begin

create_clk:process
begin
wait for 1 ns;
clk<=not clk after 50 ns;
end process create_clk;
create_data: process
begin
reset<='1';
sel<='0';
we<='1';
reset_reg<='0';
in1<="1101";
in2<="0111";
wait for 5 ns;
reset<='1';
sel<='0';
wait for 45 ns;
reset<='0';
we<='0';
sel<='1';
wait for 100 ns;

sel<='0';
wait;
end process create_data;
radix8 : component radixbooth2
port map(reset=>reset,
reset_reg=>reset_reg,
we=>we,
clk=>clk,
sel=>sel,
in1=>in1,
in2=>in2,
product=>product1);
end test;