Ngi thc hin : Nguyn Nam Phong Nhm : BKFET

i hc Bch Khoa H Ni

BI 1: M u
Gii thiu v h VK AVR. Cc php ton c bn. Thc hin ci t cc phn mm lin quan. Lm quen vi Atmega16.

Gii thiu h VK AVR

Xut x:
Do hng Atmel sn xut. L 1 trong 3 dng vi iu khin thng dng nht trn th

trng hin nay. C nhiu tnh nng vt tri.

Gii thiu h VK AVR

c im chung:
L dng vi iu khin kh mnh.
C cu trc RISC. C nhiu thanh ghi iu khin. C nhiu loi b nh : Flash , EEPROM , SRAM. Cc chn vo ra c kh nng chu dng ln : 20mA. C nhiu ch tit kim nng lng: idle, power- down,

standby C kh nng hot ng nhiu tn s.

Gii thiu h VK AVR

c im chung:
C nhiu ngt trong v ngt ngoi. Tch hp nhiu chc nng : PWM , timer/counter , ADC

vv . Tch hp nhiu chun giao tip ngoi vi : UART, USART , TWI , SPI . Di in p lm vic rng. Hot ng n nh ng tin cy. Chng loi phong ph ph hp vi nhiu mc ch s dng.

Gii thiu h VK AVR

Mt vi dng vk AVR:
Dng ATtiny : ATtiny 11 , ATtiny 12 Dng AT90 : AT90C8515 , AT90S2313 , AT90S8515 Dng Mega : ATmega8 , ATmega16 , ATmega32 ,

ATmega128

Cc php ton c bn
Php ton AND ( & ) :
Cu lnh trong C : Y = A & B ;

A 0 0 1 1

B 0 1 0 1

Y 0 0 0 1

Cc php ton c bn
Php ton OR ( | ) :
Cu lnh trong C : Y = A | B ;

A 0 0 1 1

B 0 1 0 1

Y 0 1 1 1

Cc php ton c bn
Php ton NOT ( ~ ) :
Cu lnh trong C : Y = ~A ;

A 0 1

Y 1 0

Cc php ton c bn
Php ton dch bt ( << , >> ) :
Cu lnh trong C :

Y = A << B ; // Y = A* 2^B Y = A >> B ; // Y = A/ 2^B

Thc hin ci t hng dn s dng cc phn mm h tr

Lm quen vi Atmega16

BI 2: Chc nng I/Ov Ngt ngoi

Thit lp chc nng I/O cho VK Thit lp chc nng s dng ngt ngoi

Chc nng I/O

M t:
Atmega16 c 32 chn vo/ra (I/O) c th lp trnh c PORTA (cng A): 8 chn : PA0 PA7 . PORTB (cng B): 8 chn : PB0 PB7 . PORTC (cng C): 8 chn : PC0 PC7. PORTD (cng D): 8 chn : PD0 PD7. Cc chn ny c iu khin thng qua cc thanh ghi

tng ng vi cc cng ca chng.

Chc nng I/O

Cc thanh ghi iu khin chc nng I/O:
Vi PORTA (Cng A ) Cc cng khc tng t :
Thanh ghi PORTA: Thanh ghi d liu ca cc PORT . c ghi c .

Thc hin set bit : PORTA |= ( 1<<PAn )

Gii thch cu lnh : Php ton |= : A |= B ; ~ A = A | B ; Tng t : A &= B; ~ A = A&B; A += B; ~ A = A+B; PAn (n : 0-7 ): Trong th vin < avr/io.h > cc chn PA0 n PA7 c nh ngha tng ng vi cc s nguyn t 0 7. Vy ta c : PORTA |= (1<<PA2); => PORTA = PORTA | (1*2^2) ;

1*2^2 = 4 => 0000 0100 PORTA = PORTA | 0b00000100 ;

PORTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 0 0 0

PORTA
PA7 PA6 PA5 0 0 0 0 0 1 0 0

0 0 1 0 0

PA4 PA3 PA2 PA1 PA0

Tng t khi ta mun t 1 bit v 0: PORTA &= ~ ( 1 << PA2 ); => PORTA &= ~ 0b 0000 0100 ; => PORTA = PORTA & 0b 1111 1011 ;

PORTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 1 1 1 1 1 1 1 1 1 1 1

PORTA
PA7 PA6 1 1 1 1 1 0 1 1

&

1 1 0 1 1

PA5 PA4 PA3 PA2 PA1 PA0

 Vy ta c cng thc tng qut cho vic set bt ca 1 thanh ghi

nh sau

Set ln 1 : Tn_thanh_ghi | = (1 << Tn_bit ); PORTB |= (1<<PB2); Set v 0 : Tn_thanh_ghi &= ~ (1 << Tn_bit ); PORTB&=~(1<<PB3);

Chc nng I/O

Cc thanh ghi iu khin chc nng I/O:
Vi PORTA (Cng A ):
Thanh ghi DDRA : Thanh ghi ch hng vo/ra . c ghi c

Thc hin set bit : DDRA |= ( 1<< DDAn ); // vi chn tng ng l u ra. DDRA &= ~( 1<< DDAn ); // vi chn tng ng l u vo.

Chc nng I/O

Cc thanh ghi iu khin chc nng I/O:
Vi PORTA (Cng A ):
Thanh ghi PINA : Thanh ghi ch dng cho mc ch c cc gi

tr u vo. Ch c c .

Cch kim tra cc chn vo: if (PINA == 0b00000100) // Kim tra chn 2 ca PORTA c // phi mc 1 khng. { /*code*/}

Thc hnh s dng chc nng I/O

Hn ch :
if (PINA = 0x00000100) {}

khi c nhiu phm n ng thi th khng nhn bit c => cn thc hin kim tra c lp theo u vo => If (!( PINA & ( 1<< PA2 ))) {/* code */} Vic s dng phm bm theo dng ny i hi VK phi hot ng lin tc ( ch hi vng )

Chc nng ngt ngoi (External Interrupt)

M t:
Ngt : l mt tn hiu khn cp c gi n b x l

trung tm , yu cu tm dng tt c cc cng vic khc u tin thc hin cng vic m ngt yu cu. Khi c tn hiu ngt , cc chng trnh ang chy s c lu vo cc ngn xp , b x l trung tm s gi 1 chng trnh phc v ngt tng ng vi ngt c yu cu thc hin cc thao tc x l ngt , sau khi thc hin xong chng trnh con phc v ngt , chng trnh s quay tr v trng thi trc .

Chc nng ngt ngoi (Extrenal Interrupt)

M t:
Atmega16 c 3 chn ngt ngoi l INT0, INT1, INT2 INT0 (cng D): chn : PD2 INT1 (cng D): chn : PD3 INT2 (cng B): chn : PB2 Chc nng ngt ca cc chn ny c iu khin bi cc

thanh ghi : MCUCR , MCUCSR , GICR . Thanh ghi c : GIFR.

Chc nng ngt ngoi (External Interrupt)

MCUCR MCU Control Register

ISC11 ,ISC10 : thit lp kiu ngt cho chn INT1

ISC11 0 0 1 1 ISC10 0 1 0 1 Ch Ngt mc thp Ngt thay i mc logic Ngt sn xung Ngt sn ln

Chc nng ngt ngoi (External Interrupt)

MCUCR MCU Control Register

ISC01 ,ISC00 : thit lp kiu ngt cho chn INT0

ISC01 0 0 1 1 ISC00 0 1 0 1 Ch Ngt mc thp Ngt thay i mc logic Ngt sn xung Ngt sn ln

Chc nng ngt ngoi (External Interrupt)

MCUCSR MCU Control and Status Register

ISC2 : thit lp kiu ngt cho chn INT2

ISC2 0 1 Ch Ngt sn xung Ngt sn ln

xy ra ngt chn ny th xung tn hiu vo phi c rng ln hn 50ns

Chc nng ngt ngoi (External Interrupt)

GICR General Interrupt Control Register

INT1 : Cho php ngt chn INT1 INT0 : Cho php ngt chn INT0 INT2 : Cho php ngt chn INT2

Chc nng ngt ngoi (External Interrupt)

GIFR General Interrupt Flag Register

INTF1 : c set ln 1 khi xy ra ngt sn hoc thay i mc logic chn INT1. Lun l 0 khi l ngt mc. INTF0 : c set ln 1 khi xy ra ngt sn hoc thay i mc logic chn INT0. Lun l 0 khi l ngt mc. INTF2 : c set ln 1 khi xy ra ngt chn INT2.

Cc bit ny c xa v 0 khi cc vector ngt c gi.

Chc nng ngt ngoi (External Interrupt)

Thc hin xc lp ch ngt ngoi :
#include <avr/io.h> #include <avr/interrupt.h> #include <util/delay.h> unsigned char x=0; SIGNAL(SIG_INTERRUPT1) { PORTA |= (1<<PA0); _delay_ms(100); PORTA &= ~(1<<PA0); }

void main() { DDRA = 0xFF; DDRB = 0xFF; DDRD = 0x00; PORTD = 0xFF; PORTB = 0x00; MCUCR &=~ ((1<<ISC11)|(1<<ISC10)); // ngat muc thap o chan ngat INT1 GICR |= (1<<INT1); // cho phep ngat ngoai sei(); // cho phep ngat toan cuc while(1) { for(x=0;x<8;x++) { PORTB =(1<<x); _delay_ms(100); } } }

B Timer/Counter
M t:
Atmega16 c 2 Timer/Counter 8 bits v 1 Timer/Counter

16 bits
Timer/Counter0 : 8 bits. Timer/Counter1 : 16 bits. Timer/Counter2 : 8 bits.

Cc b Timer/Counter ny c rt nhiu chc nng ng

dng a dng trong thc t .

B Timer/Counter
Cc chn ca b timer/counter:
Timer/Counter 0:
T0 ( PB0 ) : OC0 ( PB3 ) :

Timer/Counter 1:
T1 ( PB1) :
OC1A ( PD5 ): OC1B ( PD4 ) : ICP ( PD6 ) :

Timer/Counter 2:
OC2 ( PD7 ) :

B Timer/Counter
Cc vn trong bi hc:
Cc vn c bn ca b Timer/Counter. S dng Timer/Counter nh 1 b Timer. S dng Timer/Counter nh 1 b Counter. S dng Timer/Counter lm b PWM ( Pulse Width

Modulation ).

B Timer/Counter
Cc vn c bn:
L Module c lp so vi CPU. Chc nng chnh l lm b nh thi (timer) v b m s

kin (counter). 3 b Timer/Counter ca ATmega16 u c b canh chnh thi gian ( Caliration ) s dng trong cc ng dng thi gian thc rt tin li. Thng thng 1 b Timer/Counter s c cc ch hot ng : Normal Mode , CTC Mode , PWM Mode.

Kho st Timer/Counter0
Cc nh ngha quan trng cn nm c:
BOTTOM : gi tr nh nht m 1 T/C c th m c ,

gi tr ny bng 0. MAX : gi tr ln nht m 1 T/C c th m c , gi tr ny ph thuc vo phn gii ca T/C . VD: T/C0 l T/C 8bits => MAX = 2^8 - 1 = 255. BOTTOM v MAX l 2 hng s i vi 1 T/C. TOP : L gi tr m khi T/C t ti n s thay i trn thi. BOTTOM TOP MAX . Gi tr TOP c thit lp thng qua 1 thanh ghi ng vi mi T/C.

Kho st Timer/Counter0
Cc thanh ghi iu khin Timer/Counter :
TCCR0 : Time/Counter Control Register :

Bit 6,3 : WGM00 , WGM01 : Thit lp ch hot ng ca T/C

Kho st Timer/Counter0
TCCR0 : Time/Counter Control Register :

Bit 5,4 : COM01,COM00 : Thit lp ch u ra ca chn OC0.

Kho st Timer/Counter0
i vi cc ch khng phi PWM

i vi ch Fast PWM

Kho st Timer/Counter0
i vi cc ch Phase Correct PWM Mode

Kho st Timer/Counter0
Cc thanh ghi iu khin Timer/Counter :
TCCR0 : Time/Counter Control Register :

Bit 2,1,0 : CS02-0 : Thit lp ch chia tn

Kho st Timer/Counter0
Cc ch chia tn :

Kho st Timer/Counter0
TCNT0 : Time/Counter Register :

Thanh ghi ny lm nhim v lu gi tr m ca b T/C . Gi tr ca thanh ghi ny s tng 1 n v sau mi khong thi gian c nh sn trong qu trnh chia tn. Mi khi gi tr ca TCNT bng vi gi tr ca thanh ghi OCR s xy ra 1 s kin ngt v chn OC0 s cho ra dng sng c thit lp mode .

Kho st Timer/Counter0
OCR0 : Output Compare Register :

Gi tr ca thanh ghi ny c ngi s dng thit lp .

Kho st Timer/Counter0
TIMSK : Time/Counter Interrupt Mask :

Bit OCIE0 : Cho php ngt khi thanh ghi OCR = TCNT Bit TOIE0 : Cho php ngt trn Timer/Counter0.

B Timer/Counter
S dng T/C nh 1 b Timer:
M t hot ng :
( Normal Mode ) Trong ch Normal Mode thanh ghi TCNT tng gi tr ca n ln 1 n v sau mi 1 khong thi gian c nh trc trong qu trnh chia tn . Khi TCNT t gi tr bng MAX = 255 , n sinh ra mt ngt. Ta tn dng ngt ny bin T/C thnh 1 b Timer.

V d : Thc hin nhy n LED sau mi 0.1ms .Vi

VDK hot ng tn s 8Mhz.

B Timer/Counter
1us 155 1us 156 157 (255-155) x 1us = 0.1ms 158 159 255

Chng trnh con phc v Ngt : thay i trng thi ca LED

B Timer/Counter
S dng T/C nh 1 b Counter:
M t hot ng : ( Normal Mode )
Cc s kin c m t chn T0 v lu li s s kin trong thanh ghi TCNT.

V d : Thc hin m s kin v a cc gi tr m

c ra PORTD.

B Timer/Counter
#include <avr/io.h> #include <util/delay.h> void main() { DDRD = 0xFF; // PORTD ra PORTD = 0x00; // muc thap , cho giong voi thanh ghi TCNT0 DDRB = 0x00; // PORTB dau vao cho chn T0 PORTB = 0xFF; // Muc cao TCCR0 |= (1<<CS01)|(1<<CS02); // su dung suon xuong de bat su kien TCNT0 =0;

B Timer/Counter
while(1) { if (TCNT0 == 200) TCNT0 = 0; // cho phep dem den 200 PORTD = TCNT0; } }

B Timer/Counter
S dng T/C lm b PWM:
M t hot ng :
( ch fast PWM ) T chn OC0 ca VK s c xung ra vi rng xung thay i c bng cch thay i gi tr ca OCR0 ( 0 255 ). Tn s ca chui xung ny c tnh bng cng thc:

fPWM = fclk / ( N.256 )

Trong : fPWM : Tn s xung ra. fclk : Tn s hot ng ca VK. N : H s chia tn.

V d : Thc hin nhy n LED bng ch PWM , nhn xt

s nhp nhy ca LED .

B Timer/Counter
fPWM = 8/(8 x 256) = 0,004 Mhz

TPWM = 1/ fPWM = 250 us

B Timer/Counter
#include <avr/io.h> void main() { DDRB = 0xFF; TCCR0 |= (1<<CS01); //chia tan 8 TCCR0 |= (1<<WGM01)|(1<<WGM00); // che do fast PWM OCR0 = 10; // khoi tao thanh ghi OCR0 TCCR0 |= (1<<COM01)|(1<<COM00); //chon che do OC0 =1 khi TCNT = OCR }

Khi USART
M t:
Atmega16 c 1 b USART ( Universal Synchronous/

Asynchronous serial Receiver and Transmitter) . y l khi giao tip ni tip rt linh hot :
Hot ng c ch song cng ( truyn nhn c lp ) Truyn thng ni tip ng b ( Synchronous )hoc khng

ng b ( Asynchronous ). ng b giao tip Master / Slave Gii tc truyn a cp Cho php s dng nhiu khung truyn : 5,6,7,8,9 Databits ; 1,2 Stopbit.

Khi USART
M t:
C kh nng to bit kim tra chn l v kim tra bit kim tra

chn l. C kh nng pht hin li trn C kh nng pht hin li khung truyn C kh nng x2 tc ch khng ng b C cc ngt pht hin: kt thc qu trnh nhn , thanh ghi truyn trng , kt thc qu trnh truyn

Khi USART
Cc chn ca khi USART:
Chn TXD ( PD1 ) :

Chn xut tn hiu ra ca khi USART. Chn RXD ( PD0 ) : Chn nhn tn hiu vo ca khi USART. =>> Mun 2 khi truyn thng ny giao tip vi nhau th phi kt ni TXD ca b ny vi RXD ca b kia. Chn XCK ( PB0 ) : Chn kt ni xung Clock ca cc b USART . Chn ny ch s dng trong ch ng b ( Synchronous )

Khi USART
Khung truyn:

St : Start bit : lun mc thp v ch c 1. Data bits : 5, 6, 7, 8 hoc 9 bits. Khng c Parity bit , Parity bit chn , Parity bit l. Sp : Stop bit : 1 hoc 2 Stop bit : lun mc cao. IDLE : khng c giao tip ( mc cao ).

Khi USART
Gii thch v khung truyn
Start bit: L bt u tin c gi i thng bo vi bn nhn l c d liu ang c gi ti.

Stop bit:
L bt cui cng thng bo kt thc 1 khung truyn .

Parity bit:
Nu c s dng th bt ny nm gia data bit cui cng v

Stop bit u tin. Bit ny c tnh nh sau :

Parity chn : l kt qu ca php XOR cc databit v bit 0. Parity l : l kt qu ca php XOR cc databit v bit 1.

Khi USART
Gii thch v khung truyn
Cc data bit:
Cc data bit s c kim tra bng tc truyn Baudrate.

Kt lun : 2 khi giao tip c vi nhau th: C cng 1 khung truyn ( frame format ). Phi c cng tc truyn ( baud rate ).

Cc vn trn c thit lp ti cc thanh ghi iu khin khi USART

Khi USART
Cc thanh ghi :
UDR ( USART Data buffer Register )

Thanh ghi d liu ca khi USART. Khi truyn thi y l thanh ghi ghi d liu cn truyn. Khi nhn thanh ghi ny ghi d liu nhn. Phn bit ? Thanh ghi ny ban u mc nh l nhn Mun ghi d liu gi i th trc cn UCSRA |= ( 1<< UDRE ). Sau khi ghi d liu xong , b Transmitter c khi ng th d liu ny s c chuyn vo thanh ghi dch khi thanh ghi trng, ri d liu c truyn i.

Khi USART
Cc thanh ghi :
UCSRA ( USART Control and Status Register A)

RXC : Receive complete : Set ln 1 khi trong UDR c d liu cha c c. Xa v 0 khi b m trng. TXC : Transmit complete : Set ln 1 khi ton b d liu trong thanh ghi dch c y ra ngoi v khng c d liu mi xut hin trong UDR. T v 0 khi chng trnh con phc v ngt c gi, hoc ngi dng c th xa bng cch ghi 0 vo.

Khi USART
Cc thanh ghi :
UCSRA ( USART Control and Status Register A)

UDRE: UDR is Empty: Set ln 1 khi UDR trng v sn sng nhn d liu mi. Xa v 0 khi b m trng. FE : Frame Error : Set ln 1 khi xy ra li khung truyn. 0 khi khng c li khung truyn Lun t bit ny l 0 khi tc ng vo UCSRA

Khi USART
Cc thanh ghi :
UCSRA ( USART Control and Status Register A)

DOR : Data Over Run : Set ln 1 khi xy ra s c trn d liu: ang c d liu trong b m , c d liu trong thanh ghi dch v ng thi pht hin 1 start bit mi. Xa v 0 khi c thao tc c d liu t UCR Khi s dng thanh ghi UCSRA th phi bit ny l 0 PE : Parity Error : Set ln 1 khi xy ra li bit kim tra chn l. Xa v 0 khi c thao tc c d liu t UCR

Khi USART
Cc thanh ghi :
UCSRA ( USART Control and Status Register A)

U2X : Double the USART Transmittion speed : Ch c tc dng vi ch Asynchronous. MPCM : Multi processor Communication Mode : Khi set ln 1 , tt c cc khung truyn khng c a ch s b loi b.

Khi USART
Cc thanh ghi :
UCSRB ( USART Control and Status Register B)

RXCIE : RX Complete Interrupt Enable : Cho php ngt khi nhn xong. TXCIE : TX Complete Interrupt Enable : Cho php ngt khi nhn xong. UDRIE : UDR Empty Interrupt Enable: Cho php ngt khi UDR trng.

Khi USART
Cc thanh ghi :
UCSRB ( USART Control and Status Register B)

RXEN : RX Enable : Cho php nhn. TXEN : TX Enable : Cho php truyn. UCSZ2 : Character size: s lng databit kt hp cng UCSZ1, UCSZ0 thanh ghi UCSRC xc nh s databit.

Khi USART
Ch s data bit:

Khi USART
Cc thanh ghi :
UCSRB ( USART Control and Status Register C)

URSEL: Bit ny l 1 th thanh ghi ny l UCRSC ( chnh n :D ) Bit ny l 0 th thanh ghi ny tr thnh UBRRH s dng set Baudrate. UMSEL : Mode Select : Chn ch : Set ln 1: ch ng b Synchronous. Set v 0 : ch khng ng b Asynchronous.

Khi USART
Cc thanh ghi :
UCSRB ( USART Control and Status Register C)

UPM1, UPM0: Parity Mode : Chn ch cho bt kim tra chn l.

Khi USART
Cc thanh ghi :
UCSRB ( USART Control and Status Register C)

USBS: Stop Bit Select : 0 : 1 Stop bit. 1 : 2 Stop bits. UCPOL : Clock Polarity : Ch s dng trong ch Synchronous. Trong ch Asynchronous bit ny l 0. Chn sn ly mu tn hiu .

Khi USART
Cc thanh ghi :
UBRRL v UBRRH ( Baudrate Register )

URSEL : bit chn = 0 th l UBRRH Khi set baudrate ta tra bng v gn gi tr cho UBRRH v UBRRL

Khi USART
M phng :
Thc hin giao tip truyn thng ni tip gia 2 VK. Yu cu khung truyn : 8 data bits , 1 stop bit , no parity ,

Baudrate 9600 bps. Gi s 2 VK Atmega16 s dng thch anh 8Mhz.