G. H.

Raisoni College of Engineering, Nagpur Department of Electronics Engineering CMOS VLSI Design Question Bank
UNIT I Subjective 1. Design CMOS logic gates for the following function. a) Z = /(A.B.C.D) b) Z = /(A+B+C+D) 2. Use a combination of CMOS gates to generate the following functions. a) Z = A (buffer) b) Z = A. /B+/A.B (XOR) 3. Design the following logic functions. A 2:4 decoder defined by Z0 = A0. A1 Z1 = A0. A1 Z2 = A0. A1 Z3 = A0. A1 4. Design the following logic functions. A 3:2-priority encoder defined by Z0 = /A0. (A1+/A2) Z1 = /A0. /A1 5. Design CMOS logic gates for the following function. a) Z = /((A.B.C)+D) b) Z = /((A.B)+C. (A+B)) 6. Design CMOS logic gates for the following function. Z = ((((A.B)+C). D) 7. Use a combination of CMOS gates to generate the following functions. a) Z = A.B + /A. /B (XNOR) b) Z = A. /B. /C +/A. /B.C + /A. /C.B +A.B.C 8. Design a 2-input multiplexer that uses CMOS logic gates in place of CMOS switches. 9. Design a 4:1 multiplexer using a combination of CMOS switches and logic gates. 10. Design a 4:1 multiplexer using only CMOS logic gates. 11. Design a 4:1 multiplexer using a combination of CMOS switches and logic gates. & Using only CMOS logic gates. Assess the efficiency of each implementation by counting the total number of switches used in each implementation. Which is more efficient? Why? 12. Design a positive level-sensitive D latch in which the Q output, by a signal RESET, may be reset to O independently of the state of the CLK signal (i.e. RESET=1 Q=1). This is the basis for an asynchronously resettable latch. 13. Design a positive edge-triggered D register that can be asynchronously set. 14. Design a positive edge-triggered D register in which the Q output may be reset, synchromout with the clock input. Objective 1. What do you mean by IC Technology?

2. How the no. of transistors is categorized? 3. What is SSI? 4. What is MSI? 5. What is LSI? 6. What is VLSI? 7. What is ULSI? 8. What is SLSI? 9. What is GSI? 10. What do you mean by Feature size? 11. What are L and W? 12. What is the thickness of Oxide layer? 13. What do you mean by MOS transistor as Switch? 14. Why N-mos transistor produces weak 1? 15. Why P-mos transistor produces weak 0? 16. Show the series connection of Switches. 17. Show the parallel connection of Switches. 18. What do you mean by Channel? 19. What is the range of Feature size?

UNIT II Subjective 1. Explain nMOS enhancement transistor. 2. What are the different regions in which the MOS transistor operates? 3. Explain pMOS enhancement transistor. 4. Explain threshold voltage. 5. Explain Body effect. 6. Explain MOS device design equations. 7. Explain basic DC equations. 8. Explain Second Order Effects. 9. Write a short note on Small Signal AC Characteristics. 10. Explain Threshold voltage body effect. 11. Explain Subthreshold Region. 12. Explain Channel-length Modulation. 13. Explain Mobility Vairation. 14. Explain Fowler-Nordheim Tunneling 15. Explain Drain Punchthrough. 16. Explain Impact Ionization- Hot electrons. 17. Write a short note on MOS Models. 18. Write a short note on a) Subthreshold Region 19. Channel-length Modulation 20. Write a short note on a. Drain Punchthrough b. Small Signal AC Characteristics. Objective 1. Which material is used to make Gate, Drain and Source? 2. What do you mean by MOSFET? 3. What is nMOS? 4. What is pMOS? 5. What is the difference between MOS and MOSFET? 6. How many devices that can be fabricated on 4 inch silicon wafer with 5 technology? 7. What do you mean by Compound gate? 8. What do you mean by Combinational gates? 9. What do you mean by Edge Triggered D-Register? 10. What do you mean by Rising Edge Triggered D-Register? 11. How the no. of devices are calculated? 12. How MOS is classified? 13. What do you mean by Wafer? 14. What do you mean by Microelecotronics Technology? 15. What are the two basic technologies? 16. What do you mean by MOS Technology?

UNIT III Subjective 1. 2. 3. 4. Explain Complementary CMOS Inverter. Explain DC characteristic of CMOS Inverter. Explain n/ p Ratio. Explain the five regions of operation of CMOS inverter DC transfer characteristic. Hence write the equations for Vout in the different regions. 5. Explain Noise Margin. 6. The CMOS Inverter as an Amplifier, explain. 7. What is Static Load MOS Inverters, explain. 8. Explain the Pseudo-nMOS Inverters. 9. Explain Saturated Load Inverters. 10. A MOS transistor has a threshold voltage of 0.75volt. The body effect coefficient r = 0.54. Calculate the threshold voltage for Vsb = 4V and 2 F = -0.6V. 11. Derive the VOH and VOL for saturated load inverter using an nMOS transistor load. 12. Explain More Saturated MOS Inverters. 13. Explain The Cascode Inverters. 14. Explain TTL Interface Inverter. 15. Explain The Differential Inverter. 16. Write a short note on the Transmission Gate. 17. Explain the Tristate Inverter. 18. Write a short note on Bipolar Transistors. 19. Write a short note on BICMOS Inverters. 20. Calculate the noise margin for the BiCMOS inverter shown in fig. i. a. BiCMOS CMOS ( n = p) and ii. b. BiCMOS pseudo-nMOS ( n/ p = 4) (Vbe = 0.7volts) Objective 1. What do you mean by Bipolar Technology? 2. What do you mean by nMOS Technology? 3. What do you mean by pMOS Technology? 4. What do you mean by CMOS Technology? 5. What do you mean by n-well? 6. What do you mean by p-well? 7. How CMOS is differing from nMOS and pMOS? 8. What is the difference between CMOS and Bipolar Technologies? 9. Which MOS is required more processing steps? 10. Which MOS is required less power consumption? 11. What do you mean by Static Power dissipation? 12. What do you mean by input impedance? 13. What do you mean by Noise Margin? 14. What do you mean by Packaging density?

UNIT IV Subjective 1. Explain Resistance Estimation. 2. Explain Resistance of Nonrectangular Regions. 3. Explain Contact and Via Resistance. 4. Explain Capacitance Estimation. 5. Explain MOS Capacitor Characteristics. 6. Explain MOS Device Capacitances. 7. Explain SPICE Modeling of MOS capacitances. 8. Explain Switching Characteristics. 9. What is Fall Time? Explain 10. What is Rise Time? Explain 11. What is Delay Time? Explain 12. Write a short note on Power Dissipation. 13. What is Static Dissipation? Explain. 14. What is Dynamic Dissipation? Explain. 15. What is Short-Circuit Dissipation? Explain. 16. Explain total power dissipation. Objective 1. What is fan-out? 2. What is Static power dissipation for CMOS and BIPOLAR? 3. What is Input impedance for CMOS and BIPOLAR? 4. What is Noise Margin for CMOS and BIPOLAR? 5. What is Packaging density for CMOS and BIPOLAR? 6. What is Fan-out for CMOS and BIPOLAR? 7. What is Direction for CMOS and BIPOLAR? 8. What do you mean by BI-CMOS technology? 9. What do you mean by GaAs technology? 10. What is Metal Oxide Semiconductor Field Effect Transistor? 11. How many terminals are present in MOS? 12. What do you mean by Insulated gate field effect transistor? 13. What do you mean by Enhancement type MOSFET? 14. What do you mean by Depletion type MOSFET? 15. What is the symbol of nMOS? 16. What is the symbol of pMOS? 17. What is the symbol of CMOS? 18. Show the Drain curve for nMOS operated with Vgs > Vt. 19. What do you mean by Cut_off region? 20. What do you mean by Linear region? 21. What do you mean by Saturation region? 22. How the operation of nMOS takes place? Give the three different regions. 23. What do you mean by Current-voltage relation? 24. What do you mean by Inversion layer? 25. What do you mean by pinch-off condition? 26. What is ? 27. What is Kn? 28. 77. What is tOX?

UNIT V Subjective 1. Explain Silicon Semiconductor Technology. 2. What is Wafer Processing? Explain. 3. What is Oxidation? Explain. 4. What are Epitaxy, Deposition, Ion-Implantation and Diffusion? Explain. 5. Explain Basic CMOS Technology. 6. Explain a basic n-well process. 7. Draw the layout for CMOS inverter. 8. Write a short note on Twin-tub process. 9. Explain a basic p-well process. 10. Write a note on Layout Design Rules. 11. Why design rules are essential for fabrication of CMOS Ics. 12. List the alternate CMOS logic structures that can be used instead of full complementary static CMOS gates. Explain in details clocked CMOS logic. 13. State various components of power dissipation in CMOS circuits. 14. Implement the equation Z = /((A+B)(C+D+E) F) using depletion load NMOS design technique, size the devices so that the output resistance is same as that of an inverter with driver (W/L) = 1. 15. Design the physical layout of a. NAND gate and b. NOR gate Objective 1. What do you mean by effective channel length? 2. What do you mean by effective channel length modulation? 3. What is ? 4. Show the V-I characteristic of nMOS. 5. What do you mean by inverter? 6. What do you mean by Static load inverter? 7. What do you mean by CMOS Inverter? 8. What is Noise Margin? 9. What do you mean by switching characteristics of CMOS Inverter? 10. What do you mean by Active Resistive Load? 11. Show the Actual Inverter characteristic of CMOS inverter. 12. What do you mean by Resolution of gate output level? 13. Give the voltage relation for regions of operation of CMOS inverter? 14. What is n/ p Ratio?

UNIT VI Subjective 1. Write a short note on Clocking Strategies. 2. Discuss how the rise time and fall time of an inverter can be made equal. Suggest schemes to reduce rise and fall time of an inverter. 3. Explain CMOS logic Structures. 4. Explain Fan in and Fan out for CMOS gates. 5. Explain Latch up. How it can be avoided? 6. Explain the MOS capacitor characteristics for accumulation, depletion, and inversion region. 7. Design the layout for NAND and NOR gates? 8. Write short note on Charge Sharing. 9. With regard to CMOS D-flip-flop explain the terms setup time and hold time. What is metastability? 10. Explain briefly the Silicon on Insulator technology with regard to CMOS logic. 11. Explain where and how phase locked loop clock is used on chip. 12. What is Metastability? Explain. 13. What are Channel Stops? Explain. 14. How is the clocking strategies related to the setup and hold time in a latch? 15. Design a two-phase CMOS clock generator circuit to be used as a part of VLSI system and explain its operation. 16. Explain where and how phase locked loop clock is used on chip. 17. Draw the scheme to design 16 input AND gate that is optimized for area. Objective 1. What do you mean by Switching characteristics? 2. What do you mean by Rise time? 3. What do you mean by Fall time? 4. What do you mean by Delay time? 5. What do you mean by n= p? 6. What do you mean by Pull up network? 7. What do you mean by Pull down network? 8. What do you mean by Transmission gate? 9. Where does Power go in CMOS? 10. What is Dynamic Power Dissipation? 11. What is Short circuit Power Dissipation? 12. What is Stage Ratio? 13. What are the Layout design rules? 14. What do you mean by Layout, Physical and symbolic? 15. What do you mean by stick diagrams? 16. Is there any difference between Layout and Stick diagrams?