Combinational Logic Circuit (CLC)

Course Conducted by Shuvodip Das, Lecturer, ETE Dept., Prime University, Bangladesh.

Parity Generator and Detector Circuit

Parity bit: Parity bits are used to detect that an error has occurred between the storing and retrieving of a byte or the sending and receiving of a byte. Two kinds of Parity bit. a) Even and b) Odd Parity. Odd parity: Odd parity requires the number of 1s in a byte plus the parity bit be odd For example If a byte contains the pattern 11001100, the parity bit would be 1, thus giving an odd number of 1s If the pattern were 11110001, the parity bit would be 0, giving an odd number of 1s Even parity uses the same scheme, but the number of 1 bits must be even.

Parity Bit
For example, the ASCII code for 'S' is 1010011. To get even parity, we add 0, giving us 01010011. If we count the 1's, we get 4 which is an even number. To get odd parity, we simply add another 1, giving us 11010011, containing 5 1's. Error Detection by Parity: The type of parity is determined by the transmitter and receiver. Both systems must use the same parity scheme. For example, if even parity is used, and say ASCII 'O' (11001111) is transmitted and the receiver receives 11001011, it is obvious an error has happened because there is an odd number of 1's. The receiving system can then call for retransmission. Problems with this Type of Error Detection The main drawback to this type of error detection is that multiple errors cannot be detected. For example, ASCII 'k' with even parity (11101011) is transmitted. The receiver receives 11011011. This is the ASCII code for [. This is not the character we want, but it is not detected as an error because it is still even parity.

Parity Bit
Usage or Applications of Parity:
Because of its simplicity, parity is used in many hardware applications where an operation can be repeated in case of difficulty, or where simply detecting the error is helpful. For example, the SCSI (Small Computer System Interface) and PCI (Peripheral Component Interconnect) buses use parity to detect transmission errors, and many microprocessor instruction caches include parity protection. Because the I-cache data is just a copy of main memory, it can be disregarded and re-fetched if it is found to be corrupted. In serial data transmission, a common format is 7 data bit, an even parity bit, and one or two stop bits. This format neatly accommodates all the 7-bit ASCII characters in a convenient 8-bit byte. Other formats are possible; 8 bits of data plus a parity bit can convey all 8-bit byte values. In serial communication contexts, parity is usually generated and checked by interface hardware (e.g., a UART) and, on reception, the result made available to the CPU (and so to, for instance, the operating system) via a status bit in a hardware register in the interface hardware. Recovery from the error is usually done by retransmitting the data, the details of which are usually handled by software (e.g., the operating system I/O routines).

Principle of Parity Generation and Detection

Parity Generator
4 bit Even Parity Generator: 8 bit Parity Generator works as Even or Odd parity generator.

3 bit Even Parity Generation and Detection

3 bit Even Parity Generation and Detection

Odd Parity Generation and Detection

3 bit Odd parity Generator:
INPUT OUTPUT ( Three bit message ) bit) ( Odd Parity
SL .No

0. 1. 2. 3. 4. 5. 6. 7.

A
0 0 0 0 1 1 1 1

B
0 0 1 1 0 0 1 1

C
0 1 0 1 0 1 0 1

P 1 0 0 1 0 1 1 0

From P( A, Also P =

the truth table the expression for the output parity bit is , B, C) = (0, 3, 5, 6) written as , A B C + A BC + AB C + ABC = ( B C) A

Odd Parity Generation and Detection

B C P) S.No

INPUT ( four bit message Received )OUTPUT

A B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1

(Parity error check) X

0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

Odd Parity Generation and Detection

From the truth table the expression for the output parity checker bit is, X (A, B, C, P) = (0, 3, 5, 6, 9, 10, 12, 15) The above expression is reduced as, X = (A B C P) CIRCUIT DIAGRAM: ODD PARITY CHECKER

TTL, ECL and CMOS 8 bit Parity Generator

I :7 4 1 8 0 C 8 B i O d d / E ve n Pa ri G e n e ra to r / C h e cke r t ty