Tng s bi gi: 8 c THANKS: 0 Join date: 25/11/2010 Tiu : Thi lai VHDL Tue Mar 01, 2011 9:38

am da co de thi lai ! Ni dung n tp Thi li t chc di hnh thc thi vit, thi lng khonga5 pht. Khi thi khng c s dng ti liu, bi tp lp trnh khng cn vit phn Test, mi c 3 cu v ni dung n tp cho tng cu nh sau: Cu 1 1. Cng logic c bn, tham s thi gian ca cng logic t hp, nu v d. Khi nim mch t hp v cch tnh thi gian tr trn mch t hp, khi nim critical paths. 2. Cc loi Flip-flop c bn, tham s thi gian ca Flip-flop. Khi nim mch dy, cch tnh thi gian tr trn mch dy. Khi nim pipelined, cc phng php tng hiu sut mch dy. 3. Cc phng php th hin thit k mch logic s, nu v phn tch cc u im ca phng php s dng VHDL. 4. Nguyn l hin thc ha cc hm logic trn cc IC kh trnh dng PROM, PAL, PLA, GAL, cu trc ma trn AND, OR, macrocell. 5. Cu trc ca thit k bng VHDL, c im v ng dng ca cc dng m t kin trc trong VHDL, v d. 6. Trnh by v i tng d liu trong VHDL. Cc kiu d liu trong VHDL, kiu d liu tin nh ngha v d liu nh ngha bi ngi dng. D liu kiu BIT v STD_LOGIC. 7. Pht biu tun t, bn cht, ng dng, ly v d VHDL v pht biu ny. 8. Pht biu ng thi, bn cht, ng dng, ly v d VHDL v pht biu ny. 9. Khi nim FPGA, Cc u im ca FPGA so snh vi cc IC kh trnh trc . 10. Trnh by kin trc tng quan ca Spartan 3E FPGA. 11. Trnh by cu trc ca CLB, SLICE, LUT, cch thc thc hin hm logic 4 v nhiu u vo trn FPGA. 12. Trnh by v khi kt ni kh trnh trong FPGA, cc dng kt ni c trong FPGA. 13. Trnh by cu trc ca IOB trong FPGA, khi lm tr kh trnh v ng dng, khi nim DDR.14. Quy trnh thit k trn FPGA. Khi nim tng hp thit k.Khi nim kim tra sau tng hp v ti sao phi thc hin kim tra sau tng hp. Cu hai 1. Trnh by thut ton cng Carry look ahead adder, so snh vi thut ton cng ni tip. 2. Trnh by thut ton cng dng 1 full_adder, u nhc im ca thut ton ny.

3. Trnh by cu trc thanh ghi dch, thut ton dch khng dng ton t dch, v d ng dng thanh ghi dch. 4. Trnh by thut ton v cu trc khi nhn cng dch tri cho s khng du. 5. Trnh by thut ton v cu trc khi nhn cng dch phi cho s khng du, so snh vi khi nhn cng dch tri. 6. Trnh by thut ton v cu trc khi nhn s c du dng m ha BOOTH c s 2. 7. Trnh by thut ton v cu trc khi nhn s c du dng m ha BOOTH c s 4, so snh vi cc thut ton nhn thng thng. 8. Trnh by thut ton v cu trc khi chia s khng du phc hi phn d. 9. Trnh by thut ton v cu trc khi chia s khng du khng phc hi phn d. 10. Trnh by thut ton v cu trc khi chia s c du. 11. Trnh by thut ton xy dng FIFO v LIFO trn c s Dual-port RAM. Cu 3 : bi tp 1. Thit k full_adder trn VHDL, trn c s thit k b cng 4 bit 2. Thit k b gii m nh phn 3_to_8 c u ra thun, nghch. 3. Thit b chn knh 4 u vo 1 u ra MUX4_1. 4. Thit b phn knh 1 u vo 4 u ra DEMUX1_4. 5. Thit k b cng/ tr 4 bit s dng ton t cng trn VHDL. 6. Thit k cc b chuyn i m t NBCD 7-SEG(LED 7 on), h tr cng LamTest, khi cng ny c gi tr bng 1, tt c n phi sng khng ph thuc m u NBCD u vo.7. Thit k cc flip-flop ng b D, T. 8. Thit k cc flip-flop ng b RS, JK. 9. Thit k b m nh phn thun ng b, RESET khng ng b, c tn hiu ENABLE, Kd = 16, trn VHDL. 10. Thit k trn VHDL thanh ghi dch tri qua phi 32-bit, s lng bit dch l mt s nguyn t 1-31 trn VHDL. 11. Thit k trn VHDL b m thun, Kd = 8 ng b, RESET khng ng b v c tn hiu ENABLE. 12. Thit k trn VHDL b m nghch, Kd = 8 ng b, RESET khng ng b v c tn hiu ENABLE. 13. Thit k b m thp phn ng b, RESET khng ng b, c tn hiu ENABLE. 14. S dng b m n 25 thit k b chia tn t tn s 50Hz thnh 1Hz, tn hiu tn s a ra c dng i xng. 15. Thit k khi gii m u tin, u vo l chui 4 bit u ra l m nh phn 3 bit th hin v tr u tin t tri qua phi xut hin bit 1. Trng hp khng c bt 1, th u ra nhn gi tr (100) 16. Thit k khi gii m u tin, u vo l chui 4 bit u ra l m nh phn 3 bit th hin v tr u tin t tri qua phi xut hin bit 0. Trng hp khng c bt 0, th u ra nhn gi tr (100)