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Mc lc
1
2
3
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Bt in
PROGRAM
RUN
PARAMETER
SET CLOCK
SET CLOCK
SUMMER TIME
SET CLOCK
YY/MM/DD
00/01/01
00:03 (SA)
Trang 3
SET CLOCK
YY/MM/DD
00/04/01
11:35 (SU)
SET CLOCK
SET ?
OK/ESC
11:35 (SU)
Trang 4
3.1
u ni ngun cp
Chng
trnh bc
thang
Ti
3.2-
Xo chng trnh
Cn phi xo chng trnh trong b nh ca ZEN trc khi vit 1 chng trnh
mi. Khi dng lnh DELETE PROG xo, ch c phn chng trnh l b
xo, cn cc phn khc nh ngn ng hin th , thi gian ngy thng v cc
thit lp khc khng b nh hng.
Cn phi chuyn ZEN v ch STOP (ch dng) mi xo c chng
trnh.
PROGRAM
RUN
PARAMETER
SET CLOCK
EDIT PROG
DELETE PROG
DELETE PROG
DELETE ?
OK/ESC
EDIT PROG
DELETE PROG
Trang 5
3.3-
PROGRAM
RUN
PARAMETER
SET CLOCK
EDIT PROG
DELETE PROG
Chng trnh v d mu
Hin th khi c nhiu dng chng trnh di. Dng ph m mi tn xung hin th tip
Hin th khi c nhiu dng chng trnh trn. Dng ph m mi tn ln hin th tip
Trang 6
a- Vit u vo cho I0
Bm OK hin th v tr vit ban u (u
vo NO a ch I0) v chuyn con tr nhp
nhy v v tr Bit type. Dng cc ph m mi
tn ln xung la chn loi ca bit (Bit
type). Dng ph m mi tn
chuyn
sang v tr a ch bit v bm cc ph m mi
tn ln xung thay i a ch bit
Bm nt OK hai ln hon tt vic nhp
a ch I0. Con tr gi y chuyn sang v tr
nhp tip theo.
Bm OK hin th li tip im u vo NO
v a ch I0
Bm ALT chuyn sang loi tip im l
NC (Bm ALT chuyn v loi tip im l
NO)
Bm ph m mi tn phi chuyn con tr
nhy sang v tr a ch bit v dng ph m mi
tn ln UP chuyn thnh 1
Bm OK chuyn con tr sang v tr nhp tip
theo. ng ni (connection line) s t ng
c ni gia tip im I0 v tip im I1
Trang 7
V cc u vo
K hiu cc u vo
M t
Cc bit u vo ca module c CPU
Cc bit u ra ca module c CPU
Cc bit u vo ca module m rng
Cc bit u ra ca module m rng
Cc bit t do dng trong chng trnh
(work bit)
Cc bit t do dng trong chng trnh c
lu trng thi (holding bit)
Cc bit bo trng thi cc nt bm
Loi a ch bit v s
I0 --> I5 (6 u)
Q0 --> Q3 (4 u)
X0 --> XB (12 u) (1)
Y0 --> YB (12 u)(1)
M0 --> QF (16 bit)
H0 --> HF (16 bit)
B0 --> B7 (8 bit) (2)
M t
Timer tr thng thng
Timer c lu trng thi khi mt in
(Holding Timer)
Timer tun (Weekly Timer)
Timer ngy thng (Calendar Timer)
Counter
B so snh tng t (Analog
Comparator)
B so snh thng
Loi a ch bit v s
T0 --> T7 (8 timer)
#0 --> #3 (4 timer)
@0 --> @7 (8 timer) (1)
*0 --> *7 (8 timer) (1)
C0 --> C7 (8 counter)
A0-A3 (4 b so snh) (2)
P0-PF (16 b so snh)
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V u ra
Cc vng nh cho u ra
K hiu
Q
Y
M
H
3.1.1.1.1.1 M t
Cc bit u ra ca module c CPU
Cc bit u ra ca module m rng
Cc bit t do dng trong chng trnh
(work bit)
Cc bit t do dng trong chng trnh c
lu trng thi (holding bit)
Loi a ch bit v s
Q0 --> Q3 (4 u)
Y0 --> YB (12 u)(1)
M0 --> MF (16 bit)
H0 --> HF (16 bit)
K hiu
[
S
M t
Hot ng ca u ra output s nh bnh thng
Khi c bt bi lnh output kiu S (Set) ny, bit u ra s gi
nguyn trng thi bt k c sau khi cc bit i trc l OFF v ch b
tt vi lnh output kiu R
Khi c tt bi lnh output kiu R (Reset) ny, bit u ra s gi
nguyn trng thi tt k c sau khi cc bit i trc l OFF v ch
c bt vi lnh output kiu S
Mi khi lnh output kiu A (Alternate) c thc hin bit output s
chuyn sang trng thi ngc li, v d khi ang ON s chuyn
sang OFF v ngc li
Q0 bt v tt
khi I0 bt v tt
Q1 bt v vn
ON khi I1 bt ri
tt
Q2 tt khi I2 bt
Trang 9
Q3 chuyn
trng thi gia
ON v OFF mi
khi I3 bt
K hiu
T
#
M t
Timer
Timer c lu trng
thi khi mt in
(Holding Timer)
Counter
Loi a ch bit v s
T0 --> T7 (8 timer)
#0 --> #3 (4 timer)
C0 --> C7 (8 counter)
Loi u ra
T: u vo k ch
hot timer
R: u vo
Reset cho timer
C: u vo m
cho counter
D: Chiu m
cho counter
R: u vo
reset cho
counter
D
Ch :
- Khng vit chng trnh vi cc ng ni to thnh vng k n. Chng trnh
c th hot ng khng ng nu v nh vy
- Lun lun bm ESC quay tr v mn hnh Menu. Nu khng quay tr v
mn hnh Menu trc khi tt in, cc thit lp v chng trnh s b mt.
Trang 11
MONITOR
STOP
PARAMETER
SET CLOCK
Trang 12
Bm ESC
chuyn sang
mn hnh ch nh
PROGRAM
STOP
PARAMETER
SET CLOCK
Q0 s ON khi
I0 ln ON
Q0 s vn ON
k c khi I0 v
OFF
Chn Monitor
ch RUN
Bm ph m OK
chuyn sang mn
hnh theo di
chng trnh bc
thang
Q0 s ON khi I0
ln ON. Khi bit
ny ON, cc
ng ni ng
v ngang s
m ln
Q0 s v OFF
khi I1 bt ln
ON
Thay i u vo
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5.2
5.3
Xo cc u vo, u ra v cc ng ni
Bm DEL xo u vo v xo lun
ng ni i cng
V d: Xo cc ng ni thng ng
Di chuyn con tr ti v tr ca u vo bn
phi ca ng ni ny. Bm ALT
chuyn sang ch v ng ni. Con tr
chuyn sang hnh mi tn
Bm DEL xo
5.4
Chn cc dng
Mt dng mi s c chn ti y
Bm ALT chn ti y
Dng trng
Mt dng mi s c chn ti y
5.5
Xo cc dng trng
Dng ny s c xo
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Holding timer
6.1
Loi timer
K hiu
Hot ng
Loi ng
dng
ch nh
On
DELAY
timer
Bt sau 1
khong thi
gian t trc
sau khi u
vo trigger ln
ON
Tr thi
gian
OFF
DELAY
timer
t thi
gian cho
chiu sng
v qut
thng gi
One-shot
pulse
timer
Vn ON
trong khi u
vo trigger ON
v tt sau 1
khong thi
gian t trc
sau khi u
vo trigger v
OFF
Vn ON
trong 1 khong
thi gian t
trc khi u
vo trigger bt
ln ON
Flashing
pulse
timer
Bt v tt lp i
lp li trong
khong chu k
t trc trong
khi u vo
trigger ON
Mch bo
ng bo
ci v n
nhp nhy
Trang 16
6.2
Loi timer
Hot ng
Loi ng
dng
ch nh
Tr thi
gian c
yu cu
tip tc
tr li sau
khi mt
in
On
DELAY
timer
Bt sau 1
khong
thi gian
t trc
sau khi
u vo
trigger ln
ON
6.3
Timer address
( a ch timer)
Trigger input
Reset input
Timer bit
6.4
T0 n T7 hoc #0 n #3
T (TRG)
Trang 17
Timer Type
Sai s: 0 n 10ms
Sai s: 0 n 1s
Sai s: 0 n 1 pht
Monitor Enabled/Disabled
A
D
6.5
7 S dng b m (Counter)
C th s dng ti 8 b m ch m tng hay m gim. Gi tr hin
hnh ca counter (Present Value - PV) v trng thi ca u ra counter c
lu c khi ch hot ng ca ZEN thay i hay khi mt in.
Hot ng
Bit u ra ca counter (counter bit) bt ln ON khi gi tr m (hay gi tr hin
hnh Present Value PV) vt qu gi tr t (set value - SV) (PVSV). Gi tr
m s quay v 0 v bit u ra tt khi u vo reset bt ln ON. Cc u vo
m b b qua trong khi u vo reset ON.
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7.1
Counter address
( a ch counter)
Counter input
(u vo m)
Counter direction
input
(Xc nh chiu
m)
Reset input
(Reset)
Timer bit
7.2
C0 n C7
C (CNT)
D (DIR)
R (RES)
Trang 19
Set Value
0001 n 9999 ln
A
Cc thng s c th c theo di v thay
Monitor
i
enabled/disabled D
Cc thng s khng c ph p theo di v
thay i
7.3
Ch :
1. xo gi tr hin ti ca counter (PV) v bit u ra ca counter
(counter bit) khi ngt in hay khi thay i ch hot ng,
hy to 1 mch xo (reset) lc bt u thc hin chng trnh.
Sau y l 1 v d:
Thi
gian
Trang 20
8.1
8.2
Set Value
Day
(ngy)
0001 n 9999 ln
Start day
T Ch Nht n Th By
(Sun/Mon/Tues/Wed/Thurs/Fri/Sat)
Stop day
T Ch Nht n Th By
(Sun/Mon/Tues/Wed/Thurs/Fri/Sat)
Time
Start time
00:00 n 23:59
(thi gian)
Stop time
00:00 n 23:59
A
Cc thng s c th c theo di v
Monitor
thay i
enabled/disabled D
Cc thng s khng c ph p theo
di v thay i
Ch : Khi con tr nm start day (ngy bt), bm
ri bm / t
ngy tt (stop day). Nu stop day khng c t, timer s ch hot ng theo
thi gian t.
Quan h gia thi gian v ngy bt v tt (Start-Stop Day/Time)
Thng s t
Khi Start day trc
Stop day
Khi Start day sau
Start-Stop
Stop day
Day
Khi Start day trng
(ngy)
vi Stop day
Khi Stop day khng
c t
V d
MO-FR
FR-MO
MO-MO
FR-
Trang 21
Hot ng
Hot ng t Th Hai n
Th Su hng tun
Hot ng t Th Su hng
tun n Th Hai tun sau
Hot ng bt k ngy
trong tun
Hot ng ch vo Th Su
hng tun
Time
(thi gian)
8.3
ON: 08:00
OFF: 17:00
ON: 18:00
OFF: 07:00
ON: 18:00
OFF: 18:00
Hot ng t 08:00 n
17:00 hng ngy
Hot ng t 18:00 n
07:00 ngy hm sau
Hot ng bt k thi gian
Ngy hin ti
Thi gian hin ti
Trang 22
9.2
Start Date
(ngy bt)
Stop Date
(ngy tt)
T 1/1 n 31/12
T 1/1 n 31/12
A
Monitor
enabled/disabled D
Start-Stop Day
(ngy)
Khi Start
date trc
Stop date
Khi Start
date sau
Stop date
Khi Start
date trng
vi Stop
date
V d
ON: 04/01
OFF: 09/01
Hot ng
Hot ng t 1/4 n 1/9
ON: 04/01
OFF: 02/01
ON: 02/01
OFF: 02/01
9.3
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Hot ng
V d 1
Khi u vo analog I4 5.2V
V d 2
Khi u vo analog I5 I4
u ra ca b comparator s bt ln u ra ca b comparator s bt ln ON
khi in p u vo 2 cao hn u vo 1
ON khi in p u vo 1 t n
5,2V hoc cao hn
Ch :
Khng c a t n hiu in p m vo cc u vo I4 v I5. Lm nh
vy c th lm hng cc mch bn trong ZEN.
10.1 Thit lp trong mn hnh sa chng trnh bc thang
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V d 1
Khi so snh u vo analog vi 1
hng s (v d I4 hng s)
V d 2
Khi so snh cc u vo analog ( v
d I5 I4)
D liu so snh 1
D liu so snh 1
Ton t so snh
Ton t so snh
D liu so snh 2
D liu so snh 2
Analog Comparator
address
D liu so snh
T A0 n A3
1
2
Ton t so snh
A
Monitor
enabled/disabled
I4: u vo analog 1
I5: u vo analog 2
I5: u vo analog 2
Hng s: t 00.0 n 10.5
u ra ca b so snh (analog
comparator bit) s bt khi d liu so snh
1 d liu so snh 2
u ra ca b so snh (analog
comparator bit) s bt khi d liu so snh
1 d liu so snh 2
Cc thng s c th c theo di v
thay i
Cc thng s khng c ph p theo di
v thay i
Trang 25
V d 2
Khi so snh counter C1 counter C2
Trang 26
V d 2
Loi so snh
D liu so snh 1
Loi so snh
D liu so snh 1
Ton t so snh
Ton t so snh
D liu so snh 2
D liu so snh 2
Loi so snh
D liu so snh
Ton t so snh
Monitor
enabled/disabled
T: Timer
#: Holding timer
C: Counter
1
T: T0
T7
#: #0
#7
C: C0
C7
2
T: T0
T7
#: #0
#7
C: C0
C7
Hng s:
- t 00.0 n 99.99 khi loi so snh l T hoc
#
- t 0000 n 9999 khi loi so snh l C
u ra ca b so snh (comparator bit) s bt khi
Trang 27
Ghi ch:
- Bm ALT chuyn d liu so snh gia a ch timer/counter v hng
s
- n v thi gian c xc nh nh sau khi loi so snh l Timer hay
Holding timer:
o Khi hng s c t cho d liu so snh 2, n v thi gian
c t ng nh ph hp vi n v thi gian ca timer trong
d liu so snh 1
o Cc n v thi gian c t ng chnh nh ph hp khi cc
n v thi gian l khc nhau gia timer trong trong d liu so
snh 1 v 2.
V d 1
V d 2
Trang 28
Backlight/Display L0
Display start
position
(V tr bt u
hin th )
Display object
CHR
DAT
CLK
I4-I5
T0-T7
#0-#3
C0-C7
A
Monitor
enabled/disabled D
Cc k t (ti a 13 k t ch s v k hiu)
Thng/Ngy (5 k t: / )
Gi/pht (5 k t: : )
Gi tr analog (4 k t: . )
Gi tr hin ti ca timer (5 k t: . )
Gi tr hin ti ca timer (5 k t: . )
Gi tr hin ti ca counter (4 k t:
)
Cc thng s c th c theo di v thay
i
Cc thng s khng c ph p theo di v
thay i
Ch :
(1) Khi L0 hay L1 c chn tt chc nng hin th trang thng
bo, trang hin th thng bo s khng c hin th t ng.
Dng cc ph m chuyn ti trang hin th hot ng.
(2) Khi L2 hay L3 c chn bt chc nng hin th trang thng
bo, trang hin th thng bo s c hin th t ng hin th
d liu t. Mn hnh ch nh s khng c hin th . hin
th mn hnh ch nh, phi chuyn CPU v ch STOP.
Trang 29
K t s oc chn
K t trc v sau k t s oc chn
Dng ph m
chuyn v tr t k t hin th
sang phi. Dng ph m chuyn v tr t k t
hin th sang tri
Trang 30
S dng bit nt bm
Cc nt bm c th c dng nh cc ph m n xo gi tr hin hnh ca
counter hay holding bit.
V d:
Bm DEL+ALT ng thi trong khi ang chy reset
counter C2 v 0 v bit H5 v OFF chng trnh bn.
Ch :
- Cc nt bm c th c dng nh l nt hot ng cho mi mn hnh.
Khi dng cc nt nh l cc bit nt bm, hy thc hin cc la chn tu
theo tnh trng ca mn hnh
- Cc nt c th c dng cho cc hot ng h thng ca ZEN nh
la chn menu, bt k bit nt bm c ang c s dng khng.
Khi 1 nt bm c nhn cho cc hot ng h thng ca ZEN, bit
tng ng cng bt. Hy m bo l h thng khng b nh hng
trc khi bm cc nt ny
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OMRON, 2001
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form, or by any means, mechanical, electronic, photocopying,
recording, or otherwise, without the prior written permission of OMRON.
No patent liability is assumed with respect to the use of the information contained herein.
Moreover, because OMRON is constantly striving to improve its high-quality products, the
information contained in this manual is subject to change without notice. Every precaution
has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting
from the use of the information contained in this publication.
Vn phng i din:
TP H Ch Minh:
99 Nguyn Th Minh Khai, Q1
Tel : 830 1105 / 839 6666
Fax : 830 1279.
E-mail : OMRONHCM@HCM.VNN.VN
Revision: 1 7/01
Produced: TNBINH
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