Nhim v n mn hc

ti:

iu khin lp trnh bng plc cho h thng ng thng bia t ng

Gio vin hng dn : Sinh vin thc hin :

Ni dung ca phn thuyt minh: 1. Gii thiu chung v iu khin lp trnh bng plc 2. Gii thiu v PLC - S7-200 ca SIEMEN 3. Tm hiu tp lnh PLC ca S7-200 4. Vit chng trnh iu khin ng thng bia t ng 5. Chy th chng trnh trn phn mm m phng Simulator ca Siemen. Cc bn v: (trong thuyt minh) 1. Bn v lu gii thut m ho (bng li) 2. Bn v mch kt ni ca thit b iu khin 3. Bn v mch ng lc. 4. Bn v mch iu khin

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Mc lc
Li ni u Chng I. Gii thiu chung v iu khin lp trnh bng plc Chng II. Gii thiu v PLC - S7-200 ca SIEMEN 2.1 Gii thiu thit b iu khin lp trnh 2.2 Tp lnh c bn dng c thit b iu khin kh trnh PLC S7-200 2.3 S kt ni vo ra ca thit b PLC S7-200 2.4 Chng trnh iu khin Chng III. Tm hiu tp lnh PLC ca S7-200 3.1 S mch ng lc 3.2 S mch iu khin Chng IV. Vit chng trnh iu khin cho ng thng bia t ng. 4.1 Thit b dng trong h thng 4.2 Nhng ch khi vn hnh v thay th, sa cha kt lun. Chng V. Chy th chng trnh trn phn mm m phng Simulator ca Siemen.

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Li ni u
Hin nay trong cng nghip hin i ho t nc, yu cu ng dng t ng ho ngy cng cao vo trong i sng sinh hot, sn xut (yu cu iu khin t ng, linh hot, tin li, gn nh ). Mt khc nh cng ngh thng tin, cng ngh in t pht trin nhanh chng lm xut hin mt loi thit b iu khin kh trnh PLC. thc hin cng vic mt cch khoa hc nhm t c s lng sn phm ln, nhanh m li tin li v kinh t. Cc Cng ty, x nghip sn xut thng s dng cng ngh lp trnh PLC s dng cc loi phn mm t ng. Dy chuyn sn xut t ng PLC gim sc lao ng ca cng nhn m sn xut li t hiu qu cao p ng kp thi cho i sng x hi. Qua bi tp ca n mn hc ti s gii thiu v lp trnh PLC v ng dng n vo sn xut ng gi sn phm bng hai bng ti ca cng ty,x nghip sn xut. Trong thc t lp trnh PLC c th c s dng nhiu hng phn mm sn xut nh l hng Siemens-c, omron-Nht bn, Goldstar-Hn Quc, tu thuc vo i tc, tim lc ca Cng ty, x nghip s dng cng ngh Trn y l mt phn nh v chng trnh iu khin vit cho h thng iu khin ng thng bia t ng. Trong qu trnh thc hin chng trnh cn gp nhiu kh khn l ti liu tham kho cho vn ny ang rt t,v hn hp, n lin quan n nhiu vn nh phn c trong dy chuyn. Mc d rt c gng nhng kh nng, thi gian c hn v kinh nghim cha nhiu nn khng th trnh khi nhng sai st rt mong s ng gp kin b sung ca cc thy c gio, cc qu bn c cng nh cc bn ng nghip n ny c hon thin hn. ca hng.

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Chng I: Gii thiu chung v iu khin lp trnh bng plc 1. Gii thiu phn cng ca b iu khin kh trnh PLC. PLC vit tt ca Program Mable Logic Controller l thit b iu khin logic kh trnh, cho php thc hin linh hot cc thut ton iu khin logic thng qua mt ngn ng lp trnh, b iu khin tho mn cc yu cu: - Lp trnh d dng v ngn ng lp trnh d hc. - Gn nh, d dng tu sa, bo qun. - Dung lng b nh ln, c th cha c nhng chng trnh phc tp. - Hon ton tin cy trong mi trng cng nghip. - Giao tip vi cc thit b thng tin, my tnh, ni mng cc modul m rng. - Gi c ph hp. B iu khin lp trnh PLC c thit k nhm thay th phng php iu khin truyn thng dng rle v thit b cng knh, n to ra mt kh nng iu khin thit b d dng v linh hot da trn vic lp trnh trn cc lnh logic c bn. PLC cn thc hin cc tc v nh th v m lm tng kh nng iu khin, thc hin logic c lp trong chng trnh v a ra tn hiu iu khin cho thit b bn ngoi tng ng. C s ca vic s dng PLC: Trong cng nghip trc y, cc h thng iu khin s thng c cu to trn c s cc rle v cc mch logic in t kt ni vi nhau theo nguyn l lm vic ca h thng. iu c ngha l: Quan h gia cc bin vo v cc bin ra tun theo mt hm s, m hm s ny chnh c xc nh bi lut kt ni gia cc phn t logic. (y1, y2,... yn ) = f (x1, x2,... xn ) Nh vy i vi mc ch iu khin xc nh th hm f c nh. i vi cc h thng lm vic n gin v lm vic c lp th vic s dng cc phn t c sn lin kt cng vi nhau c nhiu u im v gi thnh. Tuy nhin trong cc h thng iu khin phc tp nhiu chc nng th nhng cu trc theo kiu cng c nhiu nhc im nh: - H thng cng knh, u ni phc tp dn n tin cy km. - Trng hp cn thay i chc nng ca h thng hoc sa cha cc h hng th phi dng c h thng u ni... Hin nay vi s pht trin ca ngnh cng nghip in t cho php ch to cc h vi x l lin tip, da trn c s ca b vi x l, cc b iu khin logic c kh nng
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lp trnh c (PLC) ra i, cho php khc phc c rt nhiu nhc im ca cc h iu khin lin kt cng trc y, vic dng PLC tr nn rt ph bin trong cng nghip t ng ho. C th lit k cc u im chnh ca vic s dng PLC gm: - Gim bt vic u ni dy khi thit k h thng, gi tr logic ca nhim v iu khin c thc hin trong chng trnh thay cho vic u ni dy. - Tnh mm do cao trong h thng. - B nh: - B nh vo ra: B nh thi B m vora Khi vi x l trung tm + H iu hnh B m Bit c Bus ca PLC

Cng vo ra Onboard

Qun l ghp ni Cng ngt v m tc cao

Hnh 2.1: Nguyn l chung v cu trc ca b PLC Trng thi tn hiu vo c nhn bit v cha trong b nh, ni PLC thc hin cc lnh logic c lp trnh x l cc tn hiu vo my v to ra cc tn hiu ra iu khin cc thit b lin quan. * Cu trc PLC bao gm: i vi PLC c nh cc b phn thng c kt hp thnh mt khi. Cng c mt s hng thit k PLC thnh tng m un ngi s dng c th la chn cu hnh PLC cho ph hp m t tn km nht, ng thi p ng c yu cu ng dng. Mt b PLC c th c nhiu m un nhng thnh phn c bn nht ca phn cng trong b PLC bao gi cng c cc khi sau:
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Ngun cung cp + -

Nh chng trnh

M un nhp d liu

M un xut d liu

Tn hiu vo

C cu chp hnh

Hnh 2.2: S cu trc phn cng ca b lp trnh PLC Da vo s khi ta thy PLC gm c 4 khi chnh l: Khi ngun, khi vi x l b nh, khi u vo, khi u ra. Thng thng cc tn hiu xut nhp u dng s (1- 0), cn nu tn hiu l dng lin tc th ta cn gn cc khi xut nhp dng lin tc (Analog). a. M un ngun: (Moudule) L khi chc nng dng cung cp ngun v n nh in p cho PLC hot ng. Trong cng nghip ngi ta thng dng in p 24V mt chiu. Tuy nhin cng c b PLC s dng in p 220V xoay chiu. b. M un CPU (Centrol rocessor Unit module): Bao gm b vi x l v b nh: * B vi x l (CPU): CPU l mt b no ca PLC. N iu khin v kim sot tt c mi hot ng bn trong ca PLC. N thc hin nhng lnh c chng trnh ho lu tr bn trong b nh. Mt h thng BUS mang thng tin n v kt ni CPU, b nh v b xut nhp cng chu s iu khin ca CPU. CPU c cung cp bi mt tn s
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ng b do tinh th thch anh bn ngoi hay mt b giao ng RC. Mch dao ng ny c nhim v to ra tn s dao ng t 118 MHZ. Tu thuc vo b vi x l c s dng v phm vi s dng. Mt CPU bao gm 3 thnh phn ring bit sau: + B iu khin (CU Control Unit) gm khi son lnh v ngn xp c nhim v ly lnh ra t b nh v xc nh kiu lnh. + B l lun v s hc (AIU) thc hin cc php ton s hc v logic nh: cng tr, AND, OR, NOT, + B nh c tc cao, kch thc nh lu cc kt qu tm thi v cc thng tin iu khin. * B nh: Bao gm b nh cha chng trnh v b nh d liu, .n v nh nht ca b nh l bt c gi tr 1 (hoc 0). Nhiu bt hp theo hng v ct to thnh mt khi b nh. Ni dung b nh c th c ra hoc ghi vo. Mi bt c nh ngha mt a ch ring b nh d qun l. C hai loi b nh nh sau: - B nh RAM (Random Access Memory): Ram l b nh chnh trong mi my tnh. K c PLC. B nh RAM c li l dung lng ln nhng gi r. Ram l loi b nh c th c ghi chng trnh mt cch d dng. Tuy nhin d liu trong Ram s b xo sch khi c s c v in. V vy mun lu tr chng trnh iu khin tron b nh Ram th ngi ta dng phng php nui b nh Ram bng 1 ngun pin. Nu cn lu trd di th ta dng loi pin c cht lng cao... - B nh ROM (Read Only Memory): Rom l b nh ch c. B nh ny c c tnh tri ngc vi b nh Ram l rt kh xo, nn khi c s c v in th ni dung chng trnh vn cn trong b nh. Nhng hin ny ngi ta c th thay i ni dung ca n. Tu thuc vo cch to ni dung, cch xo ni dung, cch np ni dung mi vo n m ta c cc loi b nh Rom khc nhau nh: PROM, EPROM, RPROM, EEPROM, EAROM. in hnh y ta xt 2 loi b nh ROM c dng rng ri trong cc PLC l EPROM v EEPROM. + EPROM (Erasable Programmable Read Only Memory): B nh Rom c th xo ni dung chng trnh. N c xo bng tia cc tm, sau khi ni dung c xo th

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ngi ta dng mt thit b c bit ghi ni dung chng trnh mi vo trong Rom. Loi ny rt phc tp v phi dng thit b t tin. + EEPROM (Electrically Erasable Programmble Read Only Memory): B nh loi ny cng ging nh b nh EPROM nhng phng thc xo ni dung chng trnh n gin hn. Tc l n c xo bng in v vic np mt chng trnh mi cho n cng n gin. Ngoi hai loi trn trong cc PLC ngi ta cn thng dng FLASH EROM. i vi nhng b iu khin logic theo chng trnh thuc loi ln c th c nhiu Module CPU nhm tng tc x l. c. M un nhp: (Input Module) Tn hiu vo: Cc tn hiu u vo nhn cc thng tin iu khin bn ngoi dng tn hiu Logic hoc tn hiu tng t. Cc tn hiu Lgic c th t cc nt n iu khin cc cng tc hnh trnh, tn hiu bo ng, cc tn hiu ca cc quy trnh cng ngh, Cc tn hiu tng t a vo ca PLC c th l tn hiu in p t cc cn nhit iu chnh nhit cho mt l no hoc tn hiu t my pht tc, cm bin. Cc cm bin (Sensors) c ni vi Module ng vo ca PLC. Thng thng mt Module nhp c 8 ng vo hoc 16 ng vo hoc c th hn na tu thuc vo yu cu ca ngi s dng m chn cho ph hp. i vi nhng ng dng nh th cn khong 16 ng vo, ng dng trung bnh th cn khong 80 ng vo, ng dng c dng cc cun dy Rle cho ng vo. in p hot ng a vo cc cun dy ny thng vo khong 24 VDC vi dng vo vi mA (6mA), rt b so vi dng tiu th qua cun dy trong rle thc t. Cng c PLC hot ng vi in p 220V AC. Mc d in p cao nh vy nhng vn m bo an ton cho mch in t ca PLC v ngi ta s dng cc linh kin cch ly (Optocoupler). Theo tiu chun cng nghip vi in p 24 VDC, ngi ta quy nh: - in p t 0 5 VDC th hin logic 0 ng vo - in p t 11 30 VDC th hin logic 1 ng vo d. M un xut (Output Module): Trong PLC th Module xut cng ht sc quan trng khng km module nhp. N c th c 8 hoc 16 ng ra m trn mt Module xut, do vy ngi s dng c th kt ni nhiu module li vi nhau c s ng ra ph hp. i vi nhng ng dng nh th cn 16 ng ra. Nhng ng dng ln hn c th dng ti 26 hoc 256 ng ra. Cng
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ging nh Module nhp th cc ng ra ca Module xut l cc tip im ca rle, kh nng chu ti ln 220V/1A. Nu mun khng ch ph ti cng sut ln th thng qua cc thit b trung gian nh: CTT. Aptomat. Triac Ngoi ra cn c PLC vi ng ra l tn hiu in: Logic 0 ng vi in p t 0 0,8V v logic 1 ng vi in p t 12 28V vi dng ra c khi ln ti 300mA. Di in p cp ngun t 12V 28V. PLC thc hin chng trnh: PLC thc hin chng trnh theo chu trnh lp. Mi vng lp c gi l vng qut (scan). Bt u mi vng qut l vic qut cc tn hiu vo. Trong qu trnh qut ny trng thi hin thi ca mi tn hiu vo c cha trong bng nh. Vic qut cc u vo ny rt nhanh, vic qut ph thuc vo cc module vo, xung nhp cng nh cc c tnh ring ca mi loi CPU thc hin chng trnh s dng. Cng vic ny thc hin t lnh u tin n lnh cui cng ca chng trnh (lnh MEND). Nh vy thi gian thc hin chng trnh s ph thuc vo di chng trnh, phc tp ca cc lnh, v c tnh k thut ca tng loi CPU

Chuyn d liu t u ra Q ti cng ra

Chuyn d liu t u cng vo ti u vo I

Truyn thng v kim tra b nh

Thc hin chng trnh

Hnh 2.4: Chu k thc hin vng qut ca CPU trong b PLC Trong qu trnh thc hin chng trnh CPU lun lm vic vi bng nh ra. Tip theo ca vic qut chng trnh l truyn thng ni b v t kim tra li. Vng qut c kt thc bng giai on chuyn d liu t b m o ra ngoi vi. Nhng trng hp cn thit phi cp nht module ra ngay trong qu trnh thc hin chng trnh. Cc PLC hin i s c sn cc lnh thc hin iu ny. Tp lnh ca PLC cha cc lnh ra trc tip c bit, lnh ny s tm thi dng hot ng bnh thng ca chng trnh cp nht module ra, sau s quay li thc hin chng trnh. Thi gian cn thit
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PLC thc hin c mt vng qut gi l thi gian vng qut (Scan time). Thi gian vng qut khng c nh, tc l khng phi vng qut no cng c thc hin trong mt khong thi gian nh nhau. C vng qut c thc hin lu, c vng qut c thc hin nhanh tu thuc vo s lnh trong chng trnh c thc hin, vo khi lng d liu c truyn thng trong vng qut . Mt vng qut chim thi gian qut ngn th chng trnh iu khin c thc hin cng nhanh. Ti thi im thc hin lnh vo/ra, thng thng lnh khng lm vic trc tip vi cng vo ra m ch thng qua b m o ca cng trong vng nh tham s. Vic truyn thng gia b m o vi ngoi vi trong cc giai on 1 v 4 do CPU qun l. Khi gp lnh vo/ra ngay lp tc th h thng s cho dng mi cng vic khc, ngay c chng trnh x l ngt, thc hin lnh ny mt cch trc tip vi cng vo/ra. Nu s dng cc ch ngt, chng trnh con tng ng vi tng tn hiu ngt c son tho v ci t nh mt b phn ca chng trnh. Chng trnh x l ngt ch c thc hin trong vng qut khi xut hin tn hiu bo ngt v c th xy ra bt c im no trong vng qut.

chng 2: Gii thiu v PLC - S7-200 ca SIEMEN

* Cu trc b nh PLC:

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10

B iu khin lp trnh S7-200 c chia thnh 4 vng nh. Vi 1 t c nhim v duy tr d liu trong thi gian nht nh khi mt ngun b nh S7-200 c tnh nng ng cao, c v ghi trong phm vi ton vng loi tr cc bt nh c bit SM ( Special Memory) ch c th truy nhp c.

Vng chng trnh

Chng trnh Tham s D liu EEPROM

Chng trnh Tham s D liu B nh ngoi

Vng tham s Vng d liu Vng i tng

Hnh 2.3: B nh trong v ngoi ca S7-200 * Vng chng trnh: L vng b nh c s dng lu tr cc lnh chng trnh vng ny thuc b nh trong c v ghi c * Vng tham s: L vng lu gi cc tham s nh: T kho, a ch trm .cng ging nh vng chng trnh thuc b nh trong c v ghi c. * Vng d liu: L vng nh ng c s dng ct cc d liu ca chng trnh bao gm cc kt qu cc php tnh n c truy cp theo tng bit tng byte vng ny c chia thnh nhng vng nh vi cc cng dng khc nhau. Vng I (Input image register): L vng nh gm 16 byte I (c/ghi): I.O I.15 Vng Q (Output image register): L vng nh gm 16 byte Q (c/ghi): Q.15 Vng M (Internal memory bits): l vng nh gm c 32 byte M (c/ghi): M.31 Vng V (Variable memory): L vng nh gm c 10240 byte V (c/ghi): V.10239 Vng SM: (Special memory): L vng nh gm: V.O M.O Q.O

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11

- 194 byte ca CPU chia lm 2 phn: SM0 SM29 ch c v SM30 SM194 c/ghi. - SM200-SM549 c/ghi ca cc module m rng * Vng i tng: L timer (nh th), counter (b m) tc cao v cc cng vo/ra tng t c t trong vng nh cui cng vng ny khng thuc kiu non volatile nhng c ghi c. - Timer (b nh th): c/ghi T0 T255 - Counter (b m): c/ghi C0 C255 - B m vo analog (c): AIW0 AIW30 - B m ra analog (ghi): AQW0 AQW30 - Accumulator (thanh ghi): AC0 AC3 - B m tc cao: HSC0 HSC5 Tt c cc min ny u c th truy nhp c theo tng bit, tng byte, tng t n (word 2byte), t kp (Double word). a. Cu trc chng trnh: Chng trnh cho S7-200 phi c cu trc bao gm chng trnh chnh (main program) sau n cc chng trnh con v cc chng trnh x l ngt. Chng trnh chnh c kt thc bng lnh kt thc chng trnh (MEND). Chng trnh con l mt b phn ca chng trnh. Cc chng trnh con phI c vit sau lnh kt thc chng trnh chnh l mnh (MEND). Cc chng trnh x l ngt l mt b phn ca chng trnh, nu cn s dng chng trnh x l ngt phi vit sau lnh kt thc MEND. Cc chng trnh con c nhm li thnh mt nhm ngay sau chng trnh chnh, sau n ngay cc chng trnh x l ngt bng cch vit nh vy cu trc chng trnh c r rng v thun tin hn trong vic c chng trnh c th trn ln cc chng trnh con v chng trnh x l ngt ng sau chng trnh chnh.

Main program . .
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Thc hin trong 1 vng qut

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12

. MEND

SBR (n) {n=0 255} chng trnh con . . . RET INT (n){n0 255} chng trnh x l ngt . . . RETI

Thc hin khi c chng trnh chnh

Thc hin khi c tn hiu bo ngt

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Chng III. Tm hiu tp lnh PLC ca S7-200

* Phng php lp trnh PLC vi phn mm STEP7-Micro/WIN 32: - Cch lp trnh cho S7-200 da trn hai phng php c bn: Phng php hnh thang (ladder logic vit tt l LAD) v phng php lit k lnh (Statement List vit tt l STL) v phng php th 3 m khng c dng thng dng l phng php s khi chc nng (Funtion Block Diagram vit tt l FBD). - Chng trnh c vit theo kiu LAD thit b lp trnh s to ra mt chng trnh theo kiu STL tng ng. Nhng ngc li khng phi tt c cc chng trnh vit theo kiu STL u c th chuyn sang dng LAD. * Phng php LAD: LAD l ngn ng lp trnh ho nhng thnh phn c bn dng trong LAD tng ng vi cc thnh phn c bn dng biu din lnh logic nh sau: - Tip im: L biu tng (Symbol) m t cc tip im rle cc tip im c th thng ng: thng m Q 0.0 - Cun dy (coil): l biu tng -( cung cp cho rle - Hp (box): l biu tng m t cc hm khc nhau n lm vic khi c dng in chy n hp thng l cc b thi gian (timer), b m (counte) v cc hm ton hc:
CU CTU

) m t rle mc theo chiu dng in

IN PT

TON

A PV

ADD EN END IN 1 OUT

IN 2
AC1 AC2 ACD

+100

- Mng LAD: l ng ni cc phn t thnh mt mch hon thin, i t ng ngun bn tri sang ngun bn phi dng in chy t tri qua tip im n cc cun dy hoc cc hp tr v bn phi ngun.

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14

* Phng php lit k lnh STL: Phng php lit k (STL) l phng php thc hin chng trnh di dng tp hp cc cu lnh. Mi cu lnh trong chng trnh k c nhng lnh hnh thc biu din mt chc nng ca PLC. to mt chng trnh dng STL ngi lp trnh cn phi hiu r phng thc s dng ca ngn xp logic ca S7-200 (S0 S8). Ngn xp lgic l mt khi gm 9 bit chng ln nhau. Tt c cc thut ton lin quan n ngn xp, u ch lm vic vi bit u tin hoc vi bit u v bit th hai ca ngn xp (S0 S1) gi tr logic mi u c th c gi vo ngn xp. * Phng php FBD: Dng cc phn t logic vit chng trnh v d cc mch AND, OR, NOT . c. C php lnh c bn trong PLC S7-200 H lnh ca S7-200 c chia lm 3 nhm: - Nhm lnh khng iu kin: Cc lnh m khi thc hin th lm vic c lp khng ph thuc vo gi tr logic ca ngn xp. - Nhm lnh c iu kin: Cc lnh ch thc hin c khi bit u tin ca ngn xp c gi tr logic bng 1. - Nhm lnh t nhn: Cc nhn lnh nh du v tr trong tp lnh. Trong cc bng lnh cn m t s thay i tng ng ca ni dung ngn xp khi lnh c thc hin. C hai phng php LAD v STL u s dng k hiu I ch vic thc hin tc thi (Immediateli) tc l gi tr c ch dn trong lnh va c chuyn vo thanh ghi o va ng thi c chuyn n tip im ch dn trong lnh ngay khi lnh cthc hin ch khng phi ch n giai on trao i vi ngoi vi ca vng qut. iu khc vi lnh khng tc thi l gi tr c ch nh trong lnh ch c chuyn vo thanh ghi o khi thc hin lnh. Bng 3-1: Mt s lnh ca S7-200 thuc nhm lnh thc hin v iu kin. Section 1.01Tn Section 1.02M t lnh = n Gi tr ca bit u tin ngn xp c sao chp sang im n ch dn trong lnh. =I n Gi tr ca bit u tin ngn xp c sao chp trc tip sang im n ch dn trong lnh ngay khi lnh c thc hin.
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ALD

AN n

CTU Cxx, PV

CTUD Cxx,PV

ED DU LD n

LDN n

LDW <=n1, n2 LDW = n1, n2 LDW >=n1, n2 LPP

LRD

Thc hin ton t v (AND) gia gi tr logic ca bit u tin ngn xp vi gi tr logic ca im n ch dn trong lnh. Kt qu c ghi li vo bit u tin ca ngn xp. Thc hin ton t v (AND) gia gi tr logic ca bit u tin ngn xp vi gi tr logic ca bit th 2 ngn xp. Kt qu c ghi li vo bit u tin ca ngn xp. Cc gi tr cn li trong ngn xp c ko ln mt bit. Thc hin ton t v (AND) gia gi tr logic ca bit u tin ngn xp vi gi tr logic nghch o ca im n ch dn trong lnh. Kt qu c ghi li vo bit u tin ca ngn xp. Khi ng b m tin theo sn ln ca tn hiu vo. B m c t li trng thi ban u (reset) nu u vo R ca b m c kch (c mc logic 1). Khi ng b m tin theo sn ln ca tn hiu u vo th nht v m li theo sn ln ca tn hiu u vo th hai. B m c reset li nu u vo R ca b m c kch (c mc logic 1). t gi tr logic 1 vo bit u tin ca ngn xp khi xut hin sn xung ca tn hiu. t gi tr logic 1 vo bit u tin ca ngn xp khi xut hin sn ln ca tn hiu. Np gi tr logic ca im n ch dn trong lnh vo bit u tin ca ngn xp. Cc gi trong ngn xp c y xung mt bit. Np gi tr logic nghch o ca im n ch dn trong lnh vo bit u tin ca ngn xp. Cc gi trong ngn xp c y xung mt bit. Bit u tin trong ngn xp nhn gi tr logic 1 nu ni dung hai t n1 v n2 tho mn n1 n2. Bit u tin trong ngn xp nhn gi tr logic 1 nu ni dung hai t n1 v n2 tho mn n1 = n2. Bit u tin trong ngn xp nhn gi tr logic 1 nu ni dung hai t n1 v n2 tho mn n1 n2. Ko ni dung ngn xp ln mt bit. Gi tr mi ca bit trn l gi tr c ca bit di, su ngn xp gim i mt bit (Gi tr ca bit u tin b y ra khi ngn xp xo). Sao chp gi tr ca bit th hai vo bit th hai ca ngn xp. Cc gi tr cn li t bit th hai tr i c gi nguyn v tr.
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MEND NOT O n

OI n

OLD

ON n

RET RETI

Kt thc phn chng trnh chnh trong mt vng qut. o gi tr logic ca bit u tin ngn xp. Thc hin ton t hoc (OR) gia gi tr logic ca bit u tin ngn xp vi gi tr logic ca im n ch dn trong lnh. Kt qu c ghi li vo bit u tin ca ngn xp. Thc hin ton t hoc (OR) gia gi tr logic ca bit u tin ngn xp vi gi tr logic ca im n ch dn trong lnh. Kt qu c ghi li vo bit u tin ca ngn xp. Thc hin ton t hoc (OR) gia gi tr logic ca bit u tin ngn xp vi gi tr logic ca bit th hai ngn xp. Kt qu c ghi li vo bit u tin ca ngn xp. Cc gi tr cn li trong ngn xp c ko ln mt bit. Thc hin ton t v (AND) gia gi tr logic ca bit u tin ngn xp vi gi tr logic ca im n ch dn trong lnh. Kt qu c ghi li vo bit u tin ca ngn xp. Lnh thot khi chng trnh con v tr iu khin v chng trnh chnh gi n. Lnh thot khi chng trnh x l ngt (interrupt) v tr iu khin v chng trnh chnh.

Bng 3-2: Mt s lnh trong nhm lnh c Iu kin (ch thc hin khi bit u tin ngn xp c gi tr logic 1): Tn lnh Mt +D IN1, IN2 Thc hin hai php cng hai s nguyn kiu t kp IN1 v IN2. Kt qu c ghi li vo IN2 +I IN1, IN2 Thc hin hai php cng hai s nguyn kiu t IN1 v IN2. Kt qu c ghi li vo IN2 -D IN1, IN2 Thc hin hai php tr hai s nguyn kiu t kp IN1 v IN2. Kt qu c ghi li vo IN2 -I IN1, IN2 Thc hin hai php tr hai s nguyn kiu t IN1 v IN2. Kt qu c ghi li vo IN2 +R IN1,IN2 Thc hin hai php cng hai s thc (32 bit) IN1 v IN2. Kt qu c ghi li vo IN2 -R IN1,IN2 Thc hin hai php tr hai s thc (32 bit) IN1 v IN2. Kt qu c ghi li vo IN2
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Tn lnh *R IN1,IN2 /R IN1,IN2 ANDD IN1.IN2 ANDW IN1.IN2 CALL n CRET CRTI MOVB IN.OUT MOVD IN.OUT MOVR IN.OUT MOVW IN.OUT ORD IN1, IN2

Mt Thc hin hai php nhn hai s thc (32 bit) IN1 v IN2. Kt qu c ghi li vo IN2 Thc hin hai php chia hai s thc (32 bit) IN1 v IN2. Kt qu c ghi li vo IN2 Thc hin ton logic AND gia cc gi tr kiu t kp IN1 v IN2. Kt qu c ghi li vo IN2 Thc hin ton logic AND gia cc gi tr kiu t kp IN1 v IN2. Kt qu c ghi li vo IN2 Gi chng trnh con c nh nhn n Kt thc mt chng trnh con v tr li kiu iu khin v chng trnh gi n Kt thc mt chng trnh x l ngt v tr iu khin v chng trnh chnh Sao gi tr ca Byte OUT Sao gi tr ca t kp IN sang t kp OUT Sao s thc IN sang OUT Sao gi tr ca t IN sang t OUT

Thc hin ton t OR cho hai t kp IN1 v IN2. Kt qu c ghi li vo IN2 ORW IN1, IN2 Thc hin ton t OR cho hai t IN1 v IN2. Kt qu c ghi li vo IN2 PLS x a b pht xung nhanh c nh ngha trong b nh c bit vo trng thi tch cc. Xung a ra c a ra cng QO.x RLD IN, n Quay trn t kp IN sang tri n bit RLW IN, n Quay trn t IN sang tri n bit RRD IN, n Quay trn t kp IN sang phi n bit RRW IN, n Quay trn t IN sang phi n bit SLD IN, n Dch t kp IN sang tri n bit SLW IN, n Dch t IN sang tri n bit SQRT IN, OUT Ly cn bc hai ca mt s thc 32 bit IN v ghi kt qu vo OUT
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Tn lnh (32 bit) SRD IN, n SRW IN, n STOP SWAP IN

Mt

Dch t kp IN sang phi n bit Dch t IN sang phi n bit Dng mm chng trnh i b hai bit u tin v cui cng ca byte IN cho nhau

Bng 3-3: Cc lnh t nhn (Label): Tn lnh (i) INT Nn LBL xx NEXT NOP SBR n M t Khai bo nhn n cho chng trnh x l ngt t nhn xx trong chng trnh, nh hng cho lnh nhy JMP Lnh kt thc vng lp FOR .NEXT Lnh rng (No operation) Khai bo nhn n cho chng trnh con

d. Cc lnh Timer, Counter: * Timer: Timer l b to thi gian tr gia tn hiu vo v tn hiu ra nn trong iu khin thng c gi l khu tr. Nu k hiu tn hiu (logic) vo l x (1) v thi gian tr l t th tn hiu u ra ca Timer l x (l-t). trong S7-200 c hai loi Timer khc nhau: - Timer to thi gian tr khng c nh (On-Delay Timer), k hiu l TON. - Timer to thi gian tr c nh (Retentive On-Delay Timer), k hiu l TONR. Hai loi Timer ny phn bit nhau bi phn ng ca chng i vi tn hiu vo. C hai loi u bt u to thi gian tr t thi im c sn ln ca tn hiu vo. Nhng TON s t Reset khi u vo c mc logic 0, cn TONR th khng t Reset khi mt tn hiu vo. TON c dng to thi gian tr trong mt khong thi gian, cn TONR thi gian tr c to ra trong nhiu khong khc nhau. Trong phn ny chng ta ch nghin cu loi Timer TON.

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Lnh

phn gii 1 ms

Gi tr cc i 32,767 s 327,67 s 3276,7 s 32,767 s 327,67 s 3276,7 s

CPU 212

CPU 214

1) ton

T32 T33 - T36 T37 - T63 T0 T1 - T4 T5 - T31

T32, T96 T33 - T36, T97 - T100 T37 - T63, T101 - T127 T0, T64 T1-T4, T65-T68 T5-T31, T69-T95

10 ms 100 ms 1 ms

TONR

10 ms 100 ms

C php khaibo Timer trong LAD v STL nh sau: LAD M t Khai bo Timer s hiu xx kiu TON to thi gian tr tnh t khi u vo IN c kch (c mc 1). Nu nh gi tr m tc thi ln hn hoc TON Txx bng gi tr t c PT th T+n bit co gi tr Logic bng 1. C th Reset Timer kiu TON bng lnh R hoc bng gi tr Logic 0 u vo IN. STL Ton hng Txx (word): CPU 212: 32-63 CPU 214: 32-63 v 96-127 PT (wort): VW, T, C, IW . N= 1 32762 (S nguyn)

Txx IN TON PT

Thi gian tr T= PT3 phn gii * Counter:

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Couner l b m thc hin chc nng m sn ln ca xung. S7-200 c hai loi b m: b m tin (CTU) v b m tin/li (CTUD). B m tin m s sn ca xung vo, tc l m s ln thay i trng thi Logic t 0 ln 1 ca tn hiu. S sn xung m c ghi vo thanh ghi 2 byte ca b m gi l thanh ghi C-word. Ni dung ca C-word, c gi l gi tr tc thi ca b m, lun c so snh vi gi tr t trc ca b m., k hiu l PV. Khi gi tr m tc thi bng hoc ln hn gi tr t trc th b m bo ra ngoi bng cch t gi tr logic 1 vo bit c bit ca n, c gi l C-bit. Trng hp gi tr m cn nh hn gi tr t trc th C-bit c gi tr logic 0. Khc vi cc Timer, cc Counter u c chn ni vi tn hiu iu khin xo thc hin t li ch khi pht ban u (reset) cho b m, c k hiu bng ch ci R trong LAD, hay c quy nh l trng thi bit u tin ca ngn xp trong STL. B m c reset khi tn hiu xo ny c mc 1 hoc khi lnh R (reset) c thc hin vi C-bit. Khi b m reset th c C-word v C-bit u nhn gi tr 0. B m tin/li CTUD thc hin m tin khi gp sn ln ca xung vo cng m tin, k hiu l CU trong LAD hoc bit th 3 ngn xp trong STL, v m li khi gp sn ln ca xung vo cng m li, k hiu l CD trong LAD hoc bit th 2 ngn xp trong STL. Vic xo b m CTUD cng c hai cch tng t nh b m CTU. C php khai bo Counter LAD v STL nh sau:

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LAD

Cxx CU CTU R PV

Cxx CU CTUD CD

R PV

M t Ton hng Khai bo b m tin Cxx (word): theo sn ln ca tn CPU 212: 0 hiu vo cng CU s 47 hiu xx kiu CTU. Khi CTU Cxx, +n gi tr m tc thi C- CPU 214: 0 word ca Cxx ln hn 47 hoc bng gi tr t V 80 127 trc PV, C-bit (Cxx) c PV (Word): gi tr logic bng 1. B m ngng m khi C- VW, T, C, IW, word Cxx t gi tr cc n=1 32767 i 32767. (s nguyn) Khai bo b m tin/li, m tin theo sn ln ca tn hiu Cxx (word): n CU v m li theo CPU 212: 48 CTUD Cxx, sn len ca tn hiu 63 +n n CD. Khi gi tr tc thi C- word ca Cxx CPU 214: 48 ln hn hoc bng gi 79 tr t trc PV, C- bit (Cxx) c gi tr logic bng 1. B m c reset khi u vo R c gi tr logic 1. B m ngng m tin khi Cword Cxx t gi tr cc i 32767 v ngng m li khi C- word Cxx t gi tr cc tiu l - 32767.

STL

PV (Word): VW, T, C, IW, n=1 32767 (s nguyn)

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K hiu Cxx ca b m ng thi cng l a ch hnh thc ca C - word v ca C- bit. Mc d cng a ch hnh thc, song C- word v C- bit vn c phn bit vi nhau nh kiu lnh s dng lm vic vi kiu t hay kiu tip im (bit). V d: LD C48 LDW >= C48 * Cc lnh so snh: Nu cc quyt nh v iu khin c thc hin khi cn c s so snh th c th s dng lnh so snh theo byte, t hay t kp (gi tr thc hoc nguyn). Nhng lnh so snh thng l: so snh nh hn hoc bng (<=); so snh bng (=) v so snh ln hn hoc bng (>=). Khi so snh cc gi tr ca byte th khng cn phi n du ca ton hng, ngc li khi so snh cc t hoc t kp vi nhau th phi n du ca cc ton hng l bit cao nht trong t hoc t kp. Kt qu ca php so snh c gi tr bng 0 (nu ng) hoc 1 (nu sai) nn c th s dng kt hp cng vi cc lnh logic LD, A, O. to ra c cc php so snh m S7 - 200 khng c lnh tng ng nh: so snh khng bng nhau (<>), so snh nh hn (<) hoc so snh ln hn (>), c th to ra c nh dng kt hp lnh NOT vi cc lnh c (=, >= v <=). V d sau m t vic thc hin php so snh khng bng nhau (<>) gia cc ni dung ca t VW100 v hng s 50 bng cch s dng kt hp cc php tnh so snh bng nhau. LDW = v lnh o NOT. LDW = VW 100, 50; LDW>= VW100,50; LDW<=VW100,50> NOT // (<>) NOT // (<) NOT // (>) Biu din cc lnh so snh trong LAD: // Lnh lm vic vi C-bit ca b m C48. // Lnh lm vic vi C- word ca b m C48.

e. Lnh so snh lnh di chuyn ni dung nh v mt s bit nh c bit.

LAD
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M t

Ton hng
23

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LAD n1 ==B n2 n1 ==I n2 n1 ==D n2 n1 ==R n2 n1 >=B n2 n1 >=I n2 n1 >=D n2 n1 >=R n2

M t

Ton hng

Tip im ng khi n1 = n2. B = Byte.

N1, n2: VB, IB, QB, MB (byte) SMB, AC, Const, *VD* , AC

I = Integer. D = Double Integer. R = Real. n1, n2: VW, T, C, IW (t) QW, MW, SMW, AC, AIW, Hng s, *VD* , *AC Tip im ng khi n1/n2. B = Byte. I = Integer. D = Double Integer. R = Real n1, n2: VD, ID, QD, MD, (t kp) SMD, AC, HC, Hng s, *VD* , *AC

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LAD n1 <=B n2 n1 <=I n2 n1 <=D n2 n1 <=R n2

M t Tip im ng khi n1[ n2

Ton hng

B = Byte. I = Integer. D = Double Integer. R = Real

LDB =, LDW = LDD =, LDR = Lnh kim tra bng nhau ca ni dung hai byte, t, t kp hc s thc. Trong trng hp php so snh cho kt qu ng, bit u tin trong ngn xp s c gi tr logic bng 1. LDB < =, LDW < = LDD < =, LDR < = Lnh so snh ni dung ca byte, t, t kp hc s thc th nht c nh hn hoc bng ni dung ca byte, t, t kp hoc s thc th hai hay khng. Trong trng hp php so snh cho kt qu ng, bit u tin trong ngn xp c gi tr logic bng 1. LDB > =, LDW > = LDD > =, LDR > = Lnh so snh ni dung ca byte, t, t kp hoc s thc th nht c ln hn hoc bng ni dung ca byte, t, t kp hoc s thc th hai hay khng. Trong trng hp php so snh cho kt qu ng, bit u tin trong ngn xp c gi tr logic bng 1. AB =, AW = AD =, AR =

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Lnh kim tra tnh bng nhau ca ni dung hai byte, t, t kp hoc s thc. Trong trng hp php so snh cho kt qu ng, s thc hin php tnh logic And gia bit u tin trong ngn xp vi gi tr logic 1. AB < =, AW < = AD < =, AR < = Lnh so snh ni dung ca byte, t, t kp hoc s thc th nht c nh hn hoc bng ni dung ca byte, t kp hoc s thc th hai hay khng. Trong trng hp php so snh cho kt qu ng, s thc hin php tnh logic And gia bit u tin trong ngn xp vi gi tr logic 1. AB > =, AW > = AD > =, AR > = Lnh so snh ni dung ca byte, t, t kp hoc s thc th nht c ln hn hoc bng ni dung ca byte, t, t kp hoc s thc th hai hay khng. Trong trng hp php so snh cho kt qu ng, s thc hin php tnh logic And gia bit u tin trong ngn xp vi gi tr logic 1. OB =, OW = OD =, OR = Lnh kim tra tnh bng nhau ca ni dung hai byte, t, t kp hoc s thc. Trong trng hp php so snh cho kt qu ng, s thc hin php tnh logic Or gia bit u tin trong ngn xp vi gi tr logic 1. OB < =, OW < = OD < =, OR < = Lnh so snh ni dung ca byte, t, t kp hoc s thc th nht c nh hn hoc bng ni dung ca byte, t, t kp hoc s thc th hai hay khng. Trong trng hp php so snh cho kt qu ng, s thc hin php tnh logic Or gia bit u tin trong ngn xp vi gi tr logic 1. OB > =, OW > = OD > =, OR > = g. Cc lnh di chuyn ni dung nh v mt s bt nh c bit: * Lnh di chuyn nh:

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STL MOVW OUT IN

LAD MOV-W EN IN Out

M t Lnh sao chp ni dung t n IN sang t n OUT

Ton hng IN, OUT (t n) VW, T, C, IW, QW

* Cc bt nh c bit (thng s dng khi lp cc chng trnh n gin): nh M t SM0.0 Lun c gi tr logic bng 1 SM0.1 C gi tr logic bng 1 vng qut u tin SM0.2 Bit bo d liu b tht lc (0-D liu cn ; 1-D liu b tht lc) SM0.3 Bit bo PLC c ng ngun (1- vng qut u tin, 0- vng qut tip theo) SM0.4 Pht nhp 60 giy (0- cho 30 giy u, 1- cho 30 giy sau) SM0.5 Pht nhp 1 giy (0- cho 0,5 giy u, 1- cho 0,5 giy sau) SM0.6 Nhp vng qut (1- cho vng qut lun phin) SM0.7 Bt chn ch lm vic cho PLC (0- TERM, 1-RUN)

2.3. S kt ni vo ra ca thit b PLC S7-200:

Trong : in p vo 24V-DC (c th ly ngun ra ca PLC Sensor-Supply) cn in p cp u ra tu thuc vo ph ti nhng in p nh mc l 220V-AC.

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Khi s dng cc Modun m rng th cn phi nui ngun cho n vi in p 24VDC c pha ng ra v ng vo.

Chng IV. Vit chng trnh iu khin cho h thng ng thng bia t ng.
I: Phn tch yu cu cng ngh v la chn thit b iu khin I.1: Phn tch yu cu cng ngh: Gi thiu thit b: Dy chuyn bao gm: S0 nt n dng my, S1 nt n khi ng my , B1 Sensor bo sn phm ri xung , B 2 Sensor bo c thng vic. Nguyn tc iu kin: Nu cha c thng ti v tr t trc th khi ta iu khin ng c M lm vic trc ko bng ti a thng vo v tr ng sn phm , khi thng vo ng v tr th sensor B2 s tc ng ct in ng c M ng thi m van Y a sn phm vo thng mt dy 4 chai, c mi ln b 4 chai th ng c M c dch chuyn mt on v khi b ng 6 ln th van Y c ng li v ng c M hot ng.....a thng bia khc vo v tr c th c tnh cht chu k. 2. a ch cc bin vo ra. tt 1 2 3 4 5 6 7 Tn S0 S1 B1 B2 Y M H a ch I0.0 I0.1 I0.2 I0.3 I0.4 I0.5 I0.6 Ch gii
NT N DNG H THNG M my Sensor bo sn phm ng vo thng Sensor bo c thng Van m b sn phm Bng ti vn chuyn thng n bo h thng ang lm vic

Y Van

m th sn phm, M bng ti vn chuyn thng , H n bo h thng ang lm

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3. vIT CHng trnh iu khin ( dng ngn ng LaDer)

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Chng V: Chy th chng trnh trn phn mm m phng SiMulator ca Siemen

1, Cc bc chy bng phn mm m phng: - Ta vit chng trnh bng phn mm: STPEP 7 MICROWIN 3.1 - Sau khi vit chng trnh ta vo menu File chon Export - t tn tp tin v chn Save - M phn mm m phng S7_200.exe - Nhp mt khu cho PLC : 6596 - V o menu Configuration chon CPU Type de PLC chon CPU 214 - V o menu Program chon Load Programa - Chn Accept v chn vection cho ph hp vi (V3.1) - Chn file cn m phng c lu ban u, Nhn Open \ Nhn OK
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- Chn Run [iu khin cc tip im cn iu khin bng cng tc trn bng mu xanh (cc ng v o I0.0...I0.7, I1.0...I1.5) - Quan st cc n bo trn PLC 2, Kt ni v vn hnh th: - Ni dy vo cng u vo - Ni dy vo cng u ra - Ni dy cp ngun Chn PLC trn thanh cng c sau nhn Run chy chng trnh. Lu : Khi vn hnh cn phi tun th theo yu cu cng ngh: trc ht ta phi t ch cho chng trnh theo yu cu cng ngh bng cc nt n. Khi sa cha phi thay th nhng thit b c thng s k thut tng ng vi thit b c, ring PLC- S7-200 c th thay th bng Logo. Trong qu trnh vn hnh cn c ch bo dng nh k v bo m v sinh cng nghip.

Kt lun
Trong qu trnh lm mn hc trang b in c s gip ca cc Thy c, cng bn b ng nghip nn ti c bn hon thnh cc ni dung ca n. Ni dung ca n ch yu l tm hiu cng ngh, c im ca qu trnh vn hnh h thng ng gi sn phm. Tm hiu thit b kh trnh PLC v cc cu lnh dng trong PLC S7-200. c bit n gii quyt c chng trnh iu khin, xy dng mch kt ni iu khin v lp h s trang b cho h thng ng gi sn phm p ng yu cu cng ngh t ra. Tuy bn thn c nhiu c gng nhng do thi gian, iu kin, ti liu kh khn v kh nng c hn nn khng trnh khi sai st. Rt mong c s ng gp kin ca Thy c gio v cc bn b ng nghip.

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