VERILOG FINAL PROJECT

Digital Electronics B mn K thut my tnh Khoa in t - Vin thng Trng H Bch Khoa Nng
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Cu trc MIPS:
Instruction [25 0] 26 Shift left 2

JumpAddress
Shift_left28

Jump address [31 0] 28 0 M u x 1 1 M u x 0

PC+4 [31 28] Add 1 ALU result Add PC4 4 Instruction [31 26] Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2

MuxJumpOut

0
1

ALUBranchOut

MuxJr
MuxBranchOut

BranchSel

Shift_left32

ZeroFlag

ALU2Out

DataMemOut

PCin

Instruction [25 21] PC Read address Instruction [31 0] Instruction [20 16] 0 M u x 1

Read register 1

PC

Instruction memory

Read data 1 Read register 2 Registers Read Write data 2 register Write data

Instruction [15 11]

0 M u x 1

Zero ALU 2 ALU result

Address

Read data Data memory

Write data Instruction [15 0] 16 Sign extend 32 ALU control

1 M u x 0

ALUcontrolOUt

Instruction [5 0]

jreg

2
Sign_extend_Out

Phn cng nhm

Project 1
Nguyn L Hong Tun(nt)-testbench+Multiplexor V Ngc Tr Minh - Decoder ng Th Nguyn Tho - Register

Project 2
Trn Phc Thnh (nt) Nguyn Th Bo Trm - Mux Nguyn Duy Hong Trng Th Kim Ng -

Project 3:
Nguyn Vn Hiu (leader) - testbench ng Thanh Quang Nguyn Hu Ha -

Decoder (5:32)
1. Khi gii m Decoder: 1.1 Gii thiu: - Khi decoder lm nhim v gii m, la chn thanh ghi cn x l - S khi ca mt mch gii m 5:32 (5 u vo, 32 u ra)

WriteRegister[4:0]

Decoder 532

WriteEnable[31:0]

RegWrite

Decoder (5:32)
+ + + Khi Decoder gm: 1 ng vo 5 bit la chn thanh ghi: WriteRegister 1 ng vo iu khin 1 bit: RegWrite 32 ng ra enable 1 bit: WriteEnable

Decoder (5:32)
1.2 Phn tch: - Ta lp bng trng thi m t hot ng ca b decoder 5:32
a 0 0 0 0 0 ..... 1 1 1 1 1 b 0 0 0 0 0 ..... 1 1 1 1 1 c 0 0 0 0 1 0 1 1 1 1 d 0 0 1 1 0 1 0 0 1 1 e 0 1 0 1 0 1 0 1 0 1 Y0 1 0 0 0 0 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 0 0 Y2 0 0 1 0 0 0 0 0 0 0 Y3 0 0 0 1 0 0 0 0 0 0 Y4 Y27 Y28 Y29 Y30 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 .. 0 1 0 0 0 0 0 0 0 0 .. 0 0 1 0 0 0 0 0 0 0 .. 0 0 0 1 0 Y31 0 0 0 0 0 .. 0 0 0 0
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.. .. .. .. .. .. .. . ..

Decoder (5:32)
Vi a, b, c, d, e ln lt l 5 bit ng vo WriteRegister a: WriteRegister[4]; b: WriteRegister[3]; c: WriteRegister[2] d: WriteRegister[1]; e: WriteRegister[0] Y0, Y1, Y2, Y3, Y31 ln lt l 32 bit u ra WriteEnable la chn thanh ghi cn x l t Nota= a; Notb= b; Notc= c ; Notd= d; Note= e

Decoder (5:32)
Ta c phng trnh logic: - Y0=Nota.Notb.Notc.Notd.Note. t And4_0=Nota.Notb.Notc.Notd WriteEnable[0]=And4_0.RegWrite.Note - Y1=Nota.Notb.Notc.Notd.e. t And4_0=Nota.Notb.Notc.Notd WriteEnable[1]=And4_0.RegWrite.e - Y2=Nota.Notb.Notc.d.Note. t And4_1=Nota.Notb.Notc.d WriteEnable[2]=And4_1.RegWrite.Note - Y3=Nota.Notb.Notc.d.e. t And4_1=Nota.Notb.Notc.d WriteEnable[3]=And4_1.RegWrite.e - ................................ - Y30=a.b.c.d.Note. t And4_15=a.b.c.d WriteEnable[30]=And4_15.RegWrite.Note - Y31=a.b.c.d.e. t And4_15=a.b.c.d WriteEnable[31]=And4_15.RegWrite.e
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Decoder (5:32)
Code chng trnh:
`timescale 1 ps / 100 fs module Decoder(RegWrite, WriteRegister, WriteEnable); input RegWrite; input [4:0] WriteRegister; output [31:0] WriteEnable; wire Nota, Notb, Notc, Notd, Note; wire And4_0,And4_1,And4_2,And4_3,And4_4,And4_5,And4_6,And4_7,And4_8,And4_9,And4_10, And4_11,And4_12,And4_13,And4_14,And4_15; not #(50) Inv4(Nota, WriteRegister[4]); not #(50) Inv3(Notb, WriteRegister[3]); not #(50) Inv2(Notc, WriteRegister[2]); not #(50) Inv1(Notd, WriteRegister[1]); not #(50) Inv0(Note, WriteRegister[0]); and #(50) And4to1_0 (And4_0 , Nota, Notb, Notc, Notd); and #(50) And4to1_15(And4_15,WriteRegister[4],WriteRegister[3],WriteRegister[2],WriteRegister[1]); and #(50) And3to1_0 (WriteEnable[0] , RegWrite, And4_0 , Note); and #(50) And3to1_1 (WriteEnable[1] , RegWrite, And4_0 , WriteRegister[0]); and #(50) And3to1_31(WriteEnable[31], RegWrite, And4_15, WriteRegister[0]); endmodule 9

Decoder (5:32)
- S mch:

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Register
2. Register:

WriteEnable l tn hiu iu khin, cho php ghi d liu ln thanh ghi Clk l tn hiu xung ng b WriteData[31..0] l d liu c ghi vo thanh ghi ( gm 32 bit ) WrittenRegister[31..0] l gi tr ca thanh ghi (gm 32 bit )
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Construction of Register

12

Bit of Register

Write Enable 0 0 1 1

Q 0 1 x x

Bit Data x x 0 1

Output 0 1 0 1

Output = Q . Write Enable + Write Enable . Bit Data

Bit of Register

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Bit of Register
module D_FF(q, d, reset, clk); output q; input d, reset, clk; reg q; // Indicate that q is stateholding always @(posedge clk or posedge reset) if (reset) q=0; // On reset, set to 0 else q=d; // Otherwise, out = d endmodule

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Bit of Register

Output = Q . Write Enable + Write Enable . Bit Data

BitOfReg (Q of D Flip-Flop)= a BitData = b WriteEnable = c

and #(50) U1(a_and_notc,BitOfReg,(~WriteEnable)); and #(50) U2(b_and_c,BitData,WriteEnable); or #(50) U3(d,a_and_notc,b_and_c);

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Bit of Register
`timescale 1 ps / 100 fs module BitOfRegister(WriteEnable, BitData, BitOfReg, clk); output BitOfReg; // BitOfReg (Q of D Flip-Flop) = a input BitData, WriteEnable; // BitData = b, WriteEnable = c input clk; wire d,a_and_notc, b_and_c; // input of D Flip-Flop wire reset; assign reset=0; and #(50) U1(a_and_notc, BitOfReg, (~WriteEnable)); and #(50) U2(b_and_c, BitData, WriteEnable); or #(50) U3(d, a_and_notc, b_and_c); D_FF DFF0(BitOfReg, d, reset, clk); endmodule
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Register

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Register
module Register(WriteEnable, WriteData, WrittenRegister, clk); input WriteEnable, clk; input [31:0] WriteData; output [31:0] WrittenRegister; BitOfRegister Bit0 (WriteEnable, WriteData[0 ], WrittenRegister[0 ], clk); BitOfRegister Bit1 (WriteEnable, WriteData[1 ], WrittenRegister[1 ], clk); .. BitOfRegister Bit30(WriteEnable, WriteData[30], WrittenRegister[30], clk); BitOfRegister Bit31(WriteEnable, WriteData[31], WrittenRegister[31], clk); endmodule

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B chn knh
3.1-Phn tch: 3.1.1-Khi chn knh mux32_32to32_32 - Ng ra ca khi thanh ghi Register32 l 32 thanh ghi 32 bit , ty theo gi tr ca ReadRegister m ta s la chn mt thanh ghi trong tng s 32 thanh ghi trn a d liu ca n n ng ra ca ReadData. - S khi chn knh ny c dng nh sau:

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B chn knh
3.1.2-Khi chn knh mux32_1to1_1 - V 32 bit ca thanh ghi ng ra ReadData l c lp nn ta c th xy dng khi mux32_32to1_32 t 32 khi mux32_1to1_1. - S khi chn knh ny c dng nh sau:

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3.2-Tin trnh thit k khi chn knh mux32_1to1_1 3.2.1-Thnh lp bng trng thi ng ra BitReadData RR[4] 0 0 0 0 0 0 0 0 0 0 RR[3] 0 0 0 0 0 0 0 0 1 1 RR[2] 0 0 0 0 1 1 1 1 0 0 RR[1] 0 0 1 1 0 0 1 1 0 0 RR[0] 0 1 0 1 0 1 0 1 0 1 BitReadData BitDataOut0 BitDataOut1 BitDataOut2 BitDataOut3 BitDataOut4 BitDataOut5 BitDataOut6 BitDataOut7 BitDataOut8 BitDataOut9
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RR[4] 0 0 0 0 0 0 1 1 1 1 1 1

RR[3] 1 1 1 1 1 1 0 0 0 0 0 0

RR[2] 0 0 1 1 1 1 0 0 0 0 1 1

RR[1] 1 1 0 0 1 1 0 0 1 1 0 0

RR[0] 0 1 0 1 0 1 0 1 0 1 0 1

BitReadData BitDataOut10 BitDataOut11 BitDataOut12 BitDataOut13 BitDataOut14 BitDataOut15 BitDataOut16 BitDataOut17 BitDataOut18 BitDataOut19 BitDataOut20 BitDataOut21
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RR[4] RR[3] 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1

RR[2] 1 1 0 0 0 0 1 1 1 1

RR[1] 1 1 0 0 1 1 0 0 1 1

RR[0] BitReadData 0 1 0 1 0 1 0 1 0 1 BitDataOut22 BitDataOut23 BitDataOut24 BitDataOut25 BitDataOut26 BitDataOut27 BitDataOut28 BitDataOut29 BitDataOut30 BitDataOut31

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3.2.2- Thit lp phng trnh logic -T bng trng thi trn , nu ta gi: RR[4]=e;RR[3]=d;RR[2]=c;RR[1]=b;RR[0]=a Ph nh ca a,b,c,d,e ln lt l na,nb,nc,nd,ne tg[31..0] l mt mng 32 bit lu tr gi tr tm thi;th ta c: tg[0]=ne.nd.nc.nb.na.BitDataOut0 tg[10]=ne. d.nc. b.na.BitDataOut10 tg[1]=ne.nd.nc.nb. a.BitDataOut1 tg[11]=ne. d.nc. b. a.BitDataOut11 tg[2]=ne.nd.nc. b.na.BitDataOut2 tg[12]=ne. d. c.nb.na.BitDataOut12 tg[3]=ne.nd.nc. b. a.BitDataOut3 tg[13]=ne. d. c.nb. a.BitDataOut13 tg[4]=ne.nd. c.nb.na.BitDataOut4 tg[14]=ne. d. c. b.na.BitDataOut14 tg[5]=ne.nd. c.nb. a.BitDataOut5 tg[15]=ne. d. c. b. a.BitDataOut15 tg[6]=ne.nd. c. b.na.BitDataOut6 tg[16]= e.nd.nc.nb.na.BitDataOut16 tg[7]=ne.nd. c. b. a.BitDataOut7 tg[17]= e.nd.nc.nb. a.BitDataOut17 tg[8]=ne. d.nc.nb.na.BitDataOut8 tg[18]= e.nd.nc. b.na.BitDataOut18 tg[9]=ne. d.nc.nb. a.BitDataOut9 tg[19]= e.nd.nc. b. a.BitDataOut19

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tg[20]= tg[21]= tg[22]= tg[23]= tg[24]= tg[25]=

e.nd. c.nb.na.BitDataOut20 e.nd. c.nb. a.BitDataOut21 e.nd. c. b.na.BitDataOut22 e.nd. c. b. a.BitDataOut23 e. d.nc.nb.na.BitDataOut24 e. d.nc.nb. a.BitDataOut25

tg[26]= tg[27]= tg[28]= tg[29]= tg[30]= tg[31]=

e. e. e. e. e. e.

d.nc. b.na.BitDataOut26 d.nc. b. a.BitDataOut27 d. c.nb.na.BitDataOut28 d. c.nb. a.BitDataOut29 d. c. b.na.BitDataOut30 d. c. b. a.BitDataOut31

Vy: BitReadData=tg[0] + tg[1] + tg[2] + tg[3] + tg[4] + tg[5] + tg[6] + tg[7] + tg[8] + tg[9] + tg[10]+ tg[11] + tg[12] + tg[13] + tg[14] + tg[15] + tg[16] + tg[17] + tg[18] + tg[19] + tg[20] + tg[21]+ tg[22] + tg[23] + tg[24] + tg[25] + tg[26] + tg[27] + tg[28] + tg[29] + tg[30]+ tg[31]

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3.3-Tin trnh thit k khi cng 32 bit or32 3.3.1-Phn tch - Theo yu cu ca project 1, chng ta ch c th s dng cc cng logic c ti a 4 u vo. - thc hin cng 32 bit ng vo chng ta cn phn tch thnh cc khi nh hn l cc cng logic ch c ti a 4 u vo. 3.3.2-Thnh lp phng trnh logic -Gi m[9..0] l thanh ghi 10 bit lu tr tm thi. -Gi tg[31..0] ln lt l 32 bit cn thc hin vic cng gp. -Nu ta c: m[0]=tg[0]+tg[1]+tg[2]+tg[3] m[4]=tg[16]+tg[17]+tg[18]+tg[19] m[1]=tg[4]+tg[5]+tg[6]+tg[7] m[5]=tg[20]+tg[21]+tg[22]+tg[23] m[2]=tg[8]+tg[9]+tg[10]+tg[11] m[6]=tg[24]+tg[25]+tg[26]+tg[27] m[3]=tg[12]+tg[13]+tg[14]+tg[15] m[7]=tg[28]+tg[29]+tg[30]+tg[31]
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BitReadData Nu: m[8]

=m[0]+m[1]+m[2]+m[3]+m[4]+m[5]+m[6]+m[7] =m[0]+m[1]+m[2]+m[3] = =m[4]+m[5]+m[6]+m[7] = =m[8]+m[9]

m[9]

Vy:

BitReadData

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3.4-Tin trnh thit k khi chn knh mux32_32to1_32 - a tng bit t [31..0] trong 32 bit ca mi thanh ghi DataOut0, DataOut1,.., DataOut31 vo cc ng vo BitDataOut0, BitDataOut1, .., BitDataOut31 ca cc Mux32_1to1_1 th [31..0]. - 5 bit iu khin ReadRegister[1..0] c a vo 5 bit iu khin ReadRegister[1..0] ng thi tt c cc Mux32_1to1_1 th [31..0]. - 32 bit BitReadData Mux32_1to1_1 th [31..0] c a vo 32 bit t [31..0] ca thanh ghi ng ra ReadData theo ng th t bit.

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MIPS ALU
Yu cu: Thit k khi ALU (Arithmetic Logic Unit: Khi s hc logic) 32 bit n gin ca MIPS. ALU thc hin cc nhim v sau: ADD, SUB, XOR v SLT. S khi tng qut ca ALU thit k c s c dng nh hnh v sau:

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MIPS ALU
Bng thng s cho ALU control la chn nhim v cn thc hin ca ALU:

C Carryout v Overflow ch xt cc lnh ADD v SUB C Zero v Negative c xt cc lnh ADD, SUB v XOR.

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MIPS ALU
D vo yu cu thit k ,ta chia ALU thnh cc khi chnh nh sau: Khi Add_Xor_Sub. Khi chn knh MultiplexorOut. Khi MuxFag. Khi CheckFag. Khi Zero_Negative_Finder

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Khi Add_Xor_Subb
THC HIN : 1. Khi thc hin Add, Sub, Xor: 1.1 Phn tch: Khi ny s thc hin cc php ton ADD, SUB v XOR tn hiu vo 32 bit Bus A v Bus B. thc hin vic ny trc tin ta phi xy dng khi mch thc hin cc php ton ADD, SUB v XOR tn hiu 1 bit .Sau s xy dng khi mch thc hin ADD, SUB v XOR 32bit da trn cc khi mch ADD , SUB v XOR 1 bit ny. S khi ca khi ADD, SUB v XOR c dng nh sau:
CFAdd BusA[31..0] BusB[31..0] CFSub OFAdd

ADD, SUB, XOR

OFSub ADDresult[31..0] XORresult[31..0] SUBresult[31..0]

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Khi Add_Xor_Subb
1.2 Thit k khi ADD, SUB v XOR 1 bit : 1.2.1 Khi thc hin php ton XOR : Xt 2 bit vo a v b,khi ny s thc hin php ton XOR a v b.Ta ch cn dng lnh: xor #(50) U1(a_xor_b, a, b); l c th to c khi ny.

1.2.2 Khi thc hin php ton ADD:

cinAdd a b

Add

OutAdd CAdd

cinAdd: s nh ca ln cng trc CAdd : s nh ca ln cng hin ti outAdd: tng hin ti

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Khi Add_Xor_Subb
Bng gi tr b Add
input
a b cinAdd

Bng Karnaugh v ti thiu ha:

output

outAdd cinAdd ab 0 1 00 0 1 01 1 0 11 0 1 10 1 0

outAdd

CAdd

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1

0 0 0 1 0 1 1 1

CAdd ab cinAdd 00 0 0 1 0 01 0 1 11 1 1 10 0 1

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Khi Add_Xor_Subb
Phng trnh logic: outAdd CAdd

S dng 2 phng trnh logic ny vit code cho php ton cng.

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Khi Add_Xor_Subb
1.2.3 Khi thc hin php ton SUB :
cinSub a b

Sub

OutSub CSub

cinSub: s mn ca ln tr trc CSub: s mn ca ln tr hin ti outSub: hiu s hin ti Tng t nh khi Add,chng ta cng phi lp bng gi tr,bng cacno v ti thiu ha tm c phng trnh logic cho php ton SUB

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Khi Add_Xor_Subb
Bng gi tr b SUB
input
a b

Bng cacno v ti thiu ha

outSub cinSub ab 0 1 CSub cinSub ab 00 0 0 1 1 01 1 1 11 0 1 10 0 0 00 0 1 01 1 0 11 0 1 10 1 0

output
cinSub outSub CSub

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1

0 1 1 1 0 0 0 1

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Khi Add_Xor_Subb
T ta tm c phng trnh logic ca php ton SUB: outSub

CSub

S dng 2 phng trnh logic ny vit code cho php ton tr

Khi Add_Xor_Subb
Sau khi vit code v chy trong quartus ta c s mch nh sau:
U1 a b comb~3

comb~2

U6 CSub

comb~0

U5 CAdd

comb~1 U3 cinSub (GND) U2 cinAdd (GND) outAdd a_xor_b outSub

Khi Add_Xor_Subb
1.3 Thit k khi ADD, SUB v XOR 32 bit: 1.3.1 Phn tch: - V tn hiu vo c 32 bit . Do ta ch cn gi 32 ln modul Calc_bit ( xy dng phn trn) thc hin ADD, SUB , XOR 32 bit theo th t t bit 0 n bit 31. - Trong khi ny ta cng c th tm c c carry v c overflow. Da vo l thuyt nh sau: + Carryout: (trn khng du) xy ra khi c nh (mn) t MSB. Nh vy c Carry( CFAdd v CFSub ) chnh l CAdd[31] v CSub[31] + Overflow: (trn c du) xy ra khi kt qu php ton vt qu di gii hn tnh ton Cch xc nh c Overflow nh sau:

Khi Add_Xor_Subb
cinAdd cinSub 0 0 0 0 1 1 1 1 a 0 0 1 1 0 0 1 1 b 0 1 0 1 0 1 0 1 CAdd 0 0 0 1 0 1 1 1 outAdd 0 1 1 0 1 0 0 1 CSub 0 1 0 0 1 1 0 1 outSub 0 1 1 0 1 0 0 1

+ i vi php cng: 2 s hng ca php cng cng du nhng kt qu khc du vi 2 s hng . T bng, suy ra cch nhn bit thng qua bit nh: overflow xy ra khi bit nh cinAdd v CAdd ca MSB khc nhau. + i vi php tr: s b tr l s dng v s tr l s m, kt qu l s m hoc s b tr l s m v s tr l s dng, kt qu l s dng. T bng, suy ra cch nhn bit thng qua bit mn: overflow xy ra khi bit mn cinSub v CSub ca MSB khc nhau.

Khi Add_Xor_Subb
Do ta so snh 2 bit CAdd[31] v CFAdd[30] nu 2 bit ny khc nhau th c OFAdd s c set. Tng t nu 2 bit CSub[31] v CFSub[30] khc nhau th c OFSub s c set. lm c iu ny ta dng php ton XOR .

Khi chn knh MultiplexorOut

Phn tch: - Sau khi thc hin tnh ton, ta c c kt qu ca 4 php ton ADD, SUB, XOR v SLT. Cn c vo 2 bit iu khin port ALU control xc nh kt qu no s c a ra output port theo nh bng sau:
ALU CONTROL LINES FUNCTION

00 01 10 11
- Do , cn c khi chn knh MultiplexorOut.

ADD XOR SUB SLT

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Khi chn knh MultiplexorOut

S khi:
ADDresult [31..0] SUBresult [31..0] XORresult [31..0] SLTresult [31..0]

MultiplexorOut 41
ALUcontrol [1..0]

Output [31..0]

Nhn xt: 4 ng vo 32 bit l ADDresult, SUBresult, XORresult v SLTresult 1 ng vo iu khin 2 bit l ALUcontrol 1 ng ra 32 bit l Output

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Khi chn knh MultiplexorBit

Xy dng Khi chn knh MultiplexorOut t 32 Khi chn knh MultiplexorBit. S khi:
BitofADD BitofSUB BitOfXOR BitOfSLT

MultiplexorBit 41
ALUcontrol [1..0]

BitOfOutput

Nhn xt: 4 ng vo l cc bit BitOfADD, BitOfSUB, BitOfXORv BitOfSLT 1 ng vo iu khin 2 bit l ALUcontrol 1 ng ra l bit BitOfOutput
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Thit k khi MultiplexorBit

Bng trng thi: ALUcontrol ALUcontrol [1] ALUcontrol [0] 0 0 0 1 1 0 1 1 Phng trnh logic: BitOfOutput BitOfADD BitOfXOR BitOfSUB BitOfSLT

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Thit k khi MultiplexorBit

Code:
`timescale 1 ps / 100 fs module MultiplexorBit(BitOfADD, BitOfXOR, BitOfSUB, BitOfSLT, BitOfOutput, ALUcontrol); input BitOfADD, BitOfXOR, BitOfSUB, BitOfSLT; input [1:0] ALUcontrol; output BitOfOutput; wire BitSel[0:3];
U2 BitOfXOR Uout BitOfOutput BitOfSUB U3 BitOfSLT U1 ALUcontrol[1..0] BitOfADD U0

S mch:

and #(50) U0(BitSel[0], BitOfADD, (~ALUcontrol[1]), (~ALUcontrol[0])); and #(50) U1(BitSel[1], BitOfXOR, (~ALUcontrol[1]), ALUcontrol[0] ); and #(50) U2(BitSel[2], BitOfSUB, ALUcontrol[1] , (~ALUcontrol[0])); and #(50) U3(BitSel[3], BitOfSLT, ALUcontrol[1] , ALUcontrol[0] ); or #(50) Uout(BitOfOutput, BitSel[0], BitSel[1], BitSel[2], BitSel[3]); endmodule

Thc hin trn Quartus II

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Thit k khi MultiplexorOut

Tin trnh: - a tng bit t [31..0] trong 32 bit ca mi port ADDresult, SUBresult, XORresult v SLTresult vo cc ng vo BitOfADD, BitOfSUB, BitOfXOR v BitOfSLT ca cc MultiplexorBit th [31..0]. - 2 bit iu khin ALUcontrol[1..0] c a vo 2 bit iu khin ALUcontrol[1..0] ng thi tt c cc MultiplexorBit th [31..0]. - 32 BitOfOutput MultiplexorBit th [31..0] c a vo 32 bit t [31..0] ca port Output theo ng th t bit. Thc hin trn Quartus II

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Khi MuxFlag
Nhn xt: - V c CarryOut v c Overflow ch xt cc lnh ADD v SUB do ta cn c mch chn knh 2 1 chn c cn xt l ca lnh ADD hay SUB ty thuc vo 2 bit iu khin ca ALUcontrol. - Tuy nhin, cn c vo bng thng s cho ALUcontrol la chn nhim v cn thc hin ca ALU: Ta thy rng ch cn xt MSB ca ALUcontrol l c th xc nh c nhim v cn thc hin l lnh ADD hay lnh SUB xt c s dng 1 bit iu khin l ALUcontrol[1] ALUcontrol ALUcontrol [1] ALUcontrol [0] 0 0 0 1 1 0 1 1 BitOfOutput BitOfADD BitOfXOR BitOfSUB BitOfSLT
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Khi MuxFlag
S khi:
FlagOfAdd FlagOfSub

MuxFlag 21
control

FlagOut

Bng trng thi: Control 0 1 Phng trnh logic: FlagOut FlagOfAdd FlagOfSub

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Thit k khi MuxFlag

Code:
`timescale 1 ps / 100 fs module MuxFlag(FlagOfAdd, FlagOfSub, Control, FlagOut); input FlagOfAdd, FlagOfSub; input Control; output FlagOut; wire And2[0:1]; and #(50) And2_0(And2[0], FlagOfAdd, (~Control)); and #(50) And2_1(And2[1], FlagOfSub, Control ); or #(50) FlOut(FlagOut, And2[0], And2[1]); endmodule

S mch:

Thc hin trn Quartus II

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Module CheckFlag
Nhim v: Quyt nh c cp nht c mi hay gi nguyn trng thi ca c ang hin hnh. S khi :
NewFlag Currentflag Control

CheckFlag

OutFlag

Tt c cc u vo, ra u l 1 bit

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Module CheckFlag

OutFlag: c ra NewFlag: c mi cp nht CurrentFlag: c hin hnh Control: bit iu khin, Control= 0 :c ra OutFlag s ly theo c mi NewFlag, nu Control = 1:gi nguyn c hin hnh CurrentFlag.

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Module CheckFlag
NewFlag 0 0 1 1 0 0 1 1 CurrenrFlag 0 1 0 1 0 1 0 1 Control 0 0 0 0 1 1 1 1 OutFlag 0 0 1 1 0 1 0 1

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Module CheckFlag
Phng trnh logic:

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Module CheckFlag
Code Verilog:
module CheckFlag(NewFlag, CurrentFlag, Control, OutFlag); input NewFlag, CurrentFlag, Control; output OutFlag; wire NewFlag_and_NotControl, CurrentFlag_and_Control; and U1(NewFlag_and_NotControl, NewFlag , (~Control)); and U2(CurrentFlag_and_Control,CurrentFlag, Control ); or U3(OutFlag, NewFlag_and_NotControl, CurrentFlag_and_Control); Endmodule

S mch:

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Khi tnh c Zero v Negative (Zero_Negative_finder)

S khi :

1 ng vo 32 bit : OutputofALU 2 ng ra 1 bit : ZeroFlag v NegativeFlag

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Khi tnh c Zero v Negative (Zero_Negative_finder)

1. Thut ton thit k tnh c Zero v Negative. Phn tch: C Zero v Negative ch thay i gi tr i vi cc php tnh Adds, Xors , Subtracts. Php tnh SLT khng lm thay i gi tr ca c Zero v Negative. C Zero: C Zero ch lp khi c 32 bit u vo u l bit 0 C Negative: C Negative ch lp khi bit MSB=1 v 31 cn li l bit 0. Vy im chung ca 2 c nu c lp th 31 bit thp ca s c gi tr l 0. Da vo c im ny vit thut ton kim tra tra c.

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Khi tnh c Zero v Negative (Zero_Negative_Finder)

2. Thut ton thit k: Tnh Or 31 bit thp ca d liu 32 bit OutputofALU to ra bit Or31bitoutput. Tm gi tr ca c Zero bng thut ton nh sau: ZeroFlag = Or31bitoutput + OutputofALU[31]

Tm gi tr ca c Negative bng thut ton nh sau: NegativeFlag = Or31bitoutput . OutputofALU[31]

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Khi tnh c Zero v Negative (Zero_Negative_Finder)

Code chng trnh:
`timescale 1 ps / 100 fs module Zero_Negative_Finder(OutputOfALU, ZeroFlag, NegativeFlag); input [31:0] OutputOfALU; output ZeroFlag, NegativeFlag; wire Or4[0:6]; wire Or3; wire Nand4[0:1]; wire Or31bitOfOutput; // excepting MSB of Output _ Output[31] or #(50) Or4_0(Or4[0], OutputOfALU[0 ], OutputOfALU[1 ], OutputOfALU[2 ], OutputOfALU[3]); or #(50) Or4_1(Or4[1], OutputOfALU[4 ], OutputOfALU[5 ], OutputOfALU[6 ], OutputOfALU[7]); or #(50) Or4_6(Or4[6], OutputOfALU[24], OutputOfALU[25], OutputOfALU[26], OutputOfALU[27]); or #(50) Or3_0(Or3, OutputOfALU[28], OutputOfALU[29], OutputOfALU[30]); nand #(50) Nand4_0(Nand4[0], (~Or4[0]), (~Or4[1]), (~Or4[2]), (~Or4[3])); nand #(50) Nand4_1(Nand4[1], (~Or4[4]), (~Or4[5]), (~Or4[6]), (~Or3)); or #(50) Or31bit(Or31bitOfOutput, Nand4[0], Nand4[1]); nor #(50) ZeroF(ZeroFlag, Or31bitOfOutput, OutputOfALU[31]); and #(50) NegativeF(NegativeFlag, (~Or31bitOfOutput), OutputOfALU[31]); endmodule

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Khi tnh c Zero v Negative (Zero_Negative_Finder)

S mch :

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Tng hp Project 2
S khi: ALU c 8 ports: Port vo gm: Bus A v Bus B Port iu khin: ALU control Port ra gm: Output Zero Overflow Negative Carryout
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Tng hp Project 2
Bng thng s cho ALU control la chn nhim v cn thc hin ca ALU:

C Carryout v Overflow ch xt cc lnh ADD v SUB C Zero v Negative c xt cc lnh ADD, SUB v XOR.

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Tng hp Project 2
Nguyn l hot ng cu ALU: 1. Khi Add_xor_sub: - Khi ny s dng d liu 32 bit u vo t Bus A v Bus B thc hin cc php ton Add, Xor, Sub - Gi tr u ra gm: CFadd _c carry ca php ton Add CFsub _c carry ca php ton Sub OFadd _c Overflow ca php ton Add OFsub _c ca php ton Sub ADDresult_ gi tr ca php ton Add XORresult_gi tr ca php XOR SUBresult_gi tr ca php ton Sub
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Tng hp Project 2
2. Khi chn knh Multiplexorout: Sau khi thc hin tnh ton khi tnh ton, ta c c 4 kt qu ca ADD, SUB, XOR v SLT. Cn c vo 2 bit iu khin port ALUcontrol xc nh d liu no s c a ra output port C th: ALUcontrol =00_ d liu ADDresult c a n Output ALUcontrol =01_ d liu XORresult c a n Output ALUcontrol =10_d liu SUBresult c a n Output ALUcontrol =11_d liu SLTresult c a n Output

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Tng hp Project 2
3. Khi tnh v kim tra c Zero,Negative:

D liu u ra t khi MultiplexorOut c a n khi Zero_Negative_Finder xc nh gi tr ca c Zero v Negative. D liu u ra ca khi ny l gi tr ca c Zero v Negative. Gi tr ca ZeroFlag v NegativeFlag c a n khi CheckFag xc nh vic gi hay thay i gi tr ca c u ra theo gi tr ca bt iu khin control. Phng trnh logic thc hin chn c : OutFlag = control.NewFlag + control.CurrenFlag control = 0 _ cp nht c mi . control = 1 _gi nguyn gi tr ca c trc . Gi tr ca OutFlag chnh l gi tr ca c Zero v Negative u ra ca 67 ALU

Tng hp Project 2
4. Khi tnh, kim tra c Carry v OverFlow:

u vo ca khi MuxOverflowFlag l gi tr ca c OFadd v OFsub. Khi ny s chn gi tr c ca php ton add hoc sub theo s iu khin ca ALUcontrol[1] v xut ra port FlagOut. ALUcontrol[1]=1 _chn gi tr ca OFsub. ALUcontrol[1]=0 _chn gi tr ca OFadd. Gi tr FlagOut c a vo khi CheckFlag xc nh vic gi hay thay i gi tr ca c u ra ca khi CheckFlag theo gi tr ca bit iu khin ALUcontrol[0]. Phng trnh logic thc hin chn c: OutFlag = ALUcontrol[0].NewFlag + ALUcontrol[0].CurrenFlag ALUcontrol[0] =1 : gi nguyn gi tr ca c trc . 68 ALUcontrol[0] =0 : cp nht c mi .

on m khi Add
Code chng trnh:
`timescale 1 ps / 100 fs module Add(A,B,Y); input [31:0] A,B; output [31:0] Y; wire [32:0] C; assign C[0]=0; Addbit Addbit0 (A[0 ], B[0 ], C[0 ], Addbit Addbit1 (A[1 ], B[1 ], C[1 ], Addbit Addbit2 (A[2 ], B[2 ], C[2 ], Addbit Addbit3 (A[3 ], B[3 ], C[3 ], Addbit Addbit4 (A[4 ], B[4 ], C[4 ], Addbit Addbit26(A[26], B[26], C[26], Addbit Addbit27(A[27], B[27], C[27], Addbit Addbit28(A[28], B[28], C[28], Addbit Addbit29(A[29], B[29], C[29], Addbit Addbit30(A[30], B[30], C[30], Addbit Addbit31(A[31], B[31], C[31], endmodule

Y[0 Y[1 Y[2 Y[3 Y[4

], ], ], ], ],

C[1 C[2 C[3 C[4 C[5

]); ]); ]); ]); ]);

Y[26], Y[27], Y[28], Y[29], Y[30], Y[31],

C[27]); C[28]); C[29]); C[30]); C[31]); C[32]);

on m khi Addbit
Code chng trnh:
module Addbit(a,b,cin,y,cou); input a,b,cin; output y,cou; wire a_xor_b; xor #(50) (a_xor_b,a,b); xor #(50) (y,a_xor_b,cin); or #(50) (cou,a_xor_b & cin,a & b); endmodule

Khi addbit
Bng s tht:

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

cin 0 1 0 1 0 1 0 1

y 0 1 1 0 1 0 0 1

cout 0 0 0 1 0 1 1 1

Khi Addbit
Cng thc tng qut:

y a.b.cin a.b.cin a.b.cin a.b.cin a (b cin ) a (b cin ) a b cin cout a.b.cin a.b.cin a.b.cin a.b.cin ( a b)cin a.b (cin cin ) ( a b)cin a.b

Khi shift_left_2
Khi shift_left_2: Khi c tc dng dch 32 bit sang tri 2 bit V d: 1001 1000 1110 0011 0010 0101 1010 1001 Ly 30 phn t u tin sau thm 2 s 0 cui cng. Ta c nh sau: 0110 0011 1000 1100 1001 0110 1010 0100 Khi sign_extend: - Khi ny c tc dng chuyn t 16 bit c du sang 32 bit c du. - i vi MSB ca 16 bit l 0 th ta thm 16 s 0 trc n - i vi MSB ca 16 bit l 1 th ta thm 16 s 1 trc n V d: 1/ 0110 0011 0010 1000 0100 1100 1100 1101 chuyn thnh 00000000 0110 0011 0010 1000 0100 1100 1100 1101 2/ 1110 0011 0010 1000 0100 1100 1100 1101 chuyn thnh 11111111 1110 0011 0010 1000 0100 1100 1100 1101

on m shift_left_2
on m shift_left_2:
module shift_left_2(In32, Out32); input [31:0] In32; output [31:0] Out32; assign Out32 = {In32[29:0],2'b00}; Endmodule

on m sign_extend:
module sign_extend(In16,Out32); input [15:0] In16; output [31:0] Out32; assign Out32 = {{16{In16[15]}},In16}; endmodule

Chc nng b MUX

Chc nng ca b MUX 2x32 to 32 . B MUX chn d liu mt trong hai u vo 32 bit . Datain0 v Datain1 l hai d liu u vo . Sel l bit chn d liu u ra . dataOut d liu ra 32 bit .

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MUX 2x32 to 32
S khi b MUX 2x32 to 32.

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MUX 2x32 to 32

tng b MUX 2x32to32.

Trong b MUX 2x32to32 gm 32 khi MUX 2to1. Mi khi MUX 2to1 c 2 u vo l bit tng ng ca Data0 v Data1. u ra mi khi MUX 2to1 l bit c th t tng ng vi bit Data0 v Data1.

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MUX 2 to 1
bitin1 0 0 0 0 1 1 1 bitin0 0 0 1 1 0 0 1 Sel 0 1 0 1 0 1 0 bitout 0 0 1 0 0 1 1

bitout in1.in0.sel in1.in0.sel in1.in0.sel in1.in0.sel in0.sel(in1 in1) in1.sel(in0 in0) in0.sel in1.sel
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MUX 2x5 to 5

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Khi Control v ALUcontrol

Bng quan h :

Value Type R add xor sub slt lw sw bne j

opcode

function ALUOp ALUControl 100000 100110 100010 101010 00 01 10 11 00 10 xx

000000 100011 101011 000101 000010

10

I J

00 01 xx

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Kt qu phn tch

Khi Control :
o o c vit theo mc behavioural Dng casex

Phng trnh logic ca ALUcontrol :

ALUcontrol[0] = (f[5] & (not f[4]) & f[1] & (not f[0])) & A[1] & (not A[0]) & (f[3] xor f[2]) ALUcontrol[1] = ( (f[5] & (not f[4]) & f[1] & (not f[0])) & (not f[2]) & A[1] & (not A[0]) ) or ((not A[1]) & A[0])

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Khi DataMem

input [31:0] address, writedata; reg [7:0] datamem[1023:0];

always @(address or datamem[address] or datamem[address+1] or datamem[address+2] or datamem[address+3]) begin temp={datamem[address],datamem[address+1],datamem[address+2] ,datamem[address+3]}; end

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Hiu chnh DataMem

always @(address or datamem[address] or datamem[address+1] or datamem[address+2] or datamem[address+3]) if (readenable) begin temp={datamem[address],datamem[a ddress+1],datamem[address+2],datam em[address+3]}; end always @(address or datamem[address] or datamem[address+1] or datamem[address+2] or datamem[address+3]) if (readenable or writeenable) begin temp={datamem[address],datamem[address+1],datamem[address+2],datamem[address +3]}; end
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sw (store word) Mem[Adrr]

Mem[Adrr] lw (load word)

Testbench
M Assembly :
0 lw 4 lw 8 lw 12 lw 16 lw 20 lw 24 lw 28 LOOP:slt 32 bne 36 j 40 ELSE: add 44 add 48 sw 52 sub 56 j 60 lw 64 DONE: $1, 0($0) ; mem 0 ($0) = 5 $2, 4($0) ; mem 4 ($0) = 0 $3, 8($0) ; mem 8 ($0) = 0 $4, 12($0) ; mem 12($0) = 1 $5, 16($0) ; mem 16($0) = 2 $6, 20($0) ; mem 20($0) = 40 $7, 24($0) ; mem 24($0) = 4 $2, $0, $1 $2, $0, ELSE DONE $3, $3, $5 $6, $6, $7 $3, 0($6) $1, $1, $4 LOOP $8, 0($6) j DONE

M C++:
$1 = 5; // the number of repeat $3 = 0; $6 = 40; while (0<$1) { $3 = $3 + 2; $6 = $6 + 4; mem[$6] = $3; $1 = $1 1; }

Kt qu cui cng:
$1 = 0; $3 = 10; $6 = 60; // a ch word
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