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Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Gii thiu dng vi iu khin lai MSP430Gxxx (mixed-signal microcontroller) _____*****_____


Vit tng chu gi ti Thanh Vn, chc chu hay n, mau ln, vng li m.Yu chu!

I.Gii thiu tng quan : Ta hiu nm na y l dng vi iu khin tch hp c cc mch tng t v mch s trn cng mt con chip. c xy dng trn cu trc RISC CPU 16-bit , cc thnh phn tng t ngoi vi, mt h thng xung clock linh hot (theo kin ch quan ca mnh th MSP430 hn hn PIC v AVR v mt ny), cc ng bus a ch v bus d liu theo cu trc von-Neumann.V u im vt tri ca uP ny l siu tit kim in. II.Bc u lm quen vi KIT Launchpad vi dng G2xxx Tham kho: http://processors.wiki.ti.com/index.php/MSP430_LaunchPad_(MSPEXP430G2) 1.S mch KIT:

Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

*Capture:

2.Trnh bin dch: -Ta dng CCS (Code-Composer-Studio) -Tm tt s s cch dng: C bn ging MPlab,to 1 project -> to 1 source file c ui l .c hoc .asm. Ri build nh bnh thng. C g th t m nh. 3.Vi chng trnh c bn : Ch lm ht cc v d tun t, v d sau khng nhc li kin thc ca v d trc. mi v d s c tm tt kin thc cho v d . Bi vit ny dnh cho nhng ngi mun hc nhanh, cn mun tm hiu su cn tm hiu k tng thanh ghi theo datasheet. Chc vui! :D
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Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Ex1.Blinking led.(P1.0 v P1.6) *Kin thc b tr: Mi Port (P1, P2)ca MSP c 8 chn (pins), cc chn ny c cu hnh vo/ra cng nh ghi/c mt cch c lp (Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to). Port P1 v P2 c cc ngt c enable v configure c lp theo sn ln hoc xung.Hi ba l P1 chung nhau 1 vector ngt, P2 chung nhau 1 vector ngt.V cc chn ny c tr ko, khng lo phn phm bm nh. Cc thanh ghi c bn: Thanh ghi gi tr u vo PxIN (ging PINx ca AVR ) Thanh ghi u ra PxOUT (ging PORTx ca AVR ) Thanh ghi ch hng PxDIR (ging DDR ca AVR ) Thanh ghi tr ko PxREN (ci ny c :D) Bit=1 l enable pullup/pulldown Bit=0 l disable pullup/pulldown __________________________________________________________ *Source code for blinking led:
#include "msp430g2231.h" int main( void ) { unsigned int i; // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD; P1DIR = 0x01; while (1) { P1OUT = 0x01; //led on for (i = 0; i < 60000; i++); P1OUT = 0x00; //led off for (i = 0; i < 60000; i++); } return 0; }

Ex2.Button : Dng phm bm (P1.3) khi gi phm th n tt, nh th n sng (P1.0)

Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Source code:
#include <msp430g2231.h>

void main(void) { WDTCTL = WDTPW + WDTHOLD; P1DIR = 0x01; P1OUT = 0x08; P1REN |= 0x08; while (1) { if (0x10 & P1IN) P1OUT |= 0x01; else P1OUT &= ~0x01; } }

// // // //

Stop P1.0 P1.3 P1.3

watchdog timer output, else input set, else reset pullup

// Test P1.3 // if P1.0 set, set P1.0 // else reset

III.Tm hiu cc thanh ghi v chc nng nng cao 1. Thanh ghi PxSEL v PxSEL2: Do cc Port pins thng multiplexed vi nhiu b phn ngoi vi khc nhau nn ta cn c cc thanh ghi ny chn la chc nng cho pin trong tng trng hp. Da vo bng sau:

Ch 2 note: mt vi port ca MSP430F261x v MSP430F2416/7/8/9,enable tr ko ln/xung (PxREN) trong khi chc nng ngoi vi ang c s dng s disable u ra. Ngt P1, P2 s b disable khi P1xSEL hoc P2SELx c set. Bi vy, tn hiu nhng chn ny s khng khi ng ngt P1, P2 khi P1SELx, p2SEL c set/ 2.Ngt:

Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Mi chn cc port u c kh nng ngt,cc thanh ghi configure l PxIFG, PxIE, PxIES.Tt c cc chn 1 Port chung nhau 1 vector ngt.Thanh ghi PxIFG c th c test quyt nh ngun ngt cho P1 v P2. Cc c ngt (Interrupt Flag Registers P1IFG, P2IFG) Mi bit PxIFGx l c ngt cho p ng ca I/O pin v c set khi sn tc ng ln chn. Tt c cc c ngt c ngt khi c bit PxIE v GIE tng ng c set. Mi c ngt PxIFG phi c reset bng phn mm. Phn mm c set cho c PxIFG, cung cp phng php khi ng ngt mm (ging AVR vl ). Nu mi c PxIFGx c set trong trnh phc v ngt PX hoc sau ch th RETI ca ngt Px c thc thi, c ngt PxIFGx khi ng ngt khc. iu ny m bo tng vic thay i trng thi c nhn bit.

Thanh ghi chn sn(Interrupt Edge Select Registers P1IES, P2IES) . Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition

Thanh ghi enable ngt: Bit = 0: The interrupt is disabled. Bit = 1: The interrupt is enabled. 3.Timer:
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Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Timer A l thanh ghi 16 bit cng 3 thanh ghi capture/compare. Timer A h tr multiple capture/compares, u ra PWM v b m kh ngon. Timer A cng c kh nng ngt trn. Ngt ny khi ng t b m khi iu kin trn xy ra v thanh ghi compare/capture bo. 1.iu khin timer : Timer c 4 ch : stop, up, continuu, and up/down. Ch x l c la chn vi bit MCx.

1.1.Up mode: Up mode c s dng nu chu k timer khc 0FFFFh. Timer c m lp li ti gi tr thanh ghi TACCR0. Khi gi tr timer bng gi tr TACCRo, timer t ng restart t 0. Nu Up mode c chn khi gi tr timer ln hn TACCR0, timer ngay lp tc c restart t 0.

1.2.

Continuous Mode

Trong ch Continuous modem, timer m lp li ti 0FFFFh v khi ng li t 0. Thanh ghi capture/compare TCCR0 lm vic ging cc thanh ghi capture/compare khc.
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Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Ch ny s dng trong trng hp khi ng ph thuc time intervals ca tn s ngoi. Mi chu k hon thnh , ngt s c khi ng. Khong thi gian tip theo s tng gi tr TACCx trong chu k phc v ngt.

1.3 .Up/Down Mode

Ch Up/Down s dng nu chu k timer khc 0xFFFFh, nu xung ng b cn thit. Timer m ti khi bng gi tr thanh ghi TACCR0 v m ngc li.

Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

Ch ny cn 1 dead time gia khc tn hiu ra. trnh overload, 2 u ra cu H phi mc cao. Cng thc tnh: tdead = ttimer (TACCR1 TACCR2)

The up/down mode supports applications that require dead times between output signals (See section Timer_A Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the example shown in Figure 129 the tdead is: tdead = ttimer (TACCR1 TACCR2) tdead : Time during which both outputs need to be inactive ttimer : Cycle time of the timer clock

Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

2.Khi capture/compare: 3.u ra xung:

Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

4.Ngt timer Hai vector ngt kt hp vi timer A: Vector TACCR0 cho 2 thanh ghi TACCR0 CCIFG Vector TAIV cho tt c cc thanh ghi cn li Trong ch capture bt k c CCIFG no c set, gi tr timer c capture ti gi tr thanh ghi TACCRx. Trong ch compare, bt k c CCIFG c set nu m TAR c kt hp vi gi tr TACCRx.Tt c cc c CCIFG yu cu ngt khi c p t bit CCIE v GIE

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Nguyn Xun Tin -0976 031 868- YM: xuantien_bktech

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