I HC QUC GIA TP.

HCM TRNG I HC BCH KHOA

KHOA KHOA HC V K THUT MY TNH

THC HNH VI X L

BM K thut My tnh
2009

Gii thiu

Mc Lc
Mc Lc .............................................................................................................................. 1 Bi 1 : Gii thiu MPLAB IDE v KIT PIC .................................................................. 1 1.1 Mi trng pht trin MPLAB ................................................................................. 1 1.2 Np file hex vo vi iu khin PIC........................................................................... 8 1.3 Debug dng MpLab SIM ........................................................................................ 12 1.4 Debug onchip dng Mplab ICD2............................................................................ 15 1.5 Bi tp ..................................................................................................................... 15 Bi 2 : Kho st cng xut nhp ................................................................................... 16 2.1 Kin thc lin quan................................................................................................. 16 2.1.1 Cc thanh ghi iu khin cng xut nhp ........................................................ 16 2.1.2 Kt ni mch .................................................................................................... 16 2.2 Cc bc hin thc yu cu 1 ................................................................................. 18 2.3 Chng trnh mu yu cu 1................................................................................... 20 2.4 Cc bc hin thc yu cu 2 ................................................................................. 21 2.5 Chng trnh mu yu cu 2................................................................................... 22 2.6 Bi tp ..................................................................................................................... 23 Bi 3 : Kho st c ch ngt qung, giao tip LCD k t ............................................ 24 3.1 Kin thc lin quan................................................................................................. 24 3.1.1 Tm tt cc thanh ghi iu khin ngt ............................................................. 24 3.2 Cc bc hin thc yu cu 1 ................................................................................. 25 3.3 Chng trnh mu yu cu 1................................................................................... 28 3.4 LCD k t 2x16 ...................................................................................................... 31 3.4.1 Hnh dng v ngha cc chn: ....................................................................... 31 3.4.2 T chc vng nh ca LCD............................................................................. 32 3.4.3 Cc lnh giao tip vi LCD ............................................................................. 34 3.4.4 Khi to LCD................................................................................................... 35 3.5 Cc bc hin thc yu cu 2 ................................................................................. 36 3.6 Bi tp ..................................................................................................................... 41 Bi 4 : Kho st b nh thi ........................................................................................ 42 4.1 Cc bc hin thc yu cu 1 ................................................................................. 42 4.2 Chng trnh mu ................................................................................................... 46 4.3 Bi tp ..................................................................................................................... 48 Bi 5 : K thut qut ma trn phm .............................................................................. 49 5.1 Kt ni mch ma trn phm..................................................................................... 49 5.2 Cc bc hin thc ................................................................................................. 50 5.3 Bi tp ..................................................................................................................... 54 Bi 6 : K thut qut LED ............................................................................................ 56 6.1 Cu to LED 7 on v LED ma trn ..................................................................... 56 6.2 Kt ni mch ........................................................................................................... 58 6.3 Cc thanh ghi lin quan v cch iu khin............................................................ 59 6.4 Cc bc hin thc. ................................................................................................ 62 6.5 Bi tp ..................................................................................................................... 65 Bi 7 : Kho st b truyn nhn ni tip ...................................................................... 66 7.1 Cc bc hin thc. ................................................................................................ 66

7.2 Chng trnh mu ................................................................................................... 68 7.3 Bi tp ..................................................................................................................... 70 Bi 8 : Kho st khi chuyn i A-D.......................................................................... 71 8.1 Cc bc hin thc ................................................................................................. 71 8.2 Bi tp ..................................................................................................................... 72 Bi 9 : Kho st cc khi chc nng c bit khc ...................................................... 73 9.1 Cc bc hin thc PWM....................................................................................... 73 9.2 Chng trnh mu ................................................................................................... 74 9.3 Bi tp ..................................................................................................................... 75

Trng H. Bch Khoa TP.HCM

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Bi 1 :

Gii thiu MPLAB IDE v KIT PIC

Ni dung : To project trn MPLAB IDE. Vit chng trnh ASM. Dch v np chng trnh vo vi iu khin PIC. Chy v g ri chng trnh.

1.1 Mi trng pht trin MPLAB

Double Click vo biu tng MPLAB trn Desktop hoc theo cch sau: Start -> All Programs -> Microchip -> MPLAB IDE v76.2 -> MPLAB IDE. T thanh Menu, click chn tab Project -> Project Wirazd

Ca s Welcome hin ln v bn chn Next.

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Chn PIC cn s dng ti khung Device >> Click Next:

Chn tool Microchip C18 Toolsuite ti Active Toolsuite. Chn MPLAB C18 C Compiler ti Tollsuite contents. Nu lp trnh bng assembly th ta chon Active Toolsuite theo hnh sau:

Click Next

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Chn Browse. chn th mc lu project.

nh vo tn Project mun to. Save, sau chng ta chn Next th hin ra ca s nh sau:

y l ni cc bn add th vin cho project. B mn K Thut My Tnh 3 Thc hnh Vi x l

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Bn nn add ht cc file cn thit cho vic lp trnh trc khi bt u vit chng trnh gm file .lib v file .lkr. Nu vit chng trnh cho con chip no th ta ly file .lib v file .lkr ca chp tng ng, nh hnh trn chung ta ang s dng chip 18f4550. Click Next.

Click Finish. Ta s c mt project nh hnh sau:

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Mt project n gin nht phi gm c 2 thnh phn Source files v Hearder Files. Th mc Source files cha file text *.asm hoc file *.c cha code lp trnh. Th mc Hearder Files cha file *.h hoc *.INC: file c sn ca microchip. User khai bo dng loi chip g => add vo th mc ny. Nu bn qun khng add cc file cn c vo th lm theo hng dn sau. ADD header file: ( Copy header file vo th mc cha project tin cho vic s dng sau ny).

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Chn header file ph hp vi PIC mnh chn. Open. ADD source file: Click chn New trn toolbar: Ca s hin ln nh sau: T Menu bar chn File >> Save lu.

t tn v Save vi ui .c nu bn lp trnh trn c18 ca maplab hoc .asm nu bn lp trnh trn assembly. Nhp phi vo Source Files chn Add file >>> chn file chng ta va to xong.

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Ca s hin ln nh sau:

Chng ta hon tt vic add file vo cc th mc Source files v header files. Cng vic tip theo l vit code ( ca s text editor :D:\MAPLAB\Untiled.asm). i vi project m s dng cng 1 loi chip, cng loi ngn ng lp trnh ( ASM hay C) th ch cn to 1 ln. Nhng ln sau, ch cn add/ remove file text (*.asm hoc *.c) vo th mc Source files.

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1.2 Np file hex vo vi iu khin PIC

Sau khi to c mt project, ta tin hnh build n to ra *.hex. C th m t cng vic nh sau: V d, ta c mt chng trnh cho PIC nh sau: ;=====================================; ; Name: nut_nhan.asm ; Project: Nhap du lieu tu nt nhan RA4. ; Khi nt RA4 du?c nh?n th led don RB0 sng, ; Khi khng nh?n RA4 th led don RB0 t?t ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================; list p=18f4520 #include p18f4520.inc org 0 goto start start call main BTFSC GOTO BSF SWOFF BTFSS GOTO BCF GOTO INIT clrf bcf bsf bsf return END PORTB TRISB,0 PORTA,4 TRISA,4 ; setup portb for outputs ; setup porta.4 for input PORTA,4 ;Wait for SW1 to be pressed main PORTB,0 ;Turn on LED1. PORTA,4 ;Wait for SW1 to be released. SWOFF PORTB,0 ;Switch off LED1. main ;Repeat sequence. INIT

By gi chng ta lu chng trnh va vit thnh nut_nhan.asm vo mt th mc to project pha trn. compile chng trnh ta vo menu Project -> Build All nh hnh bn di.

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Nu vic build tht bi, nhng vic ny th khng mong mun, ta c thy kt qu nh hnh sau:

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Nu thnh cng, ta s thy hnh sau:

Nu vic build thnh cng, chng trnh s dch nut_nhan.asm thnh nut_nhan.hex trong cng th mc chng trnh nut_nhan.asm. Sau khi c c file hex, cng vic tip theo l lm th no np c file Hex xung board. u tin l chn mch np bng cch vo menu Programmer -> Select Programmer -> Mplab ICD2 nh hnh sau :

Sau khi chn Mplab ICD2 xong th ta s thy giao din nh sau:

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Lc ny np chng trnh ta ch cn vo menu Programmer -> Program nh hnh sau l c th np c chng trnh.

Sau khi nhn Program nu download xung chip thnh cng th ta s thy hin th ra ca s Output nh sau: MPLAB ICD 2 Ready Programming Target... ...Validating configuration fields ...Erasing Part ...Programming Program Memory (0x0 - 0x3F) Verifying... ...Program Memory ...Verify Succeeded Programming Configuration Bits .. Config Memory Verifying configuration memory... ...Verify Succeeded ...Programming succeeded

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Trng H. Bch Khoa TP.HCM 04-Aug-2009, 14:23:39 MPLAB ICD 2 Ready

Khoa KH & KTMT

bt u chy chng trnh ta phi rt dy kt ni mch np v kit ra. Khi chng trnh mi c th chy c. Trn y l ton b cc bc to mt project, vit assembly cho Pic trn Mplab cng nh lm th no compile v download chng trnh xung chip thc thi. y l trng hp l tng l khi vit code khng c li no xy ra. Nu c li no xy ra th ta phi debug n nh th no. Trong chng ny s hng dn cc bn hai cch debug.

1.3 Debug dng MpLab SIM

Bc 1: s dng MpLab SIM ta vo menu Debugger -> Select Debugger -> Mplab SIM nh hnh v sau:

Bc 2: Khi chn Mplab SIM xong th trn menu Debugger c thm nhiu chc nng khc h tr cho vic debug nh hnh sau:

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T y ta c th m phng c chng trnh ca mnh mt cch d dng. V d nh Run (F9) dng chy chng trnh, chng trnh s chy lin tc n khi no c breakpoint th dng. Vy lm th no to Breakpoint, ta s dng lnh Breakpoints (F2) nh trn hnh to ra breakpoint ti v tr hin ti ca con tr hoc double click vo hng code mnh mong mun t con tr. Hay s dng Step Into (F7) chy tng lnh mt, gp li gi hm th n s vo bn trong li gi hm chy tng lnh trong . Khc vi Step Over (F8) mt t l khi c li gi hm th Step Over xem nh l mt lnh bnh thng, khng i vo hm chi tit nh Step Into. Reset: tr v u chng trnh. Bc 3: Khi debug th ta cng cn phi bit gi tr ca cc thanh ghi cng nh b nh ca chip nh th no, xem c cc gi tr ny th chng ta qua menu View. xem c gi tr ca cc thanh ghi trong PIC ta chn View -> File registers s xut hin ca s nh hnh sau:

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xem c gi tr ca cc thanh ghi SFR th ta chn View -> Special Function Registers s xut hin ca s nh hnh sau:

Hay xem mt v thanh ghi m ta quan tm th c th dng Watch xem bng cch vo View -> Watch th hnh sau s xut hin:

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Mun xem thanh ghi no, ta ch vic chn thanh ghi tng ng trong combobox bn trn, sau nhn Add SFR.

1.4 Debug onchip dng Mplab ICD2.

Cng ging nh debug trn Mplab SIM, Mplab ICD2 cng c nhng tnh nng tng t, nhng khi s dng Mplab ICD2 th cn phi c mch debug, v cc hin tng xy ra ging nh khi chy thc t.

1.5 Bi tp

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Bi 2 :

Kho st cng xut nhp

Ni dung: Kho st hot ng ca nt nhn, LED. Kho st cc thanh iu khin cng xut nhp. Tnh ton thi gian thc thi lnh, vit chng trnh con lm nhim v delay. Vit chng trnh c gi tr ca t hp nt nhn v iu khin gi tr hin th LED. Yu cu: Vit chng trnh xut d liu ra 4 led n m t 0 -> 15 -> 0. Thi gian gia cc ln m ln 1 n v l 1s. Nhp d liu t nt nhn RA4. Khi nt RA4 c nhn th led n RB0 sng, khi khng nhn RA4 th led n RB0 tt.

2.1 Kin thc lin quan

2.1.1 Cc thanh ghi iu khin cng xut nhp
Mi Port c ba thanh ghi iu khin hot ng chnh: Cc bit trong thanh ghi TRIS: thit lp chn tng ng l ng vo (logic 1) hoc ng ra (logic 0). Cc bit trong thanh ghi PORT: c mc logic t chn tng ng. Cc bit trong thanh ghi LAT: ghi mc logic ra chn tng ng.

2.1.2 Kt ni mch
V tr LED hin th v nt nhn trn board nh hnh di y:

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Trng H. Bch Khoa TP.HCM LED hin th c kt ni nh sau:

D2 R21 LED D3 R22 LED D4 R23 LED D5 R24 LED J6 1 2 470 RB3 470 RB2 470 RB1 470 RB0

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LED sng, J6 phi c ni li v chn iu khin tng ng c thit lp l ng ra v mc logic 1. Cc nt nhn c kt ni nh sau:

VCC R1 10K

VCC

VCC

R3 10K D401 4007 MCLR S1 RESET RA4 S2 SW RA4 C1 104

R7 10K

RB0 S3 SW RB0 C2 104

Nt nhn RESET dng reset vi iu khin Nt nhn RA4, RB0 khi c nhn s lm cho chn tng ng mc logic 0. Cn thit lp cc chn RA4 v RB0 l ng vo. Hin tng rung phm:
VCC

R7 10K

RB0 S3 SW RB0 C2 104

Khi phm c nhn, do tc ng ca hin tng rung c hc, tn hiu in ti

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ng ra b chuyn trng thi gia logic 0 v logic 1. Khi phm c th, hin tng rung cng xy ra tng t. B dao ng chnh c kt ni nh sau:
C4 22pF C5 22pF Y2 OSC1 Y1 4MHz OSC2 R4 VCC 4.7K 22pF 2 1 2 NC/OE GND VCC OUT 4 3 VCC

OSC1

J7 C3 1

4MHz

Trn kit th nghim, thch anh Y2 c s dng cho tt c cc bi th nghim.

2.2 Cc bc hin thc yu cu 1

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l Led_don, to file led_don.asm v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file led_don.asm. Bc 3: Khi to PortB l output s dng cc lnh clrf, bcf. INIT clrf PORTB ; setup portb for outputs

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bcf TRISB,0 bcf TRISB,1 bcf TRISB,2 bcf TRISB,3 return Bc 4: To hm delay1ms s dng GOTO. delay equ 0ch

; clear trisb.0 ; clear trisb.1 ; clear trisb.1 ; clear trisb.1 cc lnh CLRF, NOP, DECFSZ, ; declare variable delay

Delay1ms ;Approxiamtely at 4Mhz clrf delay ; clear variable delay Delay_1 nop decfsz delay goto Delay_1 return Bc 5: T y ta c th to ra c hm delay1s: Delay1s Movwf Movlw Delay1s_1 Movwf Movlw Delay1s_2 Call decfsz goto decfsz goto return .4 delay_1sa .250 delay_1sb Delay1ms delay_1sb Delay1s_2 delay_1sa Delay1s_1

Bc 6: Vit chng trnh cho hm main thc hin cc yu cu ca bi s dng lnh INCF: begin INCF PORTB call Delay1s goto begin

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2.3 Chng trnh mu yu cu 1

;=====================================; ; Name: led_don.asm ; Project: Xut d liu ra 4 led n m t 0 -> 15 -> 0. ; Thi gian gia cc ln m ln 1 n v l 1s. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================; list p=18f4520 #include p18f4520.inc delay res 1 delay_1sa res delay_1sb res org 0 goto start start call INIT begin INCF PORTB call Delay1ms goto begin INIT clrf bcf bcf bcf bcf return Delay1ms clrf Delay_1 nop decfsz goto return Delay1s movwf movlw
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PORTB TRISB,0 TRISB,1 TRISB,2 TRISB,3

; setup portb for outputs

;Approxiamtely at 4Mhz delay delay Delay_1

.4 delay_1sa
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Delay1s_1 movwf movlw Delay1s_2 call decfsz goto decfsz goto return END

.250 delay_1sb Delay1ms delay_1sb Delay1s_2 delay_1sa Delay1s_1

Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung mch chy chng trnh nh hng dn chng 1.

2.4 Cc bc hin thc yu cu 2

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l Nut_nhan v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file nut_nhan.asm.

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Bc 3: Khi to PortB l output v PortA l input s dng cc lnh clrf, bcf, bsf INIT CLRF PORTB ;setup portb for outputs BCF TRISB,0 BCF TRISB,1 BCF TRISB,2 BCF TRISB,3 BSF PORTA,4 ; setup porta.4 for input BSF TRISA,4 RETURN Bc 4: Vit chng trnh cho hm main thc hin yu cu ca bi
MAIN BTFSC GOTO BSF SWOFF BTFSS GOTO BCF GOTO PORTA,4 MAIN PORTB,0 PORTA,4 SWOFF PORTB,0 MAIN ;Wait for SW1 to be pressed ;Turn on LED1. ;Wait for SW1 to be released. ;Switch off LED1. ;Repeat sequence.

2.5 Chng trnh mu yu cu 2

;=====================================; ; Name: nut_nhan.asm ; Project: Nhp d liu t nt nhn RA4. ; Khi nt RA4 c nhn th led n RB0 sng, ; Khi khng nhn RA4 th led n RB0 tt ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================; list p=18f4520 #include p18f4520.inc ORG 0 GOTO START START CALL INIT
MAIN BTFSC B mn K Thut My Tnh PORTA,4 22 ;Wait for SW1 to be pressed Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM GOTO BSF SWOFF BTFSS GOTO BCF GOTO MAIN PORTB,0 PORTA,4 SWOFF PORTB,0 MAIN

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;Turn on LED1. ;Wait for SW1 to be released. ;Switch off LED1. ;Repeat sequence.

INIT CLRF
BCF

BSF ; setup porta.4 for input BSF RETURN END Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung mch chy chng trnh nh hng dn chng 1.

PORTB TRISB,0 PORTA,4 TRISA,4

; setup portb.0 for outputs

2.6 Bi tp
Vit chng trnh khi nhn RA4 th cc led s sng m ln, mi ln nhn m ln 1 n v. Vit chng trnh sao cho mi ln nhn RA4 th 2 led tri v 2 led phi thay nhau sng. To hiu ng light river trn 4 led ca board mch starter kit. Nhn RA4 thay i chiu ca light river.

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Bi 3 : t

Kho st c ch ngt qung, giao tip LCD k

Ni dung: Kho st cc nguyn nhn gy ngt qung, cch x l ngt qung, tnh u tin gia cc ngt ca vi iu khin PIC16F877. Kho st ngt ngoi ca vi iu khin PIC16F877. iu khin LCD k t 2x16. Yu cu:

1. Vit chng trnh khi to 2 ngt: Ngt ngoi 0 vi u tin cao. Ngt timer 0 vi u tin thp. Trong chng trnh ngt ngoi 0 bt 3 led n RB1, RB2, RB3sng cng lc. Trong chng trnh timer 0 sau 1s khi 3 led c bt trong ngt ngoi th tt 3 led n RB1, RB2, RB3 cng lc. 2. Vit chng trnh hin th k t ln LCD.

3.1 Kin thc lin quan

3.1.1 Tm tt cc thanh ghi iu khin ngt
Thanh ghi INTCON:

Thanh ghi PIE1:

Thanh ghi PIE2:

Thanh ghi PIR1:

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Thanh ghi PIR2:

S iu khin ngt:

3.2 Cc bc hin thc yu cu 1

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l Interrupt, to file interrupt.asm v chn chip 18f4520. Ta c hnh sau:

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Bc 2: Include file p18f4520.inc vo file interrupt.asm Bc 3: Khi to PortB l output s dng cc lnh clrf, bcf INIT ;assigning PORTB is a digital output MOVLW 0x0e MOVWF ADCON1 ; setup portb for outputs BCF TRISB,1 BCF PORTB,1 BCF TRISB,2 BCF PORTB,2 BCF TRISB,3 BCF PORTB,3 ;initialize delay variable MOVLW .10 MOVWF delay RETURN Bc 4: Khi to timer 0, cho timer 0 ngt c u tin thp, thit lp timer0 c 100ms th xy ra ngt mt ln. INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BCF INTCON2,TMR0IP ;timer0 with low priority
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BSF INTCON,TMR0IF;set timer0 interrupt flag bit BSF INTCON,TMR0IE ; enable timer 0 ;set the global interrupt enable bits BSF INTCON,GIEH BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN Bc 5: Khi to ngt ngoi 0 tch cc cnh xung. i vi ngt ngoi 1 v ngt ngoi 2 th u tin ngt ph thuc vo 2 bit INT1IP v INT2IP trong thanh ghi INTCON3. Cn vi ngt ngoi 0 th khng c bt xc nh u tin, n ch c mt mc u tin l high priority. INIT_EXTERNAL_INTERRUPT ;falling edge on RB0 BCF INTCON2,INTEDG0 ; clear external interrupt flag bit BCF INTCON,INT0IF ; enable external 0 interrupt BSF INTCON,INT0IE ;set the global interrupt enable bits BSF INTCON,GIEH BSF INTCON,GIEL RETURN Bc 6: Vit chng trnh cho ngt ngoi 0, bt 3 n led n cng sng v khi to li gi tr cho bin delay 1s sau th ngt timer s tt 3 n . EXTERNAL_INTERUPT_ROUTINE BCF INTCON,INT0IF BSF PORTB,1 BSF PORTB,2 BSF PORTB,3 MOVLW .10 MOVWF delay RETURN Bc 7: Vit chng trnh cho ngt timer0, sau 1s sau khi led c bt sng th n s lm cho led tt. Thi gian timer m ln 1 n v c tnh bng cng thc :

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T = 1/((Focs/4)/2) = 1/((4Mhz/4)/2) = 0.5us Nn khi ta gi tr trong cc thanh ghi ca timer gi tr 50000 th c sau 100ms, timer s ngt mt ln. tnh c gi tr s Hex gn cho thanh ghi m ca timer ta lm nh sau: i s 50000 sang s hex: C350. Ly FFFF C350 = 3CAF. Byte cao s c lu vo TMR0H, byte thp lu vo TMR0L. TIMER0_INTERRUPT_ROUTINE BCF INTCON,TMR0IF DECFSZ delay,1 GOTO TIMER0_ROUTINE_1 BCF PORTB,1 BCF PORTB,2 BCF PORTB,3 MOVLW .10 MOVWF delay TIMER0_ROUTINE_1 BCF T0CON,TMR0ON MOVLW 0x3C MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN

3.3 Chng trnh mu yu cu 1

;=====================================; ; Name: led_don.asm ; Project: Vit chng trnh khi to 2 ngt: ;- Ngt ngoi 0 vi u tin cao. ;- Ngt timer 0 vi u tin thp. ;- Trong chng trnh ngt ngoi 0 bt 3 led n RB1, RB2, RB3sng cng ;lc ;- Trong chng trnh timer 0 sau 1s khi 3 led c bt trong ngt ngoi th ;tt 3 led n RB1, RB2, RB3 cng lc ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================;

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list p = 18f4520 #include P18f4520.inc delay res 1 ORG 00h GOTO MAIN ORG 08H GOTO ISR_HIGH ORG 18H GOTO ISR_LOW MAIN CALL INIT CALL INIT_TIMER0 CALL INIT_EXTERNAL_INTERRUPT GOTO $ INIT ;assigning PORTB is a digital output MOVLW 0x0e MOVWF ADCON1 BCF TRISB,1 BCF PORTB,1 BCF TRISB,2 BCF PORTB,2 BCF TRISB,3 BCF PORTB,3 MOVLW .10 MOVWF delay RETURN INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BCF INTCON2,TMR0IP BSF INTCON,TMR0IF BSF INTCON,TMR0IE BSF INTCON,GIEH ;set the global interrupt enable bits BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN INIT_EXTERNAL_INTERRUPT
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;Interrupt priority for INT1 and INT2 is determined by the ;value contained in the interrupt priority bits, INT1IP ;(INTCON3<6>) and INT2IP (INTCON3<7>). There is ;no priority bit associated with INT0. It is always a high ;priority interrupt source BCF BCF BSF BSF BSF RETURN INTCON2,INTEDG0 INTCON,INT0IF INTCON,INT0IE INTCON,GIEH ;set the global interrupt enable bits INTCON,GIEL

EXTERNAL_INTERUPT_ROUTINE BCF INTCON,INT0IF BSF PORTB,1 BSF PORTB,2 BSF PORTB,3 MOVLW .10 MOVWF delay RETURN TIMER0_INTERRUPT_ROUTINE ; BSF INTCON,INT0IF BCF INTCON,TMR0IF DECFSZ delay,1 GOTO TIMER0_ROUTINE_1 BCF PORTB,1 BCF PORTB,2 BCF PORTB,3 MOVLW .10 MOVWF delay TIMER0_ROUTINE_1 BCF T0CON,TMR0ON MOVLW 0x3c MOVWF TMR0H MOVLW 0xaf MOVWF TMR0L BSF T0CON,TMR0ON RETURN ISR_HIGH
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CALL EXTERNAL_INTERUPT_ROUTINE RETFIE ISR_LOW CALL TIMER0_INTERRUPT_ROUTINE RETFIE END Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung mch chy chng trnh nh hng dn chng 1.

3.4 LCD k t 2x16

3.4.1 Hnh dng v ngha cc chn:

Tn chn GND VCC VEE RS R/W E D0 D1 D2 D3 D4 D5 D6

Mc logic 0 1 0 1 0 1 T 1 xung 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 31

M t t (0V) Ngun (+5V) Chnh contrast (0 VCC) D0-D7 l gi tr lnh D0-D7 l gi tr d liu Ghi gi tr vo LCD c gi tr ra t LCD Cm truy xut LCD LCD hot ng trao i d liu D liu/Lnh a vo LCD Bit 0/LSB Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Thc hnh Vi x l

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Khoa KH & KTMT Bit7/MSB Chn Anode ca n nn Chn Cathode ca n nn

3.4.2 T chc vng nh ca LCD

Display Data Ram (DDRAM): lu tr m k t hin th ra mn hnh. M ny ging vi m ASCII. C tt c 80 nh DDRAM. Vng hin th tng ng vi ca s gm 16 nh hng u tin v 16 nh hng th hai. Chng ta c th to hiu ng dch ch bng cch s dng lnh dch (m t sau), khi ca s hin th s dch em li hiu ng dch ch.

Character Generator Ram (CGRAM): lu tr tm mu k t do ngi dng nh ngha. Tm mu k t ny tng ng vi cc m k t D7-D0 = 0000*D2D1D0 (* mang gi tr ty nh 0 hay 1).

Character Generator Rom (CGROM): lu tr cng cc mu k t tng ng vi m ASCII. Di y l bng nh x gia m k t v mu k t.

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Chng ta mun hin th ch CE gia hng u tin, gi s ca s hin th ang bt u t v tr u tin (hng th nht hin th d liu ca nh t 0x00 n 0x0f, hng th hai hin th d liu ca nh t 0x40 n 0x4f, y l v tr home). Gi tr ca nh 0x07 l 0x43 (k t C), ca nh 0x08 l 0x45 (k t E). Chng ta mun hin th ch gi hng th hai, gi s c s hin th ang v tr home. Trong bng mu k t chng ta thy khng c mu . Lc ny chng ta phi nh ngha mu 5x8 im, gm c 8 byte, sau lu vo v tr ca mu k t CGRAM th nht. Lc ny gi tr ca nh 0x47 l 0x00 hoc 0x08 (v tr ca mu k t CGRAM th nht ).

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3.4.3 Cc lnh giao tip vi LCD

Lnh Clear display Return home Entry mode set Display on/off control Cursor/Display shift Function set Set CGRAM address Set DDRAM address Read BUSY flag (BF) Write to DDRAM or CGRAM Read from DDRAM or CGRAM RS 0 0 0 0 0 0 0 0 0 1 1 RW 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 1 BF D7 D7 D6 D6 D5 D5 D6 0 0 0 0 0 0 1 D5 0 0 0 0 0 1 D4 0 0 0 0 1 DL D3 0 0 0 1 S/ C N D2 0 0 1 D R/ L F D1 0 1 D0 1 * Thi gian thc thi 1.52ms 1.52ms 37s 37s 37s 37s 37s 37s 0s D1 D1 D0 D0 43s 43s

I/D SH C * * B * *

CGRAM address DDRAM address DDRAM address D4 D4 D3 D3 D2 D2

Cc bit trn bng tm tt cc lnh c ngha nh sau: I/D SH S/C R/L DL N F BF 1 1 1 1 1 1 1 1 Increment Entire shift on Display shift Shift to the Right 8 bits 2 Lines 5x10 dots Font Internally operating 0 0 0 0 0 0 0 0 Decrement Entire shift off Cursor move Shift to the Left 4 bits 1 Lines 5x8 dots Font Can accept instruction

Trn kit th nghim LCD k t 2x16 c kt ni vo Port D ch 4 bit. ch 4 bit, c hay ghi mt byte phi tin hnh ci d liu hai ln, ln u l 4 bit cao, ln th hai l 4 bit thp.

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3.4.4 Khi to LCD

S kt ni LCD:
VCC RD7 R20 2.2K Q2 MMBT2222A LCD1 Vss Vdd Vee RS R/W E D0 D1 D2 D3 D4 D5 D6 D7 A K

RD4 RD5 RD6

RD0 RD1 RD2 RD3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Trc khi xut k t ra mn hnh LCD, LCD controller phi c khi to khi mi c cp ngun. Trnh t khi to nh lc sau. Trn lc , lnh Display clear c gi tr 0x01 c gi hai ln, ln u l 4 bit cao c gi tr 0x0, ln th hai l bn bit thp c gi tr 0x01. Lnh Function set gi hai ln gi tr 0x2.

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Bt ngun (chn PD7 out ra mc logic 1)

Ch ti thiu 30ms (i VDD > 4.5V)

Ch ti thiu 39s

Gi lnh Function set RS RW D7 0 0 0 0 0 0 0 0 N D6 0 0 F D5 1 1 * D4 0 0 *

Gi lnh Display clear RS RW D7 0 0 0 0 0 0 D6 0 0 D5 0 0 D4 0 1

Gi lnh Entry mode set Ch ti thiu 39s RS RW D7 0 Gi lnh Display on/off control RS RW D7 0 0 0 0 0 1 D6 0 D D5 0 C D4 0 B Kt thc khi to 0 0 0 0 0 D6 0 1 D5 0 I/D D4 0 SH

3.5 Cc bc hin thc yu cu 2

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l LCD, to file lcd.asm v chn chip 18f4520. Ta c hnh sau:

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Bc 2: Include file p18f4520.inc vo file lcd.asm Bc 3: Da vo s nguyn l kt ni vi iu khin vi LCD k t ta define li d dng s dng hn. #define LCD_D4 PORTD, 0 ; LCD data bits #define LCD_D5 PORTD, 1 #define LCD_D6 PORTD, 2 #define LCD_D7 PORTD, 3 #define LCD_D PORTD #define #define #define #define #define #define #define #define #define #define #define #define LCD_D4_DIR LCD_D5_DIR LCD_D6_DIR LCD_D7_DIR LCD_E LCD_RW LCD_RS LCD_E_DIR LCD_RW_DIR LCD_RS_DIR LCD_INS LCD_DATA TRISD, 0 TRISD, 1 TRISD, 2 TRISD, 3 PORTD, 6 PORTD, 5 PORTD, 4 TRISD, 6 TRISD, 5 TRISD, 4 0 1 ; LCD data bits

; LCD E clock ; LCD read/write line ; LCD register select line

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Bc 4: Vit hm xut d liu 4 bt ra cho LCD k t : LCDWriteNibble btfss STATUS, C ; Set the register select bcf LCD_RS btfsc STATUS, C bsf LCD_RS bcf LCD_RW ; Set write mode bcf LCD_D4_DIR ; Set data bits to outputs bcf LCD_D5_DIR bcf LCD_D6_DIR bcf LCD_D7_DIR NOP ; Small delay NOP bsf LCD_E ; Setup to clock data NOP ; Small delay NOP btfss temp_wr, 7 ; Set high nibble bcf LCD_D7 btfsc temp_wr, 7 bsf LCD_D7 btfss temp_wr, 6 bcf LCD_D6 btfsc temp_wr, 6 bsf LCD_D6 btfss temp_wr, 5 bcf LCD_D5 btfsc temp_wr, 5 bsf LCD_D5 btfss temp_wr, 4 bcf LCD_D4 btfsc temp_wr, 4 bsf LCD_D4 NOP ; Small delay NOP bcf LCD_E ; Send the data return Bc 5: Tip tc ta vit hm truyn lnh (command) cho lcd k t. Macro LCDWrite_command c mt i s l data, ta dng i s ny truyn lnh cho lcd. y, LCD ta thit lp ch 4 bt nn khi truyn lnh n cng ch cn 4 bit iu khin. Trong macro ny data1 ch s dng 4 bit cao m thi.
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LCDWrite_command macro data1 bcf LCD_RS ;write command movlw data1 movwf temp_wr call LCDWriteNibble movlw 0xF movwf delay rcall DelayXCycles endm Bc 6: Sau vit thm hm truyn d liu hin th ra LCD k t. Macro LCDWrite_data c mt i s l data1, ta dng macro vi i s tng ng truyn data hin th ln mn hnh LCD. Nh trn ta cp, trong ng dng ny ta s dng LCD ch 4 bt, nn data y c truyn theo th t l 4 bit cao truyn trc sau 4 bt thp c truyn sau. LCDWrite_data macro data1 bsf LCD_RS ;write data movff data1,temp_wr rcall LCDBusy bsf STATUS, C rcall LCDWrite movlw 0x0F ;Wait ~100us @ 20 MHz movwf delay rcall DelayXCycles endm Bc 7: Hm quan trng nht ca LCD k t chnh l hm khi to LCD. Trc khi s dng c lcd ta phi khi to cho n theo nh gin khi to lcd trn phn hng dn l thuyt. Ngoi ra do thit k mch, LCD c th hin th bnh thng trc tin ta phi bt ngun ca LCD ln, chn ngun ca LCD c iu khin bi PortD.7 tch cc mc cao, nn trc khi mun s dng LCD ta phi bt PortD.7 ln 1. LCDInit1 CALL Init_variable bsf bcf bsf bcf bcf bcf movlw movwf
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LATD,7 TRISD,7 LATD,7 LCD_E_DIR LCD_RW_DIR LCD_RS_DIR b'00001110' ADCON1

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;configure control lines

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movlw movwf lil11 movlw movwf rcall decfsz bra

0xff COUNTER 0xFF delay DelayXCycles COUNTER,F lil11 0x20 0x20 0x80 0x00 0xf0 0x00 0x10 0x00 0x20

; Wait ~15ms @ 20 MHz

LCDWrite_command LCDWrite_command LCDWrite_command LCDWrite_command LCDWrite_command LCDWrite_command LCDWrite_command call LongDelay ;2ms call LongDelay ;2ms LCDWrite_command LCDWrite_command

call Lcd_clear return Bc 8: n y ta c th vit chng trnh hin th k t ln lcd k t. tng thc hin y l lc u ta khai bo mt vng nh gm 32 nh tng ng vi 32 v tr trn lcd k t. Hm lcd_display ca chng ta s thc hin mt vic n gin l ly d liu cha trong vng nh ny ra hin th ln lcd k t. Cn ngi dng mun hin th ln lcd th ch cn update gi tr vo vng nh ny l xong. Lcd_display movff INDF0,temp_wr1 movlw .0 cpfseq temp_wr1 goto Lcd_display1 movlw 0x20 movwf temp_wr1 Lcd_display1 LCDWrite_data temp_wr1 INCF CLRF ADDWFC
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FSR0L WREG FSR0H,F

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MOVLW cpfseq goto ;display line1 INCF MOVLW CPFSEQ GOTO CLRF MOVLW MOVWF Set_cursor goto ;display line2 Lcd_display_line2 INCF MOVLW CPFSEQ GOTO CLRF MOVLW MOVWF Movlw Movwf Movlw Movwf Set_cursor Exit_Lcd_display RETURN

.0 flag_line Lcd_display_line2 index_of_lcd MAX_INDEX index_of_lcd Exit_Lcd_display Index_of_lcd .1 flag_line .0,.1 Exit_Lcd_display

index_of_lcd MAX_INDEX index_of_lcd Exit_Lcd_display Index_of_lcd .0 flag_line HIGH Lcd_buffer FSR0H LOW Lcd_buffer FSR0L .0, .0

3.6 Bi tp
Vit chng trnh chy ch qua LCD. Vit chng trnh thay i ch hin th trn LCD khi nhn nt.

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Bi 4 :

Kho st b nh thi

Ni dung: Kho st cc ch hot ng ca cc b nh thi. Kho st cc thanh ghi iu khin b nh thi. S dng b nh thi trong chng trnh. Yu cu: S dng b timer 1 c sau 1s m ln 1 n v ri xut gi tr ra led n. Vit chng trnh s dng b nh thi lm ng h iu khin n giao thng.

4.1 Cc bc hin thc yu cu 1

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l timer v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file timer.asm Bc 3: Khi to PortB l output. Cn gn gi tr cho thanh ghi ADCON1 v thanh ghi ny c chc nng chn cc PORT c chc nng l input/output digital hay l input Analog. Do , trc khi s dng cc port ta phi kim tra xem thanh ghi ADCON1 cu hnh ng cha. INIT

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;assigning PORTB is a digital output MOVLW 0x0e MOVWF ADCON1 ; setup portb for outputs CLRF TRISB CLRF PORTB RETURN Bc 4: Khi to cc vector ngt. a ch 0x00 bt u chng trnh chnh. a ch 0x08 a ch ca vector ngt c u tin cao a ch 0x18 a ch ca vector ngt c u tin thp. Ch : VK Pic ch c 2 u tin khi ngt xy ra nh ni trn. org 0x0 goto MAIN ORG GOTO ORG GOTO MAIN GOTO MAIN ;interrupt sevice routine for high priority interrupt ISR_HIGH RETFIE ;interrupt sevice routine for low priority interrupt ISR_LOW RETFIE Bc 5: Khi to ngt timer 0 c sau 100ms th vo ngt mt ln. Thi gian timer m ln 1 n v c tnh bng cng thc T = 1/((Focs/4)/2) = 1/((4Mhz/4)/2) = 0.5us Nn khi ta gi tr trong cc thanh ghi ca timer gi tr 50000 th c sau 100ms, timer s ngt mt ln. tnh c gi tr s Hex gn cho thanh ghi m ca timer ta lm nh sau : u tin i s 50000 sang s hex: C350. Sau ly FFFF C350 = 3CAF. C c s ny ri ta ly byte cao lu vo TMR0H, byte thp lu vo TMR0L. 0x000008 ; high priority interrupt vector ISR_HIGH 0x000018 ISR_LOW ; low priority interrupt vector

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;=====================; ; Initializing timer 0: 16BIT ;=====================; INIT_TIMER0 ;enable priority interrupts. BSF RCON,IPEN ;set Timer0 as a HIGH priority interrupt source BSF INTCON2,TMR0IP ;Clear the Timer0 interrupt flag. BCF INTCON,TMR0IF ;enable Timer0 interrupts BSF INTCON,TMR0IE ;set the global interrupt enable bits BSF INTCON,GIEH BSF INTCON,GIEL ;initialize timer0: 10ms CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xaf MOVWF TMR0L ;turn on timer0 BSF T0CON,TMR0ON RETURN Bc 6: Vit chng trnh con chy trong timer, sau 1s tng gi tr hin th ra ngoi led n. V c 100ms th c ngt mt ln, do sau 1s ta tng ln mt gi tr th cn 10 ln ngt nh vy, nn ban u ta phi khi to cho bin delay = 10. V y l hm chnh thc hin chc nng ca bi tp 1. TIMER0_ROUTINE BCF INTCON,TMR0IF DECFSZ delay,1 GOTO TIMER0_ROUTINE_1 INCF PORTB MOVLW .10 MOVWF delay TIMER0_ROUTINE_1 BCF T0CON,TMR0ON
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MOVLW MOVWF MOVLW MOVWF BSF RETURN

0x3c TMR0H 0xaf TMR0L T0CON,TMR0ON

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4.2 Chng trnh mu

;=====================================; ; Name: timer.asm ; Project: S dng b timer 1 c sau 1s m ln 1 n v ri xut gi tr ra led
; n.

; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 8 - 6 - 2009 ;======================================; list p=18f4520 #include p18f4520.inc delay res 1 org 0x0 goto MAIN ORG GOTO ORG GOTO MAIN CALL CALL GOTO INIT INIT_TIMER0 $ 0x000008 ISR_HIGH 0x000018 ISR_LOW ; high priority interrupt vector ; low priority interrupt vector

INIT ;assigning PORTB is a digital output movlw 0x0e movwf ADCON1 ; setup portb for outputs clrf TRISB clrf PORTB MOVLW .10 MOVWF delay return

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;===========================================; ; Initializing timer 0: 16BIT ;===========================================; ;to calculate the accurately timing scheduling of timer 0. ;we have to know something ;1. External clock: 4Mhz (this ex) ;2. Timer0 Prescaler: 1/2 (this ex) ;cycle of timer0 = 1/((Fexternal/4)/2) = 0.5us INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BSF INTCON2,TMR0IP BSF INTCON,TMR0IF BSF INTCON,TMR0IE BSF INTCON,GIEH BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN ISR_HIGH ; high priority isr BTFSC INTCON,TMR0IF GOTO ISR_TIMER0_HIGH ISR_TIMER0_HIGH CALL TIMER0_ROUTINE GOTO EXIT_ISR_HIGH EXIT_ISR_HIGH RETFIE ;===============================================; ; interrupt service routine for low priority interrupts ;===============================================; ISR_LOW BTFSC INTCON,TMR0IF GOTO ISR_TIMER0_LOW ISR_TIMER0_LOW CALL TIMER0_ROUTINE GOTO EXIT_ISR_LOW EXIT_ISR_LOW RETFIE

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;===============================================; ;===============================================; ;===============================================; ;===============================================; TIMER0_ROUTINE BCF INTCON,TMR0IF DECFSZ delay,1 GOTO TIMER0_ROUTINE_1 INCF PORTB MOVLW .10 MOVWF delay TIMER0_ROUTINE_1 BCF T0CON,TMR0ON MOVLW 0x3c MOVWF TMR0H MOVLW 0xaf MOVWF TMR0L BSF T0CON,TMR0ON RETURN END
Yu cu 2 ca bi thc hnh ny xem nh bi tp

4.3 Bi tp
Dng b nh thi to xung vung chu k 10ms, duty cycle 30%.

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Bi 5 :

K thut qut ma trn phm

Ni dung: Kho st cu to, hot ng ca ma trn phm. Tm hiu k thut ly d liu t ma trn phm, chng rung phm nhn. Yu cu: Vit chng trnh ly d liu t phm nhn sau hin th gi tr ca phm nhn ra led n.

5.1 Kt ni mch ma trn phm

R1 ROW1 1 10K R2 ROW2 10K R3 ROW3 10K R4 ROW4 10K 2 1 SW4 3 4 2 1 SW8 3 4 2 1 SW12 3 4 2 1 SW16 3 4 2 1 SW3 3 4 2 1 SW7 3 4 2 1 SW11 3 4 2 1 SW15 3 4 2 1 SW2 3 4 2 1 SW6 3 4 2 1 SW10 3 4 2 1 SW14 3 4 SW1 4 1 SW5 4 1 SW9 4 1 SW13 4

2 3 COLUMN1 VCC R5 100R COL1

2 3 COLUMN2 R6 100R COL2 J4 COL2 COL4 ROW2 ROW4 1 3 5 7 9 11 RD1 RD0 RD3 RD2 RD5 RD4 RD7 RD6 RE1 RE0 GNDVCC CON12A 2 4 6 8 10 12

2 3 COLUMN3 R7 100R COL3

2 3 COLUMN4 R8 100R COL4

COL1 COL3 ROW1 ROW3 VCC

Ma trn phm gm 16 phm nhn kt ni chung 4 hng v 4 ct. Bn ct COL1COL4 ni vo bn bit thp ca Port D D0-D3. Bn hng ROW1-ROW4 ni vo bn bit cao ca Port D D4-D7. Bn hng c ni vi in tr ko ln m bo mc logic 1 khi phm khng c nhn.

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5.2 Cc bc hin thc

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l Key v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file key.asm Bc 3: Define cc port tng ng vi hng v ct ca ma trn phm d

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s dng sau ny. Da vo s mch ta nh ngha nh sau: #define COLUMN_1 PORTD, 0 #define COLUMN_2 PORTD, 1 #define COLUMN_3 PORTD, 2 #define COLUMN_4 PORTD, 3 #define #define #define #define ROW_1 ROW_2 ROW_3 ROW_4 PORTD, 4 PORTD, 5 PORTD, 6 PORTD, 7

Bc 4: Khi to input v output cho cc port tng ng. y column l output, cn row l input. Portb dng hin th led n cng c cu hnh l output. INIT_IO ;assigning PORTB is a digital output MOVLW 0x0F MOVWF ADCON1 ; setup portb for outputs CLRF TRISB CLRF PORTB MOVLW 0x0F MOVWF TRISD MOVLW 0xFF MOVWF PORTD RETURN Bc 5: Khi to timer, phn ny chng ta hc t chng 4, ta c th c mt hm khi to timer n gin nh sau: INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BSF INTCON2,TMR0IP BSF INTCON,TMR0IF BSF INTCON,TMR0IE BSF INTCON,GIEH BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN Bc 6: Vit hm Get_key vi 2 i s. i s th nht c tn l temp_wr,
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chnh l gi tr output tng ng vi cc ct ca ma trn phm, i s th 2 c tn l col chnh l gi tr bt u ca mi ct. V d ct 1 th gi tr bng 0, ct 2 th gi tr bng 1, ct 3 th gi tr bng 2 v ct 4 th gi tr bng 3. GET_KEY BTFSS temp_wr, 0 BCF COLUMN_1 BTFSS temp_wr, 0 BSF COLUMN_1 BTFSS temp_wr, 1 BCF COLUMN_2 BTFSS temp_wr, 1 BSF COLUMN_2 BTFSS temp_wr, 2 BCF COLUMN_3 BTFSS temp_wr, 2 BSF COLUMN_3 BTFSS temp_wr, 3 BCF COLUMN_4 BTFSS temp_wr, 3 BSF COLUMN_4 BTFSC GOTO MOVLW MOVWF GOTO PORTD,4 ;BIT TEST F, SKIP IF SET NEXT_BUTTON_1 .0 KeyReg1 EXIT_GET_KEY

NEXT_BUTTON_1 BTFSC PORTD,5 ;BIT TEST F, SKIP IF SET GOTO NEXT_BUTTON_2 MOVLW .4 MOVWF KeyReg1 GOTO EXIT_GET_KEY NEXT_BUTTON_2 BTFSC PORTD,6 ;BIT TEST F, SKIP IF SET GOTO NEXT_BUTTON_3 MOVLW .8 MOVWF KeyReg1 GOTO EXIT_GET_KEY NEXT_BUTTON_3 BTFSC PORTD,7 ;BIT TEST F, SKIP IF SET GOTO NEXT_BUTTON_2 MOVLW .12
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MOVWF

KeyReg1

EXIT_GET_KEY MOVFF COL,W ADDWF KeyReg1,d RETURN Bc 7: Da vo hm Get_key trn ta c th hon thin hm Scan_button mt cch d dng. y ta nhc li cch m s l phm nhn d liu ngc tr v l ti mt thi im ch cho mt ct c tch cc ( y l mc 0) sau c ngc gi tr t cc hng. Hng 1 tng ng vi ct 1 l s 0, tng t hng 2 vi ct 1 l s 4 Khi nhn phm th s c hin tng rung phm, gii quyt trng hp ny ta c mt cch gii quyt y l c d liu 3 ln lin tip mi ln cch nhau 10ms, sau so snh 3 gi tr c c. Nu 3 gi tr bng nhau th ta xem nh c mt nt nhn c nhn. Trong hm Scan_button ta dng 3 bin KeyReg1, KeyReg2 v KeyReg3 lu gi tr ca 3 ln c d liu lin tip, khi kim tra 3 bin ny c gi tr bng nhau th ta s lu vo bin KeyReg v xut d liu ra PORTB. Scan_button MOVFF MOVFF MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF
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KeyReg2,KeyReg3 KeyReg1,KeyReg2 0x0E temp_wr .0 COL GET_KEY 0x0D temp_wr .1 COL GET_KEY 0x0B temp_wr .2 COL GET_KEY 0x07 temp_wr
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MOVLW MOVWF CALL MOVFF CPFSEQ GOTO CPFSEQ GOTO MOVFF CPFSEQ GOTO GOTO Scan_button1 MOVFF CALL

.3 COL GET_KEY KeyReg1,W KeyReg2 EXIT_SCAN_BUTTON KeyReg3 EXIT_SCAN_BUTTON KeyReg,W KeyReg1 Scan_button1 EXIT_SCAN_BUTTON KeyReg1,KeyReg Button_process

EXIT_SCAN_BUTTON RETURN Bc 8: Nh gii thut trn ni l c mi 10ms th ta c d liu mt ln, cho iu ny c thc hin d dng th ta phi dng n interrupt timer. Ta khi to mt interrupt timer c sau 10ms th interrupt mt ln. lm c iu ny cc bn c th xem li chng timer c th lm vic mt cch d dng. y ch gii thiu cho cc bn l hm Timer0_routine, hm ny c gi trong interrupt timer v trong hm ny ta gi hm Scan_button trn. TIMER0_ROUTINE BCF BCF MOVLW MOVWF MOVLW MOVWF BSF CALL RETURN INTCON,TMR0IF T0CON,TMR0ON 0x3c TMR0H 0xaf TMR0L T0CON,TMR0ON SCAN_BUTTON

5.3 Bi tp
Ci tin hm chng rung phm, khi nhn 1 phm th phi sau 1 thi gian TimeOutForKey th mi tch cc phm nhn . Vit ng dng ng h casio n gin (hin th gi, ngy, cho php chnh sa

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Trng H. Bch Khoa TP.HCM ngy gi) s dng ma trn phm v LCD.

Khoa KH & KTMT

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Bi 6 :

K thut qut LED

Ni dung: Kho st cu to, hot ng ca LED 7 on, LED ma trn. Tm hiu k thut qut LED 7 on v LED ma trn. Yu cu: Vit chng trnh cho php hin th gi tr ra led 7 on v led ma trn.

6.1 Cu to LED 7 on v LED ma trn

LED 7 on gm c 7 on c nh du: a, b, c, d, e, f, g v mt im dp.

LED 7 on c hai loi l Common Anode v Common Cathode, tng ng cc LED ni chung Anode hay ni chung Cathode.

LED ma trn 8x8 hai mu c b tr thnh 8 hng v 8 ct. Mi im c hai LED.

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Cc LED trn cng mt hng ni chung Anode, cc LED cng loi trn cng mt ct ni chung Cathode.

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6.2 Kt ni mch
ENABLE_LED1 3 8 3 LED1 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 LED2 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 ENABLE_LED2 8 3 LED3 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 ENABLE_LED3 8 3 Vcc LED4 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 ENABLE_LED4 8

Vcc

Vcc

Vcc

Vcc

Vcc

Vcc

a b c d e f g dot

8.
Green.1

a b c d e f g dot

8.
Green.2 Row.2 Red.2

a b c d e f g dot

8.
Green.4 Row.4 Red.4

a b c d e f g dot

8.

led7

led7 Green.3

led7

led7

Row.1

24 GR1

23 RD1

22 RW1

21 GR2

20 RD2

19 RW2

18 GR3

17 RD3

Row.3

Red.1

Red.3

16 RW3

15 GR4

14 RD4

13 RW4

LED 8x8x2

ML1

GR5

GR6

GR7

GR8

RD5

RD6

RD7

RW5

RW6

RW7

RD8

1 Green.5

3 Row.5

4 Green.6

6 Row.6

7 Green.7

9 Row.7

10 Green.8

11

12 Row.8

Red.5

Red.6

Red.7

Mch LED m rng gm c 4 LED 7 on v 1 LED ma trn hai mu xanh . Mch c ni vo mt phn ca Port PICtail. D liu c dch ni tip v c ci bi IC 74HC595, TPIC6595. Module SPI ca PIC m nhn vic dch d liu ni tip thng qua chn d liu SDO v chn clock dch SCK. Sau khi dch 4 byte, tn hiu LATCH chuyn t mc 0 ln mc 1 s y d liu ca 4 byte tm ra 4 byte ng ra QA-QH tng ng. Tn hiu CLR_DISP tch cc mc 0 khng cho php hin th.

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RW8

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U1 SDO LATCH SCK VCC CLR_DISP 3 12 13 8 9 SDI TPIC6595 SDO 18 4 5 6 7 14 15 16 17 330 330 330 330 330 330 330 330 R1 R2 R3 R4 R5 R6 R7 R8 Red.1 Red.2 Red.3 Red.4 Red.5 Red.6 Red.7 Red.8

Khoa KH & KTMT

RCLK DRAIN0 SRCLK DRAIN1 DRAIN2 SRCLR DRAIN3 G DRAIN4 DRAIN5 DRAIN6 DRAIN7

3 LATCH SCK VCC CLR_DISP 12 13 8 9

U2 SDI

TPIC6595 SDO

18 4 5 6 7 14 15 16 17 100 100 100 100 100 100 100 100 R9 R10 R11 R12 R13 R14 R15 R16 Green.1 Green.2 Green.3 Green.4 Green.5 Green.6 Green.7 Green.8

RCLK DRAIN0 SRCLK DRAIN1 DRAIN2 SRCLR DRAIN3 G DRAIN4 DRAIN5 DRAIN6 DRAIN7

SDO SCK

3 LATCH SCK VCC CLR_DISP 12 13 8 9

U3 SDI

TPIC6595 SDO

18 4 5 6 7 14 15 16 17 330 330 330 330 330 330 330 330 R17 R18 R19 R20 R21 R22 R23 R24 A B C D E F G DOT

LATCH CLR_DISP

RCLK DRAIN0 SRCLK DRAIN1 DRAIN2 SRCLR DRAIN3 G DRAIN4 DRAIN5 DRAIN6 DRAIN7

VCC

12 11 10 9 8 7 6 5 4 3 2 1

PICtail RA3 RC5 RC4 RC3 RA0 RA1 RA2 RC0 RC1 RC2 +5V GND CON12

LATCH SCK VCC

14 12 11 10 13

U4 SDI

74HC595 SDO QA QB QC QD QE QF QG QH

9 15 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 10

U3

VCC 18 17 16 15 14 13 12 11 Row.1 Row.2 Row.3 Row.4 Row.5 Row.6 Row.7 Row.8 ENABLE_LED1 ENABLE_LED2 ENABLE_LED3 ENABLE_LED4

RCLK SRCLK CLR G

IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8

V+

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8

COM UDN2981

6.3 Cc thanh ghi lin quan v cch iu khin

- Thanh ghi trng thi SSPSTAT:

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- Thanh ghi iu khin SSPCON1:

- S khi module Synchronous Serial Port:

Vi s mch trn, mi ln c mt hng LED LED ma trn hay mt con LED 7 on hin th d liu. Li dng hin tng lu nh ca mt, d liu ca mi hng LED ma trn hay mi con LED 7 on c xut ra tun t hng (con) ny n hng (con) khc, chng ta s thy c hnh nh ca c mn hnh ma trn LED hay ca c 4 con LED 7 on. Khi tt c cc hng LED ma trn v tc c cc con LED 7 on c hin th (qut) qua mt ln, ta ni hin th mt frame. mt khng cm thy hnh nh b rung th s ln hin th frame trong mt giy phi ln hn 24 ln (thng l 30 ln). u tin tn hiu CLR_DISP tch cc (mc 0) khng cho LED hin th, sau dch bn byte d liu, tn hiu LATCH chuyn t mc 0 ln mc 1 a d liu mong mun sn sn ng ra, cui cng a tn hiu CLR_DISP ln mc 1 cho php LED hin th d liu mong mun. C nh vy lp li chu trnh ny. B mn K Thut My Tnh 60 Thc hnh Vi x l

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Bn byte d liu c dch ra mi ln c ngha tng ng l d liu ca mt hng LED , d liu ca mt hng LED xanh, d liu ca mt con LED 7 on, iu khin hng (con) LED no hin th. Cch iu khin c minh ha thng qua hnh sau :

Gi tr ca byte control ch cha nhiu nht mt bit 1. Nh hnh v, cn 12 ln xut d liu (4 byte) cho 1 frame gm c LED ma trn v LED 7 on, 8 ln xut d liu cho 1 frame gm ch c LED ma trn (khng quan tm ni dung hin th LED 7 on), 4 B mn K Thut My Tnh 61 Thc hnh Vi x l

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ln xut d liu cho 1 frame gm ch c LED 7 on(khng quan tm ni dung hin th LED ma trn).

6.4 Cc bc hin thc.

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l Led v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file Led_matran.asm Bc 3: Khai bo cc buffer cn thit vit driver cho led. V y ta vit driver nn mi ngi khi s dng nhng module ny s khng s dng nhng hm m chng ta vit trong ny ch c th thao tc trn cc buffer m thi. GREEN_SCREEN_BUFFER RES .8 RED_SCREEN_BUFFER RES .8 SEVEN_LED_BUFFER RES .8 COLUMN_BUFFER RES .8 INDEX_OF_BUFFER RED_DATA GREEN_DATA SEVEN_LED_DATA COLUMN_DATA RES RES RES RES RES .1 .1 .1 .1 .1

Bc 4: Ngoi ra nhn vo mch ta c th d dng nhn thy c rng d liu ca chng ta c truyn theo kiu truyn ng b ni tip, chnh xc hn y ngi ta s dng chc nng SPI truyn d liu. Do ta phi cu hnh cho chip lm sao c th hot ng c ch SPI ny. INIT_SPI CLRF SSPCON1 ;SET Fspi = f/4 BSF SSPCON1,5 ;ENALBLE SPI MODE BCF TRISC,5
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BCF TRISC,3 RETURN Trn y ta mi ch khi to module SPI n c th hot ng nhng nhn li s mch ta li thy c thm vi kt ni na t vi iu khin ra IC74595. IC ny hot ng c th ta cn thm mt chn to clock c th chuyn d liu ni tip ra song song ca IC ny. Ta define thm cho chn Latch ca IC 74595. #define LATCH_DIR TRISA,1 #define LATCH_DATA PORTA,1 ng thi khi to cc PORT lin quan: INIT MOVLW 0x0F MOVWF ADCON1 BCF LATCH_DIR BCF LATCH_DATA CLRF INDEX_OF_BUFFER RETURN Bc 5: Ngoi ra thc hin c bi ny khng th no thiu timer c, v hin th ra led ma trn ta phi qut tng ct led trn ma trn led. Khi nhn vo cu to ca ma trn led ta thy hin th c mt hnh g trn ma trn led th ta phi qut led, v ti mt thi im ch c th hin th mt ct led m thi. Nh vo hin tng lu nh mt m khi qut vi tn s cao th mt ta s thy nh l ct sng ch khng phi chp nhy na. Vy lm sao bit c ta qut led vi tn s bao nhiu l hp l. Nh trong phim nh khi xem phim thc cht ta bit l n ang chy vi tn s l 24 hnh /s. y ta cng gi s nh vy, c mn hnh ca led cng chp nhy vi tn s l 24 hnh/s, m mi hnh ta phi qut 8 ln v c 8 ct. T ta c th suy ra tn s ta cn phi qut cho mi ct l 8x24 ln/s. T y ta c th d dng tnh c timer ca chng ta cn bao nhiu c th qut led c mt cch d dng. INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BSF INTCON2,TMR0IP BSF INTCON,TMR0IF BSF INTCON,TMR0IE BSF INTCON,GIEH BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON
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RETURN Bc 6: Ban u ta khi to cc buffer hin th cng nh qut ct led. d dng trong vic s l ta s khi to cho Column_Buffer cc gi tr tng ng lm sao, khi xut ra n ch tch cc mt ct ca led m thi. y gi s tch cc ti mi ct l tch cc mc cao th ta c th khi to cho Column_buffer cc gi tr sau: 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80. Bc 7: n y mi s chun b xong, ta c th bt u vit hm hin th d liu ra led. u tin ta s vit mt macro SPI_transmit vi i s s l gi tr byte s c truyn ni tip ra ngoi. SPI_TRANSMIT MACRO TEMP_DATA ;Has data been received (transmit complete)? BTFSS SSPSTAT, BF GOTO $-2 ;No MOVF TEMP_DATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ENDM Bc 8: Tip theo l lm sao ly d liu t cc buffer a vo cc bin tng ng xut ra led. Ta vit thm mt Macro na gm 2 i s l buffer v temp_data. Macro ny s lm nhim v l ly d liu ti v tr (c lu trong bin index_of_buffer) ca buffer lu vo temp_data. UPDATE_DATA MACRO BUFFER,TEMP_DATA MOVLW HIGH BUFFER MOVWF FSR0H MOVLW LOW BUFFER MOVWF FSR0L MOVFF INDEX_OF_BUFFER,W ADDWF FSR0L,F CLRF W ADDWFC FSR0H MOVFF INDF0,TEMP_DATA ENDM Bc 9: Nh trn gii thiu xut d liu ra led, ngoi vic dng module SPI xut d liu ta cn phi c thm mt tn hiu clock tc ng ln IC74595 th d liu ni tip ca ta mi chuyn qua song song v hin th ra led. Do ta phi vit thm mt hm to clock trn chn define khi ny l Latch_data. CLOCK_STORAGE BSF LATCH_DATA NOP NOP BCF LATCH_DATA NOP NOP
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BSF LATCH_DATA RETURN Bc 10: Cui cng l hm quan trng nht, hm ny c gi trong timer thc hin vic qut led. DISPLAY CALL INCREASING_INDEX UPDATE_DATA RED_SCREEN_BUFFER,RED_DATA UPDATE_DATA GREEN_SCREEN_BUFFER,GREEN_DATA UPDATE_DATA SEVEN_LED_BUFFER,SEVEN_LED_DATA UPDATE_DATA COLUMN_BUFFER,COLUMN_DATA SPI_TRANSMIT RED_DATA SPI_TRANSMIT GREEN_DATA SPI_TRANSMIT SEVEN_LED_DATA SPI_TRANSMIT COLUMN_DATA CALL CLOCK_STORAGE RETURN

6.5 Bi tp
Xy dng ng dng cho php s 1234 chy qua cc led 7 on. Xy dng ng dng cho php 1 dng ch chy qua led ma trn.

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Bi 7 :

Kho st b truyn nhn ni tip

Ni dung: Kho st cng COM my PC, cc thng s truyn ni tip. Kho st b truyn ni tip ca PIC. Tm hiu cch s dng chng trnh Hyper Terminal truyn nhn ni tip trn my PC. Yu cu: Vit chng trnh giao tip gia my tnh v vi iu khin PIC.

7.1 Cc bc hin thc.

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l Uart v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file uart.asm Bc 3: Khi to PortB l output, PORTC.6 l output, PORTC.7 l input. INIT_PORT CLRF LATB ; Clear PORTB output latches CLRF TRISB ; Config PORTB as all outputs BCF TRISC,6 ; Make RC6 an output
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BSF RETURN

TRISC,7

Bc 4: Khi to cc vector ngt org 00000h goto Start org 00008h goto IntVector Start GOTO IntVector RETFIE $ ; Reset Vector ; Interrupt vector

Bc 5: Khi to cho ngt UART, tc 9600baud ti tn s 4Mhz. INIT_UART MOVLW 19h ; 9600 baud @4MHz MOVWF SPBRG BSF BSF BSF BSF TXSTA,TXEN TXSTA,BRGH RCSTA,SPEN RCSTA,CREN ; Enable transmit ; Select high baud rate ; Enable Serial Port ; Enable continuous reception

BCF PIR1,RCIF ; Clear RCIF Interrupt Flag BSF PIE1,RCIE ; Set RCIE Interrupt Enable BSF INTCON,PEIE ; Enable peripheral interrupts BSF INTCON,GIE ; Enable global interrupts RETURN Bc 6: Vit chng trnh trong ngt thc hin nhim v nhn mt d liu t my tnh truyn xung sau gi li k t cho my tnh nhn li. IntVector btfss PIR1,RCIF ; Did USART cause interrupt? goto ISREnd ; No, some other interrupt movlw 06h ; Mask out unwanted bits andwf RCSTA,W ; Check for errors btfss STATUS,Z ; Was either error status bit set? goto RcvError ; Found error, flag it

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movf movwf movwf goto return RcvError bcf bsf movlw movwf goto return ISREnd retfie

RCREG,W LATB TXREG ISREnd

; Get input data ; Display on LEDs ; Echo character back ; go to end of ISR, restore context,

RCSTA,CREN ; Clear receiver status RCSTA,CREN 0FFh ; Light all LEDs PORTB ISREnd ; go to end of ISR, restore context,

7.2 Chng trnh mu

;=====================================; ; Name: uart.asm ; Project: Vit chng trnh giao tip gia my tnh v vi iu khin PIC. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 8 - 8 - 2009 ;======================================; list p=18F4520 ; set processor type include <P18f4520.INC> ;************************************************************ ; Reset and Interrupt Vectors org 00000h goto Start org 00008h goto IntVector ; Reset Vector ; Interrupt vector

;************************************************************ ; Program begins here

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org Start CALL CALL Main goto

00020h

; Beginning of program EPROM

INIT_PORT INIT_UART Main ; loop to self doing nothing LATB ; Clear PORTB output latches TRISB ; Config PORTB as all outputs TRISC,6 ; Make RC6 an output TRISC,7 ; Make RC7 an input

INIT_PORT clrf clrf bcf bsf RETURN INIT_UART movlw movwf bsf bsf bsf bsf bcf bsf bsf bsf RETURN

19h ; 9600 baud @4MHz SPBRG TXSTA,TXEN; Enable transmit TXSTA,BRGH ; Select high baud rate RCSTA,SPEN RCSTA,CREN ; Enable Serial Port ; Enable continuous reception

PIR1,RCIF ; Clear RCIF Interrupt Flag PIE1,RCIE ; Set RCIE Interrupt Enable INTCON,PEIE ; Enable peripheral interrupts INTCON,GIE; Enable global interrupts

;************************************************************ ; Interrupt Service Routine IntVector btfss goto movlw andwf btfss goto PIR1,RCIF ISREnd 06h RCSTA,W STATUS,Z RcvError ; Did USART cause interrupt? ; No, some other interrupt ; Mask out unwanted bits ; Check for errors ; Was either error status bit set? ; Found error, flag it

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movf movwf movwf goto RcvError bcf bsf movlw movwf goto ISREnd retfie end

RCREG,W LATB TXREG ISREnd

; Get input data ; Display on LEDs ; Echo character back ; go to end of ISR, restore context, return

RCSTA,CREN ; Clear receiver status RCSTA,CREN 0FFh ; Light all LEDs PORTB ISREnd ; go to end of ISR, restore context, return

7.3 Bi tp
Vit chng trnh trn PC, gi 1 chui string xung board, dng ch ny s chy qua led ma trn hoc LCD. Khi nhn 1 phm trn board nhn, s gi 1 chui string ln PC qua cng COM, vit chng trnh trn PC nhn chui string ny v in ra giao din.

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Bi 8 :

Kho st khi chuyn i A-D

Ni dung: Kho st hot ng khi chuyn i A-D. Kho st cc thanh ghi iu khin hot ng khi chuyn i A-D. Yu cu: Vit chng trnh c v hin th gi tr in p thay i bi bin tr.

8.1 Cc bc hin thc

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l a2d v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file a2d.asm Bc 3: Khi to module ADC ta c th s dng mt cch d dng. InitializeAD Movlw B'00000100' ; Make RA0,RA1,RA4 analog inputs movwf ADCON1 movlw B'11000001' ; Select RC osc, AN0 selected, movwf ADCON0 ; A/D enabled movlw 0x01 movwf ADCON2 call SetupDelay ; delay for 15 instruction cycles bsf ADCON0,GO ; Start first A/D conversion return khi to c module ADC ta ch cn quan tm ch yu ti cc thanh

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ghi ADCCON1, ADCCON0, ADCON2. Nh chng trnh khi to trn ta thy u tin phi cu hnh cho cc pin tng ng phi l chn AN0, mc nh ca cc chn ny c chc nng l Input/Output digital. Sau ta phi chn knh ADC tng ng, y ta s dng knh AD0. V mt im quan trng na chnh l bit GO trong thanh ghi ADCON0, khi bt ny c bt ln th module AD mi bt u chuyn i tn hiu. Bc 4: Tip theo l hm c gi tr ADC: Update_adc bsf ADCON0,GO ;start conversion btfsc ADCON0,GO bra $-2 movf ADRESH,W return Sau khi chuyn i tn hiu A-D, gi tr s s c lu vo thanh ghi ADRESH. n y ty vo ng dng c th m ta c th bin i gi tr ny ty theo yu cu m ta mong mun.

8.2 Bi tp
Tch hp module LCD, ly gi tr in th t bin tr hin th ln LCD. S dng module ADC ca Pic o nhit trong phng, dng LCD hin th gi tr nhit .

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Bi 9 :

Kho st cc khi chc nng c bit khc

Ni dung: Kho st khi chc nng WDT. Kho st khi chc nng PWM . Kho st cc ch hot ng ca vi iu khin. Yu cu: Vit chng trnh s dng chc nng WDT. Vit chng trnh s dng chc nng PWM iu khin sng ca LED. Vit chng trnh s dng chc nng Power control.

9.1 Cc bc hin thc PWM

Bc 1: To project mi ging nh hng dn chng 1 ly tn project l pwm v chn chip 18f4520. Ta c hnh sau:

Bc 2: Include file p18f4520.inc vo file pwm.asm. Bc 3: Tch hp module LCD vo project pwm, tham kho bi tp v LCD. Bc 4: Khi to module PWM ta c th s dng mt cch d dng. Init_pwm ;configure CCP1 module for buzzer bcf TRISC,2 movlw 0x80

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Trng H. Bch Khoa TP.HCM

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movwf movlw movwf bcf bcf

PR2 ;initialize PWM period 0x80 ;initialize PWM duty cycle CCPR1L CCP1CON,CCP1X CCP1CON,CCP1Y

;postscale 1:1, prescaler 4, Timer2 ON movlw 0x05 movwf T2CON movlw 0x0F ;turn buzzer on movwf CCP1CON return khi to chc nng pwm, u tin ta phi cu hnh cho PORTC2 l output. Tip theo khi to chu k ca PWM thng qua vic cu hnh thanh ghi PR2. Sau ta khi to duty cycle ca xung pwm bng cch cu hnh thanh ghi CCPR1L.

9.2 Chng trnh mu

;=====================================; ; Name: pwm.asm ; Project: Su dung Pwm de xuat am thanh ra loa. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 20 - 8 - 2009 ;======================================; list p=18f4520 #include "p18f4520.inc" ; vectors org bra 0x000000 START ; reset vector

;************************************************************ ; program START call Init_pwm

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Trng H. Bch Khoa TP.HCM

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goto $ Init_pwm bcf movlw movwf movlw movwf bcf bcf

TRISC,2 0x80 PR2 ;initialize PWM period 0x80 ;initialize PWM duty cycle CCPR1L CCP1CON,CCP1X CCP1CON,CCP1Y

;postscale 1:1, prescaler 4, Timer2 ON movlw 0x05 movwf T2CON movlw 0x0F ;turn buzzer on movwf CCP1CON return END

9.3 Bi tp
Tm hiu v hin thc chng trnh iu khin RC Servo.

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