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VHDL l vit tt ca cm t Very High Speed Intergrated Circuit Hardware Description Language - ngn ng m t phn cng cho cc mch tch hp tc rt cao. VHDL l ngn ng m t phn cng c pht trin dng cho chng trnh VHSIC (Very High Speed Intergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m t phn cng tiu chun v thng nht cho php pht trin th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h thng vo ng dng trong thc t. Ngn ng VHDL c ba cng ty Intermetics, IBM v Texas Instruments bt u nghin cu pht trin vo 7/1983. Phin bn u tin c cng b vo 8/1985. Sau VHDL c xut t chc IEEE xem xt thnh mt tiu chun. Nm 1987, a ra tiu chun v VHDL tiu chun IEEE-1076-1987. VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i v lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu m t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu ti liu k lng. Vi mt ngn ng m t phn cng th vic xem xt cc ti liu m t tr nn d dng hn v b ti liu c th c thc thi m phng hot ng ca h thng. Nh th ta c th xem xt ton b cc phn t ca h thng hot ng trong mt m hnh thng nht. Trc khi VHDL ra i, c nhiu ngn ng m t phn cng c s dng nhng khng c mt tiu chun thng nht. V cc ngn ng m phng phn cng c cc nh cung cp thit b pht trin, nn mang cc c trng gn vi cc thit b ca nh cung cp v thuc s hu ca nh cung cp. Trong khi , VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php thit k, b m phng hay cng ngh phn cng no. Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi vn s dng mt ngn ng duy nht. VHDL c mt s u im hn hn cc ngn ng m t phn cng khc l:
Tnh cng cng: VHDL c pht trin di s bo tr ca chnh ph M v hin nay l mt tiu chun ca IEEE, VHDL khng thuc s hu ca bt k c nhn hay t chc no. Do VHDL c h tr ca nhiu nh sn
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xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng. y l mt u im ni bt ca VHDL, gip VHDL tr nn ngy cng ph bin.
Kh nng h tr nhiu cng ngh v phng php thit k: VHDL cho php thit k bng nhiu phng php nh phng php thit k t trn xung, hay t di ln da vo cc th vin c sn. Nh vy VHDL c th phc v tt cho nhiu mc ch thit k khc nhau, t vic thit k cc phn t ph bin n vic thit k cc IC ng dng c bit (Application Specified IC). c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th c chuyn thnh cc bn tng hp mch khc nhau tu thuc vo cng ngh ch to phn cng no c s dng (dng CMOS, nMOS, hay GaAs). y cng l mt u im quan trng ca VHDL n cho php ngi thit k khng cn quan tm n cng ngh phn cng khi thit k h thng, nh th khi c mt cng ngh ch to phn cng mi ra i n c th c p dng ngay cho cc h thng thit k. Kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc h thng s (hp en) cho n mc cng. VHDL c kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m t mc cao v cc h con c m t chi tit. Kh nng trao i kt qu: V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL c th chy trn mi b m phng p ng c tiu chun VHDL v cc kt qu m t h thng c th c trao i gia cc nh thit k s dng cng c thit k khc nhau nhng cng tun theo chun VHDL. Hn na, mt nhm thit k c th trao i m t mc cao ca cc h thng con trong mt h thng; trong khi cc h con c thit k c lp. Kh nng h tr thit k mc ln v kh nng s dng li cc thit k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th s dng thit k mt h thng ln vi s tham gia ca mt nhm
nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia s thit k. VHDL cng cho php dng li cc phn c sn.
y tn hng constant_name ch ra tn ca mt hng dng generic (hng dng chung). Kiu (Type) c dng ch ra kiu d liu ca hng.
Init_value : ch ra gi tr khi to cho hng. b. Khai bo cng ( Port ): c dng khai bo cc cng vo, ra ca Entity. C php ca khai bo ny nh sau: Port ( port_name : [mode] type [:= init_value] {; port_name:[mode] type [:=init_value]}); Port_name c dng ch ra tn ca mt cng, mode ch ra hng vo ra ca tn hiu ti cng . Type ch ra kiu d liu ca mt cng v init_value ch ra gi tr khi to cho cng . Ch ! Vi VHDL khng phn bit ch hoa v ch thng, chng hn nh: xyz = xYz = XYZ.
C bn mode c s dng trong khai bo cng: - in: Ch c th c c, n ch c dng cho cc tn hiu u vo (ch c php nm bn phi php gn).
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- out: Ch c dng gn gi tr, n ch c dng cho cc cng u ra (n ch c nm bn tri ca php gn). - inout: C th c dng c v gn gi tr. N c th c nhiu hn mt hng iu khin (c th nm bn tri hoc bn phi php gn). - Buffer: C th c dng c v gn gi tr (c th nm bn tri hoc bn phi php gn). Inout l mt cng hai hng, cn Buffer l mt cng khng c hng. c. Entity_declarative_item : c dng khai bo cc hng, kiu d liu, hoc tn hiu m n c th c s dng trong khi thc hin ca mt Entity. d. V d : V d v khai bo cc cng vo ra: entity xxx is port ( A : in integer ; B : in integer ; C : out integer ; D : inout integer ; E : buffer integer) ; end xxx; architecture bhv of xxx is begin process (A,B) begin C <= A ; -- ( Cu lnh ng: A c gn cho C ). A <= B ; -- ( Cu lnh sai: A l mt u vo ). E <= D + 1; -- ( Cu lnh ng: D mode inout v vy n -- c th c gn v c ) D <= C + 1; -- ( Cu lnh sai : C l cng u ra nn khng -- th c c cho u vo ). end process; end bhv; V d v khai bo Entity:
Hnh 3.1: Thc th FULL_ADDER 1bit. Hnh 3.1 ch ra mt giao din ca mt b cng mt bit. Tn Entity ca phn t ny l FULL_ADDER. N bao gm cc cng u vo A, B v CIN. Cc cng ny c kiu d liu l kiu Bit, cn cc cng u ra SUM v COUT cng mang kiu d liu l kiu BIT. Ngn ng VHDL dng din t giao din ny nh sau: Entity FULL_ADDER is port ( A, B, CIN : in BIT; SUM, COUT : out BIT ); End FULL_ADDER ; Chng ta c th iu khin cu trc cng nh thi gian ca mt Entity bi vic s dng cc hng generic. V d sau s ch ra vic iu khin ny, trong v d ny hng N c dng ch ra s bt ca mt b cng. Trong qu trnh m phng hoc qu trnh tng hp, gi tr thc t cho mi hng dng chung generic c th b thay i. entity ADDER is generic (N : INTEGER := 4); M : TIME := 10ns); port ( A, B : in BIT_VECTOR (N -1 downto 0 ); CIN :in BIT; SUM : out BIT_VECTOR (N-1 downto 0); COUT : out BIT ); end ADDER;
process. Di y l v d ch ra kiu din t theo kiu hnh vi ca mt b cng vi tn l FULL_ADDER. architecture BEHAVIOUR of FULL_ADDER is begin process (A,B,CIN) begin if ( A ='0' and B ='0' and CIN='0' ) then SUM <= '0'; COUT <= '0' ; elsif (A='0' and B='0' and CIN='1') or (A='0' and B='1' and CIN='0') or (A='1' and B='0' and CIN='0') then SUM <= '1'; COUT <= '0' ; elsif (A='0' and B='1' and CIN='1') or (A='1' and B='0' and CIN='1') or (A='1' and B='1' and CIN='0') then SUM <= '0'; COUT <= '1'; elsif (A='1' and B='1' and CIN='1') then SUM <='1'; COUT <='1'; end if; end process; end BEHAVIOURAL;
nng logic t hp. Chng hn nh cc b cng, b so snh, b gii m, v cc cng logic nguyn thy. V d: architecture DATAFLOW of FULL_ADDER is signal S : BIT; begin S <= A xor B ; SUM <= S xor CIN after 10 ns; COUT <= (A and B ) or (S and CIN) after 5ns; end DATAFLOW;
mt Entity khc, m Entity ny bao gm mt cng XOR v mt cng AND. Giao tip ca mt b cng HALF_ADDER c dng nh sau:
Hnh 3.3: Giao tip b cng HALF_ADDER. B cng ny gm c hai u vo L1 v L2, u ra l SUM v CARRY. Kiu BIT l kiu tin nh ngha ca ngn ng VHDL, n c kiu lit k dng ch k t nh '0' v '1'.
3.1.3. Cc ng gi (Packages)
Mc ch chnh ca Package l tp hp cc phn t c th b chia s bi hai hay nhiu n v thit k (hay cc phn t c th dng chung c). N c cha cc kiu d liu, cc hng, cc chng trnh con c th dng chung gia cc thit k. Mt Package c cha hai phn chnh: - Phn khai bo Package. - Phn thn Package.
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constant PIN2PIN_DELAY:TIME:=125ns; function IN2BIT_VEC(INT_VALUE:INTEGER) return BIT_VECTOR; end EXAMPLE_PACK; v d ny tn ca package c khai bo l EXAMPLE_PACK. N c cha cc khai bo kiu, phn t, hng, v hm. Lu rng hot ng ca hm INT2BIT_VEC khng xut hin trong khai bo gi, m ch c giao tip ca hm xut hin. Vic nh ngha, hay thn ca hm ch xut hin trong thn ca ng gi ( Body Package ). Gi s rng ng gi ny c dch v to thnh mt th vin thit k v c gi l DESIGN _LIB. Xem xt vic dng mnh use s dng chng di y: library DESIGN_LIB; use DESIGN_LIB.EXAMPLE_PACK.all Entity RX is......... Mnh library DESIGN_LIB cho php th vin thit k DESIGN_LIB c php dng trong phn m t ny, iu c ngha l tn DESIGN_LIB c th c s dng. Mnh use tip theo s ly tt c cc khai bo c trong Package EXAMPLE_PACK vo trong khai bo Entity ca RX. C ngha l ta c th chn la cc khai bo t trong mt cc khai bo ca mt ng gi vo trong mt n v thit k khc. V d : library DESIGN_LIB; use DESIGN_LIB.EXAMPLE_PACK.D_FLIP_FLOP; use DESIGN_LIB.EXAMPLE_PACK.PIN2PIN_DELAY; architecture RX_STRUCTURE of RX is......... Hai mnh use v d ny nhm to ra khai bo cho D_FLIP_FLOP v khai bo hng cho PIN2PIN_DELAY c php s dng trong thn kin trc.
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package package_name is {package_declarative_item} end [package_name ]; package body package_name is {package_declarative_item} end [package_name] Mt thn package c dng lu cc nh ngha ca mt hm v th tc, m cc hm v th tc ny chng c khai bo trong phn khai bo package tng ng. V vy phn thn package lun c kt hp vi phn khai bo ca chng, hn na mt phn khai bo package lun c t nht mt phn thn package kt hp vi chng. V d: package EX_PKG is subtype INT8 is integer range 0 to 255; constant zero : INT8:=0; procedure Incrementer (variable Count : inout INT8); end EX_PKG; package body EX_PKG is procedure Incrementer (variable Data : inout INT8) is begin if (Count >= MAX ) then Count:=ZERO; else Count:= Count +1; end if; end Incrementer; end EX_PKG;
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(Component) trong mt thit k dng cu trc. C php khai bo ca Configuration ny nh sau: Configuration configuration_name of entity_name is {configuration_decalarative_part} For block_specification {use_cluse} {configuration_item} end for; Vi mt Entity ca b cng FULL_ADDER nh gii thiu phn trn, v d ny ta c th s dng chng trong php nh cu hnh nh sau: configuration FADD_CONFIG of FULL_ADDER is For STRUCTURE for HA1, HA2 : HALF_ADDER use entity burcin.HALF_ADDER(structure); for OR1: OR_GATE use Entity burcin.OR_GATE; end for; end FADD_CONFIG; y tn ca php nh cu hnh l tu , v d ny ta ly tn l FADD_CONFIG, cn vi dng lnh For STRUCTURE ch ra kin trc c nh cu hnh v c s dng vi thc th Entity FULL_ADDER. Gi s rng chng ta dch hai thc th HALF_ADDER v OR_GATE thnh th vin vi tn l burcin v s dng chng trong v d trn.
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Ch ! VHDL khng h tr cc th vin theo th bc. Bn c th c nhiu th vin nh theo mun nhng khng c khai bo lng nhau! m mt th vin v truy cp chng nh mt Entity c bin dch trong mt thit k VHDL mi, iu u tin cn lm l phi khai bo tn th vin. C php ca chng nh sau: Library library_name : [path/directory_name]; Bn c th truy cp cc n v c bin dch t mt th vin VHDL ti ba mc nh sau: library_name.Package_name.item_name V d: Gi s chng ta to mt ng gi ct mt hng m hng ny c s dng trong nhiu thit k, sau dch n v ct vo trong th vin vi tn l burcin . Package my_pkg is constant delay: time:=10ns; end my_pkg; Tip n chng ta gi my_pkg s dng chng trong thit k di y: architecture DATAFLOW of FULL_ADDER is signal S : BIT; begin S <= A xor B; SUM <= S xor CIN after burcin.my_pkg.delay; COUT <= (A and B ) or (S and CIN) after 5ns; end DATAFLOW;
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signal BEEP : BIT:= '0'; signal TEMP: STD_LOGIC_VECTOR (8 downto 0); signal COUNT: INTEGER range 0 to 100 :=5;
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type STD_LOGIC is ('U','X','0','1','Z','W','L','H','_'); Mi mt nh danh trong mt kiu u c mt v tr nht nh trong kiu, chng c xc nh bi th t xut hin ca chng trong kiu . Trong v d trn, mc nh RED c v tr 0, ORANGE s c v tr 1.... Nu chng ta khai bo mt i tng d liu vi kiu l COLOR v khng nh ngha gi tr khi to th i tng d liu s c khi to mc nh v tr u tin ca kiu lit k (v tr khng), trong trng hp ny COLOR s nhn gi tr RED.
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- BIT_VECTOR: c dng miu t mt mng cc gi tr kiu BIT. - STRING: Mt mng cc k t, mt gi tr kiu chui c i km bi du nhy kp. - REAL: c dng m t cc kiu s thc, di hot ng t -1.0E+38 n +1.0E+38. - Kiu thi gian vt l: M t cc gi tr thi gian c dng trong m phng. C mt vi kiu d liu c nh ngha trong gi STANDARD nh sau: Type BOOLEAN is ( fase, true); Type BIT is ( '0', '1' ); Type SEVERITY_LEVEL is (note, warning, error, failure ); Type INTEGER is range -2,147,483,648 to 2,147,483,648; Type REAL is Range -1.0E38 to 1.0E38; Type CHARACTER is (nul, soh, stx, eot, enq, ack, bel,............);
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type Bit_Vector is arrray (NATURAL range <>) of BIT; type STRING is array (POSITIVE range <>) of CHARACTER; A1 l mt mng gm ba hai phn t m trong mi phn t l mt kiu nguyn. Mt v d khc ch ra kiu Bit_vector v kiu String c to ra trong chun cc gi STANDARD. V d: subtype B1 is BIT_VECTOR ( 3 downto 0); variable B2 : BIT_VECTOR (0 to 10); Di ch s xc nh s phn t trong mng v hng ca chng (low to high | high to low). VHDL cho php khai bo cc mng nhiu chiu c th dng khai bo cc mu RAM v ROM. Xem v d di y: type Mat is array (0 to 7, 0 to 3) of BIT; constant ROM : MAT : = (( '0', '1', '0', '1'), ('1', '1', '0', '1' ), ('0', '1', '1', '1' ), ('0', '1' , '0', '0' ), ('0', '0' ,'0' , '0'), ('1', '1' , '0', '0' ), ('1', '1' , '1', '1' ), ('1', '1' , '0', '0' )); X := ROM (4,3); Bin X s ly gi tr '0' c t m khng in nghing.
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YEAR : INTEGER range 1900 to 1999; MONTH : INTEGER range 1 to 12 ; DAY : INTEGER range 1 to 31; DATE : DATE_TYPE; end record ; signal S : HOLIDAY; variable T1: integer range 1900 to 1999; variable T2 : DATE_TYPE; T1: = S.YEAR; T2:= S.DATE; S.DAY <= 30;
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3.4. CC TON T
VHDL cung cp 6 lp ton t , mi mt ton t c mt mc u tin nht nh. Tt c cc ton t trong cng mt lp th c cng mt mc u tin. Mc u tin thp nht Cc ton t Cc ton hng
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and or nand nor xor = /= < <= > Concatenation_operator arithmetic_operator arithmetic_operator arithmetic_operator >= & + + * / mod rem ** abs
Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Cng kiu Bt k kiu s no Bt k kiu s no Cng kiu Cng kiu integer integer Kiu m integer Bt k kiu s no
arithmetic_operator
3.5.1. Kiu ch
Cc kiu ch c th chia ra thnh hai nhm chnh : Kiu v hng: - Kiu ch k t - Kiu BIT - Kiu chun STD_LOGIC - Kiu Boolean - Kiu s thc - Kiu nguyn - Kiu thi gian Kiu mng: - Kiu chui - Kiu BIT_VECTOR - STD_LOGIC_VECTOR
3.5.1.1. Kiu ch k t
Kiu ch k t ch ra mt gi tr bng vic s dng mt k t n v km theo mt du nhy n. Nhn chung VHDL khng quan tm n cc trng hp ch thng v ch hoa, xong vi kiu ch k t cn phi phn bit ch thng v ch hoa. V d: 'a' hon ton khc vi kiu 'A' trong kiu ch k t. Kiu ch k t c th c dng nh ngha bt c kiu no trong cc ng gi chun v gi tr mc nh ca chng l Null. V d: 'A' , 'a' , ......'1' . Kiu ch k t khng phi l kiu bit k t nh '1' hoc kiu nguyn 1, v vy kiu ch k t cn phi c cung cp mt tn kiu no .
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type memory is array ( 0 to 7 ) of INTEGER range 0 to 123; variable DATA_ARRAY : memory; variable ADDR : INTEGER range 0 to 7; variable DATA: INTEGER range 0 to 123; DATA:= DATA_ARRAY ( ADDR );
A1' low -- Tr v gi tr l 0. A1' range -- Tr v l 10 downto 0. A1' reverse_range -- Tr v gi tr l 0 to 10. A1' length -- Tr v gi tr l 11.
3.5.6. Kiu tp hp
Kiu tp hp c th c dng gn gi tr cho mt i tng thuc kiu mng hoc kiu Record trong khi khi to khai bo hoc trong cc pht biu gn. V d: type color_list ( red, orange, blue, white ); type color_array is array (color_list) of BIT_VECTOR ( 1 downto 0 ); variable X : color_array; X := (" 00 " , " 01 " , " 10 " ," 11 " ); X := ( red => "00" , blue => "01" , orange => "10" , white => "11" ); Trong dng th hai, chng ta nh ngha mt mng m s cc phn t ca chng (di ch s) c a ra bi color_list. T color_list chng ta c mt mng gm bn phn t v mng color_array cng s bao gm bn phn t, m mi phn t ny li c nh ngha bi kiu Bit_Vector. Hn na, chng ta s dng di ch s ca mng color_list s c di t 0 n 3, v vic nh ngha ca mng ny ch ch ra di ch s ch khng ch ra kiu ca phn t trong mng.
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target_variable : = expression; Lu , cc bin c khai bo trong mt Process khng th chuyn gi tr ra ngoi Process, iu c ngha l chng ch c cp pht trong Process hoc trong chng trnh con. V d v php gn bin trong mt Process. process (C,D) variable Av, Bv, Ev : integer := 0; begin Av := 2; Bv := Av + C; Ev := Av * 2; A <= Av; B <= Bv; E <= Cv; end process; A=3 A <= 3 Av = 3 B=3 B <= 3 Bv = 3 C=1 D=2 E=6 E=6 Ev = 6 Biu thc c xc nh gi tr khi pht biu c thc thi v gi tr c tnh ton s c gn cho bin mt cch tc thi. Bin c to ti thi im sn sinh v duy tr gi tr ca n trong sut thi gian chy chng trnh. Do v mt qu trnh khng bao gi c thot ra trong mi trng thi hot ng ca n, ngha l chng c thc thi, hoc trong mt trng thi ch. Nu trng thi ch th chng phi ch cho n khi mt s kin khc chc chn xy ra. Mt qu trnh bt u thc hin ti im khi u ca mt qu trnh m phng, ti thi im ny n c thc thi cho n khi gp mt pht biu wait hoc gp cc thnh phn c khai bo trong danh mc cn c x l khai bo trong Process. Xem th d v pht biu Process nh sau: V d 1: process(A) variable EVENT_ON_A : INTEGER : = -1;
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begin EVENT_ON_A : = EVENT_ON_A +1; end process; V d 2: Subtype INT16 is INTEGER range 0 to 65536; Signal S1, S2 : INT16; Signal GT : BOOLEAN; process (S1, S2) variable A, B : INT6; constant C : INT16 : = 100; Begin A := S1 +1 ; B : = S2*2 - C; GT <= A > B; End Process; Ti lc bt u ca qu trnh m phng. Qu trnh c thc thi mt ln. Bin EVENT_ON_A c gn gi tr -1 sau tng ln 1. Sau , thi im bt k xy ra, s kin trn tn hiu A, qu trnh c hiu lc v pht biu gn bin n c thc thi. N lm cho bin EVENT_ON_A tng ln mt. Ti thi im kt thc ca qu trnh m phng, bin EVENT_ON_A cha tng s s kin xy ra trn tn hiu A. Mt th d khc ca pht biu qu trnh : signal A, Z:INTEGER; ... PZ: process(A); -- PZ l nhn ca qu trnh variable V1,V2 : INTEGER; begin V1:=A-V2; -- statement 1 Z<= -V1; -- statement 2 V2:= Z+V1*2; -- statement 3 end process PZ; Gi s mt s kin xy ra trn tn hiu A ti thi im T1 v bin V2 c gn gi tr l 10, trong pht biu th 3, sau mt s kin xy ra trn tn hiu A ti thi
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im T2, gi tr ca V2 c s dng trong pht biu 1 s cng l 10. Mt bin cng c th c khai bo bn ngoi mt qu trnh hoc mt chng trnh con. Mt bin c th c c v cp nht bi mt hoc c th nhiu qu trnh, nhng bin ny c gi l shared variable (bin chia s).
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Khi mt pht biu gn tn hiu c thc thi, gi tr ca biu thc c tnh ton v gi tr ny c chun b gn cho tn hiu sau khi delay. Lu rng biu thc c nh lng ti thi im pht biu v khng thc thi ngay m n s thc thi sau mt thi gian gi chm. C hai kiu Delay c cung cp chun b cho vic thc thi tn hiu: - Transport Delay. - Inertial Delay. a. Transport Delay. N tng t nh s gi chm bn trong ca mt dng in chy qua dy dn. Nu thi gian gi chm ny c xem nh tiu tn vo thc hin cng vic no v tip sau n (ng thi im ca mt cng vic trc hon thnh) cn phi thc hin mt cng vic khc th thi gian thc hin cc cng vic tip theo s c thm vo cui ca cng vic trc . Cn nu khong thi gian cn thc hin mt cng vic tin nh (thi gian thc hin ca mt cng vic tip theo no ng trc thi im thc hin mt cng vic trc) th cu lnh Transport s thc hin chn vo v thc hin cng vic tin nh ny. Xem v d sau: Gi s ta c mt process v biu nh sau:
Hnh 3.4: Biu thi gian Transport Delay V d: .......... process (.....) Begin S <= transport 1 after 1 ns, 3 after 3 ns, 5 after 5 ns; S <= transport 4 after 4 ns; end process;
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Nh v d v biu trn ta thy cng vic th t cn thc hin trc cng vic th 5, nhng trong phn chng trnh th pht biu ca cng vic th 5 li c thc hin trc cng vic th t. Hnh v di y m t pht biu Transport, sau 3s n s c bt sng v sng trong khong thi gian ng bng thi gian bt cng tc.
Hnh 3.5: M t Transport Delay. b. Inertial Delay Inertial Delay (gi chm do qun tnh), l gi tr mc nh ca VHDL. N c dng cho cc thit b m khng c phn ng cho n khi u vo c php trong mt khong thi gian nht nh. Thng th vi tn hiu c khong thi gian tc ng khng u v nh hn thi gian gi chm ca cc cng th s b b qua. Vi v d trn, m t hot ng ca n vi gi chm do sc qun tnh ca mch. Nu thi gian tc ng ca cng tc nh hn gi chm ca mch th u ra s khng c tc ng hay n s khng c bt sng. Gi s ta c cu lnh n s c bt sng sau 3 giy, nhng cng tc ch tc ng trong thi gian hai giy th n s khng c bt sng. Xem hnh v 3.6 di y:
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Hnh 3.6: M t Inertial Delay (thi gian bt cng tc l 2s). Gi s ta c cu lnh bt n sau 3s. Khi bt cng tc trong thi gian 4s sau tt cng tc, th n s c sng sau khi cng tc bt c 3s v sng trong 4s ng bng thi gian bt cng tc. Xem hnh 3.7 di y:
Hnh 3.7: M t Inertial Delay (thi gian bt cng tc l 4s). c. So snh Transport Delay v Inertial Delay
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Hnh 3.8: So snh Transport Delay v Inertial Delay. Nh trn hnh 3.8 ta thy trong trng hp Inertial Delay, tn hiu A c tc ng trong khong 10ns, nhng cu lnh thc hin u ra S sau 20ns, v vy u ra S s khng c tc ng. Cn trong trng hp Transport Delay tn hiu u ra s c sao y tn hiu u vo sau khi bt u sn ln ca tn hiu vo c tc ng (ng bng khong 20 ns ca cu lnh).
if IN1 = '0' or IN2 = '0' then OU <= '0' ; elsif IN1 = 'X' or IN2 = 'X' then OU <= '1'; else OU <= '1' ; end if; end process; V d 3: D_FF : process (D, CLK) begin if rising_edge (CLK) then Q <= D; end if; end process D_FF;
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tr bng vic s dng du " | " hoc s dng mnh khc. Tt c cc gi tr c th c ca biu thc phi c th hin trong pht biu case ng mt ln. Cc mnh khc c th c s dng bao qut tt c cc gi tr, v nu c, phi l nhnh cui cng trong pht biu case. Mi mt chn la phi c cng kiu vi kiu ca biu thc. Mt th d cho pht biu case: V d 1: type WEEK_DAY is (MON, TUE, WED, THU, FRI, SAT, SUN); type DOLLARS is range 0 to 10; variable DAY: WEEK_DAY; variable POCKET_MONEY: DOLLARS; case DAY is when TUE => POCKET_MONEY :=6; -- branch1 when MON | WED => POCKET_MONEY :=2; -- branch2 when FRI to SUN => POCKET_MONEY :=7; -- branch3 when others => POCKET_MONEY :=0; -- branch4 end case; Nhnh 2 c chn nu DAY c gi tr l MON hoc WED. Nhnh 3 bao gm cc gi tr FRI, SAT v SUN. Trong khi nhnh 4 gm cc gi tr cn li l THU. Pht biu case cng l pht biu tun t, tuy nhin n cng c th c pht biu xp lng nhau. V d 2: ProgrGate: process (Mode, PrGIn1, PrGIn2) begin case Mode is when 000 => PrGOut <= PrGIn1 and PrGIn2; when 001 => PrGOut <= PrGIn1 or PrGIn2; when 010 => PrGOut <= PrGIn1 nand PrGIn2; when 011 => PrGOut <= PrGIn1 nor PrGIn2; when 100 => PrGOut <= not PrGIn1; when 101 => PrGOut <= not PrGIn2; when others => PrGOut <= 0; end case; end process ProgrGate;
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sequential-statements end loop [loop-lebel]; C 3 kiu s lp. u tin l s lp c dng: for identifier in range V d 1: V d v For ...Loop FACTORAL:=1; for NUMBER in 2 to N loop FACTORAL :=FACTORAL*NUMBER; end loop; Trong th d ny, thn ca vng lp thc thi N-1 ln, vi nh danh lp l NUMBER v tng ln 1 sau mi vng lp. i tng NUMBER c khai bo n trong vng lp ty thuc vo kiu integer, n c gi tr t 2 n N. V vy khai bo khng r rng cho nh danh vng lp l iu cn thit, nh danh vng lp cng khng th c gn cho bt k gi tr no trong vng lp for. Nu mt bin khc c cng tn c to bn ngoi vng lp for, l hai loi bin c gii quyt ring r v bin s dng trong vng lp for s chuyn giao cho nh danh vng lp. Vng ca vng lp FOR cng c th l vng ca mt kiu lit k. V d 2: type HEXA is (0,1,2,3,A,B,C ); . . . . for NUM in HEXA(2) downto HEXA(0) loop -- Num s ly nhng gi tr trong kiu HEXA t 2 cho n 0. end loop; V d 3: V d v While .... loop process variable Count : integer := 0; begin wait until Clk = 1; while Level = 1 loop Count := Count +1; wait until Clk = 0; end loop; end process;
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wait until boolean -expression; wait for time-expression; V d 1: wait on A,B ; wait until A = B; wait for 10 ns; wait on CLOCK for 20 ns ; wait until SUM >100 for 50 ms; S hin din ca sensitivity list trong mt qu trnh trng vi trng hp mt trong ba trng hp trn ca pht biu wait. Mt pht biu qu trnh c wait on cui ca Process tng ng vi mt pht biu qu trnh c khai bo sensitivity-list. Xem hnh di y: Hai process ny l tng ng nhau. process begin somestatements1; somestatements2; somestatements3; wait on SomeSign; end process; ------------------process (SomeSign) begin somestatements1; somestatements2; somestatements3; end process; V d 2: process -- Khng sensitivity list variable TEMP1, TEMP2:BIT; begin TEMP1:=A and B; TEMP2:=C and D;
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TEMP1:=TEMP1 or TEMP2; Z<=not TEMP1; wait on A, B, C, D; -- Thay th cho sensitivity-list u Process . End process. V d 3: Hai Process trong v d di y ch ra hai process c pht biu Wait on. Process bn tri s lm cho Process treo ngay sau khi Start v ch cho n khi c s kin xut hin trn tn hiu SigA. Cn Process bn phi s thc hin ba cu lnh v sau ri vo trng thi ch n khi xut hin s kin trn tn hiu SigB. process begin wait on SigA; somestatements1; somestatements2; somestatements3; end process; -------------------------process begin somestatements1; somestatements2; somestatements3; wait on SigB; end process;
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biu tr v trong thn hm, nhng vi th tc th c th s dng tu trong thn th tc. C php ca pht biu tr v nh sau: return [expression]; y expression s a ra cc gi tr tr v ca hm, pht biu return trong mt hm cn phi c mt biu thc v gi tr tr v ca n, nhng i vi pht biu tr v trong th tc th khng cn phi c mt ca biu thc. Mt hm c th c nhiu hn mt pht biu tr v, nhng ch c mt pht biu tr v c s dng bi mt li gi hm.
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{sequential_statements} end process [label]; Phn khai bo ca mt process ch ra cc i tng m vng hot ng ca n ch thuc vng ca mt process v chng c th l cc i tng sau y: - Khai bo bin . - Khai bo hng . - Khai bo cc kiu. - Khai bo cc kiu con. - Khai bo cc b danh Alias. - Cc mnh USE. Mt sensitivity list (tp cc s kin thay i trng thi cn x l trong mt qu trnh) c cng ngha vi mt Process c cha pht biu wait, m pht biu wait ny l pht biu cui cng trong mt process v chng c dng sau: Wait on sensitivity list ; Mt process c chc nng ging nh mt vng lp v hn m trong n c cha ton b cc pht biu tun t c ch ra trong vng lp . V vy mt pht biu process cn phi c hoc mt sensitivity list hoc mt pht biu wait on hoc c hai. V d 1: architecture A2 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin pr1 : process (i1, i2, i3, i4) begin and_out <= i1 and i2 and i3 and i4; end process pr1; pr2 : process (i1, i2, i3, i4) begin or_out <= i1 or i2 or i3 or i4 ; end process pr2; end A2 V d 2: name: process (sensitivity list)
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declarations begin sequential statements; end process name; --------------------MUX2TO1: process (A,B,SEL) constant High : Bit := 1; begin Y <= A; if (SEL= 1) then Y <= B; end if; end process MUX2TO1;
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architecture A2 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin process (i1, i2, i3, i4) begin and_out <= i1 and i2 and i3 and i4; end process ; process (i1, i2, i3, i4) begin or_out <= i1 or i2 or i3 or i4 ; end process ; end A2; V d 3: architecture A3 of example is signal i1, i2, i3, i4, and_out, or_out : bit; begin process begin and_out <= i1 and i2 and i3 and i4; or_out <= i1 or i2 or i3 or i4; wait on i1, i2, i3, i4; end A3; Ba v d trn y l tng ng nhau.
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thc cn li s c s dng. Nh rng ch mt biu thc c s dng ti mt thi im. C php ca cu lnh ny nh sau: target <= {expression [ after time_expression ] when condition else} expression [ after time_expression ]; Mt pht biu gn tn hiu c iu kin c th c m t bi mt pht biu process m process c cha pht biu IF. Bn c th s dng pht biu gn tn hiu c iu kin trong mt process . V d 1: architecture A1 of example is signal a, b, c ,d : integer ; begin a <= b when ( d >10 ) else c when ( d >5 ) else d; end A1; V d 2: architecture A2 of example is signal a, b, c ,d : integer ; begin process (b, c, d) begin if ( d > 10) then a <= b elsif ( d >5 ) then a <= c; else a <= d; end if; end process; end A2; V d 3: S dng cc pht biu c iu kin. ExProc: process (sensitivityList) begin if Cond1 then .
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case Cond2 is when Val1 => when Val2 => when others => for I in 1 to 4 loop . end loop; end case; else while Cond3 loop . end loop . end if; end process ExProc; b. Cc php gn tn hiu c chn la. Php gn tn hiu c chn la c th ch mt ch gn v cng ch c mt biu thc with. Gi tr ny c kim tra ging nh pht biu Case thng thng. N s qun l bt c s thay i no xut hin ti cc tn hiu c chn la. C php ca chng nh sau: with choice_expression select target <= {expression [after time_expression] when choices} expression [ after time_expression] when choices; Bt k php gn tn hiu c chn la no u c th c m t tng ng bi pht biu process c cha pht biu case. Bn khng c s dng pht biu gn tn c chn la trong mt process . V d 1: with SEL select Z <= a when 0 | 1 | 2, b when 3 to 10, c when others;
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V d 2: process ( SEL, a, b, c ) case SEL is when 0 | 1 | 2| => Z <= a; when 3 to 10 => Z <= b; when others => Z <= c; end case; end process ; Hai v d trn y l hon ton tng ng nhau.
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trng tn vi i tng trong block cha th khai bo ca block con s nh ngha li i tng trng tn vi block cha. V d: architecture BHV of example is signal : out 1 : integer; signal : out 2 : bit; begin B1 : block signal S : bit; begin B1-1 : block signal S : integer; begin out 1 <= S ; end block B1-1; end block B1; B2: block begin out 2 <= S ; end block B2; end BHV; Trong v d ny ta thy block B1-1 l block con ca block B1. C B1 v B1-1 u khai bo tn hiu S. Tn hiu S trong B1-1 s l kiu integer v truyn cho tn hiu out 1 cng l kiu integer, mc d S c khai bo trong B1 l kiu Bit. Tn hiu S trong B1 c s dng trong B2 l kiu Bit, trng vi kiu tn hiu out 2.
3.7.5. Cc li gi th tc ng thi
Mt li gi th tc ng thi chnh l mt li gi th tc m n c thc thi bn ngoi mt process, n ng c lp trong mt kin trc architecture. Li gi th tc ng thi bao gm: - C cc tham s IN, OUT, INOUT. - C th c nhiu hn mt gi tr tr v - N c xem nh mt pht biu.
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- N tng ng vi mt process c cha mt li gi th tc n. Hai v d di y l tng ng nhau. V d 1: architecture ................. begin procedure_any (a,b) ; end..........; V d 2: architecture ................ begin process begin procedure_ any (a,b); wait on a,b; end process ; end .............;
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Begin {sequential_statement} end [identifier]; Cc nh danh identifier ch ra tn ca mt hm, cn interface_list ch ra nh dng tham s ca mt hm. Mi mt tham s c nh ngha theo c php sau: [class] name_list [mode] type_name [:=expression]; y class ca tham s i tng phi c ch ra l tn hiu hoc hng, cn mode ca i tng cn phi l mode in. Nu khng c tham s mode c ch ra th c hiu nh l mode IN, cn nu khng c tham s class c ch ra th tham s c hiu nh l mt hng. Xem v d sau: process function c_to_f ( c : real ) return real is variable f : real; begin f := c*9.0/5.0 + 32.0; return (f); end c_to_f; variable temp : real; begin temp : = c_to_f (5.0) + 20.0; -- temp = 61 end process; Tham s chuyn vo hm c hiu mc nh l mt hng s, v khng c khai bo ca class. b. Th tc v cc c trng ca chng. - Chng c gi nh mt li pht biu. - C th tr v khng hoc mt hoc nhiu i s. - Cc tham s chuyn giao cho th tc c th l mode in, out, v inout. - Cc tham s chuyn giao cho th tc c th l tn hiu, hng, bin. - C th c cha pht biu Wait. C php khai bo th tc nh sau: procedure identifier interface_list is
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{subprogram_declarative_item} begin {sequential_statement} end [identifier]; Identifier c s dng ch ra tn ca procedure v interface_list ch ra cc tham s hnh thc ca procedure. Mi tham s c s dng theo nh ngha sau: [class] name_list [mode] type_name [:=expression]; Class ca i tng c xem nh hng, bin , hoc l tn hiu v mode ca i tng c th l in, out , inout. Nu khng c mode c ch ra th tham s c hiu nh mode in, nu khng c class c ch ra th cc tham s mode in c hiu nh l cc hng, cn tham s mode out v inout c hiu nh l cc bin. Cc tham s c th l cc hng, cc bin, hoc cc tn hiu v mode ca chng c th l in, out, hoc inout. Nu lp ca cc tham s khng xc nh r rng th mc nhin n l constant, nu n l mode in, cn n l bin nu mode ca tham s l out hoc inout. Mt v d thn procedure m t hnh vi hot ng ca cc n v logic s hc nh sau: type OP_CODE is ( ADD, SUB, MUL, DIV, LT, LE, EQ); procedure ARITH_UNIT ( A, B : in INTEGER ; OP : in OP_CODE ; Z : out INTEGER; ZCOMP : out BOOLEAN ) is begin case OP is when ADD => Z := A+B; when SUB => Z := A-B; when MUL => Z := A*B; when DIV => Z := A/B; when LT => ZCOMP := A<B; when LE => ZCOMP := A<=B; when EQ => ZCOMP := A=B; end case ;
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end ARITH_UNIT; Ta xem mt v d khc ca thn mt procedure, procedure ny quay vc t c xc nh vi tn l ARRAY_NAME, bt u t bit START_BIT ti STOP_BIT, bi mt gi tr ROTATE_BY. Lp i tng ca tham ARRAY_NAME c xc nh mt cch tng minh. Bin FILL_VALUE ng c khi to v 0 mi khi procedure c gi. Procedure ROTATE_LEFT (signal ARRAY_NAME : inout Bit_vector ; START_BIT, STOP_BIT : in NATUAL; ROTATE_BY : in POSITIVE ) is Variable FILL_VALUE : BIT; begin
bit s t
assert STOP_BIT > START_BIT report STOP_BIT is not greater than START_BIT severity NOTE; for MACVAR3 in 1 to ROTATE_BY loop FILL_VALUE := ARRAY_NAME (STOP_BIT); for MACVAR1 in STOP_BIT downto (START_BIT + 1) loop ARRAY_NAME (MACVAR1) <= ARRAY_NAME (MACVAR1 1); end loop; ARRAY_NAME (START_BIT) <= FILL_VALUE ; end loop; end procedure ROTATE_LEFT; Cc procedure c gi bi li gi procedure. Mt li gi Procedure c th l mt pht biu tun t hoc mt pht biu ng thi, pht biu ny ph thuc vo ni xut hin li gi th tc hin ti. Nu li gi ny nm bn trong mt pht biu process hoc mt chng trnh con khc th n c gi l pht biu gi procedure tun t, ngc li n c gi l pht biu gi procedure gi ng thi. C php ca pht biu gi procedure nh sau : [ label : ] procedure_name ( list_of_actual ); Thc t cc biu thc, cc bin, cc tn hiu hoc cc file, c chuyn vo trong th tc v cc tn ca i tng v cc tn ny s c dng ly cc gi tr tnh
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ton t trong th tc. Chng c ch ra mt cch r rng bi vic s dng s kt hp theo tn v kt hp theo v tr . V d: ARITH_UNIT (D1, D2, ADD, SUM, COMP ); -- S kt hp theo v tr. ARITH_UNIT ( Z => SUM, B=> D2, A=>D1, OP=>ADD, ZCOMP => COMP); -- S kt hp theo tn. Mt pht biu gi th tc tun t c thc thi tun t cng vi cc pht biu tun t chung quanh n. Mt pht biu gi th tc ng thi c thc thi bt c lc no khi c mt s kin xy ra trn mt trong cc tham s, m cc tham s ny l mt tn hiu ch in hoc inout. Mt li gi th tc ng thi c ngha tng ng vi mt process c cha mt li gi th tc tun t v mt pht biu wait. Pht biu wait ny s lm cho qu trnh ch cho n khi c mt s kin xut hin trn cc tham s tn hiu ca mode in hoc inout. Sau y l mt v d ca li gi th tc ng thi v pht biu process tng ng vi n: architecture DUMMY_ARCH of DUMMY is -- Tip n l thn ca th tc procedure INT_2_VEC ( signal D : out BIT_VECTOR ; START_BIT, STOP_BIT : in NATUAL ; signal VALUE : in INTEGER ) is begin -- M t hot ng hnh vi ca th tc end INT_2_VEC; begin -- y l v d ca mt li gi th tc ng thi. INT_2_VEC (D_ARRAY, START, STOP, SIGNAL_VALUE); end DUMMY_ARCH; Pht biu process tng ng vi li gi mt th tc ng thi nh sau: process begin INT_2_VEC (D_ARRAY,START,STOP,SIGNAL_VALUE); -- Phn th hin ca cc li gi th tc tun t wait on SIGNAL_VALUE;
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-- Ch s kin trn SIGNAL_VALUE v xem chng nh mt tn hiu -- vo. end process; Mt procedure c th s dng hoc l mt pht biu ng thi hoc l pht biu tun t. Cc li gi ng thi thng xuyn c dng m t chnh l cc process. V d ca th tc dng c khai bo postpone (tr hon). postponend procedure INT_2_VEC ( signal D:out BIT_VECTOR ; START_BIT,STOP_BIT : in NATUAL; signal VALUE :in INTEGER) is begin -- Phn khai bo hot ng ca th tc end INT_2_VEC; Ng ngha ca mt li gi th tc ng thi dng postponed l tng ng vi ng ngha ca pht biu process tng ng vi n v c gi l pht biu process b tr hon. Mt thn process c th c pht biu wait, trong khi mt function th khng c php c. Cc function c s dng tnh ton cc gi tr mt cch tc th. V vy mt function khng cn c pht biu wait trong . Mt function khng th gi mt procedure c pht biu wait trong th tc . Mt process m c cha li gi mt th tc m trong th tc ny c cha pht biu wait, th process ny khng c khai bo sensitivity list. Hn na t thc t chng ta thy mt process khng th nhn bit cc tn hiu thuc sensitivity list v nu c process ny s ri vo trng thi ch ngay lp tc. Vi mt th tc c cha pht biu wait th bt c bin hay hng no c khai bo trong th tc s gi nguyn gi tr ca chng trong sut thi gian thc hin pht biu wait v tn ti ch khi th tc c kt thc.
3.8. CC NG GI
Bn c th ng gi ct cc chng trnh con, cc kiu d liu, cc hng... thng dng s dng chng trong cc thit k khc. Mt package bao gm hai phn chnh: Phn khai bo v phn thn package, phn khai bo ch ra giao tip cho package.
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C php ca khai bo package nh sau: package package _name is {package _declarative_item} end [package _name]; Phn package _declarative_item c th l bt k kiu no sau y: - Khai bo kiu. - Khai bo cc kiu con. - Khai bo tn hiu. - Khai bo cc hng. - Khai bo b danh ALIAS. - Khai bo cc thnh phn. - Khai bo cc chng trnh con. - Cc mnh USE. Ch ! Khai bo tn hiu trong package c mt s vn cn luu trong khi tng hp, bi v mt tn hiu khng th c chia s bi hai Entity. V vy nu mun dng chung khai bo tn hiu bn phi khai bo tn hiu ny l tn hiu ton cc. Phn thn ca package ch ra hot ng thc t ca mt package. Phn thn ca package phi lun c tn trng vi phn khai bo. C php ca khai bo ny nh sau: package body package _name is {package _body_declarative-item} end [package _name] ; Phn package _body_declarative-item c th bao gm: - Khai bo kiu. - Khai bo cc kiu con. - Khai bo cc hng - Mnh use. - Thn cc chng trnh con. V d: library IEEE; use IEEE.NUMERIC_BIT.all; package PKG is subtype MONTH_TYPE is integer range 0 to 12;
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subtype DAY_TYPE is integer range 0 to 31; subtype BCD4_TYPE is unsigned ( 3 downto 0); subtype BCD5_TYPE is unsigned ( 4 downto 0) ; constant BCD5_1: BCD5_TYPE : = b"00001" ; constant BCD5_7: BCD5_TYPE : = b"00111" ; function BCD_INC (L : in BCD4_TYPE) return BCD5_TYPE; end PKG; package body PKG is function BCD_INC (L :in BCD4_TYPE) return BCD5_TYPE is variable V,V1, V2 : BCD5_TYPE; begin V1 : = L + BCD5_1; V2 : = L + BCD5_7; case V2(4) is when ' 0 ' => V : = V1; when ' 1 ' => V : = V2; end case; return (V); end BCD_INC; end PKG;
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Hnh 3.12: Cc thnh phn bn trong b Full_adder. Nh trn hnh v chng ta thy phn thc thi c ba loi cng khc nhau v chng c mang tn nh sau: OR2_gate, AND2_gate, XOR_gate, chng c dng xy dng nn b cng. m t v th hin chng trong thit k, ta c th vit chng trnh thc thi tng thnh phn ca chng nh sau: library IEEE; use IEEE.STD_LOGIC_1164.all; Entity AND2_gate is port ( I0, I1 : in STD_LOGIC ; O : out STD_LOGIC ); End AND2_gate; Architecture BHV of AND2_gate is Begin O <= I0 and I1; End BHV; ----------library IEEE; use IEEE.STD_LOGIC_1164.all; Entity XOR_gate is port ( I0, I1 : in STD_LOGIC ;
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O : out STD_LOGIC ); End XOR_gate; Architecture BHV of XOR_gate is Begin O <= I0 xor I1; End BHV; ------------library IEEE; use IEEE.STD_LOGIC_1164.all; Entity OR2_gate is port ( I0, I1 : in STD_LOGIC ; O : out STD_LOGIC ); End OR2_gate; Architecture BHV of OR2_gate is Begin O <= I0 xor I1; End BHV; th hin cc component ny trong mt thit k, ta khai bo chng nh sau: library IEEE; use IEEE.STD_LOGIC_1164.all; Entity FULL_ADDER is port (A, B, Cin : in STD_LOGIC; Sum, Cout : out STD_LOGIC); End FULL_ADDER; Architecture IMP of FULL_ADDER is component XOR_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component ; component AND2_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC ); end component; component OR2_gate port ( I0, I1 : in STD_LOGIC; O : out STD_LOGIC );
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end component; signal N1, N2, N3: STD_LOGIC; begin U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1); U2 :AND2_gate port map ( A, B, N2); U3 :AND2_gate port map ( Cin, N1, N3); U4 :XOR_gate port map ( Cin, N1, Sum); U5 :OR2_gate port map ( N3, N2, Cout); end IMP;
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Hnh 3.13: B cng 4 bit. m t b cng 4 bit ny v s dng pht biu generate, s dng m t b cng Full_Adder nh trn ta m t. Ta c th vit chng nh sau: architecture IMP of FULL_ADDER4 is signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ; signal Cout : STD_LOGIC ; signal TMP : STD_LOGIC_VECTOR ( 4 downto 0 ) ; component FULL_ADDER port ( A, B, Cin : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; begin TMP (0) <= ' 0 '; G : for I in 0 to 3 generate FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 )); end generate ; Cout <= TMP (4); end IMP; b, S dng lc if
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Hnh 3.14: S b cng bn bit s dng mt b cng Half_ADDER v ba b cng Full_ADDER. Mt s cu trc c dng khng theo qui lut chun no, vi trng hp ny ta c th s dng lc if. Gi s ta m t b cng bn bit nh trn hnh 3.14 v s dng lc IF generate m t b cng ny. Chng trnh c vit nh sau: architecture IMP of FULL_ADDER4 is signal X, Y, Z : STD_LOGIC_VECTOR ( 3 downto 0 ) ; signal Cout : STD_LOGIC ; signal TMP : STD_LOGIC_VECTOR ( 4 downto 1) ; component FULL_ADDER port ( A, B, Cin : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; component HALF_ADDER port ( A, B : in STD_LOGIC ; Sum, Cout : out STD_LOGIC ); end component ; begin G0 : for I in 0 to 3 generate G1: if I = 0 generate HA: HALF_ADDER port map ( X (I), Y(I), Z (I), TMP ( I+1 )); end generate ; G2: if I >= 1 and I <= 3 generate
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FA: FULL_ADDER port map ( X (I), Y(I), TMP (I), Z (I),TMP ( I+1 )); end generate ; end generate ; Cout <= TMP ( 4 ); end IMP;
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for others : XOR_gate use entity work.XOR_gate (BHV); for all : AND2_gate use entity work.AND2_gate (BHV); for U5 : OR2_gate use entity work.OR2_gate (BHV); begin U1 : XOR_gate port map (I0 => A, I1=> B, O=>N1); U2 :AND2_gate port map ( A, B, N2); U3 :AND2_gate port map ( Cin, N1, N3); U4 :XOR_gate port map ( Cin, N1, Sum); U5 :OR2_gate port map ( N3, N2, Cout); end IMP;
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