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Verilog l mt trong hai ngn ng m t phn cng chnh (gm VHDL v Verilog HDL) c ngi thit k phn cng s dng m t, thit k cc h thng s, v d nh my tnh hay linh kin in t.
Vng Nh Ca Verilog
Vng nh c nh ngha ging nh vect ca thanh ghi. V d mt vng nh gm 1024 t, mi t 16 bit. reg [15:0] Mem [1024:0]; K hiu Mem[0] s tham chiu n vng nh u tin . . . Ch rng khng th tham chiu n mt bit trong 1 t ca vng nh, mun lm iu ny phi chuyn d liu vo mt thanh ghi trung gian.
Ton T Ca Verilog
Gm cc ton t quan h so snh 2 ton hng v tr ra gi tr logic. ng l 1, sai l 0. Nu bt k bit no khng xc nh th kt qu ra l khng xc nh. > ln hn >= ln hn hoc bng < nh hn <= nh hn hoc bng == bng logic != khc
Ton T Ca Verilog
Cc ton t iu kin ! o logic && AND logic || OR logic Cc ton t set bit ~ o bit & AND | OR ^ XOR ~& NAND ~| NOR
Ton T Ca Verilog
Cc ton t khc {,} ghp thanh ghi hoc dy << dch tri thanh ghi >> dch phi thanh ghi ?: iu kin
Ton T Ca Verilog
V d :
Dng iu lnh assign vit mt module gii a hp t 2 ng sang 4 ng (bn c th t vit gii a hp t 3 sang 8 hay 4 sang 16) module demux(data,in1,in0,out0,out1,out2,out3); input data; input in0,in1; output out0,out1,out2,out3; assign out0= data&(~in1)&(~in0); assign out1= data&(~in1)&(in0); assign out2= data&(in1)&(~in0); assign out3= data&(in1)&(in0); endmodule
Cc cu trc iu khin
Verilog rt phong ph cc cu lnh iu khin c th s dng trong phn th tc. Hu ht chng rt quen thuc vi nhng ngi lp trnh bng ngn ng C. im khc bit ln nht chnh l thay du ngoc {} trong ngn ng C bng t kha begin v end trong Verilog HDL, du ngoc {,} dng ni chui cc bit.
Cc cu trc iu khin
1, Cu trc ifelse
2, Cu trc case khng ging cu trc case trong C ch khng cn lnh break. V d : case (State) st0: State = st1; st1: State = st2; st2: State = st3; st3: State = st0; endcase
Cc cu trc iu khin
Ngoi ra cn c cc vng lp for, while v repeat. Tuy nhin chng rt him khi s dng trong vic m t cc module nn ta s khng cp n.
Cc cu trc iu khin
V d : Mt module 3 trng thi dng always v cu trc if . . .else, nu ng Con l 1 th ng ra bng ng vo, nu Con l 0 th ng ra s trng thi tng tr cao: module tristate(In,Con,Out); input In,Con; output Out; reg Out; always begin if (Con==1'b1) Out=In; else Out=1'bz; end endmodule
Thanks everybody