Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 1 1.

1. Li gi h thng l g. Cc phng php truyn tham s gia tin trnh v H iu hnh. 2. Phn bit a ch lgic v a ch vt l. Cc c ch lin kt a ch no c a ch lgic v a ch vt l ging nhau; c ch no c a ch lgic v a ch vt l khc nhau. Gii thch. 3. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0.0 0.5 P2 0.5 1.5 P3 1.0 2.0 P4 1.5 5.0 P5 2.0 10 Tnh thi gian hon thnh trung bnh cho cc tin trnh khi s dng cc gii thut iu phi: SJF (Shortest Job First) c quyn SJF (Shortest Job First) khng c quyn 4. Trong cc s phn phi ti nguyn di y, cho bit h thng c deadlock khng. Gii thch. a)

R2 P2 R1 P1 P3 R3

. b)

P5 R6

R5 P4 R4

R1 P R2

P2 P3 P4

5.

Cho chui tham chiu trang sau: 1, 2, 3, 4, 5, 5, 4, 3, 2, 1, 6, 7, 1, 1, 1, 7, 6, 5, 4, 3, 2, 1 Gi s ti thi im ban u cc trang 1, 2, 3, 4 ang c mt trong b nh theo ng th t. Trong trng hp h thng c 4 frames, v lc phn phi frames v tnh s li trang(Page Fault) theo cc gii thut: LRU(Least Recently Used). 6. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic sau: Tin trnh P1 P2 P3 Cng vic X2 = X1 + X2 X1 = X1 / X2 X3 = X2 + X1 X1 = X1 * X X2 = X X1 M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 LOAD Reg2, X2

ADD Reg2, Reg1 DIV Reg1, Reg2 ADD Reg2, Reg1 SAVE X2, Reg2 SAVE X1, Reg1 SAVE X3, Reg2 LOAD Reg, X LOAD Reg, X MUL Reg1, Reg SUB Reg, Reg1 SAVE X1, Reg1 SAVE X2, Reg Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 10 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh bit h thng s dng lp lch FCFS(First Come First Server)

Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 1 1. Phn bit chng trnh v tin. M t cc bc chuyn trng thi ca tin trnh. Trong ch iu phi n mc vi h thng n CPU, ti mt thi im c bao nhiu hang i waiting, ready, running; mi quan h gia ti nguyn v hng i waiting . 2. Trong on gng c th c nhiu tin trnh khng. Cho v d. 3. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0.0 10 P2 0.5 6 P3 1.0 3 P4 1.5 7 P5 2.0 1 Tnh thi gian hon thnh trung bnh cho cc tin trnh khi s dng cc gii thut iu phi: FCFS (First Come First Server) SJF (Shortest Job First) c quyn SJF (Shortest Job First) khng c quyn 4. Cho s phn phi ti nguyn sau:

R2 P2 R1 P1 P3 P5 R6 R5 P4 R4 R3

. Cho bit h thng c deadlock khng. Gii thch. 5. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5, 5, 4, 3, 2, 1, 6, 7, 1, 1, 1, 7, 6, 5, 4, 3, 2, 1 Gi s ti thi im ban u cc trang 1, 2, 3, 4 ang c mt trong b nh. V lc phn phi frames v tnh s li trang(page fault) trong trng hp h thng c 5 frames theo cc gii thut: FIFO, LRU. 6. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic sau: Tin trnh P1 P2 P3 Cng vic X2 = X1 + X2 X1 = X1 * X2 X3 = X2 + X1 X1 = X1 * X X2 = X X1 M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 LOAD Reg2, X2 ADD Reg2, Reg1 MUL Reg1, Reg2 ADD Reg2, Reg1 SAVE X2, Reg2 SAVE X1, Reg1 SAVE X3, Reg2 LOAD Reg, X LOAD Reg, X MUL Reg1, Reg SUB Reg, Reg1 SAVE X1, Reg1 SAVE X2, Reg Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 10 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh bit h thng s dng lp lch RR(Robin Round) vi thi gian lng t bng thi gian thc hin 2 lnh assembly. 7. Trong ch phn trang, tnh s bit a ch dng cho b nh o 128 trang(page), kch thc mi trang 1024 bytes. Tnh s bit a ch dng cho khng gian nh thc kch thc 16 trang nh vt l(frame).

Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 2 1. Phn bit lung mc nhn v lung mc ngi dng. M t hin tng phn mnh trong v phn mnh ngoi. C cc hin tng phn mnh trong: c ch a chng trnh vi phn vng bin i. Gii thch. 2. Khi mt tin trnh trong on gng, n c th trng thi: running, ready khng. Gii thch. 3. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n u tin Thi gian s dng CPU P1 0.0 5 20 P2 2.0 1 5 P3 1.0 4 3 P4 3.0 2 7 P5 5.0 3 5 Tnh thi gian hon thnh trung bnh v thi gian i trung bnh cho cc tin trnh khi s dng cc gii thut iu phi: a. FCFS (First Come First Server) b. iu phi theo u tin( u tin nh hn c chn thc hin trc) 4. Cho h thng c 4 ti nguyn cng kiu chia cho 3 tin trnh. Mi tin trnh yu cu ti a 2 ti nguyn. Chng minh h thng khng c deadlock.. 5. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5, 5, 4, 3, 2, 1, 6, 7, 1, 1, 1, 7, 6, 5, 4, 3, 2, 1 Gi s ti thi im ban u cc trang 1, 2, 3, 4, 5, 6 ang c mt trong b nh. V lc phn phi frames v tnh s li trang(page fault) trong trng hp h thng c 7 frames theo cc gii thut: FIFO, LRU. 6. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic trong bng sau: Tin trnh P1 P2 P3 Cng vic X2 = X1 + X2 X1 = X1 * X2 X3 = X2 + X1 X1 = X1 * X X2 = X X1 M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 LOAD Reg2, X2 ADD Reg2, Reg1 MUL Reg1, Reg2 ADD Reg2, Reg1 SAVE X2, Reg2 SAVE X1, Reg1 SAVE X3, Reg2 LOAD Reg, X LOAD Reg, X MUL Reg1, Reg SUB Reg, Reg1 SAVE X1, Reg1 SAVE X2, Reg Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 10 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh bit h thng s dng lp lch RR(Robin Round) vi thi gian lng t bng thi gian thc hin 3 lnh assembly. 7. Trong ch phn trang 2 mc( a ch lgic dng <P1, P2, D>), h thng s dng 10bit cho P1, 10bit cho P2, 12bit nh v mt nh trong trang. Tnh kch thc b nh vt l v kch thc 1 trang nh vt l.

Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 2 1>Phn bit m hnh phn phi nh lin tc v phn phi nh gin on. Ch ra s phn mnh trong v phn mnh ngoi trong m hnh phn phi MFT, MVT, phn on, phn trang. 2>Phn phi frames l g. Phn bit phn phi cng bng, phn phi theo kch thc, phn phi c u tin. C ch phn phi no cho php thay th ton cc, c ch no cho php thay th cc b. Gii thch. 3>Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n u tin Thi gian s dng CPU P1 0.0 2 20 P2 5.0 1 5 P3 1.0 3 30 P4 4.0 4 5 P5 2.0 5 10 Tnh thi gian hon thnh trung bnh v thi gian i trung bnh cho cc tin trnh khi s dng cc gii thut iu phi: FCFS (First Come First Server) iu phi theo u tin 4>Bi ton Cy cu c: trnh sp , ngi ta ch c cho php ti a 3 xe lu thng ng thi qua mt cy cu rt c. Hy xy dng th tc ArriveBridge(int direction) v ExitBridge() kim sot giao thng trn cu sao cho: Ti mi thi im, ch cho php ti a 3 xe lu thng trn cu. Mi chic xe khi n u cu s gi ArriveBridge(direction) kim tra iu kin ln cu, v khi qua cu c s gi ExitBridge() bo hiu kt thc. Gi s hot ng ca mi chic xe c m t bng mt tin trnh Car() sau y: Car(int direction) /* direction xc nh hng di chuyn ca mi chic xe.*/ { RuntoBridge(); // i v pha cu ArriveBridge(direction);//n cu PassBridge(); // i trn cu Exit Bridge();//Ri cu RunfromBridge(); // qua cu } Ch ra on gng trong tin trnh trn. Gii thch. 5>Cho chui tham chiu trang sau: 1, 2, 3, 4, 5, 5, 4, 3, 2, 1, 6, 7, 1, 1, 1, 7, 6, 5, 4, 3, 2, 1 Gi s ti thi im ban u cc trang 1, 2 ang c mt trong b nh theo ng th t. Trong trng hp h thng c 3 frames, v lc phn phi frames theo cc gii thut: FIFO(First In First Out), LRU(Least Recenly Used). 6>Cho cc tin trnh P1, P2, P3 thc hin cc cng vic trong bng sau: Tin trnh P1 P2 P3 Cng vic X2 = X1 + X2 X1 = X1 / X2 X3 = X2 + X1 X1 = X1 * X X2 = X X1 M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 LOAD Reg2, X2 ADD Reg2, Reg1 MUL Reg1, Reg2 ADD Reg2, Reg1 SAVE X2, Reg2 SAVE X1, Reg1 SAVE X3, Reg2 LOAD Reg, X LOAD Reg, X MUL Reg1, Reg SUB Reg, Reg1 SAVE X1, Reg1 SAVE X2, Reg Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 10 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh. Gi s h thng s dng lp lch: a. FCFS b. Theo u tin c c quyn, trong : P1( u tin = 3, thi im n = 0, thi gian thc hin = 10); P2( u tin = 1, thi im n = 9, thi gian thc hin = 9); P3( u tin = 2, thi im n = 5, thi gian thc hin = 5)

 thi s 1 7. Trong gii thut RR thi gian i ca mt tin trnh ph thuc vo hai yu t c bn no. 8. Mt tin trnh trong an gng c th nhng trng thi no. Gii thch. 9. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0 15 P2 2 10 P3 4 2 P4 5 5 P5 10 1 Tnh thi gian hon thnh trung bnh cho cc tin trnh khi s dng cc gii thut iu phi SJF (Shortest Job First) c quyn. 10. Trong gii thut lp lch Round-Robin vi thi gian lng t bng 3, gi s thi im hin ti ch c mt tin trnh trong hng i ready c thi gian s dng CPU l 10. Tnh thi gian hon thnh ca tin trnh (b qua thi gian chuyn trng thi tin trnh). 11. Trong s phn phi ti nguyn di y, cho bit h thng c deadlock khng. Gii thch ngn gn.

R2 R1 P1

P2 R3 P3

P5 R6

R5 P4 R4

12. Trong c ch phn trang n gin, kch thc b nh vt l 32MB, kch thc 1 trang nh l 1MB v khng gian a ch logic c 10 trang. Tnh s bit a ch vt l v logic. 13. Thao tc nguyn t l g. Test&Set() trong gii php Peterson c phi l thao tc nguyn t khng. 14. Cho mt chng trnh gm cc mdun sau: - M-dun chng trnh chnh A(i hi b nh 10KB); mi m-dun ctr khc u ph thuc vo n. M-un A s dng 2 mdun c lp B(30KB), C(20KB) - B s dng 2 m-dun c lp D(20KB), E(10K) - C s dng 2 m-dun c lp G(10KB), H(10KB) - H s dng 2 m-dun c lp I(10KB), J(5KB) Cy chng trnh nh sau: A 10KB

B 30KB D 20KB E 10K G 10K

20KB H 10KB

J 5K I 10KB Tnh tng dung lng b nh cn thit thc hin chng trnh ny khi p dng c ch Overlay

15. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic sau: Tin trnh P1 P2 Cng vic X2 = X1 + X2 X1 = X1 * X2 X1 = X1 * X M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 ADD Reg2, Reg1 MUL Reg1, Reg2 SAVE X2, Reg2 SAVE X1, Reg1 LOAD Reg, X MUL Reg1, Reg SAVE X1, Reg1

P3 X3 = X2 + X1 X2 = X X1 LOAD Reg1, X1 LOAD Reg2, X2 ADD Reg2, Reg1 SAVE X3, Reg2 LOAD Reg, X SUB Reg, Reg1 SAVE X2, Reg

Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 1 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh bit h thng s dng lp lch Round Robin vi thi gian lng t bng thi gian thc hin 10 lnh Assembly. Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 1 16. Trong c ch phn on b nh c xy ra phn mnh trong hay khng. Gii thch. 17. Mt tin trnh trng thi running th chc chn trong on gng. ng hay sai? Gii thch ngn gn. 18. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0 15 P2 2 10 P3 4 2 P4 5 5 P5 10 1 Nu h iu hnh s dng lp lch Round Robin vi thi gian lng t bng 5 th sau bao lu P2 hon thnh cng vic. 19. Trong ch phn trang 2 mc( a ch lgic dng <P1, P2, D>), h thng s dng 10bit cho P1, 10bit cho P2, 12bit nh v mt nh trong trang. Tnh kch thc b nh vt l v kch thc 1 trang nh vt l. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5,6,7,8,9,10,1,2,3,4,5,6,7,8,9,10,1,2,3,4,5,6,7,8,9,10 Gi s ti thi im ban u cc trang 1ang c mt trong b nh. Tnh s li trang (page fault) trong trng hp h thng c 1 frames theo cc gii thut: FIFO, LRU. 20. Trong c ch phn trang n gin, kch thc b nh vt l 64MB, kch thc 1 trang nh l 1MB v khng gian a ch logic c 15 trang. Tnh s bit a ch vt l v logic. 21. Gi s c 5 tin trnh P1 P5 u mun vo on gng v ban u lock=false , P1 thc hin u tin, kim tra Test&Set ri vo on gng. Gi s khi P1 trong on gng, tt c tin trnh cn li u kim tra test v set. Sau khi P1 thc hin xong on gng th look c cp nht bao nhiu ln v c gi tr bng bao nhiu.

22. Cho mt chng trnh gm cc mdun sau: - M-dun chng trnh chnh A(i hi b nh 10KB); mi m-dun ctr khc u ph thuc vo n. M-un A s dng 2 mdun c lp B(30KB), C(35KB) - B s dng 2 m-dun c lp D(20KB), E(10K) - C s dng 2 m-dun c lp G(10KB), H(10KB) - H s dng 2 m-dun c lp I(15KB), J(5KB) Cy chng trnh nh sau: A 10KB

B 30KB D 20KB E 10K G 10K

35KB H 10KB J 5K

I 15KB

Tnh tng dung lng b nh cn thit thc hin chng trnh ny khi p dng c ch Overlay 23. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic sau: Segment 0 1 2 3 4 Tnh a ch vt l tng ng vi cc a ch logic sau: A. 0,430 B. 3,10 C. 2,500 Base 219 2300 90 1327 1952 Length 600 14 100 580 96

Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 1 1. Trong mt on gng c th c nhiu tin trnh trng thi running hay khng, gii thch. 2. Vi gii php Test&Set ca Peterson, khi mt tin trnh trong on gng th cc tin trnh khc c thit lp li gi tr ca clock khng. Gii thch ngn gn. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0 10 P2 2 10 P3 4 2 P4 6 5 P5 10 1 Tnh thi gian hon thnh trung bnh cho cc tin trnh khi s dng cc gii thut iu phi RR vi thi gian lng t bng 2. Trong gii thut lp lch Round-Robin vi thi gian lng t bng 3, gi s thi im hin ti c hai tin trnh P1 c thi gian s dng CPU bng 10, P2 c thi gian s dng CPU bng 15 trong hng i sn sng (P1 n trc P2, khng c tin trnh no ang s dng CPU). Tnh thi gian hon thnh ca tin trnh (b qua thi gian chuyn trng thi tin trnh). Phn bit a ch lgic v a ch vt l. Cc c ch lin kt a ch no c a ch lgic v a ch vt l ging nhau; c ch no c a ch lgic v a ch vt l khc nhau. Gii thch. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5. Gi s ti thi im ban u cc trang 1, 2, 3, 4, 5 ang c mt trong b nh theo ng th t. Trong trng hp h thng c 5 frames, v lc phn phi frames v tnh s li trang(Page Fault) theo cc gii thut LRU(Least Recently Used). Trong c ch phn trang n gin, gi s s bits nh s trang l 8, s bits nh a ch nh trong trang l 10, khng gian nh vt l gm 1024 trang nh vt l (frame). Tnh dung lng b nh vt l. a ch (100, 200) c phi l a ch hp l khng. a ch (512, 100) c hp l khng. a ch (100, 2024) c hp l khng.

3.

4.

5.

6.

7.

8. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic sau: Tin trnh P1 P2 Cng vic X2 = X1 + X2 X1 = X1 * X2 X1 = X1 * X M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 ADD Reg2, Reg1 MUL Reg1, Reg2 SAVE X2, Reg2 SAVE X1, Reg1 LOAD Reg, X MUL Reg1, Reg SAVE X1, Reg1

P3 X3 = X2 + X1 X2 = X X1 LOAD Reg1, X1 LOAD Reg2, X2 ADD Reg2, Reg1 SAVE X3, Reg2 LOAD Reg, X SUB Reg, Reg1 SAVE X2, Reg

Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 1 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh bit h thng s dng lp lch Round Robin vi thi gian lng t bng thi gian thc hin 7 lnh Assembly.

Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 2 1. Ti sao cc frame vt l c kch thc li l ly tha ca 2. Trong ch phn trang b nh, cho kch thc 1 frame l 1MB, tnh s bits dng nh a ch offset (d) trong da ch lgic (p, d). 2. 3. Gii thch ti sao khi phn phi ti nguyn theo chui an ton th khng xy ra deallock?. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0 15 P2 2 10 P3 4 2 P4 5 5 P5 10 1 Tnh thi gian hon thnh trung bnh ca cc tin trnh nu h iu hnh s dng lp lch SJF (Short Job First) khng c quyn. 4. Trong ch phn on (a ch lgic dng <segment, offset>), h thng s dng 10bits nh a ch on, 10bits nh a ch offset. Tnh kch thc b nh vt l. a ch (100, 2024) c phi l a ch hp l khng. a ch (2024, 100) c phi l a ch hp l khng. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5,6,7,8,9,10,1,2,3,4,5,6,7,8,9,10,1,2,3,4,5,6,7,8,9,10 Gi s ti thi im ban u cc trang 1, 2, 3, 4, 5 ang c mt trong b nh. Tnh s li trang (page fault) trong trng hp h thng c 10 frames theo cc gii thut: FIFO, LRU. 5. Trong c ch phn on b nh c xy ra phn mnh ngoi hay khng. Gii thch ngn gn. 6. Gi s c 10 tin trnh P1 P10 u mun vo on gng v ban u l oc k =t rue. Hi c tin trnh no (t P1 n P10) vo c on gng khng. Sau khi P10 gi Te st &Se t () th lock c cp nht my ln. Cho bit gi tr l oc k. 7. Trong s phn phi ti nguyn di y, cho bit h thng c deadlock khng. Gii thch ngn gn.

R2 P R1 P P P
8. Cho bng phn on:

R3

R5 P R4

R6
Segment 0 1 2 3 4 Base 219 2300 90 1327 1952 Length 600 14 100 580 96

Tnh a ch vt l tng ng vi cc a ch logic sau: A. 0,430 B. 3,10 C. 2,500 D. 4, 100 E. 6, 10 F. 1, 10

Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 1 1. Trong mt on gng c th c nhiu tin trnh trng thi running hay khng, gii thch. 2. Vi gii php Test&Set ca Peterson, khi mt tin trnh trong on gng th cc tin trnh khc c thit lp li gi tr ca clock khng. Gii thch ngn gn. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0 10 P2 2 10 P3 4 2 P4 6 5 P5 10 1 Tnh thi gian hon thnh trung bnh cho cc tin trnh khi s dng cc gii thut iu phi RR vi thi gian lng t bng 2. Trong gii thut lp lch Round-Robin vi thi gian lng t bng 3, gi s thi im hin ti, trong hng i sn sng, c hai tin trnh P1 c thi gian s dng CPU bng 10, P2 c thi gian s dng CPU bng 15 (P1 n trc P2, khng c tin trnh no ang s dng CPU). Tnh thi gian hon thnh v thi gian i ca tin trnh P1. Phn bit a ch lgic v a ch vt l. Cc c ch lin kt a ch no c a ch lgic v a ch vt l ging nhau; c ch no c a ch lgic v a ch vt l khc nhau. Gii thch. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5. Gi s ti thi im ban u cc trang 1, 2, 3, 4, 5 ang c mt trong b nh theo ng th t. Trong trng hp h thng c 5 frames, v lc phn phi frames v tnh s li trang(Page Fault) theo cc gii thut LRU(Least Recently Used). Trong ch phn trang 2 mc (a ch lgic dng <P1, P2, D>), h thng s dng 10bit cho P1, 10bit cho P2, 12bit nh v mt nh trong trang. a ch (10, 200, 300) c hp l khng. a ch (2023, 10, 100) c hp l khng. Trong c ch phn trang n gin, gi s s bits nh s trang l 8, s bits nh a ch nh trong trang l 10, khng gian nh vt l gm 1024 trang nh vt l (frame). Tnh dung lng b nh vt l. a ch (100, 200) c phi l a ch hp l khng. a ch (512, 100) c hp l khng. a ch (100, 2024) c hp l khng.

3.

4.

5.

6.

7.

8.

9. Cho cc tin trnh P1, P2, P3 thc hin cc cng vic sau: Tin trnh P1 P2 Cng vic X2 = X1 + X2 X1 = X1 * X2 X1 = X1 * X M Assembly LOAD Reg1, X1 LOAD Reg1, X1 LOAD Reg2, X2 LOAD Reg2, X2 ADD Reg2, Reg1 MUL Reg1, Reg2 SAVE X2, Reg2 SAVE X1, Reg1 LOAD Reg, X MUL Reg1, Reg SAVE X1, Reg1

P3 X3 = X2 + X1 X2 = X X1 LOAD Reg1, X1 LOAD Reg2, X2 ADD Reg2, Reg1 SAVE X3, Reg2 LOAD Reg, X SUB Reg, Reg1 SAVE X2, Reg

Gi s: X1, X2, X3, X l cc bin dng chung; ban u X1 = X2 = X3 = X = 10 v cc tin trnh n hng i ready theo th t P1, P2, P3. Tnh gi tr cc bin khi cc tin trnh hon thnh bit h thng s dng lp lch Round Robin vi thi gian lng t bng thi gian thc hin 7 lnh Assembly.

Khoa Cng Ngh Thng Tin Hc Vin K Thut Mt M Nguyn L H iu Hnh Thi gian lm bi: 90 pht. thi s 2 1. Ti sao cc frame vt l c kch thc li l ly tha ca 2. Trong ch phn trang b nh, cho kch thc 1 frame l 1MB, tnh s bits dng nh a ch offset (d) trong da ch lgic (p, d). 2. Gii thch ti sao khi phn phi ti nguyn theo chui an ton th khng xy ra deallock?. 3. Ti mt thi im cho trng thi h thng nh sau: Tin trnh Thi gian n Thi gian s dng CPU P1 0 15 P2 2 10 P3 4 2 P4 5 5 P5 10 1 Tnh thi gian hon thnh trung bnh ca cc tin trnh nu h iu hnh s dng lp lch SJF (Short Job First) khng c quyn. 4. Trong ch phn on (a ch lgic dng <segment, offset>), h thng s dng 10bits nh a ch on, 10bits nh a ch offset. Tnh kch thc b nh vt l. a ch (100, 2024) c phi l a ch hp l khng. a ch (2024, 100) c phi l a ch hp l khng. Cho chui tham chiu trang sau: 1, 2, 3, 4, 5,6,7,8,9,10,1,2,3,4,5,6,7,8,9,10,1,2,3,4,5,6,7,8,9,10 Gi s ti thi im ban u cc trang 1, 2, 3, 4, 5 ang c mt trong b nh. Tnh s li trang (page fault) trong trng hp h thng c 10 frames theo cc gii thut: FIFO, LRU. 5. Trong c ch phn on b nh c xy ra phn mnh ngoi hay khng. Gii thch ngn gn. 6. Gi s c 10 tin trnh P1 P10 u mun vo on gng v ban u l oc k =t rue. Hi c tin trnh no (t P1 n P10) vo c on gng khng. Sau khi P10 gi Te st &Se t () th lock c cp nht my ln. Cho bit gi tr l oc k. 7. Trong s phn phi ti nguyn di y, cho bit h thng c deadlock khng. Gii thch ngn gn.

R2 P2 R1 P1 P3 P5 R6
8. Cho bng phn on: Segment 0 1 2 3 4 Base 219 2300 90 1327 1952 Length 600 14 100 580 96

R3

R5 P4 R4

Tnh a ch vt l tng ng vi cc a ch logic sau: A. 0,430 B. 3,10 C. 2,500 D. 4, 100 E. 6, 10 F. 1, 10