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BO CO TIN TRNH N GIA K

MC LC :
Gii thiu
Trang ba
Phiu giao ti n
Bn nhn xt ca gio vin hng dn
Bn nhn xt ca gio vin phn bin
Li cm n
Muc lc

Phn I:

C S L THUYT

Chng 1:

Dn nhp...................................................................................

1.1 L do chn ti.......................................................................................

1.2 ngha khoa hc v thc tin ca ti..................................................
Chng 2 : Tm hiu v FPGA & kit DE2.................................................
2.1

FPGA..........................................................................................
2.1.1 FPGA l g ?................................................................
2.1.2 Lch s ca FPGA.......................................................
2.1.3 Kin trc ca FPGA....................................................
3.1.1.1 Khi logic................................................
3.1.1.2 H thng mch lin kt............................
3.1.1.3
Cc phn t tch hp sn.........................
3.1.4 ng dng.....................................................................
3.1.5 ngha v vai tr ca FPGA......................................
4.2 Kit DE2.....................................................................................
4.2.1 Gii thiu....................................................................
4.2.2 Thnh phn..................................................................
4.2.3 Mt vi ng dng........................................................
Chng 3: Gii thiu v quartus II............................................................
3.1

Cc bc thc hin mt thit k.................................................

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3.2
3.3

Gii thiu....................................................................................
Cch np chng trnh cho Quartus II.......................................
3.3.1 To 1 project..............................................................
3.3.2 Vit chng trnh v bin dch...................................
3.3.3 To file m phng v m phng................................
3.3.4 Cu hnh chn v np ln board.................................

Chng 4:

Gii thiu VERILOG...............................................................

4.1
4.2
4.2
4.3
4.4
4.5
4.6
4.7

Verilog l g ?.............................................................................
Cc cng c bn trong Verilog...................................................
Cc dng d liu.........................................................................
Ton t, ton hng......................................................................
Module.......................................................................................
Khun mu hnh vi....................................................................
Khi always v khi initial.........................................................
Chc nng linh kin...................................................................

Phn II:

THIT K...................................................................................

Phn III:

KT LUN..................................................................................

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DANH SCH HNH

Hnh 3.1 Kin trc tng quan FPGA...............................................................
Hnh 3.2 Khi logic FPGA..............................................................................
Hnh 3.3 Board DE2........................................................................................
Hnh 3.4 Thng tin chi tit ca board DE2.....................................................
Hnh 3.5 TV board..........................................................................................
Hnh 3.6 Chng trnh v (paintbrush)...........................................................
Hnh 3.7 My ht karaoke v my chi nhc t card SD................................
Hnh 4.1 Quy trnh thit k CAD thng dng.................................................
Hnh 4.2 Hp hi thoi to mi project...........................................................
Hnh 4.3 Hp thoi la chn chip...................................................................
Hnh 4.4 La chn loi file cn to.................................................................
Hnh 4.5 Bin dch chng trnh.....................................................................
Hnh 4.6 Ca s chn cc tn hiu vo ra a vo dng sng m phng.......
Hnh 4.7 Thit lp gi tr cho cc tn hiu.......................................................
Hnh 4.8 Dng sng kim tra trc khi m phng..........................................
Hnh 4.9 Chn ch m phng chc nng cho trnh m phng...................
Hnh 4.10 Dng sng m phng chc nng.....................................................
Hnh 4.12 Danh sch cc chn c th c gn...............................................
Hnh 4.13 Giao din ca trnh np v cu hnh FPGA.....................................
Hnh 5.1 S mch gii m..........................................................................
Hnh 5.2 Mch gii m 3 sang 8......................................................................
Hnh 5.3 IC74LS138.......................................................................................
Hnh 5.4 Mch gii m dng IC74LS138.......................................................
Hnh 5.5 Cc dng sng vo ra ca mch gii m 3 sang 8............................
Hnh 5.6 S b chn knh..........................................................................
Hnh 5.7 Mch chn knh 2 ng vo..............................................................
Hnh 5.8 Mch chn knh 4 ng vo..............................................................
Hnh 5.9 Mch chn knh dng IC74LS151...................................................
Hnh 5.10 Cc dng sng ca mch chn knh 4 vo......................................
Hnh 5.11 Mch cng bn phn.......................................................................
Hnh 5.12 Mch cng ton phn......................................................................
Hnh 5.13 IC cng ton phn...........................................................................
Hnh 5.14 Mch cng nhn trc s nh..........................................................
Hnh 5.15 Mch cng BCD..............................................................................
Hnh 5.16 Cc dng sng ca mch cng bn phn.........................................
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Hnh 5.17 M hnh m ln.............................................................................

Hnh 5.18 M hnh m xung........................................................................
Hnh 5.19 B m ln nh phn 4 bit dng JK-FF...........................................
Hnh 5.20 Cc dng sng ng vo ra ca mch m.......................................
Hnh 6.1 S khi mt my tnh c in.....................................................
Hnh 6.2 S khi ca vi x l.....................................................................
Hnh 6.3 S khi h vi x l......................................................................
Hnh 6.4 Cc tn hiu c bn trong P............................................................
Hnh 6.5 nh th bus c bn..........................................................................
Hnh 6.6 Giao tip bus c bn.........................................................................
Hnh 6.7 Gii m a ch dng 74LS138.........................................................
Hnh 6.8 74LS138 mc cascaded (lin tng)...................................................
Hnh 6.9 Gii m dng b so snh..................................................................
Hnh 6.10 nh th c b nh.........................................................................
Hnh 6.11 nh th ghi b nh.........................................................................

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PHN I
C S L THUYT
Phn I
CHNG 1

C S L THUYT
DN NHP

1.1 L do chn ti
Gn na th k qua cng vi s pht trin khng ngng ca khoa hc k
thut. Lnh vc in t cng c nhng tin b vt bc gp phn khng nh vo
phc v mi mt ca i sng trong cng nghip cng nh trong dn dng. S
pht trin ca cng ngh mch tch hp (ch to cc IC) cng vi s ra i ca k
thut s cng lm tng tm nh hng ca k thut in t.
Nm 1971 vi s ra i ca vi x l, lm cho k thut s pht trin nhy
vt ng thi nhng ng dng ca n trong cuc sng cng ngy cng a dng
hn. S ra i ca cc vi mch lp trnh nh vi iu khin, vi x l, vi mch s lp
trnh to ra mt bc ngoc trong lnh vc x l, iu khin. Chng lm cho
lnh vc x l, iu khim tr nn t ng ha v ngy cng hin i hn. Trong
cng nghip, cc thit b iu khim bng c kh th s c chnh xc v an ton
km c th bng nhng thit b iu khin t ng vi chnh xc cao hn, an
ton hn. Nh nng sut lao ng khng ngng c nng cao. Trong i sng
hng ngy, vi x l c ng dng rt nhiu vo cc thit b dn dng nh my

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tnh, ti vi, my iu ha nhit , l vi ba qua lm cho cc thit b tr nn a

chc nng hn, d dng s dng hn, tin nghi hn.
Vi nhng ng dng rng ri nh trn, thit ngh vic tm hiu vi x l, vi
iu khin v nhng ng dng ca n l rt cn thit. Trong khun kh hn hp
ca ti, cng nh kin thc v kh nng, ti ch tm hiu mt ng dng nh ca
vi x l l thit k mt b vi x l n gin.
1.2 ngha khoa hc v thc tin ca ti
1.2.1 ngha khoa hc
Qua ti ny ti nm c cc vn sau:
-

Hiu c phn no cng vic thit k mt h thng s

Nm c cch thit k h tng s vi Altera FPGA

Hiu thm v kit DE2 ca Altera

1.4.1

ngha thc tin

B x l c kh nng thc hin cc ch dn s dng b nh v cc thit b

my tnh
1.5

Tnh hnh nghin cu

Hin nay trong thc t cc b vi x l c rt nhiu ngi qua tm v thit

k. c bit n c thit k s dng cho cc CPU ca my tnh.

1.6

Phng php nghin cu

S dng cc phng php v phng tin nghin cu thu thp ti liu v

ti xc nh. D liu thu thp c s l cht liu xy dng nn ti.

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iu cn thit l thu thp ti liu mt cch y , chnh xc v ph hp vi ti

ang thc hin.
y ti s dng phng php tham kho ti liu l ch yu. Vic tham
kho cc ti liu nhm gom gp li cc kin thc cn thit. Sau cc ti liu phi
c chn lc k cng trn c s k tha nhng nn tng ng thi cn khc phc
nhng mt hn ch. a phn cc ti liu tham kho l cc sch chuyn nghnh v
nhng lun vn tt nghip ca cc kha trc.
Vic xy dng ti c thc hin theo ng cu trc ca mt lun vn do
nh trng quy nh nhm m bo tnh s phm v ph hp vi k hoch o to
ca nh trng.

CHNG 2

TM HIU V FPGA & KIT DE2

2.1 FPGA

2.2.2 FPGA l g ?
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FPGA l vit tt ca thut ng ting anh Field programmable Gate Array,

l vi mch dng cu trc mng phn t logic m ngi dng c th lp trnh c.
Vi mch FPGA c cu thnh t cc b phn:
Cc khi logic c bn lp trnh c (logic block)

H thng mch lin kt lp trnh c

Khi vo/ra (IO Pads)
Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...

FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC,

nhng nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k
trn th vin logic th FPGA khng t c mc ti u nh nhng loi ny, v
hn ch trong kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA
u vit hn ch c th ti cu trc li khi ang s dng, cng on thit k n
gin do vy chi ph gim, rt ngn thi gian a sn phm vo s dng.
Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc
mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im: tc v
ti lp trnh ca FPGA thc hin n gin hn; kh nng lp trnh linh ng hn;
v khc bit quan trng nht l kin trc ca FPGA cho php n c kh nng cha
khi lng ln cng logic (logic gate), so vi cc vi mch bn dn lp trnh c
c trc n.
Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng
m t phn cng HDL nh VHDL, Verilog, AHDL, cc hng sn xut FPGA ln
nh Xilinx, Altera thng cung cp cc gi phn mm v thit b ph tr cho qu
trnh thit k, cng c mt s cc hng th ba cung cp cc gi phn mm kiu ny
nh Synopsys, Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc

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bc ca ton b quy trnh thit k IC chun vi u vo l m thit k trn HDL

(cn gi l m RTL).
2.2.3 Lch s ca FPGA
FPGA c thit k u tin bi Ross Freeman, ngi sng lp cng ty
Xilinx vo nm 1984, kin trc mi ca FPGA cho php tch hp s lng tng
i ln cc phn t bn dn vo 1 vi mch so vi kin trc trc l CPLD.
FPGA c kh nng cha ti t 100.000 n hng vi t cng logic, trong khi
CPLD ch cha t 10.000 n 100.000 cng logic; con s ny i vi PAL, PLA
cn thp hn na ch t vi nghn n 10.000.
CPLD c cu trc t s lng nht nh cc khi SPLD (Simple
programable devices, thut ng chung ch PAL, PLA). SPLD thng l mt mng
logic AND/OR lp trnh c c kch thc xc nh v cha mt s lng hn
ch cc phn t nh ng b (clocked register). Cu trc ny hn ch kh nng
thc hin nhng hm phc tp v thng thng hiu sut lm vic ca vi mch ph
thuc vo cu trc c th ca vi mch hn l vo yu cu bi ton.
Kin trc ca FPGA l kin trc mng cc khi logic, khi logic, nh hn
nhiu nu em so snh vi mt khi SPLD, u im ny gip FPGA c th cha
nhiu hn cc phn t logic v pht huy ti a kh nng lp trnh ca cc phn t
logic v h thng mch kt ni, t c mc ch ny th kin trc ca FPGA
phc tp hn nhiu so vi CPLD.
Mt im khc bit vi CPLD l trong nhng FPGA hin i c tch hp
nhiu nhng b logic s hc s b ti u ha, h tr RAM, ROM, tc cao,
hay cc b nhn cng (multication and accumulation, MAC), thut ng ting Anh
l DSP slice dng cho nhng ng dng x l tn hiu s DSP.

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Ngoi kh nng ti cu trc vi mch ton cc, mt s FPGA hin i cn h

tr ti cu trc cc b, tc l kh nng ti cu trc mt b phn ring l trong khi
vn m bo hot ng bnh thng cho cc b phn khc.
2.2.4 Kin trc ca FPGA
Cu trc tng th ca mt FPGA c minh ha hnh sau.

Hnh 3.1 Kin trc tng quan FPGA

2.2.4.1

Khi logic

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Hnh 3.2 Khi logic FPGA

Phn t chnh ca FPGA l cc khi logic (logic block). Khi logic c
cu thnh t LUT v mt phn t nh ng b flip-flop, LUT (Look up table) l
khi logic c th thc hin bt k hm logic no t 4 u vo, kt qu ca hm ny
ty vo mc ch m gi ra ngoi khi logic trc tip hay thng qua phn t nh
flip-flop.
Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi
nim SLICE, 1 Slice to thnh t gm 4 khi logic, s lng cc Slices thay i t
vi nghn n vi chc nghn ty theo loi FPGA.
Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h
tr thm 2 u vo b sung t cc khi logic phn b trc v sau n nng tng s
u vo ca LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic.
2.2.4.2 H thng mch lin kt

Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai

phng ngang v ng, ty theo tng loi FPGA m cc ng kt ni c chia
thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c 3 loi kt ni: ngn,
di v rt di. Cc ng kt ni c ni vi nhau thng qua cc khi chuyn
mch lp trnh c (programable switch), trong mt khi chuyn mch cha mt
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s lng nt chuyn lp trnh c m bo cho cc dng lin kt phc tp khc

nhau.
2.2.4.3 Cc phn t tch hp sn

Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t

tch hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex
4,5 ca Xilinx c cha nhn x l PowerPC, hay trong Atmel FPSLIC tch hp
nhn ARV, hay cho nhng ng dng x l tn hiu s DSP trong FPGA c
tch hp cc DSP Slide l b nhn cng tc cao, thc hin hm A*B+C, v d
dng Virtex ca Xilinx cha t vi chc n hng trm DSP slices vi A, B, C 18bit.
2.2.5

ng dng
ng dng ca FPGA bao gm: x l tn hiu s DSP, cc h thng hng

khng, v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), cc h

thng iu khin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m
hc, m hnh phn cng my tnh...
Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp
nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi
ra nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi
khi lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.
2.2.5

ngha v vai tr ca FPGA

Vi kh nng ti cu hnh mnh, FPGA ng mt vai tr v cng to ln

trong vic gim gi thnh v thi gian ch to ASIC bng cch s dng FPGA
trong qu trnh thit k lun l trc khi a ra sn xut cc ASIC mu. Quy trnh
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sn xut Chip ASIC bng cch ny gi l fabless rt ph bin hin nay trn th
gii, gip cc cng ty nh v va v c bit l cc nc yu v cng ngh nh
Vit nam tham gia vo th gii ca IC.
FPGA rt hay c s dng trong cc h thng SDR (Software Defined
Radio) v kh nng ti cu hnh gip cc chc nng ca thit b c th thay i
nhanh chng.
2.3 Kit DE2
Kit DE2 cung cp cho ngi s dng nhiu c im linh hot hc tp v
c th pht trin nhiu d n a phng tin khc nhau. Chng c thit k
khng nhng ph hp cho mi trng hp tp cc trng i hc v cao ng
m cn ph hp vi c trong mi trng lm vic cng nghip. Cc khi thit k
ng dng trn KIT c chn lc da trn nhng thit k ph bin nht trong cc
sn phm a phng tin nh DVD, VCD, MP3 player v nhiu ng dng iu
khin khc... Kit DE2 cho php ngi dng nhanh chng thu hiu c nhng th
thut thit k cc d n cng nghip. Ngoi ra n cn cung cp mt nn tng
kin thc c bn cho ngi dng am m trong lnh vc thit k vi mch nh pht
trin nhng h thng k thut s tinh vi.
2.3.1 Gii thiu
Board DE2 l board mch phc v cho vic nghin cu v pht trin v cc
lnh vc lun l s hc (digital logic), t chc my tnh (computer organization) v
FPGA.

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Hnh 3.3 Board DE2

2.3.2 Thnh phn
Board DE2 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht
trin, di y l thng tin chi tit ca mt board DE2:

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Hnh 3.4

GVHD: V TH BCH NGC

Thng tin chi tit ca board DE2

FPGA:
- Vi mch FPGA Altera Cyclone II 2C35.
- Vi mch Altera Serial Configuration EPCS16.
Cc thit b xut nhp:
- USB Blaster cho lp trnh v iu khin API ca ngi dng; h tr c 2
ch lp trnh JTAG v AS.
- B iu khin Cng 10/100 Ethernet.
- Cng VGA-out.
- B gii m TV v cng ni TV-in.
- B iu khin USB Host/Slave vi cng USB kiu A v kiu B.
- Cng ni PS/2 chut/bn phm.

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- B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm

line-in, line-out, v microphone.
- 2 Header m rng 40-pin vi lp bo v diode.
- Cng giao tip RS-232 v cng ni 9-pin.
- Cng giao tip hng ngoi.
B nh:
- SRAM 512-Kbyte.
- SDRAM 8-Mbyte.
- B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte).
- Khe SD card.
Switch, cc n led, LCD, xung clock
- 4 nt nhn, 18 nt gt.
- 18 LED , 9 LED xanh, 8 Led 7 on
- LCD 16x2
- B dao ng 50-MHz v 27-MHz cho ng h ngun.
2.3.3 Mt vi ng dng ca board DE2
ng dng lm TV box

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Hnh 3.5 TV box

Chng trnh v bng chut USB (paintbrush)

Hnh 3.6 Chng trnh v (paintbrush)

My ht Karaoke v my chi nhc SD

Hnh 3.7 My ht karaoke v my chi nhc t card SD

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CHNG 3
3.1

GVHD: V TH BCH NGC

GII THIU V QUARTUS II

Cc bc thc hin mt thit k

Cng c CAD (Computer Aided Design) to nn s thun li khi thc hin

mt mch logic mong mun bng cch s dng cc thit b logic lp trnh c,
nh chip FPGA.

Hnh 4.1 Quy trnh thit k CAD thng dng

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Design Entry (nhp thit k): Mch logic mong mun c m t bng ngn
ng m t phn cng nh VHDL/Verilog hoc bng s mch.

Synthesis (tng hp): Cng c thc hin chuyn cc biu din mch in
trn thnh dng tp netlist, trong biu din cc thnh phn logic cn cho
mch cng cc kt ni gia cc thnh phn logic.

Functional Simulation (m phng chc nng): Mch tng hp c kim

tra phn tch tnh chnh xc v chc nng; trnh m phng khng quan
tm n vn thi gian

Fitting: Cng c CAD Fitter xc nh v tr t cc thnh phn logic a

ra trong tp netlist vo trong FPGA, ng thi xc nh cc ng i dy
trong FPGA kt ni cc thnh phn logic.

Timinh Analysis (phn tch thi gian): Tr ng truyn theo cc ng

khc nhau trong mch c fit trn c phn tch xc nh kh nng
hot ng mong mun ca mch.

Timing Silmulation (m phng thi gian): Mch c fit c kim tra

phn tch c v chc nng v c v mt thi gian.

Programming and configuration (lp trnh v cu hnh): Mch logic mong

mun c trin khai trn FPGA/CPLD thc t thng qua chng trnh np
v cu hnh cho FPGA/CPLD.

3.2

Gii thiu
B phn mm thit k i km vi board DE2 bao gm 2 a: Quartus II v

Nios II Integrated Development Environment (IDE).

Quartus II l phn mm h tr tt c mi qu trnh thit k mt mch logic,
bao gm qu trnh thit k, tng hp, placement v routing (sp xp v chy dy),
m phng (simulation), v lp trnh ln thit b (DE2).
3.3

Cch np chng trnh cho Quartus II

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3.3.1

GVHD: V TH BCH NGC

To 1 project

Bc 1. Vo Menu > file chn New Project Wizard

Bc 2. Ta chn th mc cha project v t tn cho project, xong chn Next
xem hnh bn di

Hnh 4.2 Hp hi thoi to mi project

Bc 3. Sau ta chn hng sn xut chip v tn loi chip trn mch.

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Hnh 4.3 Hp thoi la chn chip

Bc 4. Cui cng chn Finish hon tt
3.3.2

Vit chng trnh v bin dch

Bc 1. Vo Menu > file chn New

Bc 2. Sau chn loi file m chng ta mun vit chng trnh. y ta chn
loi file VHDL

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Hnh 4.4 La chn loi file cn to

Bc 3. Nhp m VHDL vo trong ca s son tho vn bn.
Bc 4. Chn mc File > Save As m ca s Save As. Trong phn Save as
type chn VHDL File. Trong phn File name nhp test. Nhp chn Save a
tp ny vo trong th mc ca d n.
Bc 5. Bin dch chng trnh.

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Hnh 4.5 Bin dch chng trnh

Bc 6. Chn OK
3.3.3 To file m phng (simulate) v bt u simulate
Bc 1. Vo Menu > file chn New, sau chn Vector Waveform File
Bc 2: Nhp chn Edit > End Time v nhp vo 200 ns trong hp thoi bung ra,
iu ny cho php thi gian m phng t 0 dn 200 ns. Nhp chn View > Fit in
Window nhn thy ton b phn m phng t 0 n 200 ns.
Bc 3: Nhp chn Edit > Insert > Insert Node or Bus m ca s nhp cc u
vo ra. Nhp nt Node Finder m ca s nh trong hnh 4.5.

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Hnh 4.6 Ca s chn cc tn hiu vo ra a vo dng sng m phng

hin th ra tt c cc chn :

Chn Pins: all.

Sau chn nt List hin tt c cc chn

Nt >

: Chn tng tn hiu

Nt >> : Chn tt c cc tn hiu

Nt <

: B tng tn hiu

Nt << : B tt c cc tn hiu
Nhn OK hon tt vic chn tn hiu

Bc 4. Thit lp gi tr cc tn hiu
Ta r chut t khi chng li
Sau s dng cc nt 0, 1 thit lp gi tr cho chng (xem hnh 4.6)

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Hnh 4.7 Thit lp gi tr cho cc tn hiu

Bc 5. Sau khi thit lp gi tr ca cc chn xong ta Save li.
Bc 6: Thc hin m phng
M phng chc nng
Nhp chn Assignments > Settings. Bn tri ca ca s Settings nhp chn
Simulator Settings c ca s nh trong Hnh 4.7, chn Functional trong mc
chn ch m phng, v nhp OK.

Hnh 4.8 Dng sng kim tra trc khi m phng

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Hnh 4.9 Chn ch m phng chc nng cho trnh m phng

Nhp chn Processing > Generate Functional Simulation Netlist. Sau
nhp chn Processing > Start Simulation thc hin m phng. Kim tra dng
sng u ra c ng theo chc nng ca mch hay khng.

Hnh 4.10 Dng sng m phng chc nng

M phng thi gian
Nhp chn Assignments > Settings. Bn tri ca ca s Settings nhp chn
Simulator Settings c ca s nh trong Hnh 4.8, chn Timing trong mc chn
ch m phng, v nhp OK.
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Sau thc hin m phng theo cch va thc hin nh trn, quan st dng
sng u ra.
3.3.4 Cu hnh chn v np ln board
Cu hnh chn
cu hnh chn bn tin hnh ln lt theo cc bc sau:
Bc 1. Chn Assignments-> Pins ca s la chn chn s xut hin nh hnh:

Hnh 4.11 Ca s gn chn

Bc 2. Nhp p vo <<new>> ct To nh trn hnh. Mt menu cha danh
sch cc chn cn gn s c hin ra. Bn chn chn cn gn (v d y chn
tn hiu cn gn x1).
Bc 3. Tip theo nhn vo <<new>> ct Location. Mt menu cha danh
sch cc chn trong FPGA s c hin ra bn chn chn ca FPGA s ni vi tn
hiu (v d y chn chn PIN_N25).
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Hnh 4.12 Danh sch cc chn c th c gn

Bc 4. Lp li qu trnh ny cho n khi gn ht cc chn linh kin.
Bc 5. lu li file cu hnh chn bn chn File -> Export, sau nhp tn file
cn lu.
Np ln board
Bc 1: Nhp chn Tools > Programmer c ca s nh trong Hnh 4.12. nh
du vo ty chn Program/Configue cho php np tp cu hnh light.sof.

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Hnh 4.13 Giao din ca trnh np v cu hnh FPGA

Bc 2: Nhp nt Start bn tri ca s np tp cu hnh ny xung FPGA. Sau
khi np thnh cng xung FPGA, hy kim tra mch in ny thc hin trn FPGA
c chy ng theo chc nmg mong mun hay khng bng cch dng cc chuyn
mch SW nhp u vo ri quan st u ra hin th trn LED.

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CHNG 4

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TM HIU VERILOG / VHDL

I. Tm hiu v Verilog HDL/VHDL

1. Verilog HDL la mot trong hai ngon ng mo phong
phan cng thong dung nhat,c dung trong thiet
ke IC, ngon ng kia la VHDL.
HDL cho phep mo phong cac thiet ke de dang,
sa cha loi, hoac thc nghiem, bang nhng cau
truc khac nhau. Cac thiet ke c mo ta trong HDL
la nhng ky, thuat oc lap, de thiet ke, de thao
g, va thng de oc hn dang bieu o, ac
biet la cac mach ien ln.
Verilog thng c m t thit k bn dng:

Thuat toan (mot so lenh giong ngon ng C

nh: if, case, for,while).

Chuyen oi thanh ghi (ket noi bang cac bieu

thc Boolean).

Cac cong ket noi( cong: OR, AND, NOT).

Chuyen mach (BJT, MOSFET).

Ngon ng nay cung ch ro cach thc ket noi,
ieu khien vao/ra trong mo phong.
Cu trc chng trnh dung ngn ng Verilog:
// Khai bao module
Module ten chng trnh (ten bien I/O);
// ten chng trnh trung ten file.v.
Input [msb:lsb] bien;
Output [msb:lsb] bien;
Reg [msb:lsb] bien reg;
Wire [msb: lsb] bien wire;
// Khai bao khoi always, hoac khoi initial.
cac lenh
Endmodule
2. Nhng tap tin van ban nguon Verilog bao gom
nhng bieu hien thuoc tnh t vng sau ay:

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a. Khong trng:
Khoang trang ngan nhng t va co the cha
khoang cach, khoang dai, dong miva dang ng
dan. Do o, mot lenh co the a ra nhieu dong
phc tap hn ma khong co nhng ac tnh ac
biet.
b. Ch gii:
Nhng chu giai co the ch nh bang hai cach:
( giong trong C/C++).Chu giai c viet sau hai dau
gach xien (//). c viet tren cung mot dong.c
viet gia /* */, khi viet nhieu dong chu giai.
c. Ch s:
Lu tr so c nh ngha nh la mot con so
cua cac bit, gia tr co the la: sonh phan, bat
phan, thap phan, hoac thap luc phan.
d. T nh danh:
T nh danh do ngi dung quy nh cho bien so,
ten ham, ten moun,

ten khoi va ten trng

hp. T nh danh bat au bang mot mau t hoac

ng gach di _ ( khong bat au bang mot con
so hoac $ ) va ke ca moi ch so cua mau t,
nhng con so

va ng gach di, t nh danh

trong Verilog th phan biet dang ch.

2. Ngn ng VHDL trong thit k phn cng
Ngn ng VHDL c cung cp h tr pht trin cc h thng phn
cng da trn cc loi mch(chip) tch hp tc cao(VHSIC-Very High
Speed Integrated Circuit). Vic s dng cc loi chp kiu ny thay th
dn cc IC logic m thng c s dng trong vic thit k mch s, em
li nhiu li ch v thun tin trong vic pht trin cc h thng s m
phng thc thit mch s truyn thng kh hoc khng th thc hin
c.

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VHDL l 1 loi ngn ng m t phn cng. Hin nay c nhiu loi ngn
ng m t phn cng ang c s dng nh l verilog hay ABEL mi
ngn ng c nhng u im v thun tin cho ngi s dng. y chng
ta khng so snh gia cc ngn ng miu t phn cng vi nhau. Vic quan
trong l phi nm bt v s dng thnh thao 1 loi ngn ng khi mi bt
u tip cn vi vic thit k h thng mch s da trn cc chip tch hp.
VHDL khng phi l 1 ngn ng lp trnh tuy vy n cung c h tr
cc cu trc, c php nh ging nh nhng ngn ng lp trnh thng dng
nh C hay Basic. Do vy VHDL s phi lc b i nhng phn khng
thch hp khi p dng cho vic thit k 1 phn cng ch khng phi 1 phn
mm. VHDL l ngn ng miu t phn cng kh thng dng c th tng
thch vi nhiu mi trng ( cng c) pht trin cho chip ca nhiu hng
sn xut chip khc nhau.
S dng VHDL miu t phn cng tc l ch r cch thc giao tip
ca mch cng vi cc mch bn ngoi v hot ng, cu trc bn trong
ca mch n c th p ng v x l cc tn hiu khi lp ghp n vo 1
h thng . Cch thc giao tip bao gm vic thng k s lng cc chn
giao tip vi mch bn ngoi v nh dng cho chng l chn nhp hay l
xut tn hiu.S miu t y c cc mc nh miu t cu trc (Structural)
v miu t cch thc, c tnh (behavioral) Miu t cu trc h thng tc l
miu t h thng thng qua tp hp cc cng logic c bn hoc cc thnh
phn c h tr v cch thc kt ni gia cc thnh phn vi nhau.
Hnh thc miu t ny c s dng nhiu trong cc cng c thit k
phn cng truyn thng. cn i vi ngn ng VHDL th vic s dng
cch thc miu t ny thng qua cc ton t logic (AND, OR,..) tng ng
vi cc thnh phn logc c bn kt hp cc ton t ny hnh thnh ln
cu trc s.
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Hnh thc miu t cao nht l behavioral. Hnh thc ny s ch cch

thc x l tn hiu khi n i qua h thng. M t behavioral c chia
thnh 2 hnh thc miu t l dataflow v Algorithmic. Ngi thit k c
th kt hp cc hnh thc miu t ny vi nhau trong file thit k ca mnh.
Mc m t behavioral thng c ngi thit k s dng do vi hnh
thc m t ny th ngi thit k khng phi quan tm nhiu n cu trc
phn cng bn trong ca h thng m ch tp chung vo m t hay nh
hnh vic x l d liu ca h thng. Cn i vi mc m t cu trc th
i hi ngi thit k phi nm bt v xy dng cu trc ca h thng
thng qua cc phn t logic c bn, khi i hi ngi thit k phi c
rt nhiu kinh nghim trong vic thit k mch s v qu trnh phn tch h
thng rt kh khn. Thng thng ngi thit k thng s dng kiu m
t ny ghp ni cc phn c thit k ca h thng vi nhau.
Cu trc ca 1 file thit k da trn ngn ng VHDL thng thng bao
gm 3 phn:
-phn khai bo cc th vin s dng trong thit k.
-phn khai bo i tng thit k .
-phn m t cu trc ca i tng.
Trn 1 bn thit k c th c nhiu i tng thit k c lp ghp vi
nhau. Mi i tng (entry) c th hiu nh l 1 module mch hay 1 t hp
logic. Cc chn giao tip ca i tng phi c nh ngha trong phn
khai bo i tng.
Trong phn m t cu trc ca i tng th ngi thit k s s dng
cc mc m t cp pha trn m t cu trc bn trong hay cch
thc x l tn hiu ca i tng thit k.
Bi vit ny khng cp su v c php hay k thut lp trnh ca
ngn ng VHDL m ch trnh by mt cch tng quan v cch thc s
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dng ngn ng miu t trong thit k phn cng c s dng cc vi mch t

hp.

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