05-Apr-11

ESD with PIC MCU Part 1

Chapter 1
A VERY BRIEF HISTORY OF MICROPROCESSORS & MICROCONTROLLERS

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Chapter 2 PIC Peripheral Interface Controller

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A generic microcontroller

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Advantages of PIC
It is a RISC (Reduced Instruction Set Computer) design Only thirty seven instructions to remember Its code is extremely efficient, allowing the PIC to run with typically less program memory than its larger competitors. It is low cost, high clock speed
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Harvard Architecture

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Von-Neumann Architecture

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Complex Instruction Set Computer (CISC)

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PICs and most Harvard chips are RISC

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Family Core Architectural Differences

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Family Core Architectural Differences ..

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The PIC Family: Program Memory

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The PIC Family: Data Memory

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The PIC Family: Control Registers

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The PIC Family: Peripherals

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PIC Peripherals: Ports (Digital I/O)

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Comparison of PIC families

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Some members of the PIC 16 Series family

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Some members of the PIC 16 Series family ..

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The PIC 16F84A pin connection diagram

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PIC16C8X PINOUT DESCRIPTION

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PIC16C8X PINOUT DESCRIPTION ..

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Block diagram of the 16F84A (supplementary labels in shaded boxes added by the author)

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W Register

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The 16F84A Status register

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The PIC16F84 Status register

Unlike most MCUs, there are no instructions to specifically clear or set a flag, such as sec for SEt Carry (MC6800). However, as the Status register is accessible as a file in the Data store, then any instruction that can alter the contents of a file can potentially change the state of a flag.

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16F84A memory features

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The 16F84A program memory and Stack

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Data memory and Special Function Register map of the 16F84A

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16F84A Configuration Word

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The EECON1 Special Function Register (address 88H)

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Data EEPROM
The PIC16F84 has a blockof 64 bytes of data that does not require power to retain its contents. This non-volatile memory is not part of the (volatile) Data store and is accessed through SPRs as a peripheral device. Any byte can be addressed and then read from or written to via the EEDATA register as addressed by the EEADR register and controlled by the EECON1 and EECON2 control file registers. Data EEPROM has a minimum endurance of 1,000,000 writes and such data is retained for upwards of 40 years. Some typical uses of a non-volatile depository would be to hold the number of pages printed in a laser printer or total miles/kilometers travelled in a car. 40

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EEPROM
To read an EEPROM location, the required address must be placed in EEADR and the RD bit set in EECON1. The data in that memory location is then copied to the EEDATA register and can be read immediately. To write to an EEPROM location, the required data and address must be placed in EEDATA and EEADR respectively. The write process is enabled by the WREN (Write Enable) bit being set high, followed by the bytes 55H followed by AAH being sent to the EECON2 register. The built-in requirement for these codes helps to ensure that accidental writes do not take place, for example on power-up or down. The WR bit is then set high and writing actually commences. The write completion is signalled by the setting of bit EEIF in EECON1.
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EEPROM Read & Write

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Clock oscillator and instruction cycle

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Microcontroller oscillator generator circuits

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Three ways to provide the clock signal to a PIC

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Pipelining

The combination of the RISC instruction set and the Harvard memory map used by PIC microcontrollers has an added advantage: instructions can be pipelined. Every instruction in a computers program memory has first to be fetched and then executed. In many CPUs these two steps are done one after the other first the CPU fetches and then it executes. If, however, program memory has its own address and data bus, separate from data memory (i.e. a Harvard structure), then there is no reason why a CPU cannot be designed so that while it is executing one instruction, it is already fetching the next. This is called pipelining.
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Power-up and Reset

R = 10100 k

In the 16F84A there is a Reset input, MCLR (Master Clear, on pin 4). As long as this is held low, the microcontroller is held in Reset. When it is taken high, program execution starts. If the pin is taken low while the program is running, then program execution stops immediately and the microcontroller is forced back into Reset mode.

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Some ways to power a PIC

The last one is only for a PIC that is not powering an LED or other high-current load.

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The 16F84A on-chip reset circuit

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Addressing Modes

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DIRECT/INDIRECT ADDRESSING

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Data store memory map.

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Direct address mode

Indirect address mode

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PIC18Fxx2 MCU

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PIC18Fxx2 Simplified Block Diagram

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PIC18Fxx2 Memory Organization

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PIC18Fxx2 Data Memory Organization

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PIC18Fxx2 Accessing Data Memory

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PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are readmodify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The RA4 pin is multiplexed with the TMR0 clock input.
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PORTA and TRISA Registers

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Logic circuit diagram for pins RA0 to RA3

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PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' on any bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins have a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION_REG<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTBs pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The pins value in input mode are compared with the old value latched on the last read of PORTB. The mismatch outputs of the pins are ORed 67 together to generate the RB port change interrupt.

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Parallel input/output with PORTA & PROTB

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