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Phn I GII THIU V SPARTAN -3E KIT BOARD V MI TRNG LP TRNH ISE 9.2I ..................................................................................................................... 3 I.1 Hng Xilinx ..................................................................................................................... 3 I.2 Mch pht trin h Spartan 3E Kit Board ca hng Xilink ........................... 3 I.2.1 Kin trc c bn .................................................................................................... 3 I.2.2 Cc thng s k thut v mt s hnh nh ................................................ 5 I.2.3 M s Chip v ngha ca n .......................................................................... 6 I.3 Mi trng lp trnh ISE Foundation 9.2i ............................................................ 7 I.3.1. Gii thiu mi trng lp trnh ISE .............................................................. 7 I.3.2 ngha ca b cng c ISE .............................................................................. 9 I.3.3 Gii thiu cc cng c lp trnh ca hng Xilink ...................................... 9 I.3.4 S lc cch s dng phn mm ISE Foundation 9.2i ........................ 11 Phn II : GII THIU V BN PHM PS2, LCD V SDRAM .............................. 15 II.1 Gii thiu v bn phm PS2 ................................................................................... 15 II.1.1 Tng quan v bn phm PS2 ......................................................................... 15 II.1.2 Giao tip bn phm vi kit Spartar-3E thng qua cng PS2 ............ 17 II.2. Gii thiu v LCD: ................................................................................................... 19 II.2.1 Gii thiu chung................................................................................................. 19 II.2.2 Nguyn l hot ng........................................................................................ 20 II.2.3. Cc thun li v bt li ca LCD ................................................................ 21 II.2.4 S chn chc nng ..................................................................................... 22 II.2.5. Tp lnh ca LCD ............................................................................................. 25 II.2.6 Bng m ca LCD.............................................................................................. 29 II.3 SDRAM (kit Spartan-3E) ........................................................................................ 31 Phn III : CHI TIT THIT K V THI CNG .......................................................... 34 III.1 Truyn d liu t bn phm PS2: ...................................................................... 35 III.1.1 Module ps2_rx .................................................................................................. 36 III.1.2 Module key_code ............................................................................................. 38 III.1.3 Module chuyn m ASCII ............................................................................. 38 III.1.4 Module hin th & test PS2 .......................................................................... 38 III.2 LCD controller : ........................................................................................................ 39 III.2.1 S khi ca module LCD_controller ................................................... 39 III.2.2 Hot ng ca module LCD_controller ................................................... 41 Phn IV: KT QU ............................................................................................................. 45
Mc lc
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Tm tt:
VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mt loi ngn ng m t phn cng c pht trin dng cho trng trnh VHSIC (Very High Speed Itergrated Circuit) ca b quc phng M. N l mt ngn ng c lp khng gn vi bt k mt phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi ch s dng mt ngn ng duy nht. Chnh v vy m trong bi bo co ny chng ti s dng ngn ng lp trnh VHDL thc hin thit k mt chip x l ( trn kit FPGA Spartar 3E ca hang Xilinx) x l giao tip tn hiu vi bn phm PS2 v xut d liu ra LCD. D liu ny ng thi s c lu tr trong SDRAM di dng tn trong mt danh b in thoi v chip cng chu trch nhim thc hin vic search tn ny ly d liu ra. Bi bo co s gm 4 phn, phn 1 s gii thiu v Kit Spartar-3E phn th 2 s ni ti cc phn cng giao tip vi KIT bao gm keyboard, LCD, v SDRAM. Phn 3 s l phng n thc hin v cui cng l tng kt cc kt qu thu c.
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Phn I GII THIU V SPARTAN -3E KIT BOARD V MI TRNG LP TRNH ISE 9.2I
I.1 Hng Xilinx
Xilinx l nh pht trin hng u hin nay trong lnh vc chip kh trnh, c thnh lp bi Ross Freeman, Bernie Vonderschmitt, v Jim Barnett, v c tr s ti thung lng Silicon. Tr s chnh hin nay San Jose, California. L thnh vin ca nhm 100 cng ti hng u th gii hin nay do tp ch Fortune bnh chn. Xilinx l nh pht trin FPGA, CPLD c s dng rng ri trong nhng ng dng truyn thng, t ng ha, mt m...v cc lnh vc khc. Cc sn phm phn cng ca Xilin gm c cc dng CPLD : CoolRunner, cc h FPGA nh Spartans, Virtex... Xilinx cn cung cp cc phn mm h tr lp trnh FPGA, CPLD nh ISE, EDK, LogicCore, System Generator. Cc cng c ny h tr rt nhiu cho qu trnh lp trnh FPGA, gip gim thi gian v cng sc thit k. Cc phin bn phn mm trn c nng cp thng xuyn.
I.2 Mch pht trin h Spartan 3E Kit Board ca hng Xilink I.2.1 Kin trc c bn
Cu trc tng quan ca Spartan 3E gm c 5 thnh phn c chc nng kh trnh c bn sau: + Configurable Logic Blocks (CLBs): Bao gm cc Look-Up Tables (LUTs) rt linh ng c chc nng thc thi cc logic v cc phn t nh dng nh l cc flip-flop hoc cc cht (latch). CLB thc hin phn ln cc chc nng logic nh l lu tr d liu,.. + Input/Output Blocks (IOBs): iu khin dng d liu gia cc chn vo ra I/O v cc logic bn trong ca FPGA. IOBs h tr lung d liu 2 chiu (bidirectional data flow) v hot ng logic 5 trng thi (5 state). H tr phn ln cc chun tn hiu, bao gm mt vi chun tc cao, nh Double Data- Rate (DDR). + Block RAM : Cho php lu tr d liu di dng cc khi (block) dual-port 18-Kbit. 3 ----Nhm 9----
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+ Multiplier Blocks : Cho php 2 s nh phn 18bit lm u vo v d dng tnh ton tch ca chng. + Digital Clock Manager (DCM) Blocks : Cung cp kh nng t xc nh xung clock, l gii php s hon chnh cho cc tn hiu clock phn phi, tr, nhn, chia v dch bit. Cc phn t ny c t chc nh trong hnh sau:
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ny c mt switch matrix dnh ring cho php chn la kt ni cho vic i dy trong FPGA.
Phn t S hng S ct logic h thng 100K 250K 500K 1200K 1600K 2,160 5,508 10,476 19,512 33,192 22 34 46 60 76 16 26 34 46 58
S cng
T khi sn xut dng sn phm Spartan-3 Platform FPGA, Xilinx tr thnh hng u tin trn th gii tip cn cng ngh 90nm. Dng sn phm Spartan 3E cng c k tha v pht trin da trn cng ngh ny.
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Spartan-3E Starter kit board l mt cng c hu hiu cho bt k ai ang c nh thit k cc sn phm da trn cng ngh FPGA. y l mt gii php c bn cho nhm ti u thi gian v chi ph ban u. N cho php ch to ngay vi gi thnh sn phm thp. B kit ny l mt thit b cu trc logic c th c ngi s dng lp trnh trc tip m khng phi s dng bt k mt cng c ch to mch tch hp no.
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Pb-Free Packaging
I.3 Mi trng lp trnh ISE Foundation 9.2i I.3.1. Gii thiu mi trng lp trnh ISE
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Phn mm ISE (Integrated Software Environment) ny l mt mi trng thit k hon ho ca Xilinx, n tr gip cho ngi thit k hu ht cc cng c cn thit c th hon thnh mt n thit k nhanh nht v hiu qu nht. ISE tch hp cc cng ngh tin tin nht mng li tnh linh hot, giao din GUI thn thin vi ngi s dng. Mt s u im ca ISE l: - Tn dng ti a tt c cc cng ngh tin tin nht ca PLD. - Tit kim thi gian thit k, h tr tt c cc dng sn phm ca Xilinx. - Tng hiu qu v gim gi thnh - H tr ti a cho vic thit k cc h thng nhng. B sn phm ISE bao gm cc gi phn mm: a. ISE WebPACK: y l gi sn phm dng pht trin h thng mt cch d dng nht v n l mi trng thit k on-line (trc tuyn) trn Web v c h tr trc tip t Xilinx. ISE WebPACK cho php ngi dng hon thnh bn thit k nhanh chng nh s kt hp ca cc thit k u vo HDL, cc cng v tng hp tin tin v kh nng kim tra i vi c CPLD v FPGA trc tuyn. b. ISE BaseX: y l gi phn mm hiu qu v kinh t nht, l mi trng thit k PLD trn my tnh c nhn linh hot v n nh. N cung cp tt c cc kh nng nh ISE WebPACK, ngoi ra n cn c b sung nhiu cng c khc h tr cho ngi dng. c. ISE Alliance: Gi phn mm ny c thit k ph hp vi mi trng thit k c sn ca ngi dng. N kt hp cc cng c hay nht ca Xilinx to mi trng thit k hon chnh vi cc tnh nng cao hn ISE BaseX. d. ISE Foundation: y l gi phn mm hon chnh nht, d s dng, tnh nng nhiu nht ng thi tch hp cc cng c phn tch, tng hp v cng ngh kim tra sn phm vi cc gii php hu hiu.
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I.3.3 Gii thiu cc cng c lp trnh ca hng Xilink 1.3.3.1 ISE 9.2
L cng c xy dng v lp trnh FPGA. ISE 9.2 thc s l mt mi trng tng hp v thc thi ton din cho cc chip kh trnh ca Xilinx. Vi ISE9.2, ngi thit k c th lp trnh, g ri, m phng, dch v np chng trnh mt cch nhanh chng v d dng. Ngi thit k cng c th thit k h thng ca mnh theo nhiu cch khc nhau : vi m HDL, vi s RTL, hoc vi s trng thi (state machine)
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RAM, ROM, cc I/O,....Cc thit k vi x l nhng cng c ti u ha. Ngoi ra EDK cng c cng c m phng rt mnh.
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* Hng dn cc bc to mt Project mi (S dng Spartan 3E) Bc 1: T menu file new project v in tn vo Poject name, chn th mc lu Project location, chn ngn ng vit ri bm next:
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Bc 3 : Sau khi thc hin xong bc trn chn Next, mt ca s mi ta thm ngun mi vo n. Chn New source, chn VHDL Module, g tn vo File Name v next :
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Nu c tp lp trnh sn, ta c th thm vo bc ny bng cch bm vo Add Source v chn ng dn n tp ngun mun thm vo. Bm Next v Finish hon thnh. Sau khi nh ngha v m t xong cc bc trn, trnh dch s t ng to ra thc th vi cc cng c m t bng lnh (VHDL) nh sau : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Bodem is Port ( clock : in STD_LOGIC; Q0 : in STD_LOGIC; Q1 : in STD_LOGIC; Q2 : in STD_LOGIC; Q3 : in STD_LOGIC; Out : out STD_LOGIC_VECTOR (7 downto 0)); end Bodem; architecture Behavioral of Bodem is begin end Behavioral; Nh vy ta to ra mt n, bc tip theo ta vit chng trnh vo ca s son tho. i vi mt n ln, ta phi thc hin vi nhiu module, c th hon thnh n th phi thit k tng module v tun th theo cc bc ch to Chip. 14 ----Nhm 9----
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M QUT BN PHM (SCAN CODE) Khi nhn 1 phm, b x l bn phm gi n PC m qut (scancode) ca phm c nhn Khi phm c nhn, m ny gi l make-code Khi phm c nh, m ny gi l break-code Break-code gm 2 byte: byte u l F0 (i vi bn phm m rng), byte k l m make-code V d: nhn SHIFT: make-code = 12 Nhn A: Nh A: Nh SHIFT:
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Hnh 2.2 : Scan-code bn phm loi 102 phm II.1.2 Giao tip bn phm vi kit Spartar-3E thng qua cng PS2 Bn phm PS2 giao tip bng giao thc ni tip bt ng b 2 chiu Xung clock c pht bi bn phm, tn s khong 1016.7kHz
Cc trng thi hot ng Data=high, clock=high: trng thi rnh Data=high, clock=low: trng thi cm giao tip Data=low, clock=high: trng thi my ch c yu cu truyn d liu
Truyn d liu t bn phm v my ch: Cc bc thc hin: Kim tra bus ang trng thi rnh Clock mc cao t nht 50us trc khi bn phm gi data Bn phm gi data tng khung d liu 11bit D liu c c ti cnh xung ca clock
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Bo co h thng nhng My ch c th cm giao tip bng cch ko clock xung thp Khi clock c gii phng, bn phm li truyn tip d liu cha hon chnh
Hnh 2.3 : D liu t keyboard n PC Truyn d liu t my ch n bn phm: Cc bc thc hin: My ch cm truyn t bn phm n bng cch ko clock xung thp My ch ko data xung thp v gii phng clock bo hiu bn phm pht xung clock bt u truyn d liu D liu c c ti cnh xung ca clock Sau khi bn phm nhn stop bit n s truyn tn hiu ACK n my ch kt thc qu trnh truyn d liu
ED
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Caps Num Scroll Lock Lock Lock Echo. Khi nhn lnh echo, bn phm s tr v cng m qut nhn EE. Thit lp tc lp m qut ca phm.Bn phm s thng bo khi nhn c m qut ca F3 bng cch tr v mt m qut FA, sau thit b iu khin s gi byte th hai thit lp tc lp phm. (Khng s dng) Gi li. Khi nhn c lnh ny, bn phm s gi li m qut va gi i trc . Reset. Resets bn phm.
EE
F3
FE FF
Bng 2.1Cc ln truyn t my ch ti bn phm II.2. Gii thiu v LCD II.2.1 Gii thiu chung Thut ng tinh th lng c ngh s dng ln u tin bi nh vt l O.Lehman vo nm 1889 ch mt trng thi c bit ca vt cht m cc tnh cht ca n l trung gian gia tinh th cht rn v cht lng ng hng . Trng thi vt cht ny kt hp nhiu tnh cht c hc ca cht lng thng thng ( c hnh dng ca vt cha , to thnh git ) v cc tnh cht d hng in t v quang ca tinh th . Cc phn t to thnh tinh th lng thng c c trng ha bng cc phn t c dng ng iu hoc dn di . Hng dn di nh ngha trc chiu di cc phn t . Cc tnh cht ch yu ca tinh th lng l tnh d hng in t v quang . Trc chiu di ca cc phn t c khuynh hng ng chnh theo cng mt hng nht nh , ngha l iu chnh theo hng . Ty loi iu chnh hng m c 3 pha vt liu tinh th lng khc nhau : nematic , smectic , cholesteric. LCD ( Lequid Crystal Display) l mt dng hin th nh ng dng ca tinh th lng , nh s sp xp c hng ca cc tinh th lng di tc dng ca in trng .
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Bo co h thng nhng Hin nay c nhiu loi LCD vi kch thc khc nhau nhng trong phn ny ch gii thiu LCD theo chun HD44780 . Hnh sau trnh by mt s loi LCD 2 dng theo chun HD44780.
Hnh 2.5 : mt s LCD chun HD44780 Cc LCD c ch to vi cu to thng dng l 16, 20, 24, 32, 40 k t trn 1 hng vi mn hnh hin th 1, 2 hay 4 hng . C loi LCD hin th theo k t hay ha . Cc module LCD thng minh l LCD c tch hp trong mch li cc chip iu khin (HD44780). Nh m n c th hin th khng nhng s m cn hin th ch , cc k hiu v c th cho php ta nh ngha cc k hiu ca ring mnh. II.2.2 Nguyn l hot ng Bng cch s dng tnh cht ca tinh th lng s phn cc nh sang i qua c th b thay i v truyn nh sang b iu khin bi in trng . Tinh th lng c th c 1 trong 2 trng thi . Khi khng c in p t vo hai in cc , chng trng thi TN . in cc trn c nh bng sao cho cc phn t lp trn song song vi s phn cc ca b phn cc trn . in cc di c chun b ng chnh lp di cc phn t tinh th vi b phn phn cc di . gia cc phn t hng t hng ny sang hng khc . Trong iu
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Bo co h thng nhng kin ny tinh th xoay phn cc nh sang i qua 900 v nh sang c th i qua b phn cc t bo bn trong sut. Khi c in p a vo phn cc , in trng gia cc in cc lm thay i nh hng ca cc phn t tinh th. Vi cc phn t c ng chnh theo in trng , khng c s thay i phn cc nh sang i qua , v do nh sng i qua cc in cc b ngn li . nh ti theo hnh dng ca cc in cc c to ra. Cc ch hin th : Hin th pht ( transmissive display) : c s dng vi iu kin nh sng bn ngoi rt yu . Hin th phn chiu ( reflective display) : ph thuc vo nh sng bn ngoi , khng th s dng hin th loi ny khi iu kin nh sng bn ngoi rt yu.
Hin th pht phn chiu (transreflective display) : c s dng cho mt dy rng iu kin chiu sng. II.2.3. Cc thun li v bt li ca LCD Thun li: Tiu th cng sut rt thp vi dng in tiu biu 20nA/mm2 . iu ny lm cho LCD ng dng c vi cc dng c , thit b dng pin. Yu cu in p thp , tiu biu : 1.5V n 5V . Tng thch CMOS. c c di nh sng mt tri. Uyn chuyn , linh ng , b hin th d dng lm cho thch hp vi cc ng dng hin th theo on , ma trn chm , th , ha v cc ng dng khc ( kh nng mu cho cc hin th TV phng cng kh dng ).
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Bo co h thng nhng Bt li : Kiu thng dng nht l pht phn x khng s dng c khi cc mc sng xung quanh thp. Thi gian p ng ca t bo LCD rt chm so vi nhiu ng dng. Gc nhn ca b hin th b hn ch. Cc dng c hay thit b ny nhy vi nhit . II.2.4 S chn chc nng
Chn 1 2 3 4
Mc Logic 0/1
I/O I
Chc nng Ngun (GND) Ngun (+5V) Chnh tng phn 0 = Nhp lnh 1 = Nhp d liu 0 = Ghi d liu 1 = c d liu
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R/W
0/1
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Bo co h thng nhng Chn 6 7 8 9 10 11 12 13 14 15 16 K hiu E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 LampLamp+ Mc Logic 1, 1->0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 I/O I I/O I/O I/O I/O I/O I/O I/O I/O Chc nng Tn hiu cho php Bus d liu 0 Bus d liu 1 Bus d liu 2 Bus d liu 3 Bus d liu 4 Bus d liu 5 Bus d liu 6 Bus d liu 7 n LCD n LCD
Chn 1 ( Vss) : chn GND Chn 2 (VDD) : ngun cung cp 5V DC. Theo s tay th ngun cp cho LCD l 5V DC (ch khong vi mA) nhng cung cp cho n 6VDC hay 4.5V DC th n cng hot ng tt v ngay c 3VDC cng cho mt s module.LCD tiu th nng lng rt t.
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Bo co h thng nhng Chn 3 (V0) : iu khin tng phn ca mn hin th. L tng th chn ny ni vi ngun thay i c , nhng n gin nht l ngi ta ni chn ny xung t ( 0V ). Chn 4 (RS) : Register Select , chn thanh ghi . y l mt trong 3 chn iu khin lnh. Khi chn ny mc thp th cc d liu c truyn n LCD c x l nh mnh lnh v cc d liu c ra ch trng thi ca n. Bng cch a ng RS ln mc cao th d liu k t c th xut / nhp trn module ny . Chn 5 (R/W) : Read/Write . Chn ny c ko xung mc thp ghi cc lnh hay d liu k t vo moduke hoc c ko ln mc cao c d liu k t hay thng tin trng thi t cc thanh ghi ca n. Chn 6 (E) : chn cho php , tch cc mc cao. Ng vo ny dung khi ng vic chuyn cc lnh hay d liu gia modue v cc ng d liu. Khi ghi ra mn hnh hin th LCD , d liu ch c chuyn khi c cnh xung tn hiu E ny . Tuy nhin khi c ra t LCD th d liu kh dng sau khi c chuyn tip t thp ln cao v duy tr d liu kh dng cho n khi tn hiu xung thp mt ln na. Chn 7 n chn 14 l 8 ng bus d liu t DB0 n DB7. D liu c th c chuyn n v ly ra khi b hin th LCD theo dng mt byte 8 bit hay dng hai na byte 4bit (nibble) . Trong trng hp sau ch c 4 ng d liu trn s dng ( 4 bit cao : DB7 n DB4 ). Ch 4 bit ny thun tin khi s dng vi x l , cn c t ng xut / nhp hn.
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Bo co h thng nhng Chn 15 , 16 : l chn iu khin nh sng nn ( blacklight). II.2.5. Tp lnh ca LCD Bng sau trnh by tm tt tp lnh iu khin LCD . M nh phn Tp lnh R R/ DB DB DB DB DB DB DB DB0 S W 7 6 5 4 3 2 1 M t Th i gia n th c thi
Xo hin th
0 0
Xo hin th v a 1.5 con tr v v tr 2m ban u (a ch S 0). Tr con tr v v tr ban u (a ch 0). Ngoi ra a hin th b dch 1.5 chuyn v v tr 2m ban u. Ni dung S b nh hin th d liu(DDRAM) khng thay i. Thit lp hng di chuyn ca con tr tng/gim( I/D=0:gim, I/D=1:tng) , ch r dch chuyn hin th (S=0: khng 37u dch chuyn hin S th,S=1 dch chuyn hin th). Hot ng ny c thc hin trong sut qu trnh c/ghi d liu Bt/tt hin th 37u
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Con tr ban u
0 0
Thit lp 0 0 ch
I/ D
iu
0 0
C
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khin hin th
(D=0: tt, D=1:bt)nhng d liu vn lu trong DDRAM, bt/tt con tr (C=0: tt, C=1: bt) bt tt con tr nhp nhy ti v tr ca k t (B=0: tt, B=1: bt).
S/ R/ * C L
Dch chuyn con tr/hin th qua tri /phi m khng phi c/ghi li d liu (S/C=0:di chuyn con 37u tr,S/C=1:di S chuyn hin th), (R/L=0:dch tri,R/L=1:dch phi). ni dung DDRAM khng thay i. Khi to giao din ca di d liu (DL=0: di 4 bit,DL=1:8 bit), s hng hin 37u th(N=0:1 hng S ,N=1 :2 hng) v phng ch(F=0:5x7,F=1: 5x10).
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1 DL N
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a ch CGRAM
Thit lp a ch b nh to k t 37u (CGRAM.),d liu S c gi/nhn sau thit lp ny Thit lp a ch b nh to k t 37u (DDRAM.),d liu S c gi/nhn sau thit lp ny
a ch DDRAM
c c bn
c c bn Busyflag (BF),kim tra xem h thng c ang thc thi 1 lnh c nhn trc 0 1 BF a ch CGRAM / DDRAM khng.(BF=1:h thng ang thc hin tc v bn trong,khi BF=0 th lnh tip theo mi c thc thi)
0uS
Ghi d liu
37u S
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c d liu
37u S
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Bo co h thng nhng II.2.6 Bng m ca LCD Ging nh bn phm th LCD cng c mt bng m chun ca n. Bng m LCD c trnh by nh sau :
Bng 2.5 : Bng m LCD Theo bng m trn th ta thy bng m ca LCD ging nh bng m ASCII chun ( phn k t in c ). Cn bn k t sau c
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Bo co h thng nhng thm mt s k t v c nhng k t khng ging vi bng 1 nhng hu ht cc k t in c th ging nhau. II.3.7. Hin th LCD : Khi va mi cp in cho module th cursor c nh v v tr bt u ca hang th nht. y l a ch 00h. Mi k t a vo th cursor s chuyn sang a ch mi ( 01h , 02h, ). Vic tng t ng a ch cursor lm vic a vo hin th d dng , ta khng cn phi a a ch c th ca tng k t. Tuy nhin c th ta cn nh v tr ca chui k t mt ch bt u dng th nht. Trong trng hp ny ta phi a vo a ch bt u mi nh mt dng lnh. Bt k a ch no t 00h n 7Fh c th c dung lm a ch bt u, nh vy c tng cng 128 a ch khc nhau. Tht ra LCD ch c 80 v tr hin th ( i vi LCD 2x16 l 32 k t), iu ny m phc tp vic hin th cho LCD.
Hnh 2.7 Vng RAM hin th DDRAM hin th 1 hng v hin th 2 hng.
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Bo co h thng nhng II.3 SDRAM (kit Spartan-3E) SRAM trn kit Spartan-3E l mt b nh truy xut ngoi , gm 32M x 16 t bo DDR SDRAM tnh vi ng vo 16-bit data nh hnh di S chn :
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III.1 Tng qut Ly tng t vic thit k mt thit b thng minh nhp d liu lu tr n v hin th mn hnh ng thi thc hin x l cc s liu c lu tr , nhm thc hin tng ny bng m hnh thc t l xy dng mt danh b in thoi da trn giao tip trn bn phm PS2, lu tr d liu vo ram ng thi search ra cc d liu v hin th ln mn hnh LCD. tng trc mt th n gin nhng l cng vic ca bt c mt m hnh thit b no trn th gii hin ti t my vi tnh, mp3, in thoi di ng, cc b iu kin cc thit b gia dng Thit k gm 2 module chnh thc hin chc nng chnh: Khi giao tip: bao gm nhp d liu t PS2 lu tr vo RAM v hin th LCD Khi tm kim (search) cc d liu lu tr
PS2
LCD
SDRAM
Chip x l
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----Nhm 9----
Bo co h thng nhng
Hnh 3.1 S khi tng qut ca thit k Trong danh b ny d liu c truyn t bn phm PS2 , hin th ln LCD (v 1 s LED) trn kit Spartar 3E v lu tr trong SDRAM . Chnh v vy trc ht ta thit k cc module controller ln lt cho PS2 , LCD v SDRAM. Phn thit k thc hin cc module c th c trnh by trong phn di y III.2 Truyn d liu t bn phm PS2:
Hnh 3.2. S khi module ps2 -Tn hiu reset mc cao -PS2_CLK v PS2_DAT ln lt l xung clock hot ng v d liu nhn c t bn phm. -Xung CLOCK_50 dng ng b vi xung clock ca PS2 -Module Display hin th ln led 7 on trn kit DE2 nhm kim chng kt qu.
35
----Nhm 9----
Bo co h thng nhng Ton b module ny iu ta quan tm l m make_code chuyn thnh ascii th hin cho phm nhn trn keyboard , v m break_code cho bit trng thi phm(nhn/th) III.2.1 Module ps2_rx Dng nhn 8 bit data t bn phm. S dng gii thut pht hin cnh xung ca xung clock keyboard.
36
----Nhm 9----
Bo co h thng nhng
Idle
F N=0 N=N-1
Rx_done =1
Hnh 3.3.Lu qu trnh nhn d liu t bn phm y ta nhn d liu t bn phm khi c du hiu l cnh xung ca xung clock PS2 v d liu ca bn phm ch c c theo cnh xung ( falling_edge ) ca xung clock keyboard Sau khi pht hin c cnh xung ca xung ps2_clk th bt u dch 11 bit d liu vo thanh ghi ni lu gi tr d liu. Khi nhn 11bits th bt c rx_done_tick ln 1. D liu ly c chnh l 8bits trong thanh ghi ni q (8 downto 1)
37 ----Nhm 9----
Bo co h thng nhng Kt qu m phng cnh xung v thanh ghi s ghi vo b nh ca mnh c thc hin bng Model Sim:
Hnh 3.4 Kt qu m phng pht hin cnh xung III.2.2 Module key_code Dng chuyn d liu t bn phm ra thnh make code v break code Cho ta bit phm ang c nhn hay nh S dng gii thut ly 3 byte cui khi nh phm lm make code (1byte) v break code (2byte) thng qua bin got_code_tick bo nh phm. III.2.3 Module chuyn m ASCII Module ny c tc dng chuyn make_code m keyboard pht ra thnh m ascii III.2.4 Module hin th & test PS2 Module ps2_kb (Display) : nhm kim tra li ton b qu trnh nhn d liu t keyboard cho n vic c c make_code , break_code v ascii_code . y va l module kim tra , va l module th hin s hot ng v kt qu nhn c qua s giao tip gia bn phm keyboard vi kit DE2 thng qua cng giao tip PS2. Hin th m ASCII ln cc LED . Kt qu m phng bng Modelsim , cho data vo ln lt l:
38 ----Nhm 9----
Bo co h thng nhng -Scan_code = 1C h (k t a m ascii=61h) -Scan_code = 1E h (k t 2 m ascii= 32h) -Scan_code = 58 h (k t Caps -> m ascii = 2Eh) tn hiu Caps Key on s bng 1!
Hnh 3.5.1 Kt qu m phng hot ng khi PS2(1) Nhn shift 12h tn hiu shift on = 1 v nh shift F0 12 tn hiu shift on = 0. Nhn caps 58h tn hiu caps key on = 1 v nhn caps thm ln th 2 caps key on = 0. Nhn Ctrl 14h tn hiu Ctrl on = 1 Khi c caps lock tn hiu 1Eh phm 2 m Ascii l 32h 2 Khi c caps lock tn hiu 1Ch phm a m Ascii l 41h A
Hnh 3.5.2 Kt qu m phng hot ng khi PS2(2) III.3 LCD controller : III.3.1 S khi ca module LCD_controller
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----Nhm 9----
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Hnh 3.6 S khi module LCD_controller D liu data ( 7 downto 0) chnh l m ascii ca khi bn phm gi n hoc l d liu ascii c c trong SDRAM xut ra LCD ( trong gii thut search s cp phn sau) Tn hiu nC_D l chn tn hiu tch cc mc thp c truyn n t cc module gii thut nh insert ( to danh sch contact ) , module search ( tm kim contact) nhm chn la cng vic cho LCD gia vic xut ch v thc hin lnh ( vd : xung hng , clear LCD , dch tri phi) . nC_D = 0 : LCD thc hin lnh trn mn hnh nC_D = 1 : LCD xut ch ra mn hnh ng tn hiu data_in_flag bo cho LCD khi to 1 chu trnh lm vic mi V p ng xung ca LCD chm , v n v delay LCD c th thc hin cc thao tc ca n thng tnh bng us-ms nn ta chia Xung 50Mhz trn kit Spartar-3E thnh xung 1Khz vi chu k 1ms thun tin trong vic delay cc khong time cn thit m LCD yu cu (chi tit hn phn sau).
40
----Nhm 9----
Bo co h thng nhng Cc chn LCD_RW , LCD_RS , LCD_EN ni trc tip vo LCD trn kit Spartar-3E . ng d liu 8bits LCD_DATA cung cp d liu cho vic hin th LCD v cng c ni trc tip n 8 in port ca LCD III.3.2 Hot ng ca module LCD_controller Khi to LCD: Mi khi c cp ngun, mch khi to bn trong LCD s t ng khi to cho n. V trong thi gian khi to ny c BF ( busy flag bo bn) bt ln 1, n khi vic khi to hon tt c BF cn gi trong khong 10ms sau khi Vcc t n 4.5V (v 2.7V th LCD hot ng). Mch khi to ni s thit lp cc thng s lm vic ca LCD nh sau: Display clear : Xa ton b ni dung hin th trc . Function set: DL=1 : 8bit; N=0 : 1 hng; F=0 : 5x8 Display on/off control: D=0 : Display off; C=0 : Cursor off; B=0 : Blinking off. Entry mode set: I/D =1 : Tng; S=0 : Khng dch. Nh vy sau khi m ngun, ta s thy mn hnh LCD ging nh cha m ngun do ton b hin th tt. Do , ta phi khi to LCD bng lnh. Khi to l vic thit lp cc thng s lm vic ban u. i vi LCD, khi to gip ta thit lp cc giao thc lm vic gia LCD v main_control. Vic khi to ch c thc hin 1 ln duy nht u chng trnh iu khin LCD v bao gm cc thit lp sau : Display clear : Xa/khng xa ton b ni dung hin th trc . Function set : Kiu giao tip 8bit/4bit, s hng hin th 1hng/2hng, kiu k t 5x8/5x10. Display on/off control: Hin th/tt mn hnh, hin th/tt con tr, nhp nhy/khng nhp nhy.
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----Nhm 9----
Bo co h thng nhng Entry mode set : cc thit lp kiu nhp k t nh: Dch/khng dch, t tng/gim con tr. y ta khi to cho LCD bng lnh v phi tun theo lu sau ca nh sn xut:
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Bo co h thng nhng
Hnh 3.7 Lu iu khin LCD theo nh sn xut Kt thc qu trnh ny , LCD c khi to xong ,ch l ch c thc hin thay i Function set u chng trnh. V sau khi c thc thi 1 ln, lnh thay i Function set khng c LCD chp nhn na ngoi tr thit lp chuyn i giao thc giao tip .
43 ----Nhm 9----
Hnh 3.8 Lu hot ng chnh ca LCD_controller Cn lu y chnh l thi gian lm vic thc thi lnh ca LCD ( xem li bng 2.2) , thi gian thc thi 1 lnh ca LCD mt t 37us-1.52ms , an ton th sau mi ln LCD thc hin xong 1 lnh , ta hng cho n quay v trng thi dropE tc l a tn hiu chn LCD_EN xung mc 0 trong khong thi gian l 2ms . iu ny khin cho chip x l HD44780 c 1 khong thi gian d thc hin cc thao tc ca n , lm cho qu trnh nhp d liu hin th ln LCD c din ra chnh xc v an ton.
Phn SDRAM v search nhm vn ang tm hiu v cha i vo thi cng thc t nn khng a vo phn trnh by ny.
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Bo co h thng nhng
Phn IV: KT QU
IV.1 Kt qu cc qu trnh thc hin - thc hin thnh cng vic giao tip my tnh vi PS2 v m phng thnh cng bng chng trnh Model Sim. Kt qu m phng trong phn III.2.3. - thc hin thnh cng vic giao tip v iu kin LCD - Sau ly d liu u vo cho chng trnh giao tip hin th LCD l d liu u ra ca chng trnh nhp bn phm qua bin rx_Ascii2 - Sau khi np chng trnh ln kit Spartar 3E thc hin thnh cng vic hin th ny. Nhp cc k t hin th chnh xc v thc hin lu cc d liu nhp vo b nh m ca chip x l. - Phn lu cc d liu nhp vo SDRAM v vic search d liu ny v thi gian c hn nn nhm cha kp thc hin v tm hiu nn kt qu cng vic cha c nh mong i. Nh vy khi lng cng vic ch hon thnh khong 2/3 yu cu c ra cn tng search v nhp vo SDRAM nhm vn cha thc hin c. Tuy nhin vi s n lc t tm hiu nhm thc hin thnh cng vic giao tip bn phm v hin th LCD, vic giao tip ny bao gm xut k t v cc phm hu dng khc nh shift, ctrl, capslock c th biu din k t hoa v k t thng da trn ngn ng VHDL, nh nhm hiu su hn v vic lp trnh v thit k h thng nhng. Hi vng trong nhng mn hc v bi tp ln k tip nhm s tip tc thc hin hon chnh ti v m rng thc hin nhng ti tt hn. IV.2 Kt lun v tng m rng Vic giao tip xut d liu v thc hin x l trn khi d liu c nhp vo l cng vic ca bt k thit b in t no. Trong phm vi bi tp ln ny ch thc hin giao tip gia cc thit b n gin PS2, RAM, LCD v thc hin search d liu trn tuy khng thc s hon chnh nhng n l tin cho nhng giao tip gia cc thit b cao cp hn, v d nh mn hnh cm ng chng hn, va l thit b hin th va l thit b nhp liu. Liu ta c th thit k mt chip x l v giao tip n hay khng? l mt yu cu c t ra v ta cn phi thc hin v nm bt n khi m mn hnh cm ng hu nh s c tch hp hu ht trn cc thit b in t trong tng lai gn.
45 ----Nhm 9----